LLVM  14.0.0git
HexagonMCCodeEmitter.cpp
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1 //===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixup.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Casting.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Endian.h"
31 #include <cassert>
32 #include <cstddef>
33 #include <cstdint>
34 #include <map>
35 #include <string>
36 #include <vector>
37 
38 #define DEBUG_TYPE "mccodeemitter"
39 
40 using namespace llvm;
41 using namespace Hexagon;
42 
43 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
44 
45 static const unsigned fixup_Invalid = ~0u;
46 
47 #define _ fixup_Invalid
48 #define P(x) Hexagon::fixup_Hexagon##x
49 static const std::map<unsigned, std::vector<unsigned>> ExtFixups = {
51  { _, _, _, _,
52  _, _, P(_DTPREL_16_X), P(_DTPREL_11_X),
53  P(_DTPREL_11_X), P(_9_X), _, P(_DTPREL_11_X),
54  P(_DTPREL_16_X), _, _, _,
55  P(_DTPREL_16_X), _, _, _,
56  _, _, _, _,
57  _, _, _, _,
58  _, _, _, _,
59  P(_DTPREL_32_6_X) }},
61  { _, _, _, _,
62  _, _, P(_GOT_11_X), _ /* [1] */,
63  _ /* [1] */, P(_9_X), _, P(_GOT_11_X),
64  P(_GOT_16_X), _, _, _,
65  P(_GOT_16_X), _, _, _,
66  _, _, _, _,
67  _, _, _, _,
68  _, _, _, _,
69  P(_GOT_32_6_X) }},
71  { _, _, _, _,
72  _, _, P(_GOTREL_11_X), P(_GOTREL_11_X),
73  P(_GOTREL_11_X), P(_9_X), _, P(_GOTREL_11_X),
74  P(_GOTREL_16_X), _, _, _,
75  P(_GOTREL_16_X), _, _, _,
76  _, _, _, _,
77  _, _, _, _,
78  _, _, _, _,
79  P(_GOTREL_32_6_X) }},
81  { _, _, _, _,
82  _, _, P(_TPREL_16_X), P(_TPREL_11_X),
83  P(_TPREL_11_X), P(_9_X), _, P(_TPREL_11_X),
84  P(_TPREL_16_X), _, _, _,
85  P(_TPREL_16_X), _, _, _,
86  _, _, _, _,
87  _, _, _, _,
88  _, _, _, _,
89  P(_TPREL_32_6_X) }},
91  { _, _, _, _,
92  _, _, P(_GD_GOT_16_X), P(_GD_GOT_11_X),
93  P(_GD_GOT_11_X), P(_9_X), _, P(_GD_GOT_11_X),
94  P(_GD_GOT_16_X), _, _, _,
95  P(_GD_GOT_16_X), _, _, _,
96  _, _, _, _,
97  _, _, _, _,
98  _, _, _, _,
99  P(_GD_GOT_32_6_X) }},
101  { _, _, _, _,
102  _, _, _, _,
103  _, P(_9_X), _, P(_GD_PLT_B22_PCREL_X),
104  _, _, _, _,
105  _, _, _, _,
106  _, _, P(_GD_PLT_B22_PCREL_X), _,
107  _, _, _, _,
108  _, _, _, _,
109  _ }},
111  { _, _, _, _,
112  _, _, P(_IE_16_X), _,
113  _, P(_9_X), _, _,
114  P(_IE_16_X), _, _, _,
115  P(_IE_16_X), _, _, _,
116  _, _, _, _,
117  _, _, _, _,
118  _, _, _, _,
119  P(_IE_32_6_X) }},
121  { _, _, _, _,
122  _, _, P(_IE_GOT_11_X), P(_IE_GOT_11_X),
123  P(_IE_GOT_11_X), P(_9_X), _, P(_IE_GOT_11_X),
124  P(_IE_GOT_16_X), _, _, _,
125  P(_IE_GOT_16_X), _, _, _,
126  _, _, _, _,
127  _, _, _, _,
128  _, _, _, _,
129  P(_IE_GOT_32_6_X) }},
131  { _, _, _, _,
132  _, _, P(_LD_GOT_11_X), P(_LD_GOT_11_X),
133  P(_LD_GOT_11_X), P(_9_X), _, P(_LD_GOT_11_X),
134  P(_LD_GOT_16_X), _, _, _,
135  P(_LD_GOT_16_X), _, _, _,
136  _, _, _, _,
137  _, _, _, _,
138  _, _, _, _,
139  P(_LD_GOT_32_6_X) }},
141  { _, _, _, _,
142  _, _, _, _,
143  _, P(_9_X), _, P(_LD_PLT_B22_PCREL_X),
144  _, _, _, _,
145  _, _, _, _,
146  _, _, P(_LD_PLT_B22_PCREL_X), _,
147  _, _, _, _,
148  _, _, _, _,
149  _ }},
151  { _, _, _, _,
152  _, _, P(_6_PCREL_X), _,
153  _, P(_9_X), _, _,
154  _, _, _, _,
155  _, _, _, _,
156  _, _, _, _,
157  _, _, _, _,
158  _, _, _, _,
159  P(_32_PCREL) }},
161  { _, _, _, _,
162  _, _, P(_6_X), P(_8_X),
163  P(_8_X), P(_9_X), P(_10_X), P(_11_X),
164  P(_12_X), P(_B13_PCREL), _, P(_B15_PCREL_X),
165  P(_16_X), _, _, _,
166  _, _, P(_B22_PCREL_X), _,
167  _, _, _, _,
168  _, _, _, _,
169  P(_32_6_X) }},
170 };
171 // [1] The fixup is GOT_16_X for signed values and GOT_11_X for unsigned.
172 
173 static const std::map<unsigned, std::vector<unsigned>> StdFixups = {
175  { _, _, _, _,
176  _, _, _, _,
177  _, _, _, _,
178  _, _, _, _,
179  P(_DTPREL_16), _, _, _,
180  _, _, _, _,
181  _, _, _, _,
182  _, _, _, _,
183  P(_DTPREL_32) }},
185  { _, _, _, _,
186  _, _, _, _,
187  _, _, _, _,
188  _, _, _, _,
189  _, _, _, _,
190  _, _, _, _,
191  _, _, _, _,
192  _, _, _, _,
193  P(_GOT_32) }},
195  { _, _, _, _,
196  _, _, _, _,
197  _, _, _, _,
198  _, _, _, _,
199  _ /* [2] */, _, _, _,
200  _, _, _, _,
201  _, _, _, _,
202  _, _, _, _,
203  P(_GOTREL_32) }},
205  { _, _, _, _,
206  _, _, _, _,
207  _, _, _, _,
208  _, _, _, _,
209  _, _, _, _,
210  _, _, P(_PLT_B22_PCREL), _,
211  _, _, _, _,
212  _, _, _, _,
213  _ }},
215  { _, _, _, _,
216  _, _, _, _,
217  _, _, _, P(_TPREL_11_X),
218  _, _, _, _,
219  P(_TPREL_16), _, _, _,
220  _, _, _, _,
221  _, _, _, _,
222  _, _, _, _,
223  P(_TPREL_32) }},
225  { _, _, _, _,
226  _, _, _, _,
227  _, _, _, _,
228  _, _, _, _,
229  P(_GD_GOT_16), _, _, _,
230  _, _, _, _,
231  _, _, _, _,
232  _, _, _, _,
233  P(_GD_GOT_32) }},
235  { _, _, _, _,
236  _, _, _, _,
237  _, _, _, _,
238  _, _, _, _,
239  _, _, _, _,
240  _, _, P(_GD_PLT_B22_PCREL), _,
241  _, _, _, _,
242  _, _, _, _,
243  _ }},
245  { _, _, _, _,
246  _, _, _, _,
247  _, _, _, _,
248  _, _, _, _,
249  P(_GPREL16_0), _, _, _,
250  _, _, _, _,
251  _, _, _, _,
252  _, _, _, _,
253  _ }},
255  { _, _, _, _,
256  _, _, _, _,
257  _, _, _, _,
258  _, _, _, _,
259  P(_HI16), _, _, _,
260  _, _, _, _,
261  _, _, _, _,
262  _, _, _, _,
263  _ }},
265  { _, _, _, _,
266  _, _, _, _,
267  _, _, _, _,
268  _, _, _, _,
269  _, _, _, _,
270  _, _, _, _,
271  _, _, _, _,
272  _, _, _, _,
273  P(_IE_32) }},
275  { _, _, _, _,
276  _, _, _, _,
277  _, _, _, _,
278  _, _, _, _,
279  P(_IE_GOT_16), _, _, _,
280  _, _, _, _,
281  _, _, _, _,
282  _, _, _, _,
283  P(_IE_GOT_32) }},
285  { _, _, _, _,
286  _, _, _, _,
287  _, _, _, _,
288  _, _, _, _,
289  P(_LD_GOT_16), _, _, _,
290  _, _, _, _,
291  _, _, _, _,
292  _, _, _, _,
293  P(_LD_GOT_32) }},
295  { _, _, _, _,
296  _, _, _, _,
297  _, _, _, _,
298  _, _, _, _,
299  _, _, _, _,
300  _, _, P(_LD_PLT_B22_PCREL), _,
301  _, _, _, _,
302  _, _, _, _,
303  _ }},
305  { _, _, _, _,
306  _, _, _, _,
307  _, _, _, _,
308  _, _, _, _,
309  P(_LO16), _, _, _,
310  _, _, _, _,
311  _, _, _, _,
312  _, _, _, _,
313  _ }},
315  { _, _, _, _,
316  _, _, _, _,
317  _, _, _, _,
318  _, _, _, _,
319  _, _, _, _,
320  _, _, _, _,
321  _, _, _, _,
322  _, _, _, _,
323  P(_32_PCREL) }},
325  { _, _, _, _,
326  _, _, _, _,
327  _, _, _, _,
328  _, P(_B13_PCREL), _, P(_B15_PCREL),
329  _, _, _, _,
330  _, _, P(_B22_PCREL), _,
331  _, _, _, _,
332  _, _, _, _,
333  P(_32) }},
334 };
335 //
336 // [2] The actual fixup is LO16 or HI16, depending on the instruction.
337 #undef P
338 #undef _
339 
340 uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
341  MCInst const &MCI) const {
342  bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
343  if (State.Index == 0) {
345  assert(!Duplex);
346  assert(State.Index != Last);
348  }
349  }
350  if (State.Index == 1) {
352  assert(!Duplex);
353  assert(State.Index != Last);
355  }
356  }
357  if (Duplex) {
358  assert(State.Index == Last);
360  }
361  if (State.Index == Last)
364 }
365 
366 /// Emit the bundle.
369  const MCSubtargetInfo &STI) const {
370  MCInst &HMB = const_cast<MCInst &>(MI);
371 
373  LLVM_DEBUG(dbgs() << "Encoding bundle\n";);
374  State.Addend = 0;
375  State.Extended = false;
376  State.Bundle = &MI;
377  State.Index = 0;
378  size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
379  FeatureBitset Features = computeAvailableFeatures(STI.getFeatureBits());
380 
381  for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
382  MCInst &HMI = const_cast<MCInst &>(*I.getInst());
383  verifyInstructionPredicates(HMI, Features);
384 
385  EncodeSingleInstruction(HMI, OS, Fixups, STI, parseBits(Last, HMB, HMI));
386  State.Extended = HexagonMCInstrInfo::isImmext(HMI);
387  State.Addend += HEXAGON_INSTR_SIZE;
388  ++State.Index;
389  }
390 }
391 
392 static bool RegisterMatches(unsigned Consumer, unsigned Producer,
393  unsigned Producer2) {
394  return (Consumer == Producer) || (Consumer == Producer2) ||
396  Consumer);
397 }
398 
399 /// EncodeSingleInstruction - Emit a single
402  const MCSubtargetInfo &STI, uint32_t Parse) const {
404  uint64_t Binary;
405 
406  // Pseudo instructions don't get encoded and shouldn't be here
407  // in the first place!
409  "pseudo-instruction found");
410  LLVM_DEBUG(dbgs() << "Encoding insn `"
411  << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
412 
413  Binary = getBinaryCodeForInstr(MI, Fixups, STI);
414  unsigned Opc = MI.getOpcode();
415 
416  // Check for unimplemented instructions. Immediate extenders
417  // are encoded as zero, so they need to be accounted for.
418  if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) {
419  LLVM_DEBUG(dbgs() << "Unimplemented inst `"
420  << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
421  llvm_unreachable("Unimplemented Instruction");
422  }
423  Binary |= Parse;
424 
425  // if we need to emit a duplexed instruction
426  if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
428  "Emitting duplex without duplex parse bits");
429  unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
430  // 29 is the bit position.
431  // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
432  // Last bit is moved to bit position 13
433  Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13);
434 
435  const MCInst *Sub0 = MI.getOperand(0).getInst();
436  const MCInst *Sub1 = MI.getOperand(1).getInst();
437 
438  // Get subinstruction slot 0.
439  unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI);
440  // Get subinstruction slot 1.
441  State.SubInst1 = true;
442  unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI);
443  State.SubInst1 = false;
444 
445  Binary |= SubBits0 | (SubBits1 << 16);
446  }
447  support::endian::write<uint32_t>(OS, Binary, support::little);
448  ++MCNumEmitted;
449 }
450 
451 [[noreturn]] static void raise_relocation_error(unsigned Width, unsigned Kind) {
452  std::string Text;
453  raw_string_ostream Stream(Text);
454  Stream << "Unrecognized relocation combination: width=" << Width
455  << " kind=" << Kind;
456  report_fatal_error(Stream.str());
457 }
458 
459 /// Some insns are not extended and thus have no bits. These cases require
460 /// a more brute force method for determining the correct relocation.
461 Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
462  MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
463  const MCSymbolRefExpr::VariantKind VarKind) const {
464  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
465  unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI);
466  using namespace Hexagon;
467 
468  if (InsnType == HexagonII::TypeEXTENDER) {
469  if (VarKind == MCSymbolRefExpr::VK_None) {
470  auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
471  for (auto I = Instrs.begin(), N = Instrs.end(); I != N; ++I) {
472  if (I->getInst() != &MI)
473  continue;
474  assert(I+1 != N && "Extender cannot be last in packet");
475  const MCInst &NextI = *(I+1)->getInst();
476  const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI);
477  if (NextD.isBranch() || NextD.isCall() ||
480  return fixup_Hexagon_32_6_X;
481  }
482  }
483 
484  static const std::map<unsigned,unsigned> Relocs = {
496  };
497 
498  auto F = Relocs.find(VarKind);
499  if (F != Relocs.end())
500  return Hexagon::Fixups(F->second);
501  raise_relocation_error(0, VarKind);
502  }
503 
504  if (MCID.isBranch())
506 
507  static const std::map<unsigned,unsigned> RelocsLo = {
517  };
518 
519  static const std::map<unsigned,unsigned> RelocsHi = {
529  };
530 
531  switch (MCID.getOpcode()) {
532  case Hexagon::LO:
533  case Hexagon::A2_tfril: {
534  auto F = RelocsLo.find(VarKind);
535  if (F != RelocsLo.end())
536  return Hexagon::Fixups(F->second);
537  break;
538  }
539  case Hexagon::HI:
540  case Hexagon::A2_tfrih: {
541  auto F = RelocsHi.find(VarKind);
542  if (F != RelocsHi.end())
543  return Hexagon::Fixups(F->second);
544  break;
545  }
546  }
547 
548  raise_relocation_error(0, VarKind);
549 }
550 
551 static bool isPCRel(unsigned Kind) {
552  switch (Kind){
571  return true;
572  default:
573  return false;
574  }
575 }
576 
577 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
578  const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
579  const MCSubtargetInfo &STI) const {
580  if (isa<HexagonMCExpr>(ME))
581  ME = &HexagonMCInstrInfo::getExpr(*ME);
582  int64_t Value;
583  if (ME->evaluateAsAbsolute(Value)) {
584  bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) ||
586  // Only sub-instruction #1 can be extended in a duplex. If MI is a
587  // sub-instruction #0, it is not extended even if Extended is true
588  // (it can be true for the duplex as a whole).
589  bool IsSub0 = HexagonMCInstrInfo::isSubInstruction(MI) && !State.SubInst1;
590  if (State.Extended && InstExtendable && !IsSub0) {
591  unsigned OpIdx = ~0u;
592  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
593  if (&MO != &MI.getOperand(I))
594  continue;
595  OpIdx = I;
596  break;
597  }
598  assert(OpIdx != ~0u);
599  if (OpIdx == HexagonMCInstrInfo::getExtendableOp(MCII, MI)) {
601  Value = (Value & 0x3f) << Shift;
602  }
603  }
604  return Value;
605  }
606  assert(ME->getKind() == MCExpr::SymbolRef ||
607  ME->getKind() == MCExpr::Binary);
608  if (ME->getKind() == MCExpr::Binary) {
609  MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
610  getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
611  getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
612  return 0;
613  }
614 
615  unsigned FixupKind = fixup_Invalid;
616  const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
617  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
618  unsigned FixupWidth = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
620  MCSymbolRefExpr::VariantKind VarKind = MCSRE->getKind();
621  unsigned Opc = MCID.getOpcode();
622  unsigned IType = HexagonMCInstrInfo::getType(MCII, MI);
623 
624  LLVM_DEBUG(dbgs() << "----------------------------------------\n"
625  << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
626  << "\nOpcode: " << Opc << "\nRelocation bits: "
627  << FixupWidth << "\nAddend: " << State.Addend
628  << "\nVariant: " << unsigned(VarKind)
629  << "\n----------------------------------------\n");
630 
631  // Pick the applicable fixup kind for the symbol.
632  // Handle special cases first, the rest will be looked up in the tables.
633 
634  if (FixupWidth == 16 && !State.Extended) {
635  if (VarKind == MCSymbolRefExpr::VK_None) {
637  // A2_iconst.
639  } else {
640  // Look for GP-relative fixups.
642  static const Hexagon::Fixups GPRelFixups[] = {
645  };
646  assert(Shift < array_lengthof(GPRelFixups));
647  auto UsesGP = [] (const MCInstrDesc &D) {
648  for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U)
649  if (*U == Hexagon::GP)
650  return true;
651  return false;
652  };
653  if (UsesGP(MCID))
654  FixupKind = GPRelFixups[Shift];
655  }
656  } else if (VarKind == MCSymbolRefExpr::VK_GOTREL) {
657  // Select between LO/HI.
658  if (Opc == Hexagon::LO)
660  else if (Opc == Hexagon::HI)
662  }
663  } else {
664  bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR;
665  switch (FixupWidth) {
666  case 9:
667  if (BranchOrCR)
670  break;
671  case 8:
672  case 7:
673  if (State.Extended && VarKind == MCSymbolRefExpr::VK_GOT)
677  else if (FixupWidth == 7 && BranchOrCR)
680  break;
681  case 0:
682  FixupKind = getFixupNoBits(MCII, MI, MO, VarKind);
683  break;
684  }
685  }
686 
687  if (FixupKind == fixup_Invalid) {
688  const auto &FixupTable = State.Extended ? ExtFixups : StdFixups;
689 
690  auto FindVK = FixupTable.find(VarKind);
691  if (FindVK != FixupTable.end())
692  FixupKind = FindVK->second[FixupWidth];
693  }
694 
695  if (FixupKind == fixup_Invalid)
696  raise_relocation_error(FixupWidth, VarKind);
697 
698  const MCExpr *FixupExpr = MO.getExpr();
699  if (State.Addend != 0 && isPCRel(FixupKind)) {
700  const MCExpr *C = MCConstantExpr::create(State.Addend, MCT);
701  FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
702  }
703 
704  MCFixup Fixup = MCFixup::create(State.Addend, FixupExpr,
705  MCFixupKind(FixupKind), MI.getLoc());
706  Fixups.push_back(Fixup);
707  // All of the information is in the fixup.
708  return 0;
709 }
710 
711 unsigned
714  MCSubtargetInfo const &STI) const {
715 #ifndef NDEBUG
716  size_t OperandNumber = ~0U;
717  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
718  if (&MI.getOperand(i) == &MO) {
719  OperandNumber = i;
720  break;
721  }
722  assert((OperandNumber != ~0U) && "Operand not found");
723 #endif
724 
725  if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
727  // Calculate the new value distance to the associated producer
728  unsigned SOffset = 0;
729  unsigned VOffset = 0;
730  unsigned UseReg = MO.getReg();
731  unsigned DefReg1 = Hexagon::NoRegister;
732  unsigned DefReg2 = Hexagon::NoRegister;
733 
734  auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
735  const MCOperand *I = Instrs.begin() + State.Index - 1;
736 
737  for (;; --I) {
738  assert(I != Instrs.begin() - 1 && "Couldn't find producer");
739  MCInst const &Inst = *I->getInst();
741  continue;
742 
743  DefReg1 = Hexagon::NoRegister;
744  DefReg2 = Hexagon::NoRegister;
745  ++SOffset;
746  if (HexagonMCInstrInfo::isVector(MCII, Inst)) {
747  // Vector instructions don't count scalars.
748  ++VOffset;
749  }
750  if (HexagonMCInstrInfo::hasNewValue(MCII, Inst))
751  DefReg1 = HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg();
752  if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst))
753  DefReg2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg();
754  if (!RegisterMatches(UseReg, DefReg1, DefReg2)) {
755  // This isn't the register we're looking for
756  continue;
757  }
758  if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
759  // Producer is unpredicated
760  break;
761  }
763  "Unpredicated consumer depending on predicated producer");
764  if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
766  // Producer predicate sense matched ours.
767  break;
768  }
769  // Hexagon PRM 10.11 Construct Nt from distance
770  unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset
771  : SOffset;
772  Offset <<= 1;
773  Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2);
774  return Offset;
775  }
776 
777  assert(!MO.isImm());
778  if (MO.isReg()) {
779  unsigned Reg = MO.getReg();
783  return MCT.getRegisterInfo()->getEncodingValue(Reg);
784  }
785 
786  return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
787 }
788 
790  MCRegisterInfo const &MRI,
791  MCContext &MCT) {
792  return new HexagonMCCodeEmitter(MII, MCT);
793 }
794 
795 #define ENABLE_INSTR_PREDICATE_VERIFIER
796 #include "HexagonGenMCCodeEmitter.inc"
llvm::HexagonII::INST_PARSE_PACKET_END
@ INST_PARSE_PACKET_END
Definition: HexagonBaseInfo.h:243
llvm::MCSymbolRefExpr::getKind
VariantKind getKind() const
Definition: MCExpr.h:400
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
llvm::Hexagon::fixup_Hexagon_DTPREL_LO16
@ fixup_Hexagon_DTPREL_LO16
Definition: HexagonFixupKinds.h:62
llvm::AArch64CC::LO
@ LO
Definition: AArch64BaseInfo.h:258
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:221
llvm::Hexagon::fixup_Hexagon_TPREL_HI16
@ fixup_Hexagon_TPREL_HI16
Definition: HexagonFixupKinds.h:85
llvm::Hexagon::fixup_Hexagon_B22_PCREL
@ fixup_Hexagon_B22_PCREL
Definition: HexagonFixupKinds.h:18
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::AArch64CC::HI
@ HI
Definition: AArch64BaseInfo.h:263
llvm::Hexagon::fixup_Hexagon_6_PCREL_X
@ fixup_Hexagon_6_PCREL_X
Definition: HexagonFixupKinds.h:88
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:248
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
ExtFixups
static const std::map< unsigned, std::vector< unsigned > > ExtFixups
Definition: HexagonMCCodeEmitter.cpp:49
llvm::Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X
@ fixup_Hexagon_LD_PLT_B22_PCREL_X
Definition: HexagonFixupKinds.h:116
llvm::FixupKind
static Lanai::Fixups FixupKind(const MCExpr *Expr)
Definition: LanaiMCCodeEmitter.cpp:90
llvm::Hexagon::fixup_Hexagon_B32_PCREL_X
@ fixup_Hexagon_B32_PCREL_X
Definition: HexagonFixupKinds.h:33
llvm::MCSymbolRefExpr::VK_GOT
@ VK_GOT
Definition: MCExpr.h:198
llvm::MCSymbolRefExpr::VK_Hexagon_LD_PLT
@ VK_Hexagon_LD_PLT
Definition: MCExpr.h:323
llvm::Hexagon::fixup_Hexagon_GD_GOT_LO16
@ fixup_Hexagon_GD_GOT_LO16
Definition: HexagonFixupKinds.h:68
llvm::Hexagon::fixup_Hexagon_GD_GOT_32_6_X
@ fixup_Hexagon_GD_GOT_32_6_X
Definition: HexagonFixupKinds.h:98
llvm::HexagonII::TypeCR
@ TypeCR
Definition: HexagonDepITypes.h:23
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:298
MCInstrDesc.h
llvm::createHexagonMCCodeEmitter
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
Definition: HexagonMCCodeEmitter.cpp:789
llvm::HexagonMCInstrInfo::getDuplexRegisterNumbering
unsigned getDuplexRegisterNumbering(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:253
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Hexagon::fixup_Hexagon_DTPREL_32_6_X
@ fixup_Hexagon_DTPREL_32_6_X
Definition: HexagonFixupKinds.h:95
llvm::HexagonMCCodeEmitter::getMachineOpValue
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
Definition: HexagonMCCodeEmitter.cpp:712
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:625
RegisterMatches
static bool RegisterMatches(unsigned Consumer, unsigned Producer, unsigned Producer2)
Definition: HexagonMCCodeEmitter.cpp:392
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
isPCRel
static bool isPCRel(unsigned Kind)
Definition: HexagonMCCodeEmitter.cpp:551
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:33
llvm::Hexagon::fixup_Hexagon_IE_GOT_HI16
@ fixup_Hexagon_IE_GOT_HI16
Definition: HexagonFixupKinds.h:81
Statistic.h
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
ErrorHandling.h
llvm::HexagonII::TypeEXTENDER
@ TypeEXTENDER
Definition: HexagonDepITypes.h:52
llvm::MCSymbolRefExpr::VK_Hexagon_GD_PLT
@ VK_Hexagon_GD_PLT
Definition: MCExpr.h:322
llvm::MCSymbolRefExpr::VK_GOTREL
@ VK_GOTREL
Definition: MCExpr.h:200
llvm::Hexagon::fixup_Hexagon_B9_PCREL_X
@ fixup_Hexagon_B9_PCREL_X
Definition: HexagonFixupKinds.h:38
llvm::Hexagon::fixup_Hexagon_GPREL16_0
@ fixup_Hexagon_GPREL16_0
Definition: HexagonFixupKinds.h:26
llvm::Hexagon::fixup_Hexagon_LO16
@ fixup_Hexagon_LO16
Definition: HexagonFixupKinds.h:21
Shift
bool Shift
Definition: README.txt:468
llvm::Hexagon::fixup_Hexagon_B13_PCREL_X
@ fixup_Hexagon_B13_PCREL_X
Definition: HexagonFixupKinds.h:37
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:327
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:635
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::HexagonMCInstrInfo::isSubInstruction
bool isSubInstruction(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:794
llvm::Hexagon::fixup_Hexagon_LD_GOT_LO16
@ fixup_Hexagon_LD_GOT_LO16
Definition: HexagonFixupKinds.h:72
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Hexagon::fixup_Hexagon_GOTREL_32_6_X
@ fixup_Hexagon_GOTREL_32_6_X
Definition: HexagonFixupKinds.h:89
llvm::Hexagon::Fixups
Fixups
Definition: HexagonFixupKinds.h:16
llvm::msgpack::Type::Binary
@ Binary
llvm::MCBinaryExpr
Binary assembler expressions.
Definition: MCExpr.h:480
llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT
@ VK_Hexagon_GD_GOT
Definition: MCExpr.h:320
llvm::Hexagon::fixup_Hexagon_DTPREL_HI16
@ fixup_Hexagon_DTPREL_HI16
Definition: HexagonFixupKinds.h:63
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
HexagonBaseInfo.h
HexagonFixupKinds.h
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::Hexagon::fixup_Hexagon_GPREL16_3
@ fixup_Hexagon_GPREL16_3
Definition: HexagonFixupKinds.h:29
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::Hexagon::fixup_Hexagon_IE_GOT_32_6_X
@ fixup_Hexagon_IE_GOT_32_6_X
Definition: HexagonFixupKinds.h:106
llvm::Hexagon::fixup_Hexagon_TPREL_LO16
@ fixup_Hexagon_TPREL_LO16
Definition: HexagonFixupKinds.h:84
llvm::HexagonMCInstrInfo::isPredicatedTrue
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:741
llvm::HexagonMCInstrInfo::s27_2_reloc
bool s27_2_reloc(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:895
llvm::Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL
@ fixup_Hexagon_GD_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:66
llvm::Hexagon::fixup_Hexagon_IE_HI16
@ fixup_Hexagon_IE_HI16
Definition: HexagonFixupKinds.h:77
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
HexagonMCInstrInfo.h
llvm::support::little
@ little
Definition: Endian.h:27
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:513
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:655
llvm::HexagonMCInstrInfo::isPredicated
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:718
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MCSymbolRefExpr::VK_Hexagon_LO16
@ VK_Hexagon_LO16
Definition: MCExpr.h:317
llvm::HexagonII::INST_PARSE_DUPLEX
@ INST_PARSE_DUPLEX
Definition: HexagonBaseInfo.h:246
MCContext.h
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:854
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:532
MCInstrInfo.h
llvm::MCSymbolRefExpr::VK_DTPREL
@ VK_DTPREL
Definition: MCExpr.h:357
llvm::Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X
@ fixup_Hexagon_LD_PLT_B32_PCREL_X
Definition: HexagonFixupKinds.h:117
MCInst.h
llvm::HexagonMCInstrInfo::getName
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:367
HexagonMCExpr.h
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::HexagonMCCodeEmitter
Definition: HexagonMCCodeEmitter.h:34
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:333
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::HexagonMCCodeEmitter::encodeInstruction
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
Definition: HexagonMCCodeEmitter.cpp:367
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
StdFixups
static const std::map< unsigned, std::vector< unsigned > > StdFixups
Definition: HexagonMCCodeEmitter.cpp:173
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition: HexagonMCInstrInfo.cpp:506
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1394
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MCExpr::Binary
@ Binary
Binary expressions.
Definition: MCExpr.h:38
llvm::Hexagon::fixup_Hexagon_GOT_HI16
@ fixup_Hexagon_GOT_HI16
Definition: HexagonFixupKinds.h:58
llvm::Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X
@ fixup_Hexagon_GD_PLT_B22_PCREL_X
Definition: HexagonFixupKinds.h:114
llvm::Hexagon::fixup_Hexagon_GPREL16_1
@ fixup_Hexagon_GPREL16_1
Definition: HexagonFixupKinds.h:27
llvm::Hexagon::fixup_Hexagon_B15_PCREL_X
@ fixup_Hexagon_B15_PCREL_X
Definition: HexagonFixupKinds.h:36
llvm::Hexagon::fixup_Hexagon_LD_GOT_HI16
@ fixup_Hexagon_LD_GOT_HI16
Definition: HexagonFixupKinds.h:73
HexagonMCCodeEmitter.h
llvm::MCSymbolRefExpr::VK_Hexagon_HI16
@ VK_Hexagon_HI16
Definition: MCExpr.h:318
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
uint64_t
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:279
llvm::Hexagon::fixup_Hexagon_IE_32_6_X
@ fixup_Hexagon_IE_32_6_X
Definition: HexagonFixupKinds.h:104
llvm::HexagonMCInstrInfo::SubregisterBit
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
Definition: HexagonMCInstrInfo.cpp:1008
UseReg
static Register UseReg(const MachineOperand &MO)
Definition: HexagonCopyToCombine.cpp:259
llvm::Hexagon::fixup_Hexagon_TPREL_32_6_X
@ fixup_Hexagon_TPREL_32_6_X
Definition: HexagonFixupKinds.h:109
llvm::MCSymbolRefExpr::VK_PLT
@ VK_PLT
Definition: MCExpr.h:207
llvm::Hexagon::fixup_Hexagon_GOT_LO16
@ fixup_Hexagon_GOT_LO16
Definition: HexagonFixupKinds.h:57
llvm::Hexagon::fixup_Hexagon_GOTREL_HI16
@ fixup_Hexagon_GOTREL_HI16
Definition: HexagonFixupKinds.h:55
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
MCRegisterInfo.h
llvm::Hexagon::fixup_Hexagon_GOT_32_6_X
@ fixup_Hexagon_GOT_32_6_X
Definition: HexagonFixupKinds.h:92
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:609
llvm::MCSymbolRefExpr::VK_PCREL
@ VK_PCREL
Definition: MCExpr.h:201
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Hexagon::fixup_Hexagon_GOTREL_LO16
@ fixup_Hexagon_GOTREL_LO16
Definition: HexagonFixupKinds.h:54
llvm::Hexagon::fixup_Hexagon_B9_PCREL
@ fixup_Hexagon_B9_PCREL
Definition: HexagonFixupKinds.h:32
P
#define P(x)
Definition: HexagonMCCodeEmitter.cpp:48
llvm::Hexagon::fixup_Hexagon_GD_GOT_HI16
@ fixup_Hexagon_GD_GOT_HI16
Definition: HexagonFixupKinds.h:69
llvm::Hexagon::fixup_Hexagon_B7_PCREL
@ fixup_Hexagon_B7_PCREL
Definition: HexagonFixupKinds.h:20
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
_
#define _
Definition: HexagonMCCodeEmitter.cpp:47
llvm::HexagonMCInstrInfo::isOuterLoop
bool isOuterLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:673
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:524
fixup_Invalid
static const unsigned fixup_Invalid
Definition: HexagonMCCodeEmitter.cpp:45
llvm::HexagonMCInstrInfo::isExtentSigned
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:339
llvm::Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL
@ fixup_Hexagon_LD_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:67
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:235
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
uint32_t
MCFixup.h
llvm::Hexagon::fixup_Hexagon_IE_LO16
@ fixup_Hexagon_IE_LO16
Definition: HexagonFixupKinds.h:76
Compiler.h
llvm::Hexagon::fixup_Hexagon_32_6_X
@ fixup_Hexagon_32_6_X
Definition: HexagonFixupKinds.h:34
llvm::HexagonMCInstrInfo::getNewValueOperand
const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:378
llvm::HexagonII::TypeCJ
@ TypeCJ
Definition: HexagonDepITypes.h:22
llvm::HexagonMCCodeEmitter::EncodeSingleInstruction
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
EncodeSingleInstruction - Emit a single.
Definition: HexagonMCCodeEmitter.cpp:400
llvm::X86II::isPseudo
bool isPseudo(uint64_t TSFlags)
Definition: X86BaseInfo.h:974
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:309
llvm::Hexagon::fixup_Hexagon_GPREL16_2
@ fixup_Hexagon_GPREL16_2
Definition: HexagonFixupKinds.h:28
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X
@ fixup_Hexagon_GD_PLT_B32_PCREL_X
Definition: HexagonFixupKinds.h:115
llvm::HexagonMCInstrInfo::getNewValueOperand2
const MCOperand & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:404
raise_relocation_error
static void raise_relocation_error(unsigned Width, unsigned Kind)
Definition: HexagonMCCodeEmitter.cpp:451
llvm::MCSymbolRefExpr::VK_TPREL
@ VK_TPREL
Definition: MCExpr.h:356
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
EndianStream.h
llvm::Hexagon::fixup_Hexagon_B22_PCREL_X
@ fixup_Hexagon_B22_PCREL_X
Definition: HexagonFixupKinds.h:35
llvm::HexagonMCInstrInfo::getType
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:416
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::Hexagon::fixup_Hexagon_B7_PCREL_X
@ fixup_Hexagon_B7_PCREL_X
Definition: HexagonFixupKinds.h:39
llvm::Hexagon::fixup_Hexagon_32_PCREL
@ fixup_Hexagon_32_PCREL
Definition: HexagonFixupKinds.h:48
Casting.h
llvm::HexagonII::INST_PARSE_NOT_END
@ INST_PARSE_NOT_END
Definition: HexagonBaseInfo.h:245
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT
@ VK_Hexagon_IE_GOT
Definition: MCExpr.h:325
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::Hexagon::fixup_Hexagon_GOT_16_X
@ fixup_Hexagon_GOT_16_X
Definition: HexagonFixupKinds.h:93
llvm::HexagonMCInstrInfo::IsSingleConsumerRefPairProducer
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
Definition: HexagonMCInstrInfo.cpp:705
llvm::Hexagon::fixup_Hexagon_PLT_B22_PCREL
@ fixup_Hexagon_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:53
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
llvm::Hexagon::fixup_Hexagon_LD_GOT_32_6_X
@ fixup_Hexagon_LD_GOT_32_6_X
Definition: HexagonFixupKinds.h:101
llvm::MCSymbolRefExpr::VK_Hexagon_GPREL
@ VK_Hexagon_GPREL
Definition: MCExpr.h:319
llvm::Hexagon::fixup_Hexagon_HI16
@ fixup_Hexagon_HI16
Definition: HexagonFixupKinds.h:22
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::Hexagon::fixup_Hexagon_GOT_11_X
@ fixup_Hexagon_GOT_11_X
Definition: HexagonFixupKinds.h:94
llvm::Hexagon::fixup_Hexagon_B15_PCREL
@ fixup_Hexagon_B15_PCREL
Definition: HexagonFixupKinds.h:19
llvm::Hexagon::fixup_Hexagon_IE_GOT_LO16
@ fixup_Hexagon_IE_GOT_LO16
Definition: HexagonFixupKinds.h:80
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
N
#define N
llvm::HexagonII::INST_PARSE_LOOP_END
@ INST_PARSE_LOOP_END
Definition: HexagonBaseInfo.h:244
llvm::HexagonMCInstrInfo::getExpr
const MCExpr & getExpr(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:303
llvm::Hexagon::fixup_Hexagon_B13_PCREL
@ fixup_Hexagon_B13_PCREL
Definition: HexagonFixupKinds.h:31
llvm::Hexagon::fixup_Hexagon_27_REG
@ fixup_Hexagon_27_REG
Definition: HexagonFixupKinds.h:113
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:619
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
raw_ostream.h
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
Endian.h
llvm::MCSymbolRefExpr::VK_Hexagon_IE
@ VK_Hexagon_IE
Definition: MCExpr.h:324
llvm::raw_string_ostream::str
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:643
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT
@ VK_Hexagon_LD_GOT
Definition: MCExpr.h:321
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:613
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::HexagonMCInstrInfo::isInnerLoop
bool isInnerLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:639