LLVM 22.0.0git
HexagonMCCodeEmitter.cpp
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1//===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonMCCodeEmitter.h"
10#include "MCTargetDesc/HexagonBaseInfo.h"
11#include "MCTargetDesc/HexagonFixupKinds.h"
12#include "MCTargetDesc/HexagonMCExpr.h"
13#include "MCTargetDesc/HexagonMCInstrInfo.h"
14#include "MCTargetDesc/HexagonMCTargetDesc.h"
15#include "llvm/ADT/Statistic.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCFixup.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrDesc.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/Casting.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/EndianStream.h"
28#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/raw_ostream.h"
30#include <cassert>
31#include <cstddef>
32#include <cstdint>
33#include <map>
34#include <string>
35#include <vector>
36
37#define DEBUG_TYPE "mccodeemitter"
38
39using namespace llvm;
40using namespace Hexagon;
41
42STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
43
44static const unsigned fixup_Invalid = ~0u;
45
46// clang-format off
47#define _ fixup_Invalid
48#define P(x) Hexagon::fixup_Hexagon##x
49static const std::map<unsigned, std::vector<unsigned>> ExtFixups = {
50 { HexagonMCExpr::VK_DTPREL,
51 { _, _, _, _,
52 _, _, P(_DTPREL_16_X), P(_DTPREL_11_X),
53 P(_DTPREL_11_X), P(_9_X), _, P(_DTPREL_11_X),
54 P(_DTPREL_16_X), _, _, _,
55 P(_DTPREL_16_X), _, _, _,
56 _, _, _, _,
57 _, _, _, _,
58 _, _, _, _,
59 P(_DTPREL_32_6_X) }},
60 { HexagonMCExpr::VK_GOT,
61 { _, _, _, _,
62 _, _, P(_GOT_11_X), _ /* [1] */,
63 _ /* [1] */, P(_9_X), _, P(_GOT_11_X),
64 P(_GOT_16_X), _, _, _,
65 P(_GOT_16_X), _, _, _,
66 _, _, _, _,
67 _, _, _, _,
68 _, _, _, _,
69 P(_GOT_32_6_X) }},
70 { HexagonMCExpr::VK_GOTREL,
71 { _, _, _, _,
72 _, _, P(_GOTREL_11_X), P(_GOTREL_11_X),
73 P(_GOTREL_11_X), P(_9_X), _, P(_GOTREL_11_X),
74 P(_GOTREL_16_X), _, _, _,
75 P(_GOTREL_16_X), _, _, _,
76 _, _, _, _,
77 _, _, _, _,
78 _, _, _, _,
79 P(_GOTREL_32_6_X) }},
80 { HexagonMCExpr::VK_TPREL,
81 { _, _, _, _,
82 _, _, P(_TPREL_16_X), P(_TPREL_11_X),
83 P(_TPREL_11_X), P(_9_X), _, P(_TPREL_11_X),
84 P(_TPREL_16_X), _, _, _,
85 P(_TPREL_16_X), _, _, _,
86 _, _, _, _,
87 _, _, _, _,
88 _, _, _, _,
89 P(_TPREL_32_6_X) }},
90 { HexagonMCExpr::VK_GD_GOT,
91 { _, _, _, _,
92 _, _, P(_GD_GOT_16_X), P(_GD_GOT_11_X),
93 P(_GD_GOT_11_X), P(_9_X), _, P(_GD_GOT_11_X),
94 P(_GD_GOT_16_X), _, _, _,
95 P(_GD_GOT_16_X), _, _, _,
96 _, _, _, _,
97 _, _, _, _,
98 _, _, _, _,
99 P(_GD_GOT_32_6_X) }},
100 { HexagonMCExpr::VK_GD_PLT,
101 { _, _, _, _,
102 _, _, _, _,
103 _, P(_9_X), _, P(_GD_PLT_B22_PCREL_X),
104 _, _, _, _,
105 _, _, _, _,
106 _, _, P(_GD_PLT_B22_PCREL_X), _,
107 _, _, _, _,
108 _, _, _, _,
109 _ }},
110 { HexagonMCExpr::VK_IE,
111 { _, _, _, _,
112 _, _, P(_IE_16_X), _,
113 _, P(_9_X), _, _,
114 P(_IE_16_X), _, _, _,
115 P(_IE_16_X), _, _, _,
116 _, _, _, _,
117 _, _, _, _,
118 _, _, _, _,
119 P(_IE_32_6_X) }},
120 { HexagonMCExpr::VK_IE_GOT,
121 { _, _, _, _,
122 _, _, P(_IE_GOT_11_X), P(_IE_GOT_11_X),
123 P(_IE_GOT_11_X), P(_9_X), _, P(_IE_GOT_11_X),
124 P(_IE_GOT_16_X), _, _, _,
125 P(_IE_GOT_16_X), _, _, _,
126 _, _, _, _,
127 _, _, _, _,
128 _, _, _, _,
129 P(_IE_GOT_32_6_X) }},
130 { HexagonMCExpr::VK_LD_GOT,
131 { _, _, _, _,
132 _, _, P(_LD_GOT_11_X), P(_LD_GOT_11_X),
133 P(_LD_GOT_11_X), P(_9_X), _, P(_LD_GOT_11_X),
134 P(_LD_GOT_16_X), _, _, _,
135 P(_LD_GOT_16_X), _, _, _,
136 _, _, _, _,
137 _, _, _, _,
138 _, _, _, _,
139 P(_LD_GOT_32_6_X) }},
140 { HexagonMCExpr::VK_LD_PLT,
141 { _, _, _, _,
142 _, _, _, _,
143 _, P(_9_X), _, P(_LD_PLT_B22_PCREL_X),
144 _, _, _, _,
145 _, _, _, _,
146 _, _, P(_LD_PLT_B22_PCREL_X), _,
147 _, _, _, _,
148 _, _, _, _,
149 _ }},
150 { HexagonMCExpr::VK_PCREL,
151 { _, _, _, _,
152 _, _, P(_6_PCREL_X), _,
153 _, P(_9_X), _, _,
154 _, _, _, _,
155 _, _, _, _,
156 _, _, _, _,
157 _, _, _, _,
158 _, _, _, _,
159 P(_32_PCREL) }},
160 { HexagonMCExpr::VK_None,
161 { _, _, _, _,
162 _, _, P(_6_X), P(_8_X),
163 P(_8_X), P(_9_X), P(_10_X), P(_11_X),
164 P(_12_X), P(_B13_PCREL), _, P(_B15_PCREL_X),
165 P(_16_X), _, _, _,
166 _, _, P(_B22_PCREL_X), _,
167 _, _, _, _,
168 _, _, _, _,
169 P(_32_6_X) }},
170};
171// [1] The fixup is GOT_16_X for signed values and GOT_11_X for unsigned.
172
173static const std::map<unsigned, std::vector<unsigned>> StdFixups = {
174 { HexagonMCExpr::VK_DTPREL,
175 { _, _, _, _,
176 _, _, _, _,
177 _, _, _, _,
178 _, _, _, _,
179 P(_DTPREL_16), _, _, _,
180 _, _, _, _,
181 _, _, _, _,
182 _, _, _, _,
183 P(_DTPREL_32) }},
184 { HexagonMCExpr::VK_GOT,
185 { _, _, _, _,
186 _, _, _, _,
187 _, _, _, _,
188 _, _, _, _,
189 _, _, _, _,
190 _, _, _, _,
191 _, _, _, _,
192 _, _, _, _,
193 P(_GOT_32) }},
194 { HexagonMCExpr::VK_GOTREL,
195 { _, _, _, _,
196 _, _, _, _,
197 _, _, _, _,
198 _, _, _, _,
199 _ /* [2] */, _, _, _,
200 _, _, _, _,
201 _, _, _, _,
202 _, _, _, _,
203 P(_GOTREL_32) }},
204 { HexagonMCExpr::VK_PLT,
205 { _, _, _, _,
206 _, _, _, _,
207 _, _, _, _,
208 _, _, _, _,
209 _, _, _, _,
210 _, _, P(_PLT_B22_PCREL), _,
211 _, _, _, _,
212 _, _, _, _,
213 _ }},
214 { HexagonMCExpr::VK_TPREL,
215 { _, _, _, _,
216 _, _, _, _,
217 _, _, _, P(_TPREL_11_X),
218 _, _, _, _,
219 P(_TPREL_16), _, _, _,
220 _, _, _, _,
221 _, _, _, _,
222 _, _, _, _,
223 P(_TPREL_32) }},
224 { HexagonMCExpr::VK_GD_GOT,
225 { _, _, _, _,
226 _, _, _, _,
227 _, _, _, _,
228 _, _, _, _,
229 P(_GD_GOT_16), _, _, _,
230 _, _, _, _,
231 _, _, _, _,
232 _, _, _, _,
233 P(_GD_GOT_32) }},
234 { HexagonMCExpr::VK_GD_PLT,
235 { _, _, _, _,
236 _, _, _, _,
237 _, _, _, _,
238 _, _, _, _,
239 _, _, _, _,
240 _, _, P(_GD_PLT_B22_PCREL), _,
241 _, _, _, _,
242 _, _, _, _,
243 _ }},
244 { HexagonMCExpr::VK_GPREL,
245 { _, _, _, _,
246 _, _, _, _,
247 _, _, _, _,
248 _, _, _, _,
249 P(_GPREL16_0), _, _, _,
250 _, _, _, _,
251 _, _, _, _,
252 _, _, _, _,
253 _ }},
254 { HexagonMCExpr::VK_HI16,
255 { _, _, _, _,
256 _, _, _, _,
257 _, _, _, _,
258 _, _, _, _,
259 P(_HI16), _, _, _,
260 _, _, _, _,
261 _, _, _, _,
262 _, _, _, _,
263 _ }},
264 { HexagonMCExpr::VK_IE,
265 { _, _, _, _,
266 _, _, _, _,
267 _, _, _, _,
268 _, _, _, _,
269 _, _, _, _,
270 _, _, _, _,
271 _, _, _, _,
272 _, _, _, _,
273 P(_IE_32) }},
274 { HexagonMCExpr::VK_IE_GOT,
275 { _, _, _, _,
276 _, _, _, _,
277 _, _, _, _,
278 _, _, _, _,
279 P(_IE_GOT_16), _, _, _,
280 _, _, _, _,
281 _, _, _, _,
282 _, _, _, _,
283 P(_IE_GOT_32) }},
284 { HexagonMCExpr::VK_LD_GOT,
285 { _, _, _, _,
286 _, _, _, _,
287 _, _, _, _,
288 _, _, _, _,
289 P(_LD_GOT_16), _, _, _,
290 _, _, _, _,
291 _, _, _, _,
292 _, _, _, _,
293 P(_LD_GOT_32) }},
294 { HexagonMCExpr::VK_LD_PLT,
295 { _, _, _, _,
296 _, _, _, _,
297 _, _, _, _,
298 _, _, _, _,
299 _, _, _, _,
300 _, _, P(_LD_PLT_B22_PCREL), _,
301 _, _, _, _,
302 _, _, _, _,
303 _ }},
304 { HexagonMCExpr::VK_LO16,
305 { _, _, _, _,
306 _, _, _, _,
307 _, _, _, _,
308 _, _, _, _,
309 P(_LO16), _, _, _,
310 _, _, _, _,
311 _, _, _, _,
312 _, _, _, _,
313 _ }},
314 { HexagonMCExpr::VK_PCREL,
315 { _, _, _, _,
316 _, _, _, _,
317 _, _, _, _,
318 _, _, _, _,
319 _, _, _, _,
320 _, _, _, _,
321 _, _, _, _,
322 _, _, _, _,
323 P(_32_PCREL) }},
324 { HexagonMCExpr::VK_None,
325 { _, _, _, _,
326 _, _, _, _,
327 _, _, _, _,
328 _, P(_B13_PCREL), _, P(_B15_PCREL),
329 _, _, _, _,
330 _, _, P(_B22_PCREL), _,
331 _, _, _, _,
332 _, _, _, _,
333 P(_32) }},
334};
335// clang-format on
336// [2] The actual fixup is LO16 or HI16, depending on the instruction.
337#undef P
338#undef _
339
340static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
341 const MCExpr *Value, uint16_t Kind) {
342 bool PCRel = false;
343 switch (Kind) {
344 case Hexagon::fixup_Hexagon_B22_PCREL:
345 case Hexagon::fixup_Hexagon_B15_PCREL:
346 case Hexagon::fixup_Hexagon_B7_PCREL:
347 case Hexagon::fixup_Hexagon_B13_PCREL:
348 case Hexagon::fixup_Hexagon_B9_PCREL:
349 case Hexagon::fixup_Hexagon_B32_PCREL_X:
350 case Hexagon::fixup_Hexagon_B22_PCREL_X:
351 case Hexagon::fixup_Hexagon_B15_PCREL_X:
352 case Hexagon::fixup_Hexagon_B13_PCREL_X:
353 case Hexagon::fixup_Hexagon_B9_PCREL_X:
354 case Hexagon::fixup_Hexagon_B7_PCREL_X:
355 case Hexagon::fixup_Hexagon_32_PCREL:
356 case Hexagon::fixup_Hexagon_PLT_B22_PCREL:
357 case Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL:
358 case Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL:
359 case Hexagon::fixup_Hexagon_6_PCREL_X:
360 case Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X:
361 case Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X:
362 case Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X:
363 case Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X:
364 PCRel = true;
365 }
366 Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
367}
368
369uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
370 MCInst const &MCI) const {
371 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
372 if (State.Index == 0) {
373 if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
374 assert(!Duplex);
375 assert(State.Index != Last);
376 return HexagonII::INST_PARSE_LOOP_END;
377 }
378 }
379 if (State.Index == 1) {
380 if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
381 assert(!Duplex);
382 assert(State.Index != Last);
383 return HexagonII::INST_PARSE_LOOP_END;
384 }
385 }
386 if (Duplex) {
387 assert(State.Index == Last);
388 return HexagonII::INST_PARSE_DUPLEX;
389 }
390 if (State.Index == Last)
391 return HexagonII::INST_PARSE_PACKET_END;
392 return HexagonII::INST_PARSE_NOT_END;
393}
394
395/// Emit the bundle.
396void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI,
397 SmallVectorImpl<char> &CB,
398 SmallVectorImpl<MCFixup> &Fixups,
399 const MCSubtargetInfo &STI) const {
400 MCInst &HMB = const_cast<MCInst &>(MI);
401
402 assert(HexagonMCInstrInfo::isBundle(HMB));
403 LLVM_DEBUG(dbgs() << "Encoding bundle\n";);
404 State.Addend = 0;
405 State.Extended = false;
406 State.Bundle = &MI;
407 State.Index = 0;
408 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
409
410 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
411 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
412
413 encodeSingleInstruction(HMI, CB, Fixups, STI, parseBits(Last, HMB, HMI));
414 State.Extended = HexagonMCInstrInfo::isImmext(HMI);
415 State.Addend += HEXAGON_INSTR_SIZE;
416 ++State.Index;
417 }
418}
419
420static bool RegisterMatches(MCRegister Consumer, MCRegister Producer,
421 MCRegister Producer2) {
422 return (Consumer == Producer) || (Consumer == Producer2) ||
423 HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(Producer,
424 Consumer);
425}
426
427void HexagonMCCodeEmitter::encodeSingleInstruction(
428 const MCInst &MI, SmallVectorImpl<char> &CB,
429 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI,
430 uint32_t Parse) const {
431 assert(!HexagonMCInstrInfo::isBundle(MI));
432 uint64_t Binary;
433
434 // Pseudo instructions don't get encoded and shouldn't be here
435 // in the first place!
436 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() &&
437 "pseudo-instruction found");
438 LLVM_DEBUG(dbgs() << "Encoding insn `"
439 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
440
441 Binary = getBinaryCodeForInstr(MI, Fixups, STI);
442 unsigned Opc = MI.getOpcode();
443
444 // Check for unimplemented instructions. Immediate extenders
445 // are encoded as zero, so they need to be accounted for.
446 if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) {
447 LLVM_DEBUG(dbgs() << "Unimplemented inst `"
448 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
449 llvm_unreachable("Unimplemented Instruction");
450 }
451 Binary |= Parse;
452
453 // if we need to emit a duplexed instruction
454 if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
455 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
456 "Emitting duplex without duplex parse bits");
457 unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
458 // 29 is the bit position.
459 // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
460 // Last bit is moved to bit position 13
461 Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13);
462
463 const MCInst *Sub0 = MI.getOperand(0).getInst();
464 const MCInst *Sub1 = MI.getOperand(1).getInst();
465
466 // Get subinstruction slot 0.
467 unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI);
468 // Get subinstruction slot 1.
469 State.SubInst1 = true;
470 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI);
471 State.SubInst1 = false;
472
473 Binary |= SubBits0 | (SubBits1 << 16);
474 }
475 support::endian::write<uint32_t>(CB, Binary, llvm::endianness::little);
476 ++MCNumEmitted;
477}
478
479[[noreturn]] static void raise_relocation_error(unsigned Width, unsigned Kind) {
480 std::string Text;
481 raw_string_ostream Stream(Text);
482 Stream << "Unrecognized relocation combination: width=" << Width
483 << " kind=" << Kind;
484 report_fatal_error(Twine(Stream.str()));
485}
486
487/// Some insns are not extended and thus have no bits. These cases require
488/// a more brute force method for determining the correct relocation.
489Hexagon::Fixups
490HexagonMCCodeEmitter::getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
491 const MCOperand &MO,
492 HexagonMCExpr::VariantKind VarKind) const {
493 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
494 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI);
495 using namespace Hexagon;
496
497 if (InsnType == HexagonII::TypeEXTENDER) {
498 if (VarKind == HexagonMCExpr::VK_None) {
499 auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
500 for (auto I = Instrs.begin(), N = Instrs.end(); I != N; ++I) {
501 if (I->getInst() != &MI)
502 continue;
503 assert(I+1 != N && "Extender cannot be last in packet");
504 const MCInst &NextI = *(I+1)->getInst();
505 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI);
506 if (NextD.isBranch() || NextD.isCall() ||
507 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR)
508 return fixup_Hexagon_B32_PCREL_X;
509 return fixup_Hexagon_32_6_X;
510 }
511 }
512
513 static const std::map<unsigned, unsigned> Relocs = {
514 {HexagonMCExpr::VK_GOTREL, fixup_Hexagon_GOTREL_32_6_X},
515 {HexagonMCExpr::VK_GOT, fixup_Hexagon_GOT_32_6_X},
516 {HexagonMCExpr::VK_TPREL, fixup_Hexagon_TPREL_32_6_X},
517 {HexagonMCExpr::VK_DTPREL, fixup_Hexagon_DTPREL_32_6_X},
518 {HexagonMCExpr::VK_GD_GOT, fixup_Hexagon_GD_GOT_32_6_X},
519 {HexagonMCExpr::VK_LD_GOT, fixup_Hexagon_LD_GOT_32_6_X},
520 {HexagonMCExpr::VK_IE, fixup_Hexagon_IE_32_6_X},
521 {HexagonMCExpr::VK_IE_GOT, fixup_Hexagon_IE_GOT_32_6_X},
522 {HexagonMCExpr::VK_PCREL, fixup_Hexagon_B32_PCREL_X},
523 {HexagonMCExpr::VK_GD_PLT, fixup_Hexagon_GD_PLT_B32_PCREL_X},
524 {HexagonMCExpr::VK_LD_PLT, fixup_Hexagon_LD_PLT_B32_PCREL_X},
525 };
526
527 auto F = Relocs.find(VarKind);
528 if (F != Relocs.end())
529 return Hexagon::Fixups(F->second);
530 raise_relocation_error(0, VarKind);
531 }
532
533 if (MCID.isBranch())
534 return fixup_Hexagon_B13_PCREL;
535
536 static const std::map<unsigned, unsigned> RelocsLo = {
537 {HexagonMCExpr::VK_GOT, fixup_Hexagon_GOT_LO16},
538 {HexagonMCExpr::VK_GOTREL, fixup_Hexagon_GOTREL_LO16},
539 {HexagonMCExpr::VK_GD_GOT, fixup_Hexagon_GD_GOT_LO16},
540 {HexagonMCExpr::VK_LD_GOT, fixup_Hexagon_LD_GOT_LO16},
541 {HexagonMCExpr::VK_IE, fixup_Hexagon_IE_LO16},
542 {HexagonMCExpr::VK_IE_GOT, fixup_Hexagon_IE_GOT_LO16},
543 {HexagonMCExpr::VK_TPREL, fixup_Hexagon_TPREL_LO16},
544 {HexagonMCExpr::VK_DTPREL, fixup_Hexagon_DTPREL_LO16},
545 {HexagonMCExpr::VK_None, fixup_Hexagon_LO16},
546 };
547
548 static const std::map<unsigned, unsigned> RelocsHi = {
549 {HexagonMCExpr::VK_GOT, fixup_Hexagon_GOT_HI16},
550 {HexagonMCExpr::VK_GOTREL, fixup_Hexagon_GOTREL_HI16},
551 {HexagonMCExpr::VK_GD_GOT, fixup_Hexagon_GD_GOT_HI16},
552 {HexagonMCExpr::VK_LD_GOT, fixup_Hexagon_LD_GOT_HI16},
553 {HexagonMCExpr::VK_IE, fixup_Hexagon_IE_HI16},
554 {HexagonMCExpr::VK_IE_GOT, fixup_Hexagon_IE_GOT_HI16},
555 {HexagonMCExpr::VK_TPREL, fixup_Hexagon_TPREL_HI16},
556 {HexagonMCExpr::VK_DTPREL, fixup_Hexagon_DTPREL_HI16},
557 {HexagonMCExpr::VK_None, fixup_Hexagon_HI16},
558 };
559
560 switch (MCID.getOpcode()) {
561 case Hexagon::LO:
562 case Hexagon::A2_tfril: {
563 auto F = RelocsLo.find(VarKind);
564 if (F != RelocsLo.end())
565 return Hexagon::Fixups(F->second);
566 break;
567 }
568 case Hexagon::HI:
569 case Hexagon::A2_tfrih: {
570 auto F = RelocsHi.find(VarKind);
571 if (F != RelocsHi.end())
572 return Hexagon::Fixups(F->second);
573 break;
574 }
575 }
576
577 raise_relocation_error(0, VarKind);
578}
579
580static bool isPCRel(unsigned Kind) {
581 switch (Kind){
582 case fixup_Hexagon_B22_PCREL:
583 case fixup_Hexagon_B15_PCREL:
584 case fixup_Hexagon_B7_PCREL:
585 case fixup_Hexagon_B13_PCREL:
586 case fixup_Hexagon_B9_PCREL:
587 case fixup_Hexagon_B32_PCREL_X:
588 case fixup_Hexagon_B22_PCREL_X:
589 case fixup_Hexagon_B15_PCREL_X:
590 case fixup_Hexagon_B13_PCREL_X:
591 case fixup_Hexagon_B9_PCREL_X:
592 case fixup_Hexagon_B7_PCREL_X:
593 case fixup_Hexagon_32_PCREL:
594 case fixup_Hexagon_PLT_B22_PCREL:
595 case fixup_Hexagon_GD_PLT_B22_PCREL:
596 case fixup_Hexagon_LD_PLT_B22_PCREL:
597 case fixup_Hexagon_GD_PLT_B22_PCREL_X:
598 case fixup_Hexagon_LD_PLT_B22_PCREL_X:
599 case fixup_Hexagon_6_PCREL_X:
600 return true;
601 default:
602 return false;
603 }
604}
605
606unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
607 const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
608 const MCSubtargetInfo &STI) const {
609 if (isa<HexagonMCExpr>(ME))
610 ME = &HexagonMCInstrInfo::getExpr(*ME);
611 int64_t Value;
612 if (ME->evaluateAsAbsolute(Value)) {
613 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) ||
614 HexagonMCInstrInfo::isExtended(MCII, MI);
615 // Only sub-instruction #1 can be extended in a duplex. If MI is a
616 // sub-instruction #0, it is not extended even if Extended is true
617 // (it can be true for the duplex as a whole).
618 bool IsSub0 = HexagonMCInstrInfo::isSubInstruction(MI) && !State.SubInst1;
619 if (State.Extended && InstExtendable && !IsSub0) {
620 unsigned OpIdx = ~0u;
621 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
622 if (&MO != &MI.getOperand(I))
623 continue;
624 OpIdx = I;
625 break;
626 }
627 assert(OpIdx != ~0u);
628 if (OpIdx == HexagonMCInstrInfo::getExtendableOp(MCII, MI)) {
629 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
630 Value = (Value & 0x3f) << Shift;
631 }
632 }
633 return Value;
634 }
635 assert(ME->getKind() == MCExpr::SymbolRef ||
636 ME->getKind() == MCExpr::Binary);
637 if (ME->getKind() == MCExpr::Binary) {
638 MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
639 getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
640 getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
641 return 0;
642 }
643
644 unsigned FixupKind = fixup_Invalid;
645 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
646 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
647 unsigned FixupWidth = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
648 HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
649 auto VarKind = HexagonMCExpr::VariantKind(MCSRE->getSpecifier());
650 unsigned Opc = MCID.getOpcode();
651 unsigned IType = HexagonMCInstrInfo::getType(MCII, MI);
652
653 LLVM_DEBUG(dbgs() << "----------------------------------------\n"
654 << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
655 << "\nOpcode: " << Opc << "\nRelocation bits: "
656 << FixupWidth << "\nAddend: " << State.Addend
657 << "\nVariant: " << unsigned(VarKind)
658 << "\n----------------------------------------\n");
659
660 // Pick the applicable fixup kind for the symbol.
661 // Handle special cases first, the rest will be looked up in the tables.
662
663 if (FixupWidth == 16 && !State.Extended) {
664 if (VarKind == HexagonMCExpr::VK_None) {
665 if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr())) {
666 // A2_iconst.
667 FixupKind = Hexagon::fixup_Hexagon_27_REG;
668 } else {
669 // Look for GP-relative fixups.
670 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
671 static const Hexagon::Fixups GPRelFixups[] = {
672 Hexagon::fixup_Hexagon_GPREL16_0, Hexagon::fixup_Hexagon_GPREL16_1,
673 Hexagon::fixup_Hexagon_GPREL16_2, Hexagon::fixup_Hexagon_GPREL16_3
674 };
675 assert(Shift < std::size(GPRelFixups));
676 auto UsesGP = [](const MCInstrDesc &D) {
677 return is_contained(D.implicit_uses(), Hexagon::GP);
678 };
679 if (UsesGP(MCID))
680 FixupKind = GPRelFixups[Shift];
681 }
682 } else if (VarKind == HexagonMCExpr::VK_GOTREL) {
683 // Select between LO/HI.
684 if (Opc == Hexagon::LO)
685 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
686 else if (Opc == Hexagon::HI)
687 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
688 }
689 } else {
690 bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR;
691 switch (FixupWidth) {
692 case 9:
693 if (BranchOrCR)
694 FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
695 : Hexagon::fixup_Hexagon_B9_PCREL;
696 break;
697 case 8:
698 case 7:
699 if (State.Extended && VarKind == HexagonMCExpr::VK_GOT)
700 FixupKind = HexagonMCInstrInfo::isExtentSigned(MCII, MI)
701 ? Hexagon::fixup_Hexagon_GOT_16_X
702 : Hexagon::fixup_Hexagon_GOT_11_X;
703 else if (FixupWidth == 7 && BranchOrCR)
704 FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
705 : Hexagon::fixup_Hexagon_B7_PCREL;
706 break;
707 case 0:
708 FixupKind = getFixupNoBits(MCII, MI, MO, VarKind);
709 break;
710 }
711 }
712
713 if (FixupKind == fixup_Invalid) {
714 const auto &FixupTable = State.Extended ? ExtFixups : StdFixups;
715
716 auto FindVK = FixupTable.find(VarKind);
717 if (FindVK != FixupTable.end())
718 FixupKind = FindVK->second[FixupWidth];
719 }
720
721 if (FixupKind == fixup_Invalid)
722 raise_relocation_error(FixupWidth, VarKind);
723
724 const MCExpr *FixupExpr = MO.getExpr();
725 if (State.Addend != 0 && isPCRel(FixupKind)) {
726 const MCExpr *C = MCConstantExpr::create(State.Addend, MCT);
727 FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
728 }
729
730 addFixup(Fixups, State.Addend, FixupExpr, FixupKind);
731 return 0;
732}
733
734unsigned
735HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
736 SmallVectorImpl<MCFixup> &Fixups,
737 MCSubtargetInfo const &STI) const {
738 size_t OperandNumber = ~0U;
739 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
740 if (&MI.getOperand(i) == &MO) {
741 OperandNumber = i;
742 break;
743 }
744 assert((OperandNumber != ~0U) && "Operand not found");
745
746 if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
747 &MO == &HexagonMCInstrInfo::getNewValueOperand(MCII, MI)) {
748 // Calculate the new value distance to the associated producer
749 unsigned SOffset = 0;
750 unsigned VOffset = 0;
751 MCRegister UseReg = MO.getReg();
752 MCRegister DefReg1;
753 MCRegister DefReg2;
754
755 auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
756 const MCOperand *I = Instrs.begin() + State.Index - 1;
757
758 for (;; --I) {
759 assert(I != Instrs.begin() - 1 && "Couldn't find producer");
760 MCInst const &Inst = *I->getInst();
761 if (HexagonMCInstrInfo::isImmext(Inst))
762 continue;
763
764 DefReg1 = MCRegister();
765 DefReg2 = MCRegister();
766 ++SOffset;
767 if (HexagonMCInstrInfo::isVector(MCII, Inst)) {
768 // Vector instructions don't count scalars.
769 ++VOffset;
770 }
771 if (HexagonMCInstrInfo::hasNewValue(MCII, Inst))
772 DefReg1 = HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg();
773 if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst))
774 DefReg2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg();
775 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) {
776 // This isn't the register we're looking for
777 continue;
778 }
779 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
780 // Producer is unpredicated
781 break;
782 }
783 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
784 "Unpredicated consumer depending on predicated producer");
785 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
786 HexagonMCInstrInfo::isPredicatedTrue(MCII, MI))
787 // Producer predicate sense matched ours.
788 break;
789 }
790 // Hexagon PRM 10.11 Construct Nt from distance
791 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset
792 : SOffset;
793 Offset <<= 1;
794 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2);
795 return Offset;
796 }
797
798 assert(!MO.isImm());
799 if (MO.isReg()) {
800 MCRegister Reg = MO.getReg();
801 switch (HexagonMCInstrInfo::getDesc(MCII, MI)
802 .operands()[OperandNumber]
803 .RegClass) {
804 case GeneralSubRegsRegClassID:
805 case GeneralDoubleLow8RegsRegClassID:
806 return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
807 default:
808 break;
809 }
810 return MCT.getRegisterInfo()->getEncodingValue(Reg);
811 }
812
813 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
814}
815
816MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
817 MCContext &MCT) {
818 return new HexagonMCCodeEmitter(MII, MCT);
819}
820
821#include "HexagonGenMCCodeEmitter.inc"
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
UseReg
static Register UseReg(const MachineOperand &MO)
Definition: HexagonCopyToCombine.cpp:245
ExtFixups
static const std::map< unsigned, std::vector< unsigned > > ExtFixups
Definition: HexagonMCCodeEmitter.cpp:49
P
#define P(x)
Definition: HexagonMCCodeEmitter.cpp:48
RegisterMatches
static bool RegisterMatches(MCRegister Consumer, MCRegister Producer, MCRegister Producer2)
Definition: HexagonMCCodeEmitter.cpp:420
fixup_Invalid
static const unsigned fixup_Invalid
Definition: HexagonMCCodeEmitter.cpp:44
raise_relocation_error
static void raise_relocation_error(unsigned Width, unsigned Kind)
Definition: HexagonMCCodeEmitter.cpp:479
addFixup
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)
Definition: HexagonMCCodeEmitter.cpp:340
isPCRel
static bool isPCRel(unsigned Kind)
Definition: HexagonMCCodeEmitter.cpp:580
StdFixups
static const std::map< unsigned, std::vector< unsigned > > StdFixups
Definition: HexagonMCCodeEmitter.cpp:173
_
#define _
Definition: HexagonMCCodeEmitter.cpp:47
HexagonMCCodeEmitter.h
Definition for classes that emit Hexagon machine code from MCInsts.
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:32
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
F
#define F(x, y, z)
Definition: MD5.cpp:55
I
#define I(x, y, z)
Definition: MD5.cpp:58
OpIdx
MachineInstr unsigned OpIdx
Definition: NVPTXPrologEpilogPass.cpp:56
Statistic.h
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
STATISTIC
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition: Debug.h:119
llvm::HexagonMCCodeEmitter::encodeSingleInstruction
void encodeSingleInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
Definition: HexagonMCCodeEmitter.cpp:427
llvm::HexagonMCCodeEmitter::getMachineOpValue
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
Definition: HexagonMCCodeEmitter.cpp:735
llvm::HexagonMCCodeEmitter::getBinaryCodeForInstr
uint64_t getBinaryCodeForInstr(MCInst const &MI, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
llvm::HexagonMCCodeEmitter::encodeInstruction
void encodeInstruction(MCInst const &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
Definition: HexagonMCCodeEmitter.cpp:396
llvm::MCBinaryExpr
Binary assembler expressions.
Definition: MCExpr.h:299
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.h:343
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
llvm::MCConstantExpr::create
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:212
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:414
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:43
llvm::MCExpr::Binary
@ Binary
Binary expressions.
Definition: MCExpr.h:41
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:85
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)
Consider bit fields if we need more flags.
Definition: MCFixup.h:86
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:188
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:199
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:308
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:289
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:231
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:40
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:66
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:73
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:118
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister Reg) const
Returns the encoding for Reg.
Definition: MCRegisterInfo.h:477
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:190
llvm::MCSymbolRefExpr::getSpecifier
uint16_t getSpecifier() const
Definition: MCExpr.h:233
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:574
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:82
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:662
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:680
uint16_t
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:164
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::HexagonMCInstrInfo::isExtentSigned
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:346
llvm::HexagonMCInstrInfo::isOuterLoop
bool isOuterLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:688
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:624
llvm::HexagonMCInstrInfo::IsSingleConsumerRefPairProducer
bool IsSingleConsumerRefPairProducer(MCRegister Producer, MCRegister Consumer)
Definition: HexagonMCInstrInfo.cpp:720
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:340
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:670
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:316
llvm::HexagonMCInstrInfo::getDesc
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:539
llvm::HexagonMCInstrInfo::getExpr
MCExpr const & getExpr(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:310
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:628
llvm::HexagonMCInstrInfo::getType
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:423
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:650
llvm::HexagonMCInstrInfo::getNewValueOperand
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:385
llvm::HexagonMCInstrInfo::isPredicated
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:733
llvm::HexagonMCInstrInfo::SubregisterBit
unsigned SubregisterBit(MCRegister Consumer, MCRegister Producer, MCRegister Producer2)
Definition: HexagonMCInstrInfo.cpp:1034
llvm::HexagonMCInstrInfo::s27_2_reloc
bool s27_2_reloc(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:910
llvm::HexagonMCInstrInfo::isInnerLoop
bool isInnerLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:654
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:520
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:334
llvm::HexagonMCInstrInfo::getName
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:374
llvm::HexagonMCInstrInfo::isPredicatedTrue
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:756
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:869
llvm::HexagonMCInstrInfo::isSubInstruction
bool isSubInstruction(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:809
llvm::HexagonMCInstrInfo::getNewValueOperand2
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:411
llvm::HexagonMCInstrInfo::getDuplexRegisterNumbering
unsigned getDuplexRegisterNumbering(MCRegister Reg)
Definition: HexagonMCInstrInfo.cpp:260
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:634
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition: HexagonMCInstrInfo.cpp:513
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:477
llvm::createHexagonMCCodeEmitter
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)
Definition: HexagonMCCodeEmitter.cpp:816
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:207
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition: Error.cpp:167
llvm::addFixup
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)
Definition: AVRMCCodeEmitter.cpp:38
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1916
raw_ostream.h
N
#define N
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