LLVM  9.0.0svn
HexagonMCCodeEmitter.cpp
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1 //===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixup.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Casting.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Endian.h"
31 #include <cassert>
32 #include <cstddef>
33 #include <cstdint>
34 #include <map>
35 #include <string>
36 #include <vector>
37 
38 #define DEBUG_TYPE "mccodeemitter"
39 
40 using namespace llvm;
41 using namespace Hexagon;
42 
43 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
44 
45 static const unsigned fixup_Invalid = ~0u;
46 
47 #define _ fixup_Invalid
48 #define P(x) Hexagon::fixup_Hexagon##x
49 static const std::map<unsigned, std::vector<unsigned>> ExtFixups = {
51  { _, _, _, _,
52  _, _, P(_DTPREL_16_X), P(_DTPREL_11_X),
53  P(_DTPREL_11_X), P(_9_X), _, P(_DTPREL_11_X),
54  P(_DTPREL_16_X), _, _, _,
55  P(_DTPREL_16_X), _, _, _,
56  _, _, _, _,
57  _, _, _, _,
58  _, _, _, _,
59  P(_DTPREL_32_6_X) }},
61  { _, _, _, _,
62  _, _, P(_GOT_11_X), _ /* [1] */,
63  _ /* [1] */, P(_9_X), _, P(_GOT_11_X),
64  P(_GOT_16_X), _, _, _,
65  P(_GOT_16_X), _, _, _,
66  _, _, _, _,
67  _, _, _, _,
68  _, _, _, _,
69  P(_GOT_32_6_X) }},
71  { _, _, _, _,
72  _, _, P(_GOTREL_11_X), P(_GOTREL_11_X),
73  P(_GOTREL_11_X), P(_9_X), _, P(_GOTREL_11_X),
74  P(_GOTREL_16_X), _, _, _,
75  P(_GOTREL_16_X), _, _, _,
76  _, _, _, _,
77  _, _, _, _,
78  _, _, _, _,
79  P(_GOTREL_32_6_X) }},
81  { _, _, _, _,
82  _, _, P(_TPREL_16_X), P(_TPREL_11_X),
83  P(_TPREL_11_X), P(_9_X), _, P(_TPREL_11_X),
84  P(_TPREL_16_X), _, _, _,
85  P(_TPREL_16_X), _, _, _,
86  _, _, _, _,
87  _, _, _, _,
88  _, _, _, _,
89  P(_TPREL_32_6_X) }},
91  { _, _, _, _,
92  _, _, P(_GD_GOT_16_X), P(_GD_GOT_11_X),
93  P(_GD_GOT_11_X), P(_9_X), _, P(_GD_GOT_11_X),
94  P(_GD_GOT_16_X), _, _, _,
95  P(_GD_GOT_16_X), _, _, _,
96  _, _, _, _,
97  _, _, _, _,
98  _, _, _, _,
99  P(_GD_GOT_32_6_X) }},
101  { _, _, _, _,
102  _, _, _, _,
103  _, P(_9_X), _, P(_GD_PLT_B22_PCREL_X),
104  _, _, _, _,
105  _, _, _, _,
106  _, _, P(_GD_PLT_B22_PCREL_X), _,
107  _, _, _, _,
108  _, _, _, _,
109  _ }},
111  { _, _, _, _,
112  _, _, P(_IE_16_X), _,
113  _, P(_9_X), _, _,
114  P(_IE_16_X), _, _, _,
115  P(_IE_16_X), _, _, _,
116  _, _, _, _,
117  _, _, _, _,
118  _, _, _, _,
119  P(_IE_32_6_X) }},
121  { _, _, _, _,
122  _, _, P(_IE_GOT_11_X), P(_IE_GOT_11_X),
123  P(_IE_GOT_11_X), P(_9_X), _, P(_IE_GOT_11_X),
124  P(_IE_GOT_16_X), _, _, _,
125  P(_IE_GOT_16_X), _, _, _,
126  _, _, _, _,
127  _, _, _, _,
128  _, _, _, _,
129  P(_IE_GOT_32_6_X) }},
131  { _, _, _, _,
132  _, _, P(_LD_GOT_11_X), P(_LD_GOT_11_X),
133  P(_LD_GOT_11_X), P(_9_X), _, P(_LD_GOT_11_X),
134  P(_LD_GOT_16_X), _, _, _,
135  P(_LD_GOT_16_X), _, _, _,
136  _, _, _, _,
137  _, _, _, _,
138  _, _, _, _,
139  P(_LD_GOT_32_6_X) }},
141  { _, _, _, _,
142  _, _, _, _,
143  _, P(_9_X), _, P(_LD_PLT_B22_PCREL_X),
144  _, _, _, _,
145  _, _, _, _,
146  _, _, P(_LD_PLT_B22_PCREL_X), _,
147  _, _, _, _,
148  _, _, _, _,
149  _ }},
151  { _, _, _, _,
152  _, _, P(_6_PCREL_X), _,
153  _, P(_9_X), _, _,
154  _, _, _, _,
155  _, _, _, _,
156  _, _, _, _,
157  _, _, _, _,
158  _, _, _, _,
159  P(_32_PCREL) }},
161  { _, _, _, _,
162  _, _, P(_6_X), P(_8_X),
163  P(_8_X), P(_9_X), P(_10_X), P(_11_X),
164  P(_12_X), P(_B13_PCREL), _, P(_B15_PCREL_X),
165  P(_16_X), _, _, _,
166  _, _, P(_B22_PCREL_X), _,
167  _, _, _, _,
168  _, _, _, _,
169  P(_32_6_X) }},
170 };
171 // [1] The fixup is GOT_16_X for signed values and GOT_11_X for unsigned.
172 
173 static const std::map<unsigned, std::vector<unsigned>> StdFixups = {
175  { _, _, _, _,
176  _, _, _, _,
177  _, _, _, _,
178  _, _, _, _,
179  P(_DTPREL_16), _, _, _,
180  _, _, _, _,
181  _, _, _, _,
182  _, _, _, _,
183  P(_DTPREL_32) }},
185  { _, _, _, _,
186  _, _, _, _,
187  _, _, _, _,
188  _, _, _, _,
189  _, _, _, _,
190  _, _, _, _,
191  _, _, _, _,
192  _, _, _, _,
193  P(_GOT_32) }},
195  { _, _, _, _,
196  _, _, _, _,
197  _, _, _, _,
198  _, _, _, _,
199  _ /* [2] */, _, _, _,
200  _, _, _, _,
201  _, _, _, _,
202  _, _, _, _,
203  P(_GOTREL_32) }},
205  { _, _, _, _,
206  _, _, _, _,
207  _, _, _, _,
208  _, _, _, _,
209  _, _, _, _,
210  _, _, P(_PLT_B22_PCREL), _,
211  _, _, _, _,
212  _, _, _, _,
213  _ }},
215  { _, _, _, _,
216  _, _, _, _,
217  _, _, _, P(_TPREL_11_X),
218  _, _, _, _,
219  P(_TPREL_16), _, _, _,
220  _, _, _, _,
221  _, _, _, _,
222  _, _, _, _,
223  P(_TPREL_32) }},
225  { _, _, _, _,
226  _, _, _, _,
227  _, _, _, _,
228  _, _, _, _,
229  P(_GD_GOT_16), _, _, _,
230  _, _, _, _,
231  _, _, _, _,
232  _, _, _, _,
233  P(_GD_GOT_32) }},
235  { _, _, _, _,
236  _, _, _, _,
237  _, _, _, _,
238  _, _, _, _,
239  _, _, _, _,
240  _, _, P(_GD_PLT_B22_PCREL), _,
241  _, _, _, _,
242  _, _, _, _,
243  _ }},
245  { _, _, _, _,
246  _, _, _, _,
247  _, _, _, _,
248  _, _, _, _,
249  P(_GPREL16_0), _, _, _,
250  _, _, _, _,
251  _, _, _, _,
252  _, _, _, _,
253  _ }},
255  { _, _, _, _,
256  _, _, _, _,
257  _, _, _, _,
258  _, _, _, _,
259  P(_HI16), _, _, _,
260  _, _, _, _,
261  _, _, _, _,
262  _, _, _, _,
263  _ }},
265  { _, _, _, _,
266  _, _, _, _,
267  _, _, _, _,
268  _, _, _, _,
269  _, _, _, _,
270  _, _, _, _,
271  _, _, _, _,
272  _, _, _, _,
273  P(_IE_32) }},
275  { _, _, _, _,
276  _, _, _, _,
277  _, _, _, _,
278  _, _, _, _,
279  P(_IE_GOT_16), _, _, _,
280  _, _, _, _,
281  _, _, _, _,
282  _, _, _, _,
283  P(_IE_GOT_32) }},
285  { _, _, _, _,
286  _, _, _, _,
287  _, _, _, _,
288  _, _, _, _,
289  P(_LD_GOT_16), _, _, _,
290  _, _, _, _,
291  _, _, _, _,
292  _, _, _, _,
293  P(_LD_GOT_32) }},
295  { _, _, _, _,
296  _, _, _, _,
297  _, _, _, _,
298  _, _, _, _,
299  _, _, _, _,
300  _, _, P(_LD_PLT_B22_PCREL), _,
301  _, _, _, _,
302  _, _, _, _,
303  _ }},
305  { _, _, _, _,
306  _, _, _, _,
307  _, _, _, _,
308  _, _, _, _,
309  P(_LO16), _, _, _,
310  _, _, _, _,
311  _, _, _, _,
312  _, _, _, _,
313  _ }},
315  { _, _, _, _,
316  _, _, _, _,
317  _, _, _, _,
318  _, _, _, _,
319  _, _, _, _,
320  _, _, _, _,
321  _, _, _, _,
322  _, _, _, _,
323  P(_32_PCREL) }},
325  { _, _, _, _,
326  _, _, _, _,
327  _, _, _, _,
328  _, P(_B13_PCREL), _, P(_B15_PCREL),
329  _, _, _, _,
330  _, _, P(_B22_PCREL), _,
331  _, _, _, _,
332  _, _, _, _,
333  P(_32) }},
334 };
335 //
336 // [2] The actual fixup is LO16 or HI16, depending on the instruction.
337 #undef P
338 #undef _
339 
340 uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
341  MCInst const &MCI) const {
342  bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
343  if (State.Index == 0) {
345  assert(!Duplex);
346  assert(State.Index != Last);
348  }
349  }
350  if (State.Index == 1) {
352  assert(!Duplex);
353  assert(State.Index != Last);
355  }
356  }
357  if (Duplex) {
358  assert(State.Index == Last);
360  }
361  if (State.Index == Last)
364 }
365 
366 /// Emit the bundle.
369  const MCSubtargetInfo &STI) const {
370  MCInst &HMB = const_cast<MCInst &>(MI);
371 
373  LLVM_DEBUG(dbgs() << "Encoding bundle\n";);
374  State.Addend = 0;
375  State.Extended = false;
376  State.Bundle = &MI;
377  State.Index = 0;
378  size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
379  FeatureBitset Features = computeAvailableFeatures(STI.getFeatureBits());
380 
381  for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
382  MCInst &HMI = const_cast<MCInst &>(*I.getInst());
383  verifyInstructionPredicates(HMI, Features);
384 
385  EncodeSingleInstruction(HMI, OS, Fixups, STI, parseBits(Last, HMB, HMI));
386  State.Extended = HexagonMCInstrInfo::isImmext(HMI);
387  State.Addend += HEXAGON_INSTR_SIZE;
388  ++State.Index;
389  }
390 }
391 
392 static bool RegisterMatches(unsigned Consumer, unsigned Producer,
393  unsigned Producer2) {
394  if (Consumer == Producer)
395  return true;
396  if (Consumer == Producer2)
397  return true;
398  // Calculate if we're a single vector consumer referencing a double producer
399  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
400  if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
401  return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
402  return false;
403 }
404 
405 /// EncodeSingleInstruction - Emit a single
408  const MCSubtargetInfo &STI, uint32_t Parse) const {
410  uint64_t Binary;
411 
412  // Pseudo instructions don't get encoded and shouldn't be here
413  // in the first place!
414  assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() &&
415  "pseudo-instruction found");
416  LLVM_DEBUG(dbgs() << "Encoding insn `"
417  << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
418 
419  Binary = getBinaryCodeForInstr(MI, Fixups, STI);
420  unsigned Opc = MI.getOpcode();
421 
422  // Check for unimplemented instructions. Immediate extenders
423  // are encoded as zero, so they need to be accounted for.
424  if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) {
425  LLVM_DEBUG(dbgs() << "Unimplemented inst `"
426  << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
427  llvm_unreachable("Unimplemented Instruction");
428  }
429  Binary |= Parse;
430 
431  // if we need to emit a duplexed instruction
432  if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
434  "Emitting duplex without duplex parse bits");
435  unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
436  // 29 is the bit position.
437  // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
438  // Last bit is moved to bit position 13
439  Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13);
440 
441  const MCInst *Sub0 = MI.getOperand(0).getInst();
442  const MCInst *Sub1 = MI.getOperand(1).getInst();
443 
444  // Get subinstruction slot 0.
445  unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI);
446  // Get subinstruction slot 1.
447  State.SubInst1 = true;
448  unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI);
449  State.SubInst1 = false;
450 
451  Binary |= SubBits0 | (SubBits1 << 16);
452  }
453  support::endian::write<uint32_t>(OS, Binary, support::little);
454  ++MCNumEmitted;
455 }
456 
458 static void raise_relocation_error(unsigned Width, unsigned Kind) {
459  std::string Text;
460  raw_string_ostream Stream(Text);
461  Stream << "Unrecognized relocation combination: width=" << Width
462  << " kind=" << Kind;
463  report_fatal_error(Stream.str());
464 }
465 
466 /// Some insns are not extended and thus have no bits. These cases require
467 /// a more brute force method for determining the correct relocation.
468 Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
469  MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
470  const MCSymbolRefExpr::VariantKind VarKind) const {
471  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
472  unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI);
473  using namespace Hexagon;
474 
475  if (InsnType == HexagonII::TypeEXTENDER) {
476  if (VarKind == MCSymbolRefExpr::VK_None) {
477  auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
478  for (auto I = Instrs.begin(), N = Instrs.end(); I != N; ++I) {
479  if (I->getInst() != &MI)
480  continue;
481  assert(I+1 != N && "Extender cannot be last in packet");
482  const MCInst &NextI = *(I+1)->getInst();
483  const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI);
484  if (NextD.isBranch() || NextD.isCall() ||
487  return fixup_Hexagon_32_6_X;
488  }
489  }
490 
491  static const std::map<unsigned,unsigned> Relocs = {
503  };
504 
505  auto F = Relocs.find(VarKind);
506  if (F != Relocs.end())
507  return Hexagon::Fixups(F->second);
508  raise_relocation_error(0, VarKind);
509  }
510 
511  if (MCID.isBranch())
513 
514  static const std::map<unsigned,unsigned> RelocsLo = {
524  };
525 
526  static const std::map<unsigned,unsigned> RelocsHi = {
536  };
537 
538  switch (MCID.getOpcode()) {
539  case Hexagon::LO:
540  case Hexagon::A2_tfril: {
541  auto F = RelocsLo.find(VarKind);
542  if (F != RelocsLo.end())
543  return Hexagon::Fixups(F->second);
544  break;
545  }
546  case Hexagon::HI:
547  case Hexagon::A2_tfrih: {
548  auto F = RelocsHi.find(VarKind);
549  if (F != RelocsHi.end())
550  return Hexagon::Fixups(F->second);
551  break;
552  }
553  }
554 
555  raise_relocation_error(0, VarKind);
556 }
557 
558 static bool isPCRel(unsigned Kind) {
559  switch (Kind){
578  return true;
579  default:
580  return false;
581  }
582 }
583 
584 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
585  const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
586  const MCSubtargetInfo &STI) const {
587  if (isa<HexagonMCExpr>(ME))
588  ME = &HexagonMCInstrInfo::getExpr(*ME);
589  int64_t Value;
590  if (ME->evaluateAsAbsolute(Value)) {
591  bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) ||
593  // Only sub-instruction #1 can be extended in a duplex. If MI is a
594  // sub-instruction #0, it is not extended even if Extended is true
595  // (it can be true for the duplex as a whole).
596  bool IsSub0 = HexagonMCInstrInfo::isSubInstruction(MI) && !State.SubInst1;
597  if (State.Extended && InstExtendable && !IsSub0) {
598  unsigned OpIdx = ~0u;
599  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
600  if (&MO != &MI.getOperand(I))
601  continue;
602  OpIdx = I;
603  break;
604  }
605  assert(OpIdx != ~0u);
606  if (OpIdx == HexagonMCInstrInfo::getExtendableOp(MCII, MI)) {
607  unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
608  Value = (Value & 0x3f) << Shift;
609  }
610  }
611  return Value;
612  }
613  assert(ME->getKind() == MCExpr::SymbolRef ||
614  ME->getKind() == MCExpr::Binary);
615  if (ME->getKind() == MCExpr::Binary) {
616  MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
617  getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
618  getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
619  return 0;
620  }
621 
622  unsigned FixupKind = fixup_Invalid;
623  const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
624  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
625  unsigned FixupWidth = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
627  MCSymbolRefExpr::VariantKind VarKind = MCSRE->getKind();
628  unsigned Opc = MCID.getOpcode();
629  unsigned IType = HexagonMCInstrInfo::getType(MCII, MI);
630 
631  LLVM_DEBUG(dbgs() << "----------------------------------------\n"
632  << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
633  << "\nOpcode: " << Opc << "\nRelocation bits: "
634  << FixupWidth << "\nAddend: " << State.Addend
635  << "\nVariant: " << unsigned(VarKind)
636  << "\n----------------------------------------\n");
637 
638  // Pick the applicable fixup kind for the symbol.
639  // Handle special cases first, the rest will be looked up in the tables.
640 
641  if (FixupWidth == 16 && !State.Extended) {
642  if (VarKind == MCSymbolRefExpr::VK_None) {
644  // A2_iconst.
645  FixupKind = Hexagon::fixup_Hexagon_27_REG;
646  } else {
647  // Look for GP-relative fixups.
648  unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
649  static const Hexagon::Fixups GPRelFixups[] = {
652  };
653  assert(Shift < array_lengthof(GPRelFixups));
654  auto UsesGP = [] (const MCInstrDesc &D) {
655  for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U)
656  if (*U == Hexagon::GP)
657  return true;
658  return false;
659  };
660  if (UsesGP(MCID))
661  FixupKind = GPRelFixups[Shift];
662  }
663  } else if (VarKind == MCSymbolRefExpr::VK_GOTREL) {
664  // Select between LO/HI.
665  if (Opc == Hexagon::LO)
667  else if (Opc == Hexagon::HI)
669  }
670  } else {
671  bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR;
672  switch (FixupWidth) {
673  case 9:
674  if (BranchOrCR)
675  FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
677  break;
678  case 8:
679  case 7:
680  if (State.Extended && VarKind == MCSymbolRefExpr::VK_GOT)
681  FixupKind = HexagonMCInstrInfo::isExtentSigned(MCII, MI)
684  else if (FixupWidth == 7 && BranchOrCR)
685  FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
687  break;
688  case 0:
689  FixupKind = getFixupNoBits(MCII, MI, MO, VarKind);
690  break;
691  }
692  }
693 
694  if (FixupKind == fixup_Invalid) {
695  const auto &FixupTable = State.Extended ? ExtFixups : StdFixups;
696 
697  auto FindVK = FixupTable.find(VarKind);
698  if (FindVK != FixupTable.end())
699  FixupKind = FindVK->second[FixupWidth];
700  }
701 
702  if (FixupKind == fixup_Invalid)
703  raise_relocation_error(FixupWidth, VarKind);
704 
705  const MCExpr *FixupExpr = MO.getExpr();
706  if (State.Addend != 0 && isPCRel(FixupKind)) {
707  const MCExpr *C = MCConstantExpr::create(State.Addend, MCT);
708  FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
709  }
710 
711  MCFixup Fixup = MCFixup::create(State.Addend, FixupExpr,
712  MCFixupKind(FixupKind), MI.getLoc());
713  Fixups.push_back(Fixup);
714  // All of the information is in the fixup.
715  return 0;
716 }
717 
718 unsigned
720  SmallVectorImpl<MCFixup> &Fixups,
721  MCSubtargetInfo const &STI) const {
722 #ifndef NDEBUG
723  size_t OperandNumber = ~0U;
724  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
725  if (&MI.getOperand(i) == &MO) {
726  OperandNumber = i;
727  break;
728  }
729  assert((OperandNumber != ~0U) && "Operand not found");
730 #endif
731 
732  if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
733  &MO == &HexagonMCInstrInfo::getNewValueOperand(MCII, MI)) {
734  // Calculate the new value distance to the associated producer
735  unsigned SOffset = 0;
736  unsigned VOffset = 0;
737  unsigned UseReg = MO.getReg();
738  unsigned DefReg1, DefReg2;
739 
740  auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
741  const MCOperand *I = Instrs.begin() + State.Index - 1;
742 
743  for (;; --I) {
744  assert(I != Instrs.begin() - 1 && "Couldn't find producer");
745  MCInst const &Inst = *I->getInst();
747  continue;
748 
749  DefReg1 = DefReg2 = 0;
750  ++SOffset;
751  if (HexagonMCInstrInfo::isVector(MCII, Inst)) {
752  // Vector instructions don't count scalars.
753  ++VOffset;
754  }
755  if (HexagonMCInstrInfo::hasNewValue(MCII, Inst))
756  DefReg1 = HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg();
757  if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst))
758  DefReg2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg();
759  if (!RegisterMatches(UseReg, DefReg1, DefReg2)) {
760  // This isn't the register we're looking for
761  continue;
762  }
763  if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
764  // Producer is unpredicated
765  break;
766  }
768  "Unpredicated consumer depending on predicated producer");
769  if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
771  // Producer predicate sense matched ours.
772  break;
773  }
774  // Hexagon PRM 10.11 Construct Nt from distance
775  unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset
776  : SOffset;
777  Offset <<= 1;
778  Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2);
779  return Offset;
780  }
781 
782  assert(!MO.isImm());
783  if (MO.isReg()) {
784  unsigned Reg = MO.getReg();
788  return MCT.getRegisterInfo()->getEncodingValue(Reg);
789  }
790 
791  return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
792 }
793 
795  MCRegisterInfo const &MRI,
796  MCContext &MCT) {
797  return new HexagonMCCodeEmitter(MII, MCT);
798 }
799 
800 #define ENABLE_INSTR_PREDICATE_VERIFIER
801 #include "HexagonGenMCCodeEmitter.inc"
static LLVM_ATTRIBUTE_NORETURN void raise_relocation_error(unsigned Width, unsigned Kind)
uint64_t CallInst * C
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImm() const
Definition: MCInst.h:58
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
VariantKind getKind() const
Definition: MCExpr.h:338
static const std::map< unsigned, std::vector< unsigned > > StdFixups
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned Reg
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
bool isReg() const
Definition: MCInst.h:57
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:564
#define HEXAGON_INSTR_SIZE
STATISTIC(NumFunctions, "Total number of functions")
F(f)
bool isSubInstruction(MCInst const &MCI)
bool isOuterLoop(MCInst const &MCI)
static Lanai::Fixups FixupKind(const MCExpr *Expr)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
static const unsigned fixup_Invalid
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:277
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:74
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
bool isImmext(MCInst const &MCI)
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool s27_2_reloc(MCExpr const &Expr)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:567
const MCInst * getInst() const
Definition: MCInst.h:105
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
const MCExpr * getExpr() const
Definition: MCInst.h:95
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:461
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getNumOperands() const
Definition: MCInst.h:181
Definition for classes that emit Hexagon machine code from MCInsts.
Binary assembler expressions.
Definition: MCExpr.h:417
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:90
static const std::map< unsigned, std::vector< unsigned > > ExtFixups
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
PowerPC TLS Dynamic Call Fixup
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
ExprKind getKind() const
Definition: MCExpr.h:72
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1050
#define LLVM_ATTRIBUTE_NORETURN
Definition: Compiler.h:221
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
SMLoc getLoc() const
Definition: MCInst.h:177
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
MCExpr const & getExpr(MCExpr const &Expr)
#define P(x)
static unsigned UseReg(const MachineOperand &MO)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:258
Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:40
size_t bundleSize(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
static bool RegisterMatches(unsigned Consumer, unsigned Producer, unsigned Producer2)
Binary expressions.
Definition: MCExpr.h:38
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:204
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
EncodeSingleInstruction - Emit a single.
unsigned getDuplexRegisterNumbering(unsigned Reg)
IRTranslator LLVM IR MI
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
static bool isPCRel(unsigned Kind)
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
unsigned getOpcode() const
Definition: MCInst.h:171
#define LLVM_DEBUG(X)
Definition: Debug.h:122
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
#define _
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)