llvm::RISCVInstrInfo Class Reference

#include "Target/RISCV/RISCVInstrInfo.h"

Inheritance diagram for llvm::RISCVInstrInfo:

Collaboration diagram for llvm::RISCVInstrInfo:

Public Member Functions
	RISCVInstrInfo (RISCVSubtarget &STI)
MCInst	getNop () const override
const MCInstrDesc &	getBrCond (RISCVCC::CondCode CC) const
unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override
unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
void	movImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void	insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override
bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
bool	analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
MachineInstr *	optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool	isAsCheapAsAMove (const MachineInstr &MI) const override
std::optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
bool	getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
std::optional< outliner::OutlinedFunction >	getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
virtual outliner::InstrType	getOutliningTypeImpl (MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
MachineInstr *	convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
std::string	createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
void	getVLENFactoredAmount (MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
bool	useMachineCombiner () const override
MachineTraceStrategy	getMachineCombinerTraceStrategy () const override
void	setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
bool	getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
void	finalizeInsInstrs (MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
void	genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
bool	hasReassociableSibling (const MachineInstr &Inst, bool &Commuted) const override
bool	isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override
std::optional< unsigned >	getInverseOpcode (unsigned Opcode) const override
virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
	Target-dependent implementation for foldMemoryOperand.
virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
	Target-dependent implementation for foldMemoryOperand.

Protected Attributes
const RISCVSubtarget &	STI

Detailed Description

Definition at line 44 of file RISCVInstrInfo.h.

Constructor & Destructor Documentation

RISCVInstrInfo()

RISCVInstrInfo::RISCVInstrInfo ( RISCVSubtarget &  STI )

explicit

Definition at line 67 of file RISCVInstrInfo.cpp.

Member Function Documentation

analyzeBranch()

bool RISCVInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *&  TBB, MachineBasicBlock *&  FBB, SmallVectorImpl< MachineOperand > &  Cond, bool  AllowModify  ) const

override

Definition at line 843 of file RISCVInstrInfo.cpp.

References Cond, llvm::MachineBasicBlock::end(), getBranchDestBlock(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), I, MBB, parseCondBranch(), llvm::MachineBasicBlock::rend(), and TBB.

analyzeSelect()

bool RISCVInstrInfo::analyzeSelect ( const MachineInstr &  MI, SmallVectorImpl< MachineOperand > &  Cond, unsigned &  TrueOp, unsigned &  FalseOp, bool &  Optimizable  ) const

override

Definition at line 1143 of file RISCVInstrInfo.cpp.

References assert(), Cond, MI, and STI.

areMemAccessesTriviallyDisjoint()

bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr &  MIa, const MachineInstr &  MIb  ) const

override

Definition at line 1851 of file RISCVInstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::mayLoadOrStore(), STI, and TRI.

buildOutlinedFrame()

void RISCVInstrInfo::buildOutlinedFrame ( MachineBasicBlock &  MBB, MachineFunction &  MF, const outliner::OutlinedFunction &  OF  ) const

override

Definition at line 2022 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::RegState::Define, E, llvm::MachineBasicBlock::end(), llvm::get(), I, llvm::MachineBasicBlock::insert(), and MBB.

commuteInstructionImpl()

MachineInstr * RISCVInstrInfo::commuteInstructionImpl ( MachineInstr &  MI, bool  NewMI, unsigned  OpIdx1, unsigned  OpIdx2  ) const

override

Definition at line 2299 of file RISCVInstrInfo.cpp.

References assert(), CASE_VFMA_CHANGE_OPCODE_LMULS, CASE_VFMA_CHANGE_OPCODE_LMULS_MF4, CASE_VFMA_CHANGE_OPCODE_SPLATS, CASE_VFMA_OPCODE_LMULS, CASE_VFMA_OPCODE_LMULS_MF4, CASE_VFMA_SPLATS, CC, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::FMSUB, llvm::FNMSUB, llvm::get(), llvm::RISCVCC::getOppositeBranchCondition(), llvm_unreachable, and MI.

convertToThreeAddress()

MachineInstr * RISCVInstrInfo::convertToThreeAddress ( MachineInstr &  MI, LiveVariables *  LV, LiveIntervals *  LIS  ) const

override

Definition at line 2452 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), CASE_WIDEOP_CHANGE_OPCODE_LMULS, CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4, CASE_WIDEOP_OPCODE_LMULS, CASE_WIDEOP_OPCODE_LMULS_MF4, llvm::MachineInstrBuilder::copyImplicitOps(), llvm::LiveRange::Segment::end, llvm::get(), llvm::LiveIntervals::getInterval(), llvm::LiveRange::getSegmentContaining(), llvm::RISCVII::hasVecPolicyOp(), I, Idx, llvm_unreachable, MBB, MI, llvm::LiveVariables::replaceKillInstruction(), and llvm::LiveIntervals::ReplaceMachineInstrInMaps().

copyPhysReg()

void RISCVInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, const DebugLoc &  DL, MCRegister  DstReg, MCRegister  SrcReg, bool  KillSrc  ) const

override

Definition at line 296 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), llvm::RISCVVType::decodeVLMUL(), DL, forwardCopyWillClobberTuple(), llvm::get(), llvm::getKillRegState(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::getVLOpNum(), I, llvm::RegState::Implicit, isConvertibleToVMV_V_V(), llvm_unreachable, llvm::RISCVII::LMUL_1, llvm::RISCVII::LMUL_2, llvm::RISCVII::LMUL_4, llvm::RISCVII::LMUL_8, MBB, MBBI, STI, and TRI.

createMIROperandComment()

std::string RISCVInstrInfo::createMIROperandComment ( const MachineInstr &  MI, const MachineOperand &  Op, unsigned  OpIdx, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 2063 of file RISCVInstrInfo.cpp.

References assert(), llvm::TargetInstrInfo::createMIROperandComment(), llvm::raw_ostream::flush(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::getVecPolicyOpNum(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVVType::isValidSEW(), Log2SEW, llvm::RISCVII::MASK_AGNOSTIC, MI, OS, llvm::RISCVVType::printVType(), SEW, llvm::RISCVII::TAIL_AGNOSTIC, TRI, and TSFlags.

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > RISCVInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF ) const

override

Definition at line 1883 of file RISCVInstrInfo.cpp.

References llvm::RISCVII::MO_DIRECT_FLAG_MASK.

finalizeInsInstrs()

void RISCVInstrInfo::finalizeInsInstrs ( MachineInstr &  Root, MachineCombinerPattern &  P, SmallVectorImpl< MachineInstr * > &  InsInstrs  ) const

override

Definition at line 1322 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addUse(), llvm::all_of(), assert(), llvm::RISCVFPRndMode::DYN, llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::RISCV::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RegState::Implicit, and MI.

findCommutedOpIndices()

bool RISCVInstrInfo::findCommutedOpIndices ( const MachineInstr &  MI, unsigned &  SrcOpIdx1, unsigned &  SrcOpIdx2  ) const

override

Definition at line 2137 of file RISCVInstrInfo.cpp.

References assert(), CASE_VFMA_OPCODE_LMULS, CASE_VFMA_OPCODE_LMULS_MF4, CASE_VFMA_SPLATS, llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::FMSUB, llvm::FNMSUB, llvm::RISCVII::hasVecPolicyOp(), llvm::MCInstrDesc::isCommutable(), and MI.

foldMemoryOperandImpl() [1/3]

virtual MachineInstr * llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF, MachineInstr &  MI, ArrayRef< unsigned >  Ops, MachineBasicBlock::iterator  InsertPt, int  FrameIndex, LiveIntervals *  LIS = nullptr, VirtRegMap *  VRM = nullptr  ) const

inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1269 of file TargetInstrInfo.h.

foldMemoryOperandImpl() [2/3]

MachineInstr * RISCVInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF, MachineInstr &  MI, ArrayRef< unsigned >  Ops, MachineBasicBlock::iterator  InsertPt, int  FrameIndex, LiveIntervals *  LIS = nullptr, VirtRegMap *  VRM = nullptr  ) const

override

Definition at line 668 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), llvm::get(), llvm::MachineFunction::getDataLayout(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::DataLayout::isBigEndian(), llvm::RISCV::isSEXT_W(), llvm::RISCV::isZEXT_B(), llvm::RISCV::isZEXT_W(), MI, llvm::MachineMemOperand::MOLoad, and llvm::ArrayRef< T >::size().

foldMemoryOperandImpl() [3/3]

virtual MachineInstr * llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF, MachineInstr &  MI, ArrayRef< unsigned >  Ops, MachineBasicBlock::iterator  InsertPt, MachineInstr &  LoadMI, LiveIntervals *  LIS = nullptr  ) const

inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1282 of file TargetInstrInfo.h.

genAlternativeCodeSequence()

void RISCVInstrInfo::genAlternativeCodeSequence ( MachineInstr &  Root, MachineCombinerPattern  Pattern, SmallVectorImpl< MachineInstr * > &  InsInstrs, SmallVectorImpl< MachineInstr * > &  DelInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg  ) const

override

Definition at line 1624 of file RISCVInstrInfo.cpp.

References combineFPFusedMultiply(), llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), and MRI.

getBranchDestBlock()

MachineBasicBlock * RISCVInstrInfo::getBranchDestBlock ( const MachineInstr &  MI ) const

override

Definition at line 1056 of file RISCVInstrInfo.cpp.

References assert(), and MI.

Referenced by analyzeBranch().

getBrCond()

const MCInstrDesc & RISCVInstrInfo::getBrCond

(

RISCVCC::CondCode

CC

)

const

Definition at line 805 of file RISCVInstrInfo.cpp.

References CC, llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, llvm::get(), and llvm_unreachable.

Referenced by insertBranch().

getInstSizeInBytes()

unsigned RISCVInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI ) const

override

Definition at line 1232 of file RISCVInstrInfo.cpp.

References llvm::get(), llvm::MachineFunction::getTarget(), MI, STI, and TM.

Referenced by getOutliningCandidateInfo(), insertBranch(), and removeBranch().

getInverseOpcode()

std::optional< unsigned > RISCVInstrInfo::getInverseOpcode ( unsigned  Opcode ) const

override

Definition at line 1457 of file RISCVInstrInfo.cpp.

Referenced by isAssociativeAndCommutative().

getMachineCombinerPatterns()

bool RISCVInstrInfo::getMachineCombinerPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns, bool  DoRegPressureReduce  ) const

override

Definition at line 1541 of file RISCVInstrInfo.cpp.

References getFPPatterns(), and llvm::TargetInstrInfo::getMachineCombinerPatterns().

getMachineCombinerTraceStrategy()

MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy ( ) const

override

Definition at line 1299 of file RISCVInstrInfo.cpp.

References ForceMachineCombinerStrategy, STI, llvm::TS_Local, and llvm::TS_MinInstrCount.

getMemOperandWithOffsetWidth()

bool RISCVInstrInfo::getMemOperandWithOffsetWidth	(	const MachineInstr &	LdSt,
		const MachineOperand *&	BaseOp,
		int64_t &	Offset,
		unsigned &	Width,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 1828 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), getSize(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::memoperands_begin(), and llvm::Offset.

Referenced by areMemAccessesTriviallyDisjoint().

getNop()

MCInst RISCVInstrInfo::getNop ( ) const

override

Definition at line 71 of file RISCVInstrInfo.cpp.

References llvm::MCInstBuilder::addImm(), llvm::MCInstBuilder::addReg(), llvm::RISCVSubtarget::hasStdExtCOrZca(), and STI.

getOutliningCandidateInfo()

std::optional< outliner::OutlinedFunction > RISCVInstrInfo::getOutliningCandidateInfo ( std::vector< outliner::Candidate > &  RepeatedSequenceLocs ) const

override

Definition at line 1940 of file RISCVInstrInfo.cpp.

References llvm::CallingConv::C, E, llvm::erase_if(), getInstSizeInBytes(), I, MachineOutlinerDefault, and TRI.

getOutliningTypeImpl()

outliner::InstrType RISCVInstrInfo::getOutliningTypeImpl ( MachineBasicBlock::iterator &  MBBI, unsigned  Flags  ) const

overridevirtual

Definition at line 1981 of file RISCVInstrInfo.cpp.

References F, llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::outliner::Illegal, llvm::outliner::Invisible, llvm::outliner::Legal, MBB, MBBI, MI, llvm::RISCVII::MO_PCREL_LO, and TRI.

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 1889 of file RISCVInstrInfo.cpp.

getVLENFactoredAmount()

void RISCVInstrInfo::getVLENFactoredAmount	(	MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	II,
		const DebugLoc &	DL,
		Register	DestReg,
		int64_t	Amount,
		MachineInstr::MIFlag	Flag = MachineInstr::NoFlags
	)		const

Definition at line 2528 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::LLVMContext::diagnose(), DL, llvm::get(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getRegInfo(), llvm::isPowerOf2_64(), llvm::RegState::Kill, llvm_unreachable, llvm::Log2_32(), llvm::Log2_64(), MBB, movImm(), MRI, N, llvm::MachineInstrBuilder::setMIFlag(), and STI.

hasReassociableSibling()

bool RISCVInstrInfo::hasReassociableSibling ( const MachineInstr &  Inst, bool &  Commuted  ) const

override

Definition at line 1385 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getMF(), llvm::RISCV::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RISCV::hasEqualFRM(), llvm::TargetInstrInfo::hasReassociableSibling(), and MRI.

insertBranch()

unsigned RISCVInstrInfo::insertBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *  TBB, MachineBasicBlock *  FBB, ArrayRef< MachineOperand >  Cond, const DebugLoc &  dl, int *  BytesAdded = nullptr  ) const

override

Definition at line 945 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), CC, Cond, DL, llvm::get(), getBrCond(), getInstSizeInBytes(), MBB, MI, and TBB.

insertIndirectBranch()

void RISCVInstrInfo::insertIndirectBranch ( MachineBasicBlock &  MBB, MachineBasicBlock &  NewDestBB, MachineBasicBlock &  RestoreBB, const DebugLoc &  DL, int64_t  BrOffset, RegScavenger *  RS  ) const

override

Definition at line 982 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::back(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::get(), llvm::RISCVMachineFunctionInfo::getBranchRelaxationScratchFrameIndex(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), loadRegFromStackSlot(), MBB, MI, llvm::RISCVII::MO_CALL, MRI, llvm::MachineBasicBlock::pred_size(), llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::RegScavenger::setRegUsed(), storeRegToStackSlot(), and TRI.

insertOutlinedCall()

MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall ( Module &  M, MachineBasicBlock &  MBB, MachineBasicBlock::iterator &  It, MachineFunction &  MF, outliner::Candidate &  C  ) const

override

Definition at line 2050 of file RISCVInstrInfo.cpp.

References llvm::BuildMI(), llvm::get(), llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), MBB, and llvm::RISCVII::MO_CALL.

isAsCheapAsAMove()

bool RISCVInstrInfo::isAsCheapAsAMove ( const MachineInstr &  MI ) const

override

Definition at line 1253 of file RISCVInstrInfo.cpp.

References MI.

isAssociativeAndCommutative()

bool RISCVInstrInfo::isAssociativeAndCommutative ( const MachineInstr &  Inst, bool  Invert  ) const

override

Definition at line 1404 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getFlag(), getInverseOpcode(), llvm::MachineInstr::getOpcode(), isFADD(), and isFMUL().

isBranchOffsetInRange()

bool RISCVInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc, int64_t  BrOffset  ) const

override

Definition at line 1063 of file RISCVInstrInfo.cpp.

References llvm::RISCVSubtarget::getXLen(), llvm::isIntN(), llvm_unreachable, llvm::SignExtend64(), and STI.

isCopyInstrImpl()

std::optional< DestSourcePair > RISCVInstrInfo::isCopyInstrImpl ( const MachineInstr &  MI ) const

override

Definition at line 1275 of file RISCVInstrInfo.cpp.

References MI.

isFunctionSafeToOutlineFrom()

bool RISCVInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction &  MF, bool  OutlineFromLinkOnceODRs  ) const

override

Definition at line 1906 of file RISCVInstrInfo.cpp.

References F, and llvm::MachineFunction::getFunction().

isLoadFromStackSlot() [1/2]

unsigned RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 80 of file RISCVInstrInfo.cpp.

References isLoadFromStackSlot(), and MI.

Referenced by isLoadFromStackSlot().

isLoadFromStackSlot() [2/2]

unsigned RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex, unsigned &  MemBytes  ) const

override

Definition at line 86 of file RISCVInstrInfo.cpp.

References MI.

isMBBSafeToOutlineFrom()

bool RISCVInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock &  MBB, unsigned &  Flags  ) const

override

Definition at line 1923 of file RISCVInstrInfo.cpp.

References Flags, llvm::TargetInstrInfo::isMBBSafeToOutlineFrom(), and MBB.

isStoreToStackSlot() [1/2]

unsigned RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 121 of file RISCVInstrInfo.cpp.

References isStoreToStackSlot(), and MI.

Referenced by isStoreToStackSlot().

isStoreToStackSlot() [2/2]

unsigned RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex, unsigned &  MemBytes  ) const

override

Definition at line 127 of file RISCVInstrInfo.cpp.

References MI.

loadRegFromStackSlot()

void RISCVInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  DstReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI, Register  VReg  ) const

override

Definition at line 586 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), TRI, and llvm::MemoryLocation::UnknownSize.

Referenced by insertIndirectBranch().

movImm()

void RISCVInstrInfo::movImm	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		Register	DstReg,
		uint64_t	Val,
		MachineInstr::MIFlag	Flag = MachineInstr::NoFlags
	)		const

Definition at line 726 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::get(), llvm::RISCVMatInt::Imm, llvm::RISCVSubtarget::is64Bit(), llvm::RegState::Kill, MBB, MBBI, llvm::RISCVMatInt::RegImm, llvm::RISCVMatInt::RegReg, llvm::RISCVMatInt::RegX0, llvm::report_fatal_error(), llvm::MachineInstrBuilder::setMIFlag(), and STI.

Referenced by getVLENFactoredAmount().

optimizeSelect()

MachineInstr * RISCVInstrInfo::optimizeSelect ( MachineInstr &  MI, SmallPtrSetImpl< MachineInstr * > &  SeenMIs, bool  PreferFalse  ) const

override

Definition at line 1167 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), canFoldAsPredicatedOp(), CC, llvm::MachineInstr::clearKillInfo(), DefMI, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RISCVCC::getOppositeBranchCondition(), llvm::MachineInstr::getParent(), getPredicatedOpcode(), llvm::MachineOperand::getReg(), llvm::SmallPtrSetImpl< PtrType >::insert(), MI, MRI, and STI.

removeBranch()

unsigned RISCVInstrInfo::removeBranch ( MachineBasicBlock &  MBB, int *  BytesRemoved = nullptr  ) const

override

Definition at line 911 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), getInstSizeInBytes(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, and MBB.

reverseBranchCondition()

bool RISCVInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond ) const

override

Definition at line 1047 of file RISCVInstrInfo.cpp.

References assert(), CC, Cond, and getOppositeBranchCondition().

setSpecialOperandAttr()

void RISCVInstrInfo::setSpecialOperandAttr ( MachineInstr &  OldMI1, MachineInstr &  OldMI2, MachineInstr &  NewMI1, MachineInstr &  NewMI2  ) const

override

Definition at line 1313 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getFlags(), and llvm::MachineInstr::setFlags().

shouldOutlineFromFunctionByDefault()

bool RISCVInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction &  MF ) const

override

Definition at line 1934 of file RISCVInstrInfo.cpp.

References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().

storeRegToStackSlot()

void RISCVInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  SrcReg, bool  IsKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI, Register  VReg  ) const

override

Definition at line 502 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), TRI, and llvm::MemoryLocation::UnknownSize.

Referenced by insertIndirectBranch().

useMachineCombiner()

bool llvm::RISCVInstrInfo::useMachineCombiner ( ) const

inlineoverride

Definition at line 200 of file RISCVInstrInfo.h.

verifyInstruction()

bool RISCVInstrInfo::verifyInstruction ( const MachineInstr &  MI, StringRef &  ErrInfo  ) const

override

Definition at line 1650 of file RISCVInstrInfo.cpp.

References CASE_OPERAND_UIMM, llvm::enumerate(), llvm::MachineOperand::getImm(), llvm::RISCVII::getMergeOpNum(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::getVecPolicyOpNum(), llvm::RISCVII::getVLOpNum(), llvm::RISCVII::hasMergeOp(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::hasVLOp(), llvm::RISCVSubtarget::is64Bit(), llvm::MachineOperand::isImm(), llvm::RISCVVType::isValidSEW(), llvm_unreachable, Log2SEW, llvm::RISCVII::MASK_AGNOSTIC, MI, MRI, llvm::RISCVOp::OPERAND_CLUI_IMM, llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM, llvm::RISCVOp::OPERAND_LAST_RISCV_IMM, llvm::RISCVOp::OPERAND_RVKRNUM, llvm::RISCVOp::OPERAND_RVKRNUM_0_7, llvm::RISCVOp::OPERAND_RVKRNUM_1_10, llvm::RISCVOp::OPERAND_RVKRNUM_2_14, llvm::RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO, llvm::RISCVOp::OPERAND_SIMM12, llvm::RISCVOp::OPERAND_SIMM12_LSB00000, llvm::RISCVOp::OPERAND_SIMM5, llvm::RISCVOp::OPERAND_SIMM5_PLUS1, llvm::RISCVOp::OPERAND_SIMM6, llvm::RISCVOp::OPERAND_SIMM6_NONZERO, llvm::RISCVOp::OPERAND_UIMM10_LSB00_NONZERO, llvm::RISCVOp::OPERAND_UIMM2_LSB0, llvm::RISCVOp::OPERAND_UIMM7_LSB00, llvm::RISCVOp::OPERAND_UIMM8_LSB00, llvm::RISCVOp::OPERAND_UIMM8_LSB000, llvm::RISCVOp::OPERAND_UIMM9_LSB000, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO, llvm::RISCVOp::OPERAND_VTYPEI10, llvm::RISCVOp::OPERAND_VTYPEI11, llvm::RISCVOp::OPERAND_ZERO, llvm::MCInstrDesc::operands(), SEW, STI, llvm::RISCVII::TAIL_AGNOSTIC, llvm::MCInstrDesc::TSFlags, TSFlags, and UseOpIdx.

Member Data Documentation

STI

const RISCVSubtarget& llvm::RISCVInstrInfo::STI

protected

Definition at line 231 of file RISCVInstrInfo.h.

Referenced by analyzeSelect(), areMemAccessesTriviallyDisjoint(), copyPhysReg(), getInstSizeInBytes(), getMachineCombinerTraceStrategy(), getNop(), getVLENFactoredAmount(), isBranchOffsetInRange(), movImm(), optimizeSelect(), and verifyInstruction().

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The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVInstrInfo.h
• lib/Target/RISCV/RISCVInstrInfo.cpp