llvm::RISCVInstrInfo Class Reference

#include "Target/RISCV/RISCVInstrInfo.h"

Inheritance diagram for llvm::RISCVInstrInfo:

Collaboration diagram for llvm::RISCVInstrInfo:

Public Member Functions
	RISCVInstrInfo (RISCVSubtarget &STI)
unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DstReg, unsigned SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	movImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
unsigned	insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override
bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
bool	isAsCheapAsAMove (const MachineInstr &MI) const override
bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override

Protected Attributes
const RISCVSubtarget &	STI

Detailed Description

Definition at line 26 of file RISCVInstrInfo.h.

Constructor & Destructor Documentation

RISCVInstrInfo()

RISCVInstrInfo::RISCVInstrInfo ( RISCVSubtarget &  STI )

explicit

Definition at line 32 of file RISCVInstrInfo.cpp.

Member Function Documentation

analyzeBranch()

bool RISCVInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *&  TBB, MachineBasicBlock *&  FBB, SmallVectorImpl< MachineOperand > &  Cond, bool  AllowModify  ) const

override

Definition at line 233 of file RISCVInstrInfo.cpp.

copyPhysReg()

void RISCVInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, const DebugLoc &  DL, unsigned  DstReg, unsigned  SrcReg, bool  KillSrc  ) const

override

Definition at line 85 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::getKillRegState(), and llvm_unreachable.

getBranchDestBlock()

MachineBasicBlock * RISCVInstrInfo::getBranchDestBlock ( const MachineInstr &  MI ) const

override

Definition at line 422 of file RISCVInstrInfo.cpp.

References assert(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), and llvm::MCInstrDesc::isBranch().

getInstSizeInBytes()

unsigned RISCVInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI ) const

override

Definition at line 450 of file RISCVInstrInfo.cpp.

References llvm::ISD::EH_LABEL, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, llvm::AMDGPUISD::KILL, and llvm::SystemZISD::TM.

Referenced by removeBranch().

insertBranch()

unsigned RISCVInstrInfo::insertBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *  TBB, MachineBasicBlock *  FBB, ArrayRef< MachineOperand >  Cond, const DebugLoc &  dl, int *  BytesAdded = nullptr  ) const

override

Definition at line 335 of file RISCVInstrInfo.cpp.

insertIndirectBranch()

unsigned RISCVInstrInfo::insertIndirectBranch ( MachineBasicBlock &  MBB, MachineBasicBlock &  NewDestBB, const DebugLoc &  DL, int64_t  BrOffset, RegScavenger *  RS = nullptr  ) const

override

Definition at line 372 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearVirtRegs(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::isInt< 32 >(), llvm::RegState::Kill, llvm::RISCVII::MO_HI, llvm::RISCVII::MO_LO, MRI, llvm::MachineBasicBlock::pred_size(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::RegScavenger::setRegUsed(), and llvm::SystemZISD::TM.

isAsCheapAsAMove()

bool RISCVInstrInfo::isAsCheapAsAMove ( const MachineInstr &  MI ) const

override

Definition at line 478 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::isAsCheapAsAMove(), and llvm::MachineOperand::isReg().

isBranchOffsetInRange()

bool RISCVInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc, int64_t  BrOffset  ) const

override

Definition at line 429 of file RISCVInstrInfo.cpp.

References llvm::isIntN(), and llvm_unreachable.

isLoadFromStackSlot()

unsigned RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 36 of file RISCVInstrInfo.cpp.

References llvm::X86ISD::FLD, llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::ARM_MB::LD.

isStoreToStackSlot()

unsigned RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 62 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

loadRegFromStackSlot()

void RISCVInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, unsigned  DstReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 137 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::X86ISD::FLD, llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::ARM_MB::LD, and llvm_unreachable.

movImm()

void RISCVInstrInfo::movImm	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		Register	DstReg,
		uint64_t	Val,
		MachineInstr::MIFlag	Flag = MachineInstr::NoFlags
	)		const

Definition at line 161 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RISCVMatInt::generateInstSeq(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), is64Bit(), llvm::isInt< 32 >(), llvm::RegState::Kill, MRI, llvm::report_fatal_error(), llvm::MachineInstrBuilder::setMIFlag(), and llvm::SmallVectorBase::size().

Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and llvm::RISCVFrameLowering::hasFP().

removeBranch()

unsigned RISCVInstrInfo::removeBranch ( MachineBasicBlock &  MBB, int *  BytesRemoved = nullptr  ) const

override

Definition at line 301 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), getInstSizeInBytes(), llvm::MachineBasicBlock::getLastNonDebugInstr(), and I.

reverseBranchCondition()

bool RISCVInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond ) const

override

Definition at line 414 of file RISCVInstrInfo.cpp.

storeRegToStackSlot()

void RISCVInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, unsigned  SrcReg, bool  IsKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 110 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::getKillRegState(), llvm::TargetRegisterInfo::getRegSizeInBits(), and llvm_unreachable.

verifyInstruction()

bool RISCVInstrInfo::verifyInstruction ( const MachineInstr &  MI, StringRef &  ErrInfo  ) const

override

Definition at line 491 of file RISCVInstrInfo.cpp.

References llvm::enumerate(), llvm::MCInstrInfo::get(), llvm::MachineOperand::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), llvm_unreachable, llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM, llvm::RISCVOp::OPERAND_LAST_RISCV_IMM, llvm::RISCVOp::OPERAND_SIMM12, llvm::RISCVOp::OPERAND_SIMM13_LSB0, llvm::RISCVOp::OPERAND_SIMM21_LSB0, llvm::RISCVOp::OPERAND_UIMM12, llvm::RISCVOp::OPERAND_UIMM20, llvm::RISCVOp::OPERAND_UIMM4, llvm::RISCVOp::OPERAND_UIMM5, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN, llvm::MCInstrDesc::operands(), and STI.

Member Data Documentation

STI

const RISCVSubtarget& llvm::RISCVInstrInfo::STI

protected

Definition at line 90 of file RISCVInstrInfo.h.

Referenced by verifyInstruction().

---

The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVInstrInfo.h
• lib/Target/RISCV/RISCVInstrInfo.cpp