LLVM 19.0.0git
Public Member Functions | Protected Attributes | List of all members
llvm::RISCVInstrInfo Class Reference

#include "Target/RISCV/RISCVInstrInfo.h"

Inheritance diagram for llvm::RISCVInstrInfo:
Inheritance graph
[legend]

Public Member Functions

 RISCVInstrInfo (RISCVSubtarget &STI)
 
MCInst getNop () const override
 
const MCInstrDescgetBrCond (RISCVCC::CondCode CC) const
 
Register isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
Register isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override
 
Register isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
Register isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override
 
void copyPhysRegVector (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, unsigned Opc, unsigned NF=1) const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
 
void movImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
 
void insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool optimizeCondBranch (MachineInstr &MI) const override
 
MachineBasicBlockgetBranchDestBlock (const MachineInstr &MI) const override
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 
bool analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
 
MachineInstroptimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
 
bool isAsCheapAsAMove (const MachineInstr &MI) const override
 
std::optional< DestSourcePairisCopyInstrImpl (const MachineInstr &MI) const override
 
bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
 
bool canFoldIntoAddrMode (const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
 
MachineInstremitLdStWithAddr (MachineInstr &MemI, const ExtAddrMode &AM) const override
 
bool getMemOperandsWithOffsetWidth (const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
 
bool shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
 
bool getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
 
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
bool isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
 
bool isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
 
bool shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
 
std::optional< outliner::OutlinedFunctiongetOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
 
virtual outliner::InstrType getOutliningTypeImpl (MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
 
void buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
 
MachineBasicBlock::iterator insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
 
std::optional< RegImmPairisAddImmediate (const MachineInstr &MI, Register Reg) const override
 
bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
 
MachineInstrconvertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
 
std::string createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
 
void getVLENFactoredAmount (MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
 
bool useMachineCombiner () const override
 
MachineTraceStrategy getMachineCombinerTraceStrategy () const override
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
 
void finalizeInsInstrs (MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
 
void genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
 
bool hasReassociableSibling (const MachineInstr &Inst, bool &Commuted) const override
 
bool isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override
 
std::optional< unsignedgetInverseOpcode (unsigned Opcode) const override
 
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags () const override
 
unsigned getUndefInitOpcode (unsigned RegClassID) const override
 
virtual MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
 Target-dependent implementation for foldMemoryOperand.
 
virtual MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
 Target-dependent implementation for foldMemoryOperand.
 

Protected Attributes

const RISCVSubtargetSTI
 

Detailed Description

Definition at line 52 of file RISCVInstrInfo.h.

Constructor & Destructor Documentation

◆ RISCVInstrInfo()

RISCVInstrInfo::RISCVInstrInfo ( RISCVSubtarget STI)
explicit

Definition at line 69 of file RISCVInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool RISCVInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

◆ analyzeSelect()

bool RISCVInstrInfo::analyzeSelect ( const MachineInstr MI,
SmallVectorImpl< MachineOperand > &  Cond,
unsigned TrueOp,
unsigned FalseOp,
bool Optimizable 
) const
override

Definition at line 1394 of file RISCVInstrInfo.cpp.

References assert(), Cond, MI, and STI.

◆ areMemAccessesTriviallyDisjoint()

bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr MIa,
const MachineInstr MIb 
) const
override

◆ buildOutlinedFrame()

void RISCVInstrInfo::buildOutlinedFrame ( MachineBasicBlock MBB,
MachineFunction MF,
const outliner::OutlinedFunction OF 
) const
override

◆ canFoldIntoAddrMode()

bool RISCVInstrInfo::canFoldIntoAddrMode ( const MachineInstr MemI,
Register  Reg,
const MachineInstr AddrI,
ExtAddrMode AM 
) const
override

◆ commuteInstructionImpl()

MachineInstr * RISCVInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx1,
unsigned  OpIdx2 
) const
override

◆ convertToThreeAddress()

MachineInstr * RISCVInstrInfo::convertToThreeAddress ( MachineInstr MI,
LiveVariables LV,
LiveIntervals LIS 
) const
override

◆ copyPhysReg()

void RISCVInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
const DebugLoc DL,
MCRegister  DstReg,
MCRegister  SrcReg,
bool  KillSrc 
) const
override

◆ copyPhysRegVector()

void RISCVInstrInfo::copyPhysRegVector ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
const DebugLoc DL,
MCRegister  DstReg,
MCRegister  SrcReg,
bool  KillSrc,
unsigned  Opc,
unsigned  NF = 1 
) const

◆ createMIROperandComment()

std::string RISCVInstrInfo::createMIROperandComment ( const MachineInstr MI,
const MachineOperand Op,
unsigned  OpIdx,
const TargetRegisterInfo TRI 
) const
override

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > RISCVInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 2357 of file RISCVInstrInfo.cpp.

References llvm::RISCVII::MO_DIRECT_FLAG_MASK.

◆ emitLdStWithAddr()

MachineInstr * RISCVInstrInfo::emitLdStWithAddr ( MachineInstr MemI,
const ExtAddrMode AM 
) const
override

◆ finalizeInsInstrs()

void RISCVInstrInfo::finalizeInsInstrs ( MachineInstr Root,
MachineCombinerPattern P,
SmallVectorImpl< MachineInstr * > &  InsInstrs 
) const
override

◆ findCommutedOpIndices()

bool RISCVInstrInfo::findCommutedOpIndices ( const MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2 
) const
override

◆ foldMemoryOperandImpl() [1/3]

virtual MachineInstr * llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals LIS = nullptr,
VirtRegMap VRM = nullptr 
) const
inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1313 of file TargetInstrInfo.h.

◆ foldMemoryOperandImpl() [2/3]

MachineInstr * RISCVInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals LIS = nullptr,
VirtRegMap VRM = nullptr 
) const
override

◆ foldMemoryOperandImpl() [3/3]

virtual MachineInstr * llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
MachineInstr LoadMI,
LiveIntervals LIS = nullptr 
) const
inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1326 of file TargetInstrInfo.h.

◆ genAlternativeCodeSequence()

void RISCVInstrInfo::genAlternativeCodeSequence ( MachineInstr Root,
MachineCombinerPattern  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const
override

◆ getBranchDestBlock()

MachineBasicBlock * RISCVInstrInfo::getBranchDestBlock ( const MachineInstr MI) const
override

Definition at line 1281 of file RISCVInstrInfo.cpp.

References assert(), and MI.

Referenced by analyzeBranch().

◆ getBrCond()

const MCInstrDesc & RISCVInstrInfo::getBrCond ( RISCVCC::CondCode  CC) const

Definition at line 928 of file RISCVInstrInfo.cpp.

References CC, llvm::get(), and llvm::RISCVCC::getBrCond().

Referenced by insertBranch(), and optimizeCondBranch().

◆ getInstSizeInBytes()

unsigned RISCVInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

◆ getInverseOpcode()

std::optional< unsigned > RISCVInstrInfo::getInverseOpcode ( unsigned  Opcode) const
override

Definition at line 1748 of file RISCVInstrInfo.cpp.

Referenced by isAssociativeAndCommutative().

◆ getMachineCombinerPatterns()

bool RISCVInstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns,
bool  DoRegPressureReduce 
) const
override

◆ getMachineCombinerTraceStrategy()

MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy ( ) const
override

◆ getMemOperandsWithOffsetWidth()

bool RISCVInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr MI,
SmallVectorImpl< const MachineOperand * > &  BaseOps,
int64_t &  Offset,
bool OffsetIsScalable,
unsigned Width,
const TargetRegisterInfo TRI 
) const
override

◆ getMemOperandWithOffsetWidth()

bool RISCVInstrInfo::getMemOperandWithOffsetWidth ( const MachineInstr LdSt,
const MachineOperand *&  BaseOp,
int64_t &  Offset,
unsigned Width,
const TargetRegisterInfo TRI 
) const

◆ getNop()

MCInst RISCVInstrInfo::getNop ( ) const
override

◆ getOutliningCandidateInfo()

std::optional< outliner::OutlinedFunction > RISCVInstrInfo::getOutliningCandidateInfo ( std::vector< outliner::Candidate > &  RepeatedSequenceLocs) const
override

◆ getOutliningTypeImpl()

outliner::InstrType RISCVInstrInfo::getOutliningTypeImpl ( MachineBasicBlock::iterator MBBI,
unsigned  Flags 
) const
overridevirtual

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

Definition at line 2363 of file RISCVInstrInfo.cpp.

◆ getSerializableMachineMemOperandTargetFlags()

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > RISCVInstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const
override

Definition at line 3162 of file RISCVInstrInfo.cpp.

References llvm::MONontemporalBit0, and llvm::MONontemporalBit1.

◆ getUndefInitOpcode()

unsigned llvm::RISCVInstrInfo::getUndefInitOpcode ( unsigned  RegClassID) const
inlineoverride

Definition at line 267 of file RISCVInstrInfo.h.

References llvm_unreachable.

◆ getVLENFactoredAmount()

void RISCVInstrInfo::getVLENFactoredAmount ( MachineFunction MF,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  II,
const DebugLoc DL,
Register  DestReg,
int64_t  Amount,
MachineInstr::MIFlag  Flag = MachineInstr::NoFlags 
) const

◆ hasReassociableSibling()

bool RISCVInstrInfo::hasReassociableSibling ( const MachineInstr Inst,
bool Commuted 
) const
override

◆ insertBranch()

unsigned RISCVInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc dl,
int *  BytesAdded = nullptr 
) const
override

◆ insertIndirectBranch()

void RISCVInstrInfo::insertIndirectBranch ( MachineBasicBlock MBB,
MachineBasicBlock NewDestBB,
MachineBasicBlock RestoreBB,
const DebugLoc DL,
int64_t  BrOffset,
RegScavenger RS 
) const
override

◆ insertOutlinedCall()

MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall ( Module M,
MachineBasicBlock MBB,
MachineBasicBlock::iterator It,
MachineFunction MF,
outliner::Candidate C 
) const
override

◆ isAddImmediate()

std::optional< RegImmPair > RISCVInstrInfo::isAddImmediate ( const MachineInstr MI,
Register  Reg 
) const
override

◆ isAsCheapAsAMove()

bool RISCVInstrInfo::isAsCheapAsAMove ( const MachineInstr MI) const
override

Definition at line 1545 of file RISCVInstrInfo.cpp.

References MI.

◆ isAssociativeAndCommutative()

bool RISCVInstrInfo::isAssociativeAndCommutative ( const MachineInstr Inst,
bool  Invert 
) const
override

◆ isBranchOffsetInRange()

bool RISCVInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override

◆ isCopyInstrImpl()

std::optional< DestSourcePair > RISCVInstrInfo::isCopyInstrImpl ( const MachineInstr MI) const
override

Definition at line 1571 of file RISCVInstrInfo.cpp.

References MI.

◆ isFunctionSafeToOutlineFrom()

bool RISCVInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction MF,
bool  OutlineFromLinkOnceODRs 
) const
override

Definition at line 2383 of file RISCVInstrInfo.cpp.

References F, and llvm::MachineFunction::getFunction().

◆ isLoadFromStackSlot() [1/2]

Register RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

Definition at line 82 of file RISCVInstrInfo.cpp.

References isLoadFromStackSlot(), and MI.

Referenced by isLoadFromStackSlot().

◆ isLoadFromStackSlot() [2/2]

Register RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex,
unsigned MemBytes 
) const
override

Definition at line 88 of file RISCVInstrInfo.cpp.

References MI.

◆ isMBBSafeToOutlineFrom()

bool RISCVInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock MBB,
unsigned Flags 
) const
override

Definition at line 2400 of file RISCVInstrInfo.cpp.

References llvm::TargetInstrInfo::isMBBSafeToOutlineFrom(), and MBB.

◆ isStoreToStackSlot() [1/2]

Register RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

Definition at line 123 of file RISCVInstrInfo.cpp.

References isStoreToStackSlot(), and MI.

Referenced by isStoreToStackSlot().

◆ isStoreToStackSlot() [2/2]

Register RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex,
unsigned MemBytes 
) const
override

Definition at line 129 of file RISCVInstrInfo.cpp.

References MI.

◆ loadRegFromStackSlot()

void RISCVInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
Register  DstReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI,
Register  VReg 
) const
override

◆ movImm()

void RISCVInstrInfo::movImm ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
const DebugLoc DL,
Register  DstReg,
uint64_t  Val,
MachineInstr::MIFlag  Flag = MachineInstr::NoFlags,
bool  DstRenamable = false,
bool  DstIsDead = false 
) const

◆ optimizeCondBranch()

bool RISCVInstrInfo::optimizeCondBranch ( MachineInstr MI) const
override

◆ optimizeSelect()

MachineInstr * RISCVInstrInfo::optimizeSelect ( MachineInstr MI,
SmallPtrSetImpl< MachineInstr * > &  SeenMIs,
bool  PreferFalse 
) const
override

◆ removeBranch()

unsigned RISCVInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ reverseBranchCondition()

bool RISCVInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 1159 of file RISCVInstrInfo.cpp.

References assert(), CC, Cond, and getOppositeBranchCondition().

Referenced by optimizeCondBranch().

◆ shouldClusterMemOps()

bool RISCVInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1,
int64_t  Offset1,
bool  OffsetIsScalable1,
ArrayRef< const MachineOperand * >  BaseOps2,
int64_t  Offset2,
bool  OffsetIsScalable2,
unsigned  ClusterSize,
unsigned  NumBytes 
) const
override

◆ shouldOutlineFromFunctionByDefault()

bool RISCVInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction MF) const
override

◆ storeRegToStackSlot()

void RISCVInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
Register  SrcReg,
bool  IsKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI,
Register  VReg 
) const
override

◆ useMachineCombiner()

bool llvm::RISCVInstrInfo::useMachineCombiner ( ) const
inlineoverride

Definition at line 237 of file RISCVInstrInfo.h.

◆ verifyInstruction()

bool RISCVInstrInfo::verifyInstruction ( const MachineInstr MI,
StringRef ErrInfo 
) const
override

Member Data Documentation

◆ STI

const RISCVSubtarget& llvm::RISCVInstrInfo::STI
protected

The documentation for this class was generated from the following files: