LLVM
15.0.0git
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#include "Target/RISCV/RISCVInstrInfo.h"
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const RISCVSubtarget & | STI |
Definition at line 44 of file RISCVInstrInfo.h.
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Definition at line 56 of file RISCVInstrInfo.cpp.
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Definition at line 752 of file RISCVInstrInfo.cpp.
References Cond, llvm::MachineBasicBlock::end(), getBranchDestBlock(), llvm::HexagonMCInstrInfo::getDesc(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), I, MBB, parseCondBranch(), and llvm::MachineBasicBlock::rend().
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Definition at line 1126 of file RISCVInstrInfo.cpp.
References assert(), getMemOperandWithOffsetWidth(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::max(), llvm::MachineInstr::mayLoadOrStore(), llvm::min(), STI, and TRI.
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Definition at line 1306 of file RISCVInstrInfo.cpp.
References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::RegState::Define, E, llvm::MachineBasicBlock::end(), get, I, llvm::MachineBasicBlock::insert(), and MBB.
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Definition at line 1564 of file RISCVInstrInfo.cpp.
References assert(), CASE_VFMA_CHANGE_OPCODE_LMULS, CASE_VFMA_CHANGE_OPCODE_LMULS_MF4, CASE_VFMA_CHANGE_OPCODE_SPLATS, CASE_VFMA_OPCODE_LMULS, CASE_VFMA_OPCODE_LMULS_MF4, CASE_VFMA_SPLATS, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::X86ISD::FMSUB, llvm::X86ISD::FNMADD, llvm::PPCISD::FNMSUB, get, llvm_unreachable, and MI.
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Definition at line 1700 of file RISCVInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), CASE_WIDEOP_CHANGE_OPCODE_LMULS, CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4, CASE_WIDEOP_OPCODE_LMULS, CASE_WIDEOP_OPCODE_LMULS_MF4, llvm::MachineInstrBuilder::copyImplicitOps(), get, llvm::LiveIntervals::getInterval(), llvm::SlotIndex::getRegSlot(), llvm::LiveRange::getSegmentContaining(), I, llvm_unreachable, MBB, MI, llvm::LiveVariables::replaceKillInstruction(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), and S.
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Definition at line 256 of file RISCVInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), DL, llvm::AArch64SysReg::SysReg::Encoding, get, llvm::getKillRegState(), llvm::MCRegisterInfo::getName(), llvm::RISCVSubtarget::getRegisterInfo(), I, llvm::RegState::Implicit, isConvertibleToVMV_V_V(), llvm_unreachable, llvm::RISCVII::LMUL_1, llvm::RISCVII::LMUL_2, llvm::RISCVII::LMUL_4, llvm::RISCVII::LMUL_8, llvm::AArch64SysReg::lookupSysRegByName(), MBB, MBBI, STI, and TRI.
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Definition at line 1347 of file RISCVInstrInfo.cpp.
References assert(), llvm::TargetInstrInfo::createMIROperandComment(), llvm::raw_ostream::flush(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVVType::isValidSEW(), MI, llvm::MachineOperand::MO_Immediate, llvm::RISCVVType::printVType(), and TRI.
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Definition at line 1158 of file RISCVInstrInfo.cpp.
References llvm::BitmaskEnumDetail::Mask(), and llvm::RISCVII::MO_DIRECT_FLAG_MASK.
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Definition at line 1422 of file RISCVInstrInfo.cpp.
References assert(), CASE_VFMA_OPCODE_LMULS, CASE_VFMA_OPCODE_LMULS_MF4, CASE_VFMA_SPLATS, llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::X86ISD::FMSUB, llvm::X86ISD::FNMADD, llvm::PPCISD::FNMSUB, llvm::RISCVII::hasVecPolicyOp(), llvm::MCInstrDesc::isCommutable(), and MI.
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Definition at line 937 of file RISCVInstrInfo.cpp.
Referenced by analyzeBranch().
const MCInstrDesc & RISCVInstrInfo::getBrCond | ( | RISCVCC::CondCode | CC | ) | const |
Definition at line 714 of file RISCVInstrInfo.cpp.
References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, get, and llvm_unreachable.
Referenced by insertBranch().
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Definition at line 968 of file RISCVInstrInfo.cpp.
References get, llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, MI, MRI, llvm::ARM_MB::ST, STI, and TM.
Referenced by getOutliningCandidateInfo(), insertBranch(), and removeBranch().
bool RISCVInstrInfo::getMemOperandWithOffsetWidth | ( | const MachineInstr & | LdSt, |
const MachineOperand *& | BaseOp, | ||
int64_t & | Offset, | ||
unsigned & | Width, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
Definition at line 1103 of file RISCVInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), and llvm::MachineInstr::memoperands_begin().
Referenced by areMemAccessesTriviallyDisjoint().
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Definition at line 60 of file RISCVInstrInfo.cpp.
References llvm::MCInstBuilder::addImm(), llvm::MCInstBuilder::addReg(), and STI.
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Definition at line 1214 of file RISCVInstrInfo.cpp.
References E, llvm::erase_if(), getInstSizeInBytes(), I, MachineOutlinerDefault, and TRI.
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Definition at line 1253 of file RISCVInstrInfo.cpp.
References llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::IRSimilarity::Illegal, llvm::IRSimilarity::Invisible, llvm::IRSimilarity::Legal, MBB, MBBI, MI, llvm::MachineBasicBlock::succ_empty(), and TRI.
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Definition at line 1164 of file RISCVInstrInfo.cpp.
References llvm::makeArrayRef(), llvm::RISCVII::MO_CALL, llvm::RISCVII::MO_GOT_HI, llvm::AVRII::MO_HI, llvm::AVRII::MO_LO, llvm::RISCVII::MO_PCREL_HI, llvm::RISCVII::MO_PCREL_LO, llvm::M68kII::MO_PLT, llvm::RISCVII::MO_TLS_GD_HI, llvm::RISCVII::MO_TLS_GOT_HI, llvm::RISCVII::MO_TPREL_ADD, llvm::MipsII::MO_TPREL_HI, and llvm::MipsII::MO_TPREL_LO.
Register RISCVInstrInfo::getVLENFactoredAmount | ( | MachineFunction & | MF, |
MachineBasicBlock & | MBB, | ||
MachineBasicBlock::iterator | II, | ||
const DebugLoc & | DL, | ||
int64_t | Amount, | ||
MachineInstr::MIFlag | Flag = MachineInstr::NoFlags |
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) | const |
Definition at line 1770 of file RISCVInstrInfo.cpp.
References llvm::ISD::ADD, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::LLVMContext::diagnose(), DL, get, llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getRegInfo(), llvm::RISCVSubtarget::hasStdExtM(), llvm::RISCVSubtarget::hasStdExtZba(), llvm::isInt< 32 >(), llvm::isPowerOf2_32(), llvm::RegState::Kill, llvm_unreachable, llvm::Log2_32(), MBB, movImm(), MRI, llvm::ISD::MUL, N, llvm::MachineInstrBuilder::setMIFlag(), STI, and llvm::ISD::SUB.
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Definition at line 854 of file RISCVInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, get, getBrCond(), getInstSizeInBytes(), MBB, and MI.
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Definition at line 891 of file RISCVInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearVirtRegs(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), get, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::isInt< 32 >(), MBB, MI, llvm::RISCVII::MO_CALL, MRI, llvm::MachineBasicBlock::pred_size(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegisterBackwards(), and llvm::RegScavenger::setRegUsed().
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Definition at line 1334 of file RISCVInstrInfo.cpp.
References llvm::BuildMI(), get, llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), M, MBB, and llvm::RISCVII::MO_CALL.
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Definition at line 994 of file RISCVInstrInfo.cpp.
References MI.
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Definition at line 944 of file RISCVInstrInfo.cpp.
References llvm::RISCVSubtarget::getXLen(), llvm::isIntN(), llvm_unreachable, llvm::SignExtend64(), and STI.
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Definition at line 1016 of file RISCVInstrInfo.cpp.
References MI, and llvm::None.
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Definition at line 1181 of file RISCVInstrInfo.cpp.
References F, and llvm::MachineFunction::getFunction().
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Definition at line 69 of file RISCVInstrInfo.cpp.
References llvm::X86ISD::FLD, llvm::ISD::FrameIndex, llvm::ARM_MB::LD, and MI.
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Definition at line 1198 of file RISCVInstrInfo.cpp.
References llvm::TargetInstrInfo::isMBBSafeToOutlineFrom(), and MBB.
bool RISCVInstrInfo::isRVVSpill | ( | const MachineInstr & | MI, |
bool | CheckFIs | ||
) | const |
Definition at line 1877 of file RISCVInstrInfo.cpp.
References llvm::any_of(), isRVVSpillForZvlsseg(), isRVVWholeLoadStore(), and MI.
Optional< std::pair< unsigned, unsigned > > RISCVInstrInfo::isRVVSpillForZvlsseg | ( | unsigned | Opcode | ) | const |
Definition at line 1890 of file RISCVInstrInfo.cpp.
References llvm::None.
Referenced by isRVVSpill().
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Definition at line 96 of file RISCVInstrInfo.cpp.
References llvm::ISD::FrameIndex, and MI.
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Definition at line 548 of file RISCVInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::X86ISD::FLD, get, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getRegSizeInBits(), I, llvm::ARM_MB::LD, llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), TRI, and llvm::MemoryLocation::UnknownSize.
void RISCVInstrInfo::movImm | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | MBBI, | ||
const DebugLoc & | DL, | ||
Register | DstReg, | ||
uint64_t | Val, | ||
MachineInstr::MIFlag | Flag = MachineInstr::NoFlags |
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) | const |
Definition at line 640 of file RISCVInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::RISCVMatInt::generateInstSeq(), get, llvm::RISCVSubtarget::is64Bit(), llvm::isInt< 32 >(), llvm::RegState::Kill, MBB, MBBI, llvm::report_fatal_error(), llvm::MachineInstrBuilder::setMIFlag(), and STI.
Referenced by getVLENFactoredAmount().
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Definition at line 820 of file RISCVInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), getInstSizeInBytes(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, and MBB.
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Definition at line 928 of file RISCVInstrInfo.cpp.
References assert(), Cond, and getOppositeBranchCondition().
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Definition at line 1209 of file RISCVInstrInfo.cpp.
References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().
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Definition at line 454 of file RISCVInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), get, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getRegSizeInBits(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), TRI, and llvm::MemoryLocation::UnknownSize.
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Definition at line 1040 of file RISCVInstrInfo.cpp.
References llvm::enumerate(), llvm::MCInstrInfo::get(), llvm::MachineOperand::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::MachineOperand::isImm(), llvm_unreachable, MI, llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM, llvm::RISCVOp::OPERAND_LAST_RISCV_IMM, llvm::RISCVOp::OPERAND_RVKRNUM, llvm::RISCVOp::OPERAND_SIMM12, llvm::RISCVOp::OPERAND_UIMM12, llvm::RISCVOp::OPERAND_UIMM2, llvm::RISCVOp::OPERAND_UIMM20, llvm::RISCVOp::OPERAND_UIMM3, llvm::RISCVOp::OPERAND_UIMM4, llvm::RISCVOp::OPERAND_UIMM5, llvm::RISCVOp::OPERAND_UIMM7, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN, llvm::MCInstrDesc::operands(), and STI.
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Definition at line 189 of file RISCVInstrInfo.h.
Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), getInstSizeInBytes(), getNop(), getVLENFactoredAmount(), isBranchOffsetInRange(), movImm(), and verifyInstruction().