llvm::RISCVInstrInfo Class Reference

#include "Target/RISCV/RISCVInstrInfo.h"

Inheritance diagram for llvm::RISCVInstrInfo:

Collaboration diagram for llvm::RISCVInstrInfo:

Public Member Functions
	RISCVInstrInfo (RISCVSubtarget &STI)
MCInst	getNop () const override
const MCInstrDesc &	getBrCond (RISCVCC::CondCode CC) const
unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	movImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void	insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override
bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
bool	isAsCheapAsAMove (const MachineInstr &MI) const override
Optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
bool	getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
virtual bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
virtual bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
outliner::OutlinedFunction	getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
virtual outliner::InstrType	getOutliningType (MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
virtual void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
virtual MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
MachineInstr *	convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
std::string	createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
Register	getVLENFactoredAmount (MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
bool	isRVVSpill (const MachineInstr &MI, bool CheckFIs) const
Optional< std::pair< unsigned, unsigned > >	isRVVSpillForZvlsseg (unsigned Opcode) const

Protected Attributes
const RISCVSubtarget &	STI

Detailed Description

Definition at line 44 of file RISCVInstrInfo.h.

Constructor & Destructor Documentation

RISCVInstrInfo()

RISCVInstrInfo::RISCVInstrInfo ( RISCVSubtarget &  STI )

explicit

Definition at line 56 of file RISCVInstrInfo.cpp.

Member Function Documentation

analyzeBranch()

bool RISCVInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *&  TBB, MachineBasicBlock *&  FBB, SmallVectorImpl< MachineOperand > &  Cond, bool  AllowModify  ) const

override

Definition at line 752 of file RISCVInstrInfo.cpp.

References Cond, llvm::MachineBasicBlock::end(), getBranchDestBlock(), llvm::HexagonMCInstrInfo::getDesc(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), I, MBB, parseCondBranch(), and llvm::MachineBasicBlock::rend().

areMemAccessesTriviallyDisjoint()

bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr &  MIa, const MachineInstr &  MIb  ) const

override

Definition at line 1126 of file RISCVInstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::max(), llvm::MachineInstr::mayLoadOrStore(), llvm::min(), STI, and TRI.

buildOutlinedFrame()

void RISCVInstrInfo::buildOutlinedFrame ( MachineBasicBlock &  MBB, MachineFunction &  MF, const outliner::OutlinedFunction &  OF  ) const

overridevirtual

Definition at line 1306 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::RegState::Define, E, llvm::MachineBasicBlock::end(), get, I, llvm::MachineBasicBlock::insert(), and MBB.

commuteInstructionImpl()

MachineInstr * RISCVInstrInfo::commuteInstructionImpl ( MachineInstr &  MI, bool  NewMI, unsigned  OpIdx1, unsigned  OpIdx2  ) const

override

Definition at line 1564 of file RISCVInstrInfo.cpp.

References assert(), CASE_VFMA_CHANGE_OPCODE_LMULS, CASE_VFMA_CHANGE_OPCODE_LMULS_MF4, CASE_VFMA_CHANGE_OPCODE_SPLATS, CASE_VFMA_OPCODE_LMULS, CASE_VFMA_OPCODE_LMULS_MF4, CASE_VFMA_SPLATS, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::X86ISD::FMSUB, llvm::X86ISD::FNMADD, llvm::PPCISD::FNMSUB, get, llvm_unreachable, and MI.

convertToThreeAddress()

MachineInstr * RISCVInstrInfo::convertToThreeAddress ( MachineInstr &  MI, LiveVariables *  LV, LiveIntervals *  LIS  ) const

override

Definition at line 1700 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), CASE_WIDEOP_CHANGE_OPCODE_LMULS, CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4, CASE_WIDEOP_OPCODE_LMULS, CASE_WIDEOP_OPCODE_LMULS_MF4, llvm::MachineInstrBuilder::copyImplicitOps(), get, llvm::LiveIntervals::getInterval(), llvm::SlotIndex::getRegSlot(), llvm::LiveRange::getSegmentContaining(), I, llvm_unreachable, MBB, MI, llvm::LiveVariables::replaceKillInstruction(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), and S.

copyPhysReg()

void RISCVInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, const DebugLoc &  DL, MCRegister  DstReg, MCRegister  SrcReg, bool  KillSrc  ) const

override

Definition at line 256 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), DL, llvm::AArch64SysReg::SysReg::Encoding, get, llvm::getKillRegState(), llvm::MCRegisterInfo::getName(), llvm::RISCVSubtarget::getRegisterInfo(), I, llvm::RegState::Implicit, isConvertibleToVMV_V_V(), llvm_unreachable, llvm::RISCVII::LMUL_1, llvm::RISCVII::LMUL_2, llvm::RISCVII::LMUL_4, llvm::RISCVII::LMUL_8, llvm::AArch64SysReg::lookupSysRegByName(), MBB, MBBI, STI, and TRI.

createMIROperandComment()

std::string RISCVInstrInfo::createMIROperandComment ( const MachineInstr &  MI, const MachineOperand &  Op, unsigned  OpIdx, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 1347 of file RISCVInstrInfo.cpp.

References assert(), llvm::TargetInstrInfo::createMIROperandComment(), llvm::raw_ostream::flush(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVVType::isValidSEW(), MI, llvm::MachineOperand::MO_Immediate, llvm::RISCVVType::printVType(), and TRI.

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > RISCVInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF ) const

override

Definition at line 1158 of file RISCVInstrInfo.cpp.

References llvm::BitmaskEnumDetail::Mask(), and llvm::RISCVII::MO_DIRECT_FLAG_MASK.

findCommutedOpIndices()

bool RISCVInstrInfo::findCommutedOpIndices ( const MachineInstr &  MI, unsigned &  SrcOpIdx1, unsigned &  SrcOpIdx2  ) const

override

Definition at line 1422 of file RISCVInstrInfo.cpp.

References assert(), CASE_VFMA_OPCODE_LMULS, CASE_VFMA_OPCODE_LMULS_MF4, CASE_VFMA_SPLATS, llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::X86ISD::FMSUB, llvm::X86ISD::FNMADD, llvm::PPCISD::FNMSUB, llvm::RISCVII::hasVecPolicyOp(), llvm::MCInstrDesc::isCommutable(), and MI.

getBranchDestBlock()

MachineBasicBlock * RISCVInstrInfo::getBranchDestBlock ( const MachineInstr &  MI ) const

override

Definition at line 937 of file RISCVInstrInfo.cpp.

References assert(), and MI.

Referenced by analyzeBranch().

getBrCond()

const MCInstrDesc & RISCVInstrInfo::getBrCond

(

RISCVCC::CondCode

CC

)

const

Definition at line 714 of file RISCVInstrInfo.cpp.

References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, get, and llvm_unreachable.

Referenced by insertBranch().

getInstSizeInBytes()

unsigned RISCVInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI ) const

override

Definition at line 968 of file RISCVInstrInfo.cpp.

References get, llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, MI, MRI, llvm::ARM_MB::ST, STI, and TM.

Referenced by getOutliningCandidateInfo(), insertBranch(), and removeBranch().

getMemOperandWithOffsetWidth()

bool RISCVInstrInfo::getMemOperandWithOffsetWidth	(	const MachineInstr &	LdSt,
		const MachineOperand *&	BaseOp,
		int64_t &	Offset,
		unsigned &	Width,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 1103 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), and llvm::MachineInstr::memoperands_begin().

Referenced by areMemAccessesTriviallyDisjoint().

getNop()

MCInst RISCVInstrInfo::getNop ( ) const

override

Definition at line 60 of file RISCVInstrInfo.cpp.

References llvm::MCInstBuilder::addImm(), llvm::MCInstBuilder::addReg(), and STI.

getOutliningCandidateInfo()

outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo ( std::vector< outliner::Candidate > &  RepeatedSequenceLocs ) const

override

Definition at line 1214 of file RISCVInstrInfo.cpp.

References E, llvm::erase_if(), getInstSizeInBytes(), I, MachineOutlinerDefault, and TRI.

getOutliningType()

outliner::InstrType RISCVInstrInfo::getOutliningType ( MachineBasicBlock::iterator &  MBBI, unsigned  Flags  ) const

overridevirtual

Definition at line 1253 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::IRSimilarity::Illegal, llvm::IRSimilarity::Invisible, llvm::IRSimilarity::Legal, MBB, MBBI, MI, llvm::MachineBasicBlock::succ_empty(), and TRI.

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 1164 of file RISCVInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::RISCVII::MO_CALL, llvm::RISCVII::MO_GOT_HI, llvm::AVRII::MO_HI, llvm::AVRII::MO_LO, llvm::RISCVII::MO_PCREL_HI, llvm::RISCVII::MO_PCREL_LO, llvm::M68kII::MO_PLT, llvm::RISCVII::MO_TLS_GD_HI, llvm::RISCVII::MO_TLS_GOT_HI, llvm::RISCVII::MO_TPREL_ADD, llvm::MipsII::MO_TPREL_HI, and llvm::MipsII::MO_TPREL_LO.

getVLENFactoredAmount()

Register RISCVInstrInfo::getVLENFactoredAmount	(	MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	II,
		const DebugLoc &	DL,
		int64_t	Amount,
		MachineInstr::MIFlag	Flag = MachineInstr::NoFlags
	)		const

Definition at line 1770 of file RISCVInstrInfo.cpp.

References llvm::ISD::ADD, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::LLVMContext::diagnose(), DL, get, llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getRegInfo(), llvm::RISCVSubtarget::hasStdExtM(), llvm::RISCVSubtarget::hasStdExtZba(), llvm::isInt< 32 >(), llvm::isPowerOf2_32(), llvm::RegState::Kill, llvm_unreachable, llvm::Log2_32(), MBB, movImm(), MRI, llvm::ISD::MUL, N, llvm::MachineInstrBuilder::setMIFlag(), STI, and llvm::ISD::SUB.

insertBranch()

unsigned RISCVInstrInfo::insertBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *  TBB, MachineBasicBlock *  FBB, ArrayRef< MachineOperand >  Cond, const DebugLoc &  dl, int *  BytesAdded = nullptr  ) const

override

Definition at line 854 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, get, getBrCond(), getInstSizeInBytes(), MBB, and MI.

insertIndirectBranch()

void RISCVInstrInfo::insertIndirectBranch ( MachineBasicBlock &  MBB, MachineBasicBlock &  NewDestBB, MachineBasicBlock &  RestoreBB, const DebugLoc &  DL, int64_t  BrOffset, RegScavenger *  RS  ) const

override

Definition at line 891 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearVirtRegs(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), get, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::isInt< 32 >(), MBB, MI, llvm::RISCVII::MO_CALL, MRI, llvm::MachineBasicBlock::pred_size(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegisterBackwards(), and llvm::RegScavenger::setRegUsed().

insertOutlinedCall()

MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall ( Module &  M, MachineBasicBlock &  MBB, MachineBasicBlock::iterator &  It, MachineFunction &  MF, outliner::Candidate &  C  ) const

overridevirtual

Definition at line 1334 of file RISCVInstrInfo.cpp.

References llvm::BuildMI(), get, llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), M, MBB, and llvm::RISCVII::MO_CALL.

isAsCheapAsAMove()

bool RISCVInstrInfo::isAsCheapAsAMove ( const MachineInstr &  MI ) const

override

Definition at line 994 of file RISCVInstrInfo.cpp.

References MI.

isBranchOffsetInRange()

bool RISCVInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc, int64_t  BrOffset  ) const

override

Definition at line 944 of file RISCVInstrInfo.cpp.

References llvm::RISCVSubtarget::getXLen(), llvm::isIntN(), llvm_unreachable, llvm::SignExtend64(), and STI.

isCopyInstrImpl()

Optional< DestSourcePair > RISCVInstrInfo::isCopyInstrImpl ( const MachineInstr &  MI ) const

override

Definition at line 1016 of file RISCVInstrInfo.cpp.

References MI, and llvm::None.

isFunctionSafeToOutlineFrom()

bool RISCVInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction &  MF, bool  OutlineFromLinkOnceODRs  ) const

overridevirtual

Definition at line 1181 of file RISCVInstrInfo.cpp.

References F, and llvm::MachineFunction::getFunction().

isLoadFromStackSlot()

unsigned RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 69 of file RISCVInstrInfo.cpp.

References llvm::X86ISD::FLD, llvm::ISD::FrameIndex, llvm::ARM_MB::LD, and MI.

isMBBSafeToOutlineFrom()

bool RISCVInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock &  MBB, unsigned &  Flags  ) const

overridevirtual

Definition at line 1198 of file RISCVInstrInfo.cpp.

References llvm::TargetInstrInfo::isMBBSafeToOutlineFrom(), and MBB.

isRVVSpill()

bool RISCVInstrInfo::isRVVSpill	(	const MachineInstr &	MI,
		bool	CheckFIs
	)		const

Definition at line 1877 of file RISCVInstrInfo.cpp.

References llvm::any_of(), isRVVSpillForZvlsseg(), isRVVWholeLoadStore(), and MI.

isRVVSpillForZvlsseg()

Optional< std::pair< unsigned, unsigned > > RISCVInstrInfo::isRVVSpillForZvlsseg

(

unsigned

Opcode

)

const

Definition at line 1890 of file RISCVInstrInfo.cpp.

References llvm::None.

Referenced by isRVVSpill().

isStoreToStackSlot()

unsigned RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 96 of file RISCVInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

loadRegFromStackSlot()

void RISCVInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  DstReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 548 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::X86ISD::FLD, get, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getRegSizeInBits(), I, llvm::ARM_MB::LD, llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), TRI, and llvm::MemoryLocation::UnknownSize.

movImm()

void RISCVInstrInfo::movImm	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		Register	DstReg,
		uint64_t	Val,
		MachineInstr::MIFlag	Flag = MachineInstr::NoFlags
	)		const

Definition at line 640 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::RISCVMatInt::generateInstSeq(), get, llvm::RISCVSubtarget::is64Bit(), llvm::isInt< 32 >(), llvm::RegState::Kill, MBB, MBBI, llvm::report_fatal_error(), llvm::MachineInstrBuilder::setMIFlag(), and STI.

Referenced by getVLENFactoredAmount().

removeBranch()

unsigned RISCVInstrInfo::removeBranch ( MachineBasicBlock &  MBB, int *  BytesRemoved = nullptr  ) const

override

Definition at line 820 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), getInstSizeInBytes(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, and MBB.

reverseBranchCondition()

bool RISCVInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond ) const

override

Definition at line 928 of file RISCVInstrInfo.cpp.

References assert(), Cond, and getOppositeBranchCondition().

shouldOutlineFromFunctionByDefault()

bool RISCVInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction &  MF ) const

override

Definition at line 1209 of file RISCVInstrInfo.cpp.

References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().

storeRegToStackSlot()

void RISCVInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  SrcReg, bool  IsKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 454 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), get, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getRegSizeInBits(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), TRI, and llvm::MemoryLocation::UnknownSize.

verifyInstruction()

bool RISCVInstrInfo::verifyInstruction ( const MachineInstr &  MI, StringRef &  ErrInfo  ) const

override

Definition at line 1040 of file RISCVInstrInfo.cpp.

References llvm::enumerate(), llvm::MCInstrInfo::get(), llvm::MachineOperand::getImm(), llvm::RISCVSubtarget::getInstrInfo(), llvm::MachineOperand::isImm(), llvm_unreachable, MI, llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM, llvm::RISCVOp::OPERAND_LAST_RISCV_IMM, llvm::RISCVOp::OPERAND_RVKRNUM, llvm::RISCVOp::OPERAND_SIMM12, llvm::RISCVOp::OPERAND_UIMM12, llvm::RISCVOp::OPERAND_UIMM2, llvm::RISCVOp::OPERAND_UIMM20, llvm::RISCVOp::OPERAND_UIMM3, llvm::RISCVOp::OPERAND_UIMM4, llvm::RISCVOp::OPERAND_UIMM5, llvm::RISCVOp::OPERAND_UIMM7, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN, llvm::MCInstrDesc::operands(), and STI.

Member Data Documentation

STI

const RISCVSubtarget& llvm::RISCVInstrInfo::STI

protected

Definition at line 189 of file RISCVInstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), getInstSizeInBytes(), getNop(), getVLENFactoredAmount(), isBranchOffsetInRange(), movImm(), and verifyInstruction().

---

The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVInstrInfo.h
• lib/Target/RISCV/RISCVInstrInfo.cpp