llvm::RISCVInstrInfo Class Reference

#include "Target/RISCV/RISCVInstrInfo.h"

Inheritance diagram for llvm::RISCVInstrInfo:

Public Member Functions
	RISCVInstrInfo (RISCVSubtarget &STI)
MCInst	getNop () const override
const MCInstrDesc &	getBrCond (RISCVCC::CondCode CC, bool Imm=false) const
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override
bool	isReallyTriviallyReMaterializable (const MachineInstr &MI) const override
bool	shouldBreakCriticalEdgeToSink (MachineInstr &MI) const override
void	copyPhysRegVector (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RegClass) const
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
void	movImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void	insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	optimizeCondBranch (MachineInstr &MI) const override
MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override
bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
bool	analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
MachineInstr *	optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool	isAsCheapAsAMove (const MachineInstr &MI) const override
std::optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
bool	canFoldIntoAddrMode (const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
MachineInstr *	emitLdStWithAddr (MachineInstr &MemI, const ExtAddrMode &AM) const override
bool	getMemOperandsWithOffsetWidth (const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
bool	shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
bool	getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const
bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
std::optional< std::unique_ptr< outliner::OutlinedFunction > >	getOutliningCandidateInfo (const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override
virtual outliner::InstrType	getOutliningTypeImpl (const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
std::optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override
bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
MachineInstr *	convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
std::string	createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
void	mulImm (MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const
	Generate code to multiply the value in DestReg by Amt - handles all the common optimizations for this idiom, and supports fallback for subtargets which don't support multiply instructions.
bool	useMachineCombiner () const override
MachineTraceStrategy	getMachineCombinerTraceStrategy () const override
CombinerObjective	getCombinerObjective (unsigned Pattern) const override
bool	getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
void	finalizeInsInstrs (MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
void	genAlternativeCodeSequence (MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
bool	hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
bool	hasReassociableSibling (const MachineInstr &Inst, bool &Commuted) const override
bool	isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override
std::optional< unsigned >	getInverseOpcode (unsigned Opcode) const override
void	getReassociateOperandIndices (const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > >	getSerializableMachineMemOperandTargetFlags () const override
unsigned	getTailDuplicateSize (CodeGenOptLevel OptLevel) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
	Target-dependent implementation for foldMemoryOperand.
virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
	Target-dependent implementation for foldMemoryOperand.

Protected Attributes
const RISCVSubtarget &	STI

Detailed Description

Definition at line 62 of file RISCVInstrInfo.h.

Constructor & Destructor Documentation

RISCVInstrInfo()

RISCVInstrInfo::RISCVInstrInfo ( RISCVSubtarget &  STI )

explicit

Definition at line 76 of file RISCVInstrInfo.cpp.

Member Function Documentation

analyzeBranch()

bool RISCVInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *&  TBB, MachineBasicBlock *&  FBB, SmallVectorImpl< MachineOperand > &  Cond, bool  AllowModify  ) const

override

Definition at line 995 of file RISCVInstrInfo.cpp.

References Cond, llvm::MachineBasicBlock::end(), getBranchDestBlock(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), I, MBB, parseCondBranch(), llvm::MachineBasicBlock::rend(), and TBB.

Referenced by analyzeLoopForPipelining(), and optimizeCondBranch().

analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > RISCVInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock *  LoopBB ) const

override

Definition at line 4292 of file RISCVInstrInfo.cpp.

References analyzeBranch(), assert(), Cond, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), LHS, MRI, reverseBranchCondition(), RHS, and TBB.

analyzeSelect()

bool RISCVInstrInfo::analyzeSelect ( const MachineInstr &  MI, SmallVectorImpl< MachineOperand > &  Cond, unsigned &  TrueOp, unsigned &  FalseOp, bool &  Optimizable  ) const

override

Definition at line 1442 of file RISCVInstrInfo.cpp.

References assert(), Cond, MI, and STI.

areMemAccessesTriviallyDisjoint()

bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr &  MIa, const MachineInstr &  MIb  ) const

override

Definition at line 2876 of file RISCVInstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::LocationSize::getValue(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::LocationSize::hasValue(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::mayLoadOrStore(), STI, and TRI.

buildOutlinedFrame()

void RISCVInstrInfo::buildOutlinedFrame ( MachineBasicBlock &  MBB, MachineFunction &  MF, const outliner::OutlinedFunction &  OF  ) const

override

Definition at line 3119 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::outliner::OutlinedFunction::FrameConstructionID, llvm::get(), I, llvm::MachineBasicBlock::insert(), MachineOutlinerTailCall, and MBB.

canFoldIntoAddrMode()

bool RISCVInstrInfo::canFoldIntoAddrMode ( const MachineInstr &  MemI, Register  Reg, const MachineInstr &  AddrI, ExtAddrMode &  AM  ) const

override

Definition at line 2671 of file RISCVInstrInfo.cpp.

References llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Basic, llvm::ExtAddrMode::Displacement, llvm::ExtAddrMode::Form, llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::RISCVSubtarget::is64Bit(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, and STI.

commuteInstructionImpl()

MachineInstr * RISCVInstrInfo::commuteInstructionImpl ( MachineInstr &  MI, bool  NewMI, unsigned  OpIdx1, unsigned  OpIdx2  ) const

override

Definition at line 3558 of file RISCVInstrInfo.cpp.

References assert(), CASE_VFMA_CHANGE_OPCODE_SPLATS, CASE_VFMA_CHANGE_OPCODE_VV, CASE_VFMA_OPCODE_VV, CASE_VFMA_SPLATS, CASE_VMA_CHANGE_OPCODE_LMULS, CASE_VMA_OPCODE_LMULS, CC, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::FMSUB, llvm::FNMADD, llvm::FNMSUB, llvm::get(), llvm::RISCVCC::getOppositeBranchCondition(), llvm_unreachable, and MI.

convertToThreeAddress()

MachineInstr * RISCVInstrInfo::convertToThreeAddress ( MachineInstr &  MI, LiveVariables *  LV, LiveIntervals *  LIS  ) const

override

Definition at line 3761 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4, CASE_FP_WIDEOP_OPCODE_LMULS_MF4, CASE_WIDEOP_CHANGE_OPCODE_LMULS, CASE_WIDEOP_OPCODE_LMULS, llvm::MachineInstrBuilder::copyImplicitOps(), llvm::LiveRange::Segment::end, llvm::get(), llvm::LiveIntervals::getInterval(), llvm::LiveRange::getSegmentContaining(), llvm::RISCVII::getVecPolicyOpNum(), llvm::RISCVII::hasVecPolicyOp(), I, Idx, llvm_unreachable, MBB, MI, llvm::LiveVariables::replaceKillInstruction(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), and llvm::RegState::Undef.

copyPhysReg()

void RISCVInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, const DebugLoc &  DL, MCRegister  DstReg, MCRegister  SrcReg, bool  KillSrc, bool  RenamableDest = false, bool  RenamableSrc = false  ) const

override

Definition at line 448 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyPhysRegVector(), DL, llvm::get(), llvm::getKillRegState(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::getRenamableRegState(), llvm::RISCVSubtarget::getXLen(), llvm_unreachable, MBB, MBBI, STI, and TRI.

copyPhysRegVector()

void RISCVInstrInfo::copyPhysRegVector	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		MCRegister	DstReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		const TargetRegisterClass *	RegClass
	)		const

Definition at line 324 of file RISCVInstrInfo.cpp.

References _, assert(), llvm::BuildMI(), llvm::RISCVVType::decodeVLMUL(), DL, forwardCopyWillClobberTuple(), llvm::get(), llvm::getKillRegState(), llvm::RISCVRI::getLMul(), llvm::RISCVRI::getNF(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::getVLOpNum(), I, llvm::RegState::Implicit, isConvertibleToVMV_V_V(), llvm::RISCVII::LMUL_1, llvm::RISCVII::LMUL_2, llvm::RISCVII::LMUL_4, llvm::RISCVII::LMUL_8, MBB, MBBI, STI, TRI, llvm::TargetRegisterClass::TSFlags, and llvm::RegState::Undef.

Referenced by copyPhysReg().

createMIROperandComment()

std::string RISCVInstrInfo::createMIROperandComment ( const MachineInstr &  MI, const MachineOperand &  Op, unsigned  OpIdx, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 3187 of file RISCVInstrInfo.cpp.

References assert(), llvm::TargetInstrInfo::createMIROperandComment(), llvm::RISCVVType::isValidSEW(), llvm::RISCVII::MASK_AGNOSTIC, MI, llvm::RISCVOp::OPERAND_SEW, llvm::RISCVOp::OPERAND_SEW_MASK, llvm::RISCVOp::OPERAND_VEC_POLICY, llvm::RISCVOp::OPERAND_VTYPEI10, llvm::RISCVOp::OPERAND_VTYPEI11, llvm::MCOperandInfo::OperandType, OS, llvm::RISCVVType::printVType(), llvm::RISCVII::TAIL_AGNOSTIC, and TRI.

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > RISCVInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF ) const

override

Definition at line 2909 of file RISCVInstrInfo.cpp.

References llvm::RISCVII::MO_DIRECT_FLAG_MASK.

emitLdStWithAddr()

MachineInstr * RISCVInstrInfo::emitLdStWithAddr ( MachineInstr &  MemI, const ExtAddrMode &  AM  ) const

override

Definition at line 2725 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::ExtAddrMode::BaseReg, llvm::BuildMI(), llvm::RegState::Define, llvm::ExtAddrMode::Displacement, DL, llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::mayLoad(), MBB, llvm::MachineInstr::memoperands(), llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, llvm::MachineInstrBuilder::setMemRefs(), and llvm::MachineInstrBuilder::setMIFlags().

finalizeInsInstrs()

void RISCVInstrInfo::finalizeInsInstrs ( MachineInstr &  Root, unsigned &  Pattern, SmallVectorImpl< MachineInstr * > &  InsInstrs  ) const

override

Definition at line 1685 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addUse(), llvm::all_of(), assert(), llvm::RISCVFPRndMode::DYN, llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::RISCV::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RegState::Implicit, and MI.

findCommutedOpIndices()

bool RISCVInstrInfo::findCommutedOpIndices ( const MachineInstr &  MI, unsigned &  SrcOpIdx1, unsigned &  SrcOpIdx2  ) const

override

Definition at line 3333 of file RISCVInstrInfo.cpp.

References assert(), CASE_RVV_OPCODE, CASE_RVV_OPCODE_MASK, CASE_RVV_OPCODE_UNMASK, CASE_RVV_OPCODE_WIDEN, CASE_VFMA_OPCODE_VV, CASE_VFMA_SPLATS, CASE_VMA_OPCODE_LMULS, llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::FMSUB, llvm::FNMADD, llvm::FNMSUB, llvm::RISCVII::hasVecPolicyOp(), and MI.

foldMemoryOperandImpl() [1/3]

virtual MachineInstr * llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF, MachineInstr &  MI, ArrayRef< unsigned >  Ops, MachineBasicBlock::iterator  InsertPt, int  FrameIndex, LiveIntervals *  LIS = nullptr, VirtRegMap *  VRM = nullptr  ) const

inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1362 of file TargetInstrInfo.h.

foldMemoryOperandImpl() [2/3]

MachineInstr * RISCVInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF, MachineInstr &  MI, ArrayRef< unsigned >  Ops, MachineBasicBlock::iterator  InsertPt, int  FrameIndex, LiveIntervals *  LIS = nullptr, VirtRegMap *  VRM = nullptr  ) const

override

Definition at line 759 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::get(), llvm::MachineFunction::getDataLayout(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVSubtarget::getXLen(), llvm::DataLayout::isBigEndian(), llvm::RISCV::isSEXT_W(), llvm::RISCV::isZEXT_B(), llvm::RISCV::isZEXT_W(), llvm_unreachable, MI, llvm::ArrayRef< T >::size(), and STI.

foldMemoryOperandImpl() [3/3]

virtual MachineInstr * llvm::TargetInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF, MachineInstr &  MI, ArrayRef< unsigned >  Ops, MachineBasicBlock::iterator  InsertPt, MachineInstr &  LoadMI, LiveIntervals *  LIS = nullptr  ) const

inline

Target-dependent implementation for foldMemoryOperand.

Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.

Definition at line 1375 of file TargetInstrInfo.h.

genAlternativeCodeSequence()

void RISCVInstrInfo::genAlternativeCodeSequence ( MachineInstr &  Root, unsigned  Pattern, SmallVectorImpl< MachineInstr * > &  InsInstrs, SmallVectorImpl< MachineInstr * > &  DelInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg  ) const

override

Definition at line 2413 of file RISCVInstrInfo.cpp.

References combineFPFusedMultiply(), llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genShXAddAddShift(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), MRI, llvm::SHXADD_ADD_SLLI_OP1, and llvm::SHXADD_ADD_SLLI_OP2.

getBranchDestBlock()

MachineBasicBlock * RISCVInstrInfo::getBranchDestBlock ( const MachineInstr &  MI ) const

override

Definition at line 1327 of file RISCVInstrInfo.cpp.

References assert(), and MI.

Referenced by analyzeBranch().

getBrCond()

const MCInstrDesc & RISCVInstrInfo::getBrCond	(	RISCVCC::CondCode	CC,
		bool	Imm = false
	)		const

Definition at line 971 of file RISCVInstrInfo.cpp.

References CC, llvm::get(), and llvm::RISCVCC::getBrCond().

Referenced by insertBranch(), and optimizeCondBranch().

getCombinerObjective()

CombinerObjective RISCVInstrInfo::getCombinerObjective ( unsigned  Pattern ) const

override

Definition at line 2248 of file RISCVInstrInfo.cpp.

References llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::TargetInstrInfo::getCombinerObjective(), and llvm::MustReduceDepth.

getInstSizeInBytes()

unsigned RISCVInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI ) const

override

Definition at line 1531 of file RISCVInstrInfo.cpp.

References F, llvm::get(), llvm::MachineFunction::getFunction(), llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::StatepointOpers::getNumPatchBytes(), llvm::MachineFunction::getTarget(), llvm::RISCVSubtarget::hasStdExtCOrZca(), llvm::RISCVSubtarget::is64Bit(), llvm::MachineMemOperand::isNonTemporal(), MI, and STI.

Referenced by getOutliningCandidateInfo(), insertBranch(), and removeBranch().

getInverseOpcode()

std::optional< unsigned > RISCVInstrInfo::getInverseOpcode ( unsigned  Opcode ) const

override

Definition at line 2045 of file RISCVInstrInfo.cpp.

References RVV_OPC_LMUL_CASE, and RVV_OPC_LMUL_MASK_CASE.

Referenced by isAssociativeAndCommutative().

getMachineCombinerPatterns()

bool RISCVInstrInfo::getMachineCombinerPatterns ( MachineInstr &  Root, SmallVectorImpl< unsigned > &  Patterns, bool  DoRegPressureReduce  ) const

override

Definition at line 2260 of file RISCVInstrInfo.cpp.

References getFPPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), and getSHXADDPatterns().

getMachineCombinerTraceStrategy()

MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy ( ) const

override

Definition at line 1671 of file RISCVInstrInfo.cpp.

References ForceMachineCombinerStrategy, STI, llvm::TS_Local, and llvm::TS_MinInstrCount.

getMemOperandsWithOffsetWidth()

bool RISCVInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr &  MI, SmallVectorImpl< const MachineOperand * > &  BaseOps, int64_t &  Offset, bool &  OffsetIsScalable, LocationSize &  Width, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 2743 of file RISCVInstrInfo.cpp.

References getMemOperandWithOffsetWidth(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::mayLoadOrStore(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.

getMemOperandWithOffsetWidth()

bool RISCVInstrInfo::getMemOperandWithOffsetWidth	(	const MachineInstr &	LdSt,
		const MachineOperand *&	BaseOp,
		int64_t &	Offset,
		LocationSize &	Width,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 2852 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), getSize(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::memoperands_begin(), and llvm::Offset.

Referenced by areMemAccessesTriviallyDisjoint(), and getMemOperandsWithOffsetWidth().

getNop()

MCInst RISCVInstrInfo::getNop ( ) const

override

Definition at line 80 of file RISCVInstrInfo.cpp.

References llvm::MCInstBuilder::addImm(), llvm::MCInstBuilder::addReg(), llvm::RISCVSubtarget::hasStdExtCOrZca(), and STI.

getOutliningCandidateInfo()

std::optional< std::unique_ptr< outliner::OutlinedFunction > > RISCVInstrInfo::getOutliningCandidateInfo ( const MachineModuleInfo &  MMI, std::vector< outliner::Candidate > &  RepeatedSequenceLocs, unsigned  MinRepeats  ) const

override

Definition at line 3036 of file RISCVInstrInfo.cpp.

References analyzeCandidate(), llvm::CallingConv::C, getInstSizeInBytes(), llvm::outliner::Candidate::getMF(), llvm::MachineFunction::getSubtarget(), MachineOutlinerDefault, MachineOutlinerTailCall, and MI.

getOutliningTypeImpl()

outliner::InstrType RISCVInstrInfo::getOutliningTypeImpl ( const MachineModuleInfo &  MMI, MachineBasicBlock::iterator &  MBBI, unsigned  Flags  ) const

overridevirtual

Definition at line 3084 of file RISCVInstrInfo.cpp.

References cannotInsertTailCall(), F, llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::outliner::Illegal, llvm::outliner::Invisible, isMIModifiesReg(), llvm::outliner::Legal, MBB, MBBI, MI, llvm::RISCVII::MO_PCREL_LO, and TRI.

getReassociateOperandIndices()

void RISCVInstrInfo::getReassociateOperandIndices ( const MachineInstr &  Root, unsigned  Pattern, std::array< unsigned, 5 > &  OperandIndices  ) const

override

Definition at line 1955 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::TargetInstrInfo::getReassociateOperandIndices(), llvm::RISCV::getRVVMCOpcode(), and I.

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 2915 of file RISCVInstrInfo.cpp.

getSerializableMachineMemOperandTargetFlags()

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > RISCVInstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const

override

Definition at line 3979 of file RISCVInstrInfo.cpp.

References llvm::MONontemporalBit0, and llvm::MONontemporalBit1.

getTailDuplicateSize()

unsigned RISCVInstrInfo::getTailDuplicateSize ( CodeGenOptLevel  OptLevel ) const

override

Definition at line 3986 of file RISCVInstrInfo.cpp.

References llvm::Aggressive, llvm::RISCVSubtarget::getTailDupAggressiveThreshold(), and STI.

hasReassociableOperands()

bool RISCVInstrInfo::hasReassociableOperands ( const MachineInstr &  Inst, const MachineBasicBlock *  MBB  ) const

override

Definition at line 1932 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, and MRI.

hasReassociableSibling()

bool RISCVInstrInfo::hasReassociableSibling ( const MachineInstr &  Inst, bool &  Commuted  ) const

override

Definition at line 1966 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getMF(), llvm::RISCV::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RISCV::hasEqualFRM(), llvm::TargetInstrInfo::hasReassociableSibling(), and MRI.

insertBranch()

unsigned RISCVInstrInfo::insertBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *  TBB, MachineBasicBlock *  FBB, ArrayRef< MachineOperand >  Cond, const DebugLoc &  dl, int *  BytesAdded = nullptr  ) const

override

Definition at line 1101 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), CC, Cond, DL, llvm::get(), getBrCond(), getInstSizeInBytes(), isImm(), MBB, MI, and TBB.

insertIndirectBranch()

void RISCVInstrInfo::insertIndirectBranch ( MachineBasicBlock &  MBB, MachineBasicBlock &  NewDestBB, MachineBasicBlock &  RestoreBB, const DebugLoc &  DL, int64_t  BrOffset, RegScavenger *  RS  ) const

override

Definition at line 1140 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::back(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::get(), llvm::RISCVMachineFunctionInfo::getBranchRelaxationScratchFrameIndex(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), II, loadRegFromStackSlot(), MBB, MI, llvm::RISCVII::MO_CALL, MRI, llvm::MachineBasicBlock::pred_size(), llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::RegScavenger::setRegUsed(), storeRegToStackSlot(), and TRI.

insertOutlinedCall()

MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall ( Module &  M, MachineBasicBlock &  MBB, MachineBasicBlock::iterator &  It, MachineFunction &  MF, outliner::Candidate &  C  ) const

override

Definition at line 3150 of file RISCVInstrInfo.cpp.

References llvm::BuildMI(), llvm::CallingConv::C, llvm::get(), llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), MachineOutlinerTailCall, MBB, and llvm::RISCVII::MO_CALL.

isAddImmediate()

std::optional< RegImmPair > RISCVInstrInfo::isAddImmediate ( const MachineInstr &  MI, Register  Reg  ) const

override

Definition at line 3169 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), and MI.

isAsCheapAsAMove()

bool RISCVInstrInfo::isAsCheapAsAMove ( const MachineInstr &  MI ) const

override

Definition at line 1617 of file RISCVInstrInfo.cpp.

References MI.

isAssociativeAndCommutative()

bool RISCVInstrInfo::isAssociativeAndCommutative ( const MachineInstr &  Inst, bool  Invert  ) const

override

Definition at line 1989 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getFlag(), getInverseOpcode(), llvm::MachineInstr::getOpcode(), isFADD(), and isFMUL().

isBranchOffsetInRange()

bool RISCVInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc, int64_t  BrOffset  ) const

override

Definition at line 1334 of file RISCVInstrInfo.cpp.

References llvm::RISCVSubtarget::getXLen(), llvm::isIntN(), llvm_unreachable, llvm::SignExtend64(), and STI.

isCopyInstrImpl()

std::optional< DestSourcePair > RISCVInstrInfo::isCopyInstrImpl ( const MachineInstr &  MI ) const

override

Definition at line 1643 of file RISCVInstrInfo.cpp.

References MI.

isFunctionSafeToOutlineFrom()

bool RISCVInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction &  MF, bool  OutlineFromLinkOnceODRs  ) const

override

Definition at line 2935 of file RISCVInstrInfo.cpp.

References F, and llvm::MachineFunction::getFunction().

isLoadFromStackSlot() [1/2]

Register RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 89 of file RISCVInstrInfo.cpp.

References isLoadFromStackSlot(), and MI.

Referenced by isLoadFromStackSlot().

isLoadFromStackSlot() [2/2]

Register RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex, unsigned &  MemBytes  ) const

override

Definition at line 95 of file RISCVInstrInfo.cpp.

References MI.

isMBBSafeToOutlineFrom()

bool RISCVInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock &  MBB, unsigned &  Flags  ) const

override

Definition at line 2952 of file RISCVInstrInfo.cpp.

References llvm::TargetInstrInfo::isMBBSafeToOutlineFrom(), and MBB.

isReallyTriviallyReMaterializable()

bool RISCVInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr &  MI ) const

override

Definition at line 172 of file RISCVInstrInfo.cpp.

References llvm::RISCV::getRVVMCOpcode(), llvm::TargetInstrInfo::isReallyTriviallyReMaterializable(), and MI.

isStoreToStackSlot() [1/2]

Register RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 132 of file RISCVInstrInfo.cpp.

References isStoreToStackSlot(), and MI.

Referenced by isStoreToStackSlot().

isStoreToStackSlot() [2/2]

Register RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex, unsigned &  MemBytes  ) const

override

Definition at line 138 of file RISCVInstrInfo.cpp.

References MI.

loadRegFromStackSlot()

void RISCVInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  DstReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI, Register  VReg  ) const

override

Definition at line 672 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::LocationSize::beforeOrAfterPointer(), llvm::BuildMI(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), and TRI.

Referenced by insertIndirectBranch().

movImm()

void RISCVInstrInfo::movImm	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		Register	DstReg,
		uint64_t	Val,
		MachineInstr::MIFlag	Flag = MachineInstr::NoFlags,
		bool	DstRenamable = false,
		bool	DstIsDead = false
	)		const

Definition at line 849 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::get(), llvm::getDeadRegState(), llvm::getKillRegState(), llvm::getRenamableRegState(), llvm::RISCVMatInt::Imm, llvm::RISCVSubtarget::is64Bit(), MBB, MBBI, llvm::RISCVMatInt::RegImm, llvm::RISCVMatInt::RegReg, llvm::RISCVMatInt::RegX0, llvm::report_fatal_error(), llvm::MachineInstrBuilder::setMIFlag(), llvm::SmallVectorBase< Size_T >::size(), and STI.

Referenced by llvm::RISCVRegisterInfo::lowerVRELOAD(), llvm::RISCVRegisterInfo::lowerVSPILL(), and mulImm().

mulImm()

void RISCVInstrInfo::mulImm	(	MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	II,
		const DebugLoc &	DL,
		Register	DestReg,
		uint32_t	Amt,
		MachineInstr::MIFlag	Flag
	)		const

Generate code to multiply the value in DestReg by Amt - handles all the common optimizations for this idiom, and supports fallback for subtargets which don't support multiply instructions.

Definition at line 3873 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineFunction::getRegInfo(), II, llvm::isPowerOf2_64(), llvm::RegState::Kill, llvm_unreachable, llvm::Log2_32(), llvm::Log2_64(), MBB, movImm(), MRI, N, llvm::MachineInstrBuilder::setMIFlag(), and STI.

optimizeCondBranch()

bool RISCVInstrInfo::optimizeCondBranch ( MachineInstr &  MI ) const

override

Definition at line 1213 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), analyzeBranch(), assert(), llvm::BuildMI(), CC, Cond, llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_INVALID, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_NE, llvm::MachineOperand::CreateReg(), getBrCond(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, II, INT64_MAX, LHS, MBB, MI, MRI, llvm::MachineBasicBlock::rend(), reverseBranchCondition(), RHS, and TBB.

optimizeSelect()

MachineInstr * RISCVInstrInfo::optimizeSelect ( MachineInstr &  MI, SmallPtrSetImpl< MachineInstr * > &  SeenMIs, bool  PreferFalse  ) const

override

Definition at line 1466 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), canFoldAsPredicatedOp(), CC, llvm::MachineInstr::clearKillInfo(), DefMI, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RISCVCC::getOppositeBranchCondition(), llvm::MachineInstr::getParent(), getPredicatedOpcode(), llvm::MachineOperand::getReg(), llvm::SmallPtrSetImpl< PtrType >::insert(), MI, MRI, and STI.

removeBranch()

unsigned RISCVInstrInfo::removeBranch ( MachineBasicBlock &  MBB, int *  BytesRemoved = nullptr  ) const

override

Definition at line 1067 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), getInstSizeInBytes(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, and MBB.

reverseBranchCondition()

bool RISCVInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond ) const

override

Definition at line 1205 of file RISCVInstrInfo.cpp.

References assert(), CC, Cond, and getOppositeBranchCondition().

Referenced by analyzeLoopForPipelining(), and optimizeCondBranch().

shouldBreakCriticalEdgeToSink()

bool llvm::RISCVInstrInfo::shouldBreakCriticalEdgeToSink ( MachineInstr &  MI ) const

inlineoverride

Definition at line 81 of file RISCVInstrInfo.h.

References MI.

shouldClusterMemOps()

bool RISCVInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1, int64_t  Offset1, bool  OffsetIsScalable1, ArrayRef< const MachineOperand * >  BaseOps2, int64_t  Offset2, bool  OffsetIsScalable2, unsigned  ClusterSize, unsigned  NumBytes  ) const

override

Definition at line 2818 of file RISCVInstrInfo.cpp.

References CacheLineSize, llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), and memOpsHaveSameBasePtr().

shouldOutlineFromFunctionByDefault()

bool RISCVInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction &  MF ) const

override

Definition at line 2964 of file RISCVInstrInfo.cpp.

References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().

storeRegToStackSlot()

void RISCVInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  SrcReg, bool  IsKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI, Register  VReg  ) const

override

Definition at line 583 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::LocationSize::beforeOrAfterPointer(), llvm::BuildMI(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::TargetStackID::ScalableVector, llvm::MachineFrameInfo::setStackID(), and TRI.

Referenced by insertIndirectBranch().

useMachineCombiner()

bool llvm::RISCVInstrInfo::useMachineCombiner ( ) const

inlineoverride

Definition at line 261 of file RISCVInstrInfo.h.

verifyInstruction()

bool RISCVInstrInfo::verifyInstruction ( const MachineInstr &  MI, StringRef &  ErrInfo  ) const

override

Definition at line 2445 of file RISCVInstrInfo.cpp.

References assert(), CASE_OPERAND_UIMM, llvm::RISCVCC::COND_INVALID, llvm::RISCVFPRndMode::DYN, llvm::enumerate(), llvm::RISCVII::getFRMOpNum(), llvm::MachineOperand::getImm(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::getVecPolicyOpNum(), llvm::RISCVII::getVLOpNum(), llvm::RISCVII::hasRoundModeOp(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::hasVLOp(), Idx, llvm::RISCVSubtarget::is64Bit(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::RISCVFPRndMode::isValidRoundingMode(), llvm::RISCVVType::isValidSEW(), llvm_unreachable, llvm::RISCVII::MASK_AGNOSTIC, MI, MRI, llvm::RISCVOp::OPERAND_CLUI_IMM, llvm::RISCVOp::OPERAND_COND_CODE, llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM, llvm::RISCVOp::OPERAND_FRMARG, llvm::RISCVOp::OPERAND_LAST_RISCV_IMM, llvm::RISCVOp::OPERAND_RTZARG, llvm::RISCVOp::OPERAND_RVKRNUM, llvm::RISCVOp::OPERAND_RVKRNUM_0_7, llvm::RISCVOp::OPERAND_RVKRNUM_1_10, llvm::RISCVOp::OPERAND_RVKRNUM_2_14, llvm::RISCVOp::OPERAND_SEW, llvm::RISCVOp::OPERAND_SEW_MASK, llvm::RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO, llvm::RISCVOp::OPERAND_SIMM12, llvm::RISCVOp::OPERAND_SIMM12_LSB00000, llvm::RISCVOp::OPERAND_SIMM5, llvm::RISCVOp::OPERAND_SIMM5_PLUS1, llvm::RISCVOp::OPERAND_SIMM6, llvm::RISCVOp::OPERAND_SIMM6_NONZERO, llvm::RISCVOp::OPERAND_SPIMM, llvm::RISCVOp::OPERAND_UIMM10_LSB00_NONZERO, llvm::RISCVOp::OPERAND_UIMM2_LSB0, llvm::RISCVOp::OPERAND_UIMM5_LSB0, llvm::RISCVOp::OPERAND_UIMM6_LSB0, llvm::RISCVOp::OPERAND_UIMM7_LSB00, llvm::RISCVOp::OPERAND_UIMM8_GE32, llvm::RISCVOp::OPERAND_UIMM8_LSB00, llvm::RISCVOp::OPERAND_UIMM8_LSB000, llvm::RISCVOp::OPERAND_UIMM9_LSB000, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO, llvm::RISCVOp::OPERAND_VEC_POLICY, llvm::RISCVOp::OPERAND_VEC_RM, llvm::RISCVOp::OPERAND_VTYPEI10, llvm::RISCVOp::OPERAND_VTYPEI11, llvm::RISCVOp::OPERAND_ZERO, llvm::RISCVFPRndMode::RTZ, STI, llvm::RISCVII::TAIL_AGNOSTIC, and llvm::RISCVII::usesVXRM().

Member Data Documentation

STI

const RISCVSubtarget& llvm::RISCVInstrInfo::STI

protected

Definition at line 305 of file RISCVInstrInfo.h.

Referenced by analyzeSelect(), areMemAccessesTriviallyDisjoint(), canFoldIntoAddrMode(), copyPhysReg(), copyPhysRegVector(), foldMemoryOperandImpl(), getInstSizeInBytes(), getMachineCombinerTraceStrategy(), getNop(), getTailDuplicateSize(), isBranchOffsetInRange(), movImm(), mulImm(), optimizeSelect(), and verifyInstruction().

---

The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVInstrInfo.h
• lib/Target/RISCV/RISCVInstrInfo.cpp