13#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
23class RISCVMachineFunctionInfo;
50 int VarArgsFrameIndex = 0;
52 int VarArgsSaveSize = 0;
55 int MoveF64FrameIndex = -1;
57 int BranchRelaxationScratchFrameIndex = -1;
59 unsigned LibCallStackSize = 0;
67 unsigned CalleeSavedStackSize = 0;
69 bool IsVectorCall =
false;
89 if (MoveF64FrameIndex == -1)
92 return MoveF64FrameIndex;
96 return BranchRelaxationScratchFrameIndex;
99 BranchRelaxationScratchFrameIndex =
Index;
Allocate memory in an ever growing pool, as if by bump-pointer.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasTailCall() const
Returns true if the function contains a tail call.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
void setLibCallStackSize(unsigned Size)
void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI)
bool isSExt32Register(Register Reg) const
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
void setCalleeSavedStackSize(unsigned Size)
void setRVVPadding(uint64_t Padding)
unsigned getLibCallStackSize() const
uint64_t getRVVPadding() const
void setVarArgsFrameIndex(int Index)
int getVarArgsFrameIndex() const
void setBranchRelaxationScratchFrameIndex(int Index)
bool isVectorCall() const
bool useSaveRestoreLibCalls(const MachineFunction &MF) const
void setRVVStackSize(uint64_t Size)
RISCVMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
uint64_t getRVVStackSize() const
void setVarArgsSaveSize(int Size)
Align getRVVStackAlign() const
int getBranchRelaxationScratchFrameIndex() const
unsigned getVarArgsSaveSize() const
int getMoveF64FrameIndex(MachineFunction &MF)
void setRVVStackAlign(Align StackAlign)
unsigned getCalleeSavedStackSize() const
void addSExt32Register(Register Reg)
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetSubtargetInfo - Generic base class for all target subtargets.
This is an optimization pass for GlobalISel generic memory operations.
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI)
void mappingImpl(yaml::IO &YamlIO) override
RISCVMachineFunctionInfo()=default
~RISCVMachineFunctionInfo()=default