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26 #define GET_INSTRINFO_CTOR_DTOR
27 #include "ARCGenInstrInfo.inc"
29 #define DEBUG_TYPE "arc-inst-info"
44 void ARCInstrInfo::anchor() {}
50 return Op.isImm() &&
Op.getImm() == 0;
54 return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 ||
55 Opcode == ARC::LDB_rs9;
59 return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 ||
60 Opcode == ARC::STB_rs9;
70 int Opcode =
MI.getOpcode();
72 if ((
MI.getOperand(1).isFI()) &&
73 (
MI.getOperand(2).isImm()) &&
76 return MI.getOperand(0).getReg();
89 int Opcode =
MI.getOpcode();
91 if ((
MI.getOperand(1).isFI()) &&
92 (
MI.getOperand(2).isImm()) &&
95 return MI.getOperand(0).getReg();
140 return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p;
174 bool AllowModify)
const {
185 bool CantAnalyze =
false;
188 while (
I->isDebugInstr() || !
I->isTerminator()) {
199 TBB =
I->getOperand(0).getMBB();
205 assert(!FBB &&
"FBB should have been null.");
207 TBB =
I->getOperand(0).getMBB();
208 Cond.push_back(
I->getOperand(1));
209 Cond.push_back(
I->getOperand(2));
210 Cond.push_back(
I->getOperand(3));
211 }
else if (
I->isReturn()) {
255 int *BytesRemoved)
const {
256 assert(!BytesRemoved &&
"Code size not handled");
266 I->eraseFromParent();
277 I->eraseFromParent();
286 "Only GPR32 src copy supported.");
288 "Only GPR32 dest copy supported.");
308 assert(MMO &&
"Couldn't get MachineMemOperand for store to stack.");
310 "Only support 4-byte stores to stack now.");
311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
312 "Only support GPR32 stores to stack now.");
335 assert(MMO &&
"Couldn't get MachineMemOperand for store to stack.");
337 "Only support 4-byte loads from stack now.");
338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
339 "Only support GPR32 stores to stack now.");
341 <<
" from FrameIndex=" <<
FrameIndex <<
"\n");
352 assert((
Cond.size() == 3) &&
"Invalid ARC branch condition!");
360 uint64_t
Value)
const {
362 if (isInt<12>(
Value)) {
374 const DebugLoc &dl,
int *BytesAdded)
const {
375 assert(!BytesAdded &&
"Code size not handled.");
378 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
380 "ARC branch conditions have two components!");
386 int BccOpc =
Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p;
389 for (
unsigned i = 0;
i < 3;
i++) {
404 if (
MI.isInlineAsm()) {
406 const char *AsmStr =
MI.getOperand(0).getSymbolName();
409 return MI.getDesc().getSize();
426 unsigned &OffsetPos)
const {
427 if (!
MI.mayLoad() && !
MI.mayStore())
438 if (!
MI.getOperand(BasePos).isReg() || !
MI.getOperand(OffsetPos).isImm())
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class represents lattice values for constants.
const MachineInstrBuilder & add(const MachineOperand &MO) const
return AArch64::GPR64RegClass contains(Reg)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ Define
Register definition.
A description of a memory reference used in the backend.
static bool isCondBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &dl, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned const TargetRegisterInfo * TRI
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
bool isPostIncrement(const MachineInstr &MI) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
const MachineInstrBuilder & addFrameIndex(int Idx) const
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
Representation of each machine instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static bool isStore(int Opcode)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SmallVector< MachineOperand, 4 > Cond
static bool isLoad(int Opcode)
static ARCCC::CondCode GetOppositeBranchCondition(ARCCC::CondCode CC)
Return the inverse of passed condition, i.e. turning COND_E to COND_NE.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
@ MOLoad
The memory access reads data.
Wrapper class representing virtual and physical registers.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Should compile to something r4 addze r3 instead we get
@ BR
Control flow instructions. These all have token chains.
static bool isJumpOpcode(int Opc)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Return the inverse opcode of the specified Branch instruction.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
@ MOStore
The memory access writes data.
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isPreIncrement(const MachineInstr &MI) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
static bool isZeroImm(const MachineOperand &Op)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
LLVM Value Representation.
Wrapper class representing physical registers. Should be passed by value.