RISCVInstrInfo.cpp File Reference

#include "RISCVInstrInfo.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
#include "RISCVGenCompressInstEmitter.inc"
#include "RISCVGenInstrInfo.inc"
#include "RISCVGenSearchableTables.inc"

Go to the source code of this file.

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::RISCVVPseudosTable
namespace	llvm::RISCV

Macros
#define	GEN_CHECK_COMPRESS_INSTR
#define	GET_INSTRINFO_CTOR_DTOR
#define	GET_INSTRINFO_NAMED_OPS
#define	GET_RISCVVPseudosTable_IMPL
#define	GET_RISCVMaskedPseudosTable_IMPL
#define	OPCODE_LMUL_CASE(OPC)
#define	OPCODE_LMUL_MASK_CASE(OPC)
#define	RVV_OPC_LMUL_CASE(OPC, INV)
#define	RVV_OPC_LMUL_MASK_CASE(OPC, INV)
#define	CASE_OPERAND_UIMM(NUM)
#define	CASE_OPERAND_SIMM(NUM)
#define	CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL)    RISCV::Pseudo##OP##_##LMUL
#define	CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)    RISCV::Pseudo##OP##_##LMUL##_MASK
#define	CASE_RVV_OPCODE_LMUL(OP, LMUL)
#define	CASE_RVV_OPCODE_UNMASK_WIDEN(OP)
#define	CASE_RVV_OPCODE_UNMASK(OP)
#define	CASE_RVV_OPCODE_MASK_WIDEN(OP)
#define	CASE_RVV_OPCODE_MASK(OP)
#define	CASE_RVV_OPCODE_WIDEN(OP)
#define	CASE_RVV_OPCODE(OP)
#define	CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL)    RISCV::PseudoV##OP##_##TYPE##_##LMUL
#define	CASE_VMA_OPCODE_LMULS_M1(OP, TYPE)
#define	CASE_VMA_OPCODE_LMULS_MF2(OP, TYPE)
#define	CASE_VMA_OPCODE_LMULS_MF4(OP, TYPE)
#define	CASE_VMA_OPCODE_LMULS(OP, TYPE)
#define	CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW)    RISCV::PseudoV##OP##_##TYPE##_##LMUL##_##SEW
#define	CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)
#define	CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)
#define	CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE, SEW)
#define	CASE_VFMA_OPCODE_VV(OP)
#define	CASE_VFMA_SPLATS(OP)
#define	CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
#define	CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)
#define	CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)
#define	CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
#define	CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)
#define	CASE_VMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)
#define	CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW)
#define	CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)
#define	CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)
#define	CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP)
#define	CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW)
#define	CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE, SEW)
#define	CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)
#define	CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)    RISCV::PseudoV##OP##_##LMUL##_TIED
#define	CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
#define	CASE_WIDEOP_OPCODE_LMULS(OP)
#define	CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
#define	CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
#define	CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)
#define	CASE_FP_WIDEOP_OPCODE_COMMON(OP, LMUL, SEW)    RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED
#define	CASE_FP_WIDEOP_OPCODE_LMULS_MF4(OP)
#define	CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL, SEW)
#define	CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
#define	CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS(OP)    CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)

Enumerations
enum	MachineOutlinerConstructionID { MachineOutlinerTailCall , MachineOutlinerDefault }

Functions
static bool	forwardCopyWillClobberTuple (unsigned DstReg, unsigned SrcReg, unsigned NumRegs)
static bool	isConvertibleToVMV_V_V (const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVII::VLMUL LMul)
static RISCVCC::CondCode	getCondFromBranchOpc (unsigned Opc)
static void	parseCondBranch (MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
unsigned	getPredicatedOpcode (unsigned Opcode)
static MachineInstr *	canFoldAsPredicatedOp (Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
	Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.
static bool	isFADD (unsigned Opc)
static bool	isFSUB (unsigned Opc)
static bool	isFMUL (unsigned Opc)
static bool	canCombineFPFusedMultiply (const MachineInstr &Root, const MachineOperand &MO, bool DoRegPressureReduce)
static bool	getFPFusedMultiplyPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce)
static bool	getFPPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce)
static const MachineInstr *	canCombine (const MachineBasicBlock &MBB, const MachineOperand &MO, unsigned CombineOpc)
	Utility routine that checks if.
static bool	canCombineShiftIntoShXAdd (const MachineBasicBlock &MBB, const MachineOperand &MO, unsigned OuterShiftAmt)
	Utility routine that checks if.
static unsigned	getSHXADDShiftAmount (unsigned Opc)
static bool	getSHXADDPatterns (const MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static unsigned	getFPFusedMultiplyOpcode (unsigned RootOpc, unsigned Pattern)
static unsigned	getAddendOperandIdx (unsigned Pattern)
static void	combineFPFusedMultiply (MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs)
static void	genShXAddAddShift (MachineInstr &Root, unsigned AddOpIdx, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg)
static bool	memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)
static bool	isCandidatePatchable (const MachineBasicBlock &MBB)
static bool	isMIReadsReg (const MachineInstr &MI, const TargetRegisterInfo *TRI, unsigned RegNo)
static bool	isMIModifiesReg (const MachineInstr &MI, const TargetRegisterInfo *TRI, unsigned RegNo)
static bool	cannotInsertTailCall (const MachineBasicBlock &MBB)
static std::optional< MachineOutlinerConstructionID >	analyzeCandidate (outliner::Candidate &C)
static bool	isRVVWholeLoadStore (unsigned Opcode)

Variables
static cl::opt< bool >	PreferWholeRegisterMove ("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))
static cl::opt< MachineTraceStrategy >	ForceMachineCombinerStrategy ("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy.")))

Macro Definition Documentation

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON	(		OP,
			LMUL,
			SEW
	)

Value:

  case RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED:                             \
    NewOpc = RISCV::PseudoV##OP##_##LMUL##_##SEW;                              \
    break;

Definition at line 3736 of file RISCVInstrInfo.cpp.

CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS

(

OP

)

CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)

Definition at line 3752 of file RISCVInstrInfo.cpp.

CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4

#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4

(

OP

)

Value:

  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16)                            \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16)                            \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E32)                            \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E32)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E32)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16)                             \
  CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E32)                             \

Definition at line 3741 of file RISCVInstrInfo.cpp.

CASE_FP_WIDEOP_OPCODE_COMMON

#define CASE_FP_WIDEOP_OPCODE_COMMON	(		OP,
			LMUL,
			SEW
	)		RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED

Definition at line 3722 of file RISCVInstrInfo.cpp.

CASE_FP_WIDEOP_OPCODE_LMULS_MF4

#define CASE_FP_WIDEOP_OPCODE_LMULS_MF4

(

OP

)

Value:

  CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF4, E16):                                  \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E16):                             \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E32):                             \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E16):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E32):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E16):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E32):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E16):                              \
  case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E32)                               \

Definition at line 3725 of file RISCVInstrInfo.cpp.

CASE_OPERAND_SIMM

#define CASE_OPERAND_SIMM

(

NUM

)

Value:

  case RISCVOp::OPERAND_SIMM##NUM:                                             \
    Ok = isInt<NUM>(Imm);                                                      \
    break;

CASE_OPERAND_UIMM

#define CASE_OPERAND_UIMM

(

NUM

)

Value:

  case RISCVOp::OPERAND_UIMM##NUM:                                             \
    Ok = isUInt<NUM>(Imm);                                                     \
    break;

CASE_RVV_OPCODE

#define CASE_RVV_OPCODE

(

OP

)

Value:

  CASE_RVV_OPCODE_UNMASK(OP):                                                 \
  case CASE_RVV_OPCODE_MASK(OP)

Definition at line 3272 of file RISCVInstrInfo.cpp.

CASE_RVV_OPCODE_LMUL

#define CASE_RVV_OPCODE_LMUL	(		OP,
			LMUL
	)

Value:

  CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL):                                      \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)

Definition at line 3240 of file RISCVInstrInfo.cpp.

CASE_RVV_OPCODE_MASK

#define CASE_RVV_OPCODE_MASK

(

OP

)

Value:

  CASE_RVV_OPCODE_MASK_WIDEN(OP):                                             \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, M8)

Definition at line 3264 of file RISCVInstrInfo.cpp.

CASE_RVV_OPCODE_MASK_LMUL

#define CASE_RVV_OPCODE_MASK_LMUL	(		OP,
			LMUL
	)		RISCV::Pseudo##OP##_##LMUL##_MASK

Definition at line 3237 of file RISCVInstrInfo.cpp.

CASE_RVV_OPCODE_MASK_WIDEN

#define CASE_RVV_OPCODE_MASK_WIDEN

(

OP

)

Value:

  CASE_RVV_OPCODE_MASK_LMUL(OP, MF8):                                         \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, MF4):                                    \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, MF2):                                    \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, M1):                                     \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, M2):                                     \
  case CASE_RVV_OPCODE_MASK_LMUL(OP, M4)

Definition at line 3256 of file RISCVInstrInfo.cpp.

CASE_RVV_OPCODE_UNMASK

#define CASE_RVV_OPCODE_UNMASK

(

OP

)

Value:

  CASE_RVV_OPCODE_UNMASK_WIDEN(OP):                                           \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M8)

Definition at line 3252 of file RISCVInstrInfo.cpp.

CASE_RVV_OPCODE_UNMASK_LMUL

#define CASE_RVV_OPCODE_UNMASK_LMUL	(		OP,
			LMUL
	)		RISCV::Pseudo##OP##_##LMUL

Definition at line 3234 of file RISCVInstrInfo.cpp.

CASE_RVV_OPCODE_UNMASK_WIDEN

#define CASE_RVV_OPCODE_UNMASK_WIDEN

(

OP

)

Value:

  CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF8):                                       \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF4):                                  \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF2):                                  \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M1):                                   \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M2):                                   \
  case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M4)

Definition at line 3244 of file RISCVInstrInfo.cpp.

CASE_RVV_OPCODE_WIDEN

#define CASE_RVV_OPCODE_WIDEN

(

OP

)

Value:

  CASE_RVV_OPCODE_UNMASK_WIDEN(OP):                                           \
  case CASE_RVV_OPCODE_MASK_WIDEN(OP)

Definition at line 3268 of file RISCVInstrInfo.cpp.

CASE_VFMA_CHANGE_OPCODE_COMMON

#define CASE_VFMA_CHANGE_OPCODE_COMMON	(		OLDOP,
			NEWOP,
			TYPE,
			LMUL,
			SEW
	)

Value:

  case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_##SEW:                        \
    Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL##_##SEW;                     \
    break;

Definition at line 3520 of file RISCVInstrInfo.cpp.

CASE_VFMA_CHANGE_OPCODE_LMULS

#define CASE_VFMA_CHANGE_OPCODE_LMULS	(		OLDOP,
			NEWOP,
			TYPE,
			SEW
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8, SEW)                 \
  CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW)

Definition at line 3544 of file RISCVInstrInfo.cpp.

CASE_VFMA_CHANGE_OPCODE_LMULS_M1

#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1	(		OLDOP,
			NEWOP,
			TYPE,
			SEW
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1, SEW)                  \
  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2, SEW)                  \
  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4, SEW)                  \
  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8, SEW)

Definition at line 3525 of file RISCVInstrInfo.cpp.

CASE_VFMA_CHANGE_OPCODE_LMULS_MF2

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2	(		OLDOP,
			NEWOP,
			TYPE,
			SEW
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2, SEW)                 \
  CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)

Definition at line 3531 of file RISCVInstrInfo.cpp.

CASE_VFMA_CHANGE_OPCODE_LMULS_MF4

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4	(		OLDOP,
			NEWOP,
			TYPE,
			SEW
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4, SEW)                 \
  CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)

Definition at line 3540 of file RISCVInstrInfo.cpp.

CASE_VFMA_CHANGE_OPCODE_SPLATS

#define CASE_VFMA_CHANGE_OPCODE_SPLATS	(		OLDOP,
			NEWOP
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16, E16)                 \
  CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32, E32)                 \
  CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64, E64)

Definition at line 3548 of file RISCVInstrInfo.cpp.

CASE_VFMA_CHANGE_OPCODE_VV

#define CASE_VFMA_CHANGE_OPCODE_VV	(		OLDOP,
			NEWOP
	)

Value:

  CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16)                     \
  CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32)                     \
  CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)

Definition at line 3535 of file RISCVInstrInfo.cpp.

CASE_VFMA_OPCODE_COMMON

#define CASE_VFMA_OPCODE_COMMON	(		OP,
			TYPE,
			LMUL,
			SEW
	)		RISCV::PseudoV##OP##_##TYPE##_##LMUL##_##SEW

Definition at line 3300 of file RISCVInstrInfo.cpp.

CASE_VFMA_OPCODE_LMULS_M1

#define CASE_VFMA_OPCODE_LMULS_M1	(		OP,
			TYPE,
			SEW
	)

Value:

  CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1, SEW):                                  \
  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2, SEW):                             \
  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4, SEW):                             \
  case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8, SEW)

Definition at line 3303 of file RISCVInstrInfo.cpp.

CASE_VFMA_OPCODE_LMULS_MF2

#define CASE_VFMA_OPCODE_LMULS_MF2	(		OP,
			TYPE,
			SEW
	)

Value:

  CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2, SEW):                                 \
  case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)

Definition at line 3309 of file RISCVInstrInfo.cpp.

CASE_VFMA_OPCODE_LMULS_MF4

#define CASE_VFMA_OPCODE_LMULS_MF4	(		OP,
			TYPE,
			SEW
	)

Value:

  CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4, SEW):                                 \
  case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)

Definition at line 3313 of file RISCVInstrInfo.cpp.

CASE_VFMA_OPCODE_VV

#define CASE_VFMA_OPCODE_VV

(

OP

)

Value:

  CASE_VFMA_OPCODE_LMULS_MF4(OP, VV, E16):                                     \
  case CASE_VFMA_OPCODE_LMULS_MF2(OP, VV, E32):                                \
  case CASE_VFMA_OPCODE_LMULS_M1(OP, VV, E64)

Definition at line 3317 of file RISCVInstrInfo.cpp.

CASE_VFMA_SPLATS

#define CASE_VFMA_SPLATS

(

OP

)

Value:

  CASE_VFMA_OPCODE_LMULS_MF4(OP, VFPR16, E16):                                 \
  case CASE_VFMA_OPCODE_LMULS_MF2(OP, VFPR32, E32):                            \
  case CASE_VFMA_OPCODE_LMULS_M1(OP, VFPR64, E64)

Definition at line 3322 of file RISCVInstrInfo.cpp.

CASE_VMA_CHANGE_OPCODE_COMMON

#define CASE_VMA_CHANGE_OPCODE_COMMON	(		OLDOP,
			NEWOP,
			TYPE,
			LMUL
	)

Value:

  case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL:                                \
    Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL;                             \
    break;

Definition at line 3491 of file RISCVInstrInfo.cpp.

CASE_VMA_CHANGE_OPCODE_LMULS

#define CASE_VMA_CHANGE_OPCODE_LMULS	(		OLDOP,
			NEWOP,
			TYPE
	)

Value:

  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8)                       \
  CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)

Definition at line 3510 of file RISCVInstrInfo.cpp.

CASE_VMA_CHANGE_OPCODE_LMULS_M1

#define CASE_VMA_CHANGE_OPCODE_LMULS_M1	(		OLDOP,
			NEWOP,
			TYPE
	)

Value:

  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1)                        \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2)                        \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4)                        \
  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)

Definition at line 3496 of file RISCVInstrInfo.cpp.

CASE_VMA_CHANGE_OPCODE_LMULS_MF2

#define CASE_VMA_CHANGE_OPCODE_LMULS_MF2	(		OLDOP,
			NEWOP,
			TYPE
	)

Value:

  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2)                       \
  CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)

Definition at line 3502 of file RISCVInstrInfo.cpp.

CASE_VMA_CHANGE_OPCODE_LMULS_MF4

#define CASE_VMA_CHANGE_OPCODE_LMULS_MF4	(		OLDOP,
			NEWOP,
			TYPE
	)

Value:

  CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4)                       \
  CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)

Definition at line 3506 of file RISCVInstrInfo.cpp.

CASE_VMA_CHANGE_OPCODE_SPLATS

#define CASE_VMA_CHANGE_OPCODE_SPLATS	(		OLDOP,
			NEWOP
	)

Value:

  CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16)                       \
  CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32)                       \
  CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64)

Definition at line 3514 of file RISCVInstrInfo.cpp.

CASE_VMA_OPCODE_COMMON

#define CASE_VMA_OPCODE_COMMON	(		OP,
			TYPE,
			LMUL
	)		RISCV::PseudoV##OP##_##TYPE##_##LMUL

Definition at line 3278 of file RISCVInstrInfo.cpp.

CASE_VMA_OPCODE_LMULS

#define CASE_VMA_OPCODE_LMULS	(		OP,
			TYPE
	)

Value:

  CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8):                                       \
  case CASE_VMA_OPCODE_LMULS_MF4(OP, TYPE)

Definition at line 3295 of file RISCVInstrInfo.cpp.

CASE_VMA_OPCODE_LMULS_M1

#define CASE_VMA_OPCODE_LMULS_M1	(		OP,
			TYPE
	)

Value:

  CASE_VMA_OPCODE_COMMON(OP, TYPE, M1):                                        \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, M2):                                   \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, M4):                                   \
  case CASE_VMA_OPCODE_COMMON(OP, TYPE, M8)

Definition at line 3281 of file RISCVInstrInfo.cpp.

CASE_VMA_OPCODE_LMULS_MF2

#define CASE_VMA_OPCODE_LMULS_MF2	(		OP,
			TYPE
	)

Value:

  CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2):                                       \
  case CASE_VMA_OPCODE_LMULS_M1(OP, TYPE)

Definition at line 3287 of file RISCVInstrInfo.cpp.

CASE_VMA_OPCODE_LMULS_MF4

#define CASE_VMA_OPCODE_LMULS_MF4	(		OP,
			TYPE
	)

Value:

  CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4):                                       \
  case CASE_VMA_OPCODE_LMULS_MF2(OP, TYPE)

Definition at line 3291 of file RISCVInstrInfo.cpp.

CASE_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_WIDEOP_CHANGE_OPCODE_COMMON	(		OP,
			LMUL
	)

Value:

  case RISCV::PseudoV##OP##_##LMUL##_TIED:                                     \
    NewOpc = RISCV::PseudoV##OP##_##LMUL;                                      \
    break;

Definition at line 3705 of file RISCVInstrInfo.cpp.

CASE_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS

(

OP

)

Value:

  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8)                                    \
  CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)

Definition at line 3717 of file RISCVInstrInfo.cpp.

CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4

(

OP

)

Value:

  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4)                                    \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2)                                    \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1)                                     \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2)                                     \
  CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)

Definition at line 3710 of file RISCVInstrInfo.cpp.

CASE_WIDEOP_OPCODE_COMMON

#define CASE_WIDEOP_OPCODE_COMMON	(		OP,
			LMUL
	)		RISCV::PseudoV##OP##_##LMUL##_TIED

Definition at line 3691 of file RISCVInstrInfo.cpp.

CASE_WIDEOP_OPCODE_LMULS

#define CASE_WIDEOP_OPCODE_LMULS

(

OP

)

Value:

  CASE_WIDEOP_OPCODE_COMMON(OP, MF8):                                          \
  case CASE_WIDEOP_OPCODE_LMULS_MF4(OP)

Definition at line 3701 of file RISCVInstrInfo.cpp.

CASE_WIDEOP_OPCODE_LMULS_MF4

#define CASE_WIDEOP_OPCODE_LMULS_MF4

(

OP

)

Value:

  CASE_WIDEOP_OPCODE_COMMON(OP, MF4):                                          \
  case CASE_WIDEOP_OPCODE_COMMON(OP, MF2):                                     \
  case CASE_WIDEOP_OPCODE_COMMON(OP, M1):                                      \
  case CASE_WIDEOP_OPCODE_COMMON(OP, M2):                                      \
  case CASE_WIDEOP_OPCODE_COMMON(OP, M4)

Definition at line 3694 of file RISCVInstrInfo.cpp.

GEN_CHECK_COMPRESS_INSTR

#define GEN_CHECK_COMPRESS_INSTR

Definition at line 39 of file RISCVInstrInfo.cpp.

GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 42 of file RISCVInstrInfo.cpp.

GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

Definition at line 43 of file RISCVInstrInfo.cpp.

GET_RISCVMaskedPseudosTable_IMPL

#define GET_RISCVMaskedPseudosTable_IMPL

Definition at line 71 of file RISCVInstrInfo.cpp.

GET_RISCVVPseudosTable_IMPL

#define GET_RISCVVPseudosTable_IMPL

Definition at line 64 of file RISCVInstrInfo.cpp.

OPCODE_LMUL_CASE

#define OPCODE_LMUL_CASE

(

OPC

)

Value:

  case RISCV::OPC##_M1:                                                        \
  case RISCV::OPC##_M2:                                                        \
  case RISCV::OPC##_M4:                                                        \
  case RISCV::OPC##_M8:                                                        \
  case RISCV::OPC##_MF2:                                                       \
  case RISCV::OPC##_MF4:                                                       \
  case RISCV::OPC##_MF8

OPCODE_LMUL_MASK_CASE

#define OPCODE_LMUL_MASK_CASE

(

OPC

)

Value:

  case RISCV::OPC##_M1_MASK:                                                   \
  case RISCV::OPC##_M2_MASK:                                                   \
  case RISCV::OPC##_M4_MASK:                                                   \
  case RISCV::OPC##_M8_MASK:                                                   \
  case RISCV::OPC##_MF2_MASK:                                                  \
  case RISCV::OPC##_MF4_MASK:                                                  \
  case RISCV::OPC##_MF8_MASK

RVV_OPC_LMUL_CASE

#define RVV_OPC_LMUL_CASE	(		OPC,
			INV
	)

Value:

  case RISCV::OPC##_M1:                                                        \
    return RISCV::INV##_M1;                                                    \
  case RISCV::OPC##_M2:                                                        \
    return RISCV::INV##_M2;                                                    \
  case RISCV::OPC##_M4:                                                        \
    return RISCV::INV##_M4;                                                    \
  case RISCV::OPC##_M8:                                                        \
    return RISCV::INV##_M8;                                                    \
  case RISCV::OPC##_MF2:                                                       \
    return RISCV::INV##_MF2;                                                   \
  case RISCV::OPC##_MF4:                                                       \
    return RISCV::INV##_MF4;                                                   \
  case RISCV::OPC##_MF8:                                                       \
    return RISCV::INV##_MF8

RVV_OPC_LMUL_MASK_CASE

#define RVV_OPC_LMUL_MASK_CASE	(		OPC,
			INV
	)

Value:

  case RISCV::OPC##_M1_MASK:                                                   \
    return RISCV::INV##_M1_MASK;                                               \
  case RISCV::OPC##_M2_MASK:                                                   \
    return RISCV::INV##_M2_MASK;                                               \
  case RISCV::OPC##_M4_MASK:                                                   \
    return RISCV::INV##_M4_MASK;                                               \
  case RISCV::OPC##_M8_MASK:                                                   \
    return RISCV::INV##_M8_MASK;                                               \
  case RISCV::OPC##_MF2_MASK:                                                  \
    return RISCV::INV##_MF2_MASK;                                              \
  case RISCV::OPC##_MF4_MASK:                                                  \
    return RISCV::INV##_MF4_MASK;                                              \
  case RISCV::OPC##_MF8_MASK:                                                  \
    return RISCV::INV##_MF8_MASK

Enumeration Type Documentation

MachineOutlinerConstructionID

enum MachineOutlinerConstructionID

Enumerator
MachineOutlinerTailCall
MachineOutlinerDefault

Definition at line 2954 of file RISCVInstrInfo.cpp.

Function Documentation

analyzeCandidate()

static std::optional< MachineOutlinerConstructionID > analyzeCandidate ( outliner::Candidate &  C )

static

Definition at line 3005 of file RISCVInstrInfo.cpp.

References assert(), llvm::CallingConv::C, cannotInsertTailCall(), MachineOutlinerDefault, MachineOutlinerTailCall, MI, and TRI.

Referenced by llvm::RISCVInstrInfo::getOutliningCandidateInfo().

canCombine()

static const MachineInstr * canCombine ( const MachineBasicBlock &  MBB, const MachineOperand &  MO, unsigned  CombineOpc  )

static

Utility routine that checks if.

Parameters

MO	is defined by an
CombineOpc	instruction in the basic block
MBB

Definition at line 2165 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, MI, and MRI.

canCombineFPFusedMultiply()

static bool canCombineFPFusedMultiply ( const MachineInstr &  Root, const MachineOperand &  MO, bool  DoRegPressureReduce  )

static

Definition at line 2107 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::FmContract, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RISCV::hasEqualFRM(), isFMUL(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MI, and MRI.

Referenced by getFPFusedMultiplyPatterns().

canCombineShiftIntoShXAdd()

static bool canCombineShiftIntoShXAdd ( const MachineBasicBlock &  MBB, const MachineOperand &  MO, unsigned  OuterShiftAmt  )

static

Utility routine that checks if.

Parameters

MO	is defined by a SLLI in
MBB	that can be combined by splitting across 2 SHXADD instructions. The first SHXADD shift amount is given by
OuterShiftAmt.

Definition at line 2186 of file RISCVInstrInfo.cpp.

References canCombine(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and MBB.

Referenced by getSHXADDPatterns().

canFoldAsPredicatedOp()

static MachineInstr * canFoldAsPredicatedOp ( Register  Reg, const MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII  )

static

Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.

Definition at line 1397 of file RISCVInstrInfo.cpp.

References llvm::drop_begin(), getPredicatedOpcode(), MI, and MRI.

Referenced by llvm::RISCVInstrInfo::optimizeSelect().

cannotInsertTailCall()

static bool cannotInsertTailCall ( const MachineBasicBlock &  MBB )

static

Definition at line 2983 of file RISCVInstrInfo.cpp.

References llvm::MachineBasicBlock::back(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MachineBasicBlock::getParent(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::RISCVII::getTailExpandUseRegNo(), isCandidatePatchable(), isMIModifiesReg(), isMIReadsReg(), llvm::MachineInstr::isReturn(), MBB, and MI.

Referenced by analyzeCandidate(), and llvm::RISCVInstrInfo::getOutliningTypeImpl().

combineFPFusedMultiply()

static void combineFPFusedMultiply ( MachineInstr &  Root, MachineInstr &  Prev, unsigned  Pattern, SmallVectorImpl< MachineInstr * > &  InsInstrs, SmallVectorImpl< MachineInstr * > &  DelInstrs  )

static

Definition at line 2303 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), getAddendOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), getFPFusedMultiplyOpcode(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::DILocation::getMergedLocation(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isKill(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

Referenced by llvm::RISCVInstrInfo::genAlternativeCodeSequence().

forwardCopyWillClobberTuple()

static bool forwardCopyWillClobberTuple ( unsigned  DstReg, unsigned  SrcReg, unsigned  NumRegs  )

static

Definition at line 187 of file RISCVInstrInfo.cpp.

genShXAddAddShift()

static void genShXAddAddShift ( MachineInstr &  Root, unsigned  AddOpIdx, SmallVectorImpl< MachineInstr * > &  InsInstrs, SmallVectorImpl< MachineInstr * > &  DelInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg  )

static

Definition at line 2349 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getSHXADDShiftAmount(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::RegState::Kill, llvm_unreachable, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), TII, X, and Y.

Referenced by llvm::RISCVInstrInfo::genAlternativeCodeSequence().

getAddendOperandIdx()

static unsigned getAddendOperandIdx ( unsigned  Pattern )

static

Definition at line 2290 of file RISCVInstrInfo.cpp.

References llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

getCondFromBranchOpc()

static RISCVCC::CondCode getCondFromBranchOpc ( unsigned  Opc )

static

Definition at line 908 of file RISCVInstrInfo.cpp.

References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_INVALID, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, and llvm::RISCVCC::COND_NE.

getFPFusedMultiplyOpcode()

static unsigned getFPFusedMultiplyOpcode ( unsigned  RootOpc, unsigned  Pattern  )

static

Definition at line 2268 of file RISCVInstrInfo.cpp.

References llvm::FMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

getFPFusedMultiplyPatterns()

static bool getFPFusedMultiplyPatterns ( MachineInstr &  Root, SmallVectorImpl< unsigned > &  Patterns, bool  DoRegPressureReduce  )

static

Definition at line 2134 of file RISCVInstrInfo.cpp.

References canCombineFPFusedMultiply(), llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isFADD(), isFSUB(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by getFPPatterns().

getFPPatterns()

static bool getFPPatterns ( MachineInstr &  Root, SmallVectorImpl< unsigned > &  Patterns, bool  DoRegPressureReduce  )

static

Definition at line 2157 of file RISCVInstrInfo.cpp.

References getFPFusedMultiplyPatterns().

Referenced by llvm::RISCVInstrInfo::getMachineCombinerPatterns().

getPredicatedOpcode()

unsigned getPredicatedOpcode

(

unsigned

Opcode

)

Definition at line 1357 of file RISCVInstrInfo.cpp.

Referenced by canFoldAsPredicatedOp(), and llvm::RISCVInstrInfo::optimizeSelect().

getSHXADDPatterns()

static bool getSHXADDPatterns ( const MachineInstr &  Root, SmallVectorImpl< unsigned > &  Patterns  )

static

Definition at line 2217 of file RISCVInstrInfo.cpp.

References canCombine(), canCombineShiftIntoShXAdd(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), getSHXADDShiftAmount(), MBB, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SHXADD_ADD_SLLI_OP1, and llvm::SHXADD_ADD_SLLI_OP2.

Referenced by llvm::RISCVInstrInfo::getMachineCombinerPatterns().

getSHXADDShiftAmount()

static unsigned getSHXADDShiftAmount ( unsigned  Opc )

static

Definition at line 2202 of file RISCVInstrInfo.cpp.

Referenced by genShXAddAddShift(), and getSHXADDPatterns().

isCandidatePatchable()

static bool isCandidatePatchable ( const MachineBasicBlock &  MBB )

static

Definition at line 2964 of file RISCVInstrInfo.cpp.

References F, llvm::MachineFunction::getFunction(), llvm::MachineBasicBlock::getParent(), and MBB.

Referenced by cannotInsertTailCall().

isConvertibleToVMV_V_V()

static bool isConvertibleToVMV_V_V ( const RISCVSubtarget &  STI, const MachineBasicBlock &  MBB, MachineBasicBlock::const_iterator  MBBI, MachineBasicBlock::const_iterator &  DefMBBI, RISCVII::VLMUL  LMul  )

static

Definition at line 192 of file RISCVInstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::begin(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::RISCVVType::getSEW(), llvm::RISCVVType::getVLMUL(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVLOp(), llvm::RISCVII::isRVVWideningReduction(), llvm::RISCVVType::isTailAgnostic(), MBB, MBBI, PreferWholeRegisterMove, and TRI.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector().

isFADD()

static bool isFADD ( unsigned  Opc )

static

Definition at line 1709 of file RISCVInstrInfo.cpp.

Referenced by getFPFusedMultiplyPatterns(), and llvm::RISCVInstrInfo::isAssociativeAndCommutative().

isFMUL()

static bool isFMUL ( unsigned  Opc )

static

Definition at line 1731 of file RISCVInstrInfo.cpp.

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::isAssociativeAndCommutative().

isFSUB()

static bool isFSUB ( unsigned  Opc )

static

Definition at line 1720 of file RISCVInstrInfo.cpp.

Referenced by getFPFusedMultiplyPatterns().

isMIModifiesReg()

static bool isMIModifiesReg ( const MachineInstr &  MI, const TargetRegisterInfo *  TRI, unsigned  RegNo  )

static

Definition at line 2977 of file RISCVInstrInfo.cpp.

References MI, and TRI.

Referenced by cannotInsertTailCall(), and llvm::RISCVInstrInfo::getOutliningTypeImpl().

isMIReadsReg()

static bool isMIReadsReg ( const MachineInstr &  MI, const TargetRegisterInfo *  TRI, unsigned  RegNo  )

static

Definition at line 2971 of file RISCVInstrInfo.cpp.

References MI, and TRI.

Referenced by cannotInsertTailCall().

isRVVWholeLoadStore()

static bool isRVVWholeLoadStore ( unsigned  Opcode )

static

Definition at line 4005 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCV::isRVVSpill().

memOpsHaveSameBasePtr()

static bool memOpsHaveSameBasePtr ( const MachineInstr &  MI1, ArrayRef< const MachineOperand * >  BaseOps1, const MachineInstr &  MI2, ArrayRef< const MachineOperand * >  BaseOps2  )

static

Definition at line 2782 of file RISCVInstrInfo.cpp.

References llvm::ArrayRef< T >::front(), llvm::getUnderlyingObject(), llvm::MachineInstr::hasOneMemOperand(), and llvm::MachineInstr::memoperands_begin().

parseCondBranch()

static void parseCondBranch ( MachineInstr &  LastInst, MachineBasicBlock *&  Target, SmallVectorImpl< MachineOperand > &  Cond  )

static

Definition at line 934 of file RISCVInstrInfo.cpp.

References assert(), CC, Cond, llvm::MachineOperand::CreateImm(), getCondFromBranchOpc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MCInstrDesc::isConditionalBranch().

Variable Documentation

ForceMachineCombinerStrategy

cl::opt< MachineTraceStrategy > ForceMachineCombinerStrategy("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy."))) ( "riscv-force-machine-combiner-strategy"  , cl::Hidden  , cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation.")  , cl::init(MachineTraceStrategy::TS_NumStrategies)  , cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy."))    )

static

Referenced by llvm::RISCVInstrInfo::getMachineCombinerTraceStrategy().

PreferWholeRegisterMove

cl::opt< bool > PreferWholeRegisterMove("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers.")) ( "riscv-prefer-whole-register-move"  , cl::init(false)  , cl::Hidden  , cl::desc("Prefer whole register move for vector registers.")    )

static

Referenced by isConvertibleToVMV_V_V().