LLVM 19.0.0git
Namespaces | Macros | Enumerations | Functions | Variables
RISCVInstrInfo.cpp File Reference
#include "RISCVInstrInfo.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
#include "RISCVGenCompressInstEmitter.inc"
#include "RISCVGenInstrInfo.inc"
#include "RISCVGenSearchableTables.inc"

Go to the source code of this file.

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::RISCVVPseudosTable
 

Macros

#define GEN_CHECK_COMPRESS_INSTR
 
#define GET_INSTRINFO_CTOR_DTOR
 
#define GET_INSTRINFO_NAMED_OPS
 
#define GET_RISCVVPseudosTable_IMPL
 
#define CASE_OPERAND_UIMM(NUM)
 
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)    RISCV::PseudoV##OP##_##TYPE##_##LMUL
 
#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)
 
#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)
 
#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
 
#define CASE_VFMA_OPCODE_LMULS(OP, TYPE)
 
#define CASE_VFMA_SPLATS(OP)
 
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)
 
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)    RISCV::PseudoV##OP##_##LMUL##_TIED
 
#define CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
 
#define CASE_WIDEOP_OPCODE_LMULS(OP)
 
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
 
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
 
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)
 

Enumerations

enum  MachineOutlinerConstructionID { MachineOutlinerDefault }
 

Functions

static bool forwardCopyWillClobberTuple (unsigned DstReg, unsigned SrcReg, unsigned NumRegs)
 
static bool isConvertibleToVMV_V_V (const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVII::VLMUL LMul)
 
static RISCVCC::CondCode getCondFromBranchOpc (unsigned Opc)
 
static void parseCondBranch (MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
 
unsigned getPredicatedOpcode (unsigned Opcode)
 
static MachineInstrcanFoldAsPredicatedOp (Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
 Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.
 
static bool isFADD (unsigned Opc)
 
static bool isFSUB (unsigned Opc)
 
static bool isFMUL (unsigned Opc)
 
static bool canCombineFPFusedMultiply (const MachineInstr &Root, const MachineOperand &MO, bool DoRegPressureReduce)
 
static bool getFPFusedMultiplyPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce)
 
static bool getFPPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce)
 
static unsigned getFPFusedMultiplyOpcode (unsigned RootOpc, MachineCombinerPattern Pattern)
 
static unsigned getAddendOperandIdx (MachineCombinerPattern Pattern)
 
static void combineFPFusedMultiply (MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs)
 
static bool memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)
 
static bool isRVVWholeLoadStore (unsigned Opcode)
 

Variables

static cl::opt< boolPreferWholeRegisterMove ("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))
 
static cl::opt< MachineTraceStrategyForceMachineCombinerStrategy ("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy.")))
 

Macro Definition Documentation

◆ CASE_OPERAND_UIMM

#define CASE_OPERAND_UIMM (   NUM)
Value:
case RISCVOp::OPERAND_UIMM##NUM: \
Ok = isUInt<NUM>(Imm); \
break;

◆ CASE_VFMA_CHANGE_OPCODE_COMMON

#define CASE_VFMA_CHANGE_OPCODE_COMMON (   OLDOP,
  NEWOP,
  TYPE,
  LMUL 
)
Value:
case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \
Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
break;
#define _

Definition at line 2764 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS

#define CASE_VFMA_CHANGE_OPCODE_LMULS (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)

Definition at line 2783 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_M1

#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1 (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
unsigned M1(unsigned Val)
Definition: VE.h:376

Definition at line 2769 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2 (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)

Definition at line 2775 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)

Definition at line 2779 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_SPLATS

#define CASE_VFMA_CHANGE_OPCODE_SPLATS (   OLDOP,
  NEWOP 
)
Value:
CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16) \
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32) \
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64)
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)

Definition at line 2787 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_COMMON

#define CASE_VFMA_OPCODE_COMMON (   OP,
  TYPE,
  LMUL 
)     RISCV::PseudoV##OP##_##TYPE##_##LMUL

Definition at line 2602 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS

#define CASE_VFMA_OPCODE_LMULS (   OP,
  TYPE 
)
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8): \
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)
#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
#define OP(n)
Definition: regex2.h:73

Definition at line 2619 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_M1

#define CASE_VFMA_OPCODE_LMULS_M1 (   OP,
  TYPE 
)
Value:
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)

Definition at line 2605 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF2

#define CASE_VFMA_OPCODE_LMULS_MF2 (   OP,
  TYPE 
)
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2): \
#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)

Definition at line 2611 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF4

#define CASE_VFMA_OPCODE_LMULS_MF4 (   OP,
  TYPE 
)
Value:
CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4): \
#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)

Definition at line 2615 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_SPLATS

#define CASE_VFMA_SPLATS (   OP)
Value:

Definition at line 2623 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_WIDEOP_CHANGE_OPCODE_COMMON (   OP,
  LMUL 
)
Value:
case RISCV::PseudoV##OP##_##LMUL##_TIED: \
NewOpc = RISCV::PseudoV##OP##_##LMUL; \
break;

Definition at line 2930 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS (   OP)
Value:
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)

Definition at line 2942 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4 (   OP)
Value:
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)

Definition at line 2935 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_COMMON

#define CASE_WIDEOP_OPCODE_COMMON (   OP,
  LMUL 
)     RISCV::PseudoV##OP##_##LMUL##_TIED

Definition at line 2915 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_LMULS

#define CASE_WIDEOP_OPCODE_LMULS (   OP)
Value:
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)
#define CASE_WIDEOP_OPCODE_LMULS_MF4(OP)

Definition at line 2925 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_LMULS_MF4

#define CASE_WIDEOP_OPCODE_LMULS_MF4 (   OP)

◆ GEN_CHECK_COMPRESS_INSTR

#define GEN_CHECK_COMPRESS_INSTR

Definition at line 39 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 42 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

Definition at line 43 of file RISCVInstrInfo.cpp.

◆ GET_RISCVVPseudosTable_IMPL

#define GET_RISCVVPseudosTable_IMPL

Definition at line 64 of file RISCVInstrInfo.cpp.

Enumeration Type Documentation

◆ MachineOutlinerConstructionID

Enumerator
MachineOutlinerDefault 

Definition at line 2407 of file RISCVInstrInfo.cpp.

Function Documentation

◆ canCombineFPFusedMultiply()

static bool canCombineFPFusedMultiply ( const MachineInstr Root,
const MachineOperand MO,
bool  DoRegPressureReduce 
)
static

◆ canFoldAsPredicatedOp()

static MachineInstr * canFoldAsPredicatedOp ( Register  Reg,
const MachineRegisterInfo MRI,
const TargetInstrInfo TII 
)
static

Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.

Definition at line 1355 of file RISCVInstrInfo.cpp.

References llvm::drop_begin(), getPredicatedOpcode(), MI, and MRI.

Referenced by llvm::RISCVInstrInfo::optimizeSelect().

◆ combineFPFusedMultiply()

static void combineFPFusedMultiply ( MachineInstr Root,
MachineInstr Prev,
MachineCombinerPattern  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs 
)
static

◆ forwardCopyWillClobberTuple()

static bool forwardCopyWillClobberTuple ( unsigned  DstReg,
unsigned  SrcReg,
unsigned  NumRegs 
)
static

Definition at line 161 of file RISCVInstrInfo.cpp.

◆ getAddendOperandIdx()

static unsigned getAddendOperandIdx ( MachineCombinerPattern  Pattern)
static

◆ getCondFromBranchOpc()

static RISCVCC::CondCode getCondFromBranchOpc ( unsigned  Opc)
static

◆ getFPFusedMultiplyOpcode()

static unsigned getFPFusedMultiplyOpcode ( unsigned  RootOpc,
MachineCombinerPattern  Pattern 
)
static

Definition at line 1843 of file RISCVInstrInfo.cpp.

References llvm::FMSUB, and llvm_unreachable.

Referenced by combineFPFusedMultiply().

◆ getFPFusedMultiplyPatterns()

static bool getFPFusedMultiplyPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns,
bool  DoRegPressureReduce 
)
static

◆ getFPPatterns()

static bool getFPPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns,
bool  DoRegPressureReduce 
)
static

◆ getPredicatedOpcode()

unsigned getPredicatedOpcode ( unsigned  Opcode)

◆ isConvertibleToVMV_V_V()

static bool isConvertibleToVMV_V_V ( const RISCVSubtarget STI,
const MachineBasicBlock MBB,
MachineBasicBlock::const_iterator  MBBI,
MachineBasicBlock::const_iterator DefMBBI,
RISCVII::VLMUL  LMul 
)
static

◆ isFADD()

static bool isFADD ( unsigned  Opc)
static

◆ isFMUL()

static bool isFMUL ( unsigned  Opc)
static

◆ isFSUB()

static bool isFSUB ( unsigned  Opc)
static

Definition at line 1654 of file RISCVInstrInfo.cpp.

Referenced by getFPFusedMultiplyPatterns().

◆ isRVVWholeLoadStore()

static bool isRVVWholeLoadStore ( unsigned  Opcode)
static

Definition at line 3187 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCV::isRVVSpill().

◆ memOpsHaveSameBasePtr()

static bool memOpsHaveSameBasePtr ( const MachineInstr MI1,
ArrayRef< const MachineOperand * >  BaseOps1,
const MachineInstr MI2,
ArrayRef< const MachineOperand * >  BaseOps2 
)
static

◆ parseCondBranch()

static void parseCondBranch ( MachineInstr LastInst,
MachineBasicBlock *&  Target,
SmallVectorImpl< MachineOperand > &  Cond 
)
static

Variable Documentation

◆ ForceMachineCombinerStrategy

cl::opt< MachineTraceStrategy > ForceMachineCombinerStrategy("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy."))) ( "riscv-force-machine-combiner-strategy"  ,
cl::Hidden  ,
cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation.")  ,
cl::init(MachineTraceStrategy::TS_NumStrategies)  ,
cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy."))   
)
static

◆ PreferWholeRegisterMove

cl::opt< bool > PreferWholeRegisterMove("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers.")) ( "riscv-prefer-whole-register-move"  ,
cl::init(false)  ,
cl::Hidden  ,
cl::desc("Prefer whole register move for vector registers.")   
)
static

Referenced by isConvertibleToVMV_V_V().