LLVM  14.0.0git
Namespaces | Macros | Enumerations | Functions | Variables
RISCVInstrInfo.cpp File Reference
#include "RISCVInstrInfo.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
#include "RISCVGenCompressInstEmitter.inc"
#include "RISCVGenInstrInfo.inc"
#include "RISCVGenSearchableTables.inc"
Include dependency graph for RISCVInstrInfo.cpp:

Go to the source code of this file.

Namespaces

 llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
 llvm::RISCVVPseudosTable
 

Macros

#define GEN_CHECK_COMPRESS_INSTR
 
#define GET_INSTRINFO_CTOR_DTOR
 
#define GET_RISCVVPseudosTable_IMPL
 
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)   RISCV::PseudoV##OP##_##TYPE##_##LMUL
 
#define CASE_VFMA_OPCODE_LMULS(OP, TYPE)
 
#define CASE_VFMA_SPLATS(OP)
 
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
 
#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)
 
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)
 
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)   RISCV::PseudoV##OP##_##LMUL##_TIED
 
#define CASE_WIDEOP_OPCODE_LMULS(OP)
 
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
 
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)
 

Enumerations

enum  MachineOutlinerConstructionID { MachineOutlinerDefault }
 

Functions

static bool forwardCopyWillClobberTuple (unsigned DstReg, unsigned SrcReg, unsigned NumRegs)
 
static bool isConvertibleToVMV_V_V (const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVII::VLMUL LMul)
 
static RISCVCC::CondCode getCondFromBranchOpc (unsigned Opc)
 
static void parseCondBranch (MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
 
static bool isRVVWholeLoadStore (unsigned Opcode)
 

Variables

static cl::opt< bool > PreferWholeRegisterMove ("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))
 

Macro Definition Documentation

◆ CASE_VFMA_CHANGE_OPCODE_COMMON

#define CASE_VFMA_CHANGE_OPCODE_COMMON (   OLDOP,
  NEWOP,
  TYPE,
  LMUL 
)
Value:
case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \
Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
break;

Definition at line 1528 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS

#define CASE_VFMA_CHANGE_OPCODE_LMULS (   OLDOP,
  NEWOP,
  TYPE 
)
Value:
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)

Definition at line 1533 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_SPLATS

#define CASE_VFMA_CHANGE_OPCODE_SPLATS (   OLDOP,
  NEWOP 
)
Value:
CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF16) \
CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF32) \
CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF64)

Definition at line 1542 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_COMMON

#define CASE_VFMA_OPCODE_COMMON (   OP,
  TYPE,
  LMUL 
)    RISCV::PseudoV##OP##_##TYPE##_##LMUL

Definition at line 1396 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS

#define CASE_VFMA_OPCODE_LMULS (   OP,
  TYPE 
)
Value:

Definition at line 1399 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_SPLATS

#define CASE_VFMA_SPLATS (   OP)
Value:

Definition at line 1408 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_WIDEOP_CHANGE_OPCODE_COMMON (   OP,
  LMUL 
)
Value:
case RISCV::PseudoV##OP##_##LMUL##_TIED: \
NewOpc = RISCV::PseudoV##OP##_##LMUL; \
break;

Definition at line 1664 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS (   OP)
Value:
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)

Definition at line 1669 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_COMMON

#define CASE_WIDEOP_OPCODE_COMMON (   OP,
  LMUL 
)    RISCV::PseudoV##OP##_##LMUL##_TIED

Definition at line 1652 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_OPCODE_LMULS

#define CASE_WIDEOP_OPCODE_LMULS (   OP)

◆ GEN_CHECK_COMPRESS_INSTR

#define GEN_CHECK_COMPRESS_INSTR

Definition at line 34 of file RISCVInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 37 of file RISCVInstrInfo.cpp.

◆ GET_RISCVVPseudosTable_IMPL

#define GET_RISCVVPseudosTable_IMPL

Definition at line 49 of file RISCVInstrInfo.cpp.

Enumeration Type Documentation

◆ MachineOutlinerConstructionID

Enumerator
MachineOutlinerDefault 

Definition at line 1261 of file RISCVInstrInfo.cpp.

Function Documentation

◆ forwardCopyWillClobberTuple()

static bool forwardCopyWillClobberTuple ( unsigned  DstReg,
unsigned  SrcReg,
unsigned  NumRegs 
)
static

Definition at line 119 of file RISCVInstrInfo.cpp.

◆ getCondFromBranchOpc()

static RISCVCC::CondCode getCondFromBranchOpc ( unsigned  Opc)
static

◆ isConvertibleToVMV_V_V()

static bool isConvertibleToVMV_V_V ( const RISCVSubtarget STI,
const MachineBasicBlock MBB,
MachineBasicBlock::const_iterator  MBBI,
MachineBasicBlock::const_iterator DefMBBI,
RISCVII::VLMUL  LMul 
)
static

◆ isRVVWholeLoadStore()

static bool isRVVWholeLoadStore ( unsigned  Opcode)
static

Definition at line 1819 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::isRVVSpill().

◆ parseCondBranch()

static void parseCondBranch ( MachineInstr LastInst,
MachineBasicBlock *&  Target,
SmallVectorImpl< MachineOperand > &  Cond 
)
static

Variable Documentation

◆ PreferWholeRegisterMove

cl::opt<bool> PreferWholeRegisterMove("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))
static

Referenced by isConvertibleToVMV_V_V().

CASE_WIDEOP_OPCODE_COMMON
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)
Definition: RISCVInstrInfo.cpp:1652
CASE_WIDEOP_CHANGE_OPCODE_COMMON
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
Definition: RISCVInstrInfo.cpp:1664
CASE_VFMA_OPCODE_COMMON
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)
Definition: RISCVInstrInfo.cpp:1396
OP
#define OP(n)
Definition: regex2.h:73
_
#define _
Definition: HexagonMCCodeEmitter.cpp:47
CASE_VFMA_OPCODE_LMULS
#define CASE_VFMA_OPCODE_LMULS(OP, TYPE)
Definition: RISCVInstrInfo.cpp:1399
case
we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a they should be sunk into the ones that do In this case
Definition: README.txt:429
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
CASE_VFMA_CHANGE_OPCODE_LMULS
#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)
Definition: RISCVInstrInfo.cpp:1533
llvm::M1
unsigned M1(unsigned Val)
Definition: VE.h:372
CASE_VFMA_CHANGE_OPCODE_COMMON
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
Definition: RISCVInstrInfo.cpp:1528