LLVM 17.0.0git
RISCV.h
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1//===-- RISCV.h - Top-level interface for RISC-V ----------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the entry points for global functions defined in the LLVM
10// RISC-V back-end.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
15#define LLVM_LIB_TARGET_RISCV_RISCV_H
16
19
20namespace llvm {
21class AsmPrinter;
22class FunctionPass;
23class InstructionSelector;
24class MCInst;
25class MCOperand;
26class MachineInstr;
27class MachineOperand;
28class PassRegistry;
29class RISCVRegisterBankInfo;
30class RISCVSubtarget;
31class RISCVTargetMachine;
32
33FunctionPass *createRISCVCodeGenPreparePass();
35
37 AsmPrinter &AP);
39 MCOperand &MCOp, const AsmPrinter &AP);
40
42 CodeGenOpt::Level OptLevel);
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73extern char &RISCVInitUndefID;
74
79} // namespace llvm
80
81#endif
IRTranslator LLVM IR MI
const char LLVMTargetMachineRef TM
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:84
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
Provides the logic to select generic machine instructions.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
This class provides the information for the target register banks.
Level
Code generation optimization level.
Definition: CodeGen.h:57
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeRISCVExpandPseudoPass(PassRegistry &)
FunctionPass * createRISCVExpandAtomicPseudoPass()
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
void initializeRISCVInitUndefPass(PassRegistry &)
void initializeRISCVRedundantCopyEliminationPass(PassRegistry &)
FunctionPass * createRISCVGatherScatterLoweringPass()
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
void initializeRISCVDAGToDAGISelPass(PassRegistry &)
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
FunctionPass * createRISCVRedundantCopyEliminationPass()
void initializeRISCVExpandAtomicPseudoPass(PassRegistry &)
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOpt::Level OptLevel)
FunctionPass * createRISCVOptWInstrsPass()
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVCodeGenPreparePass()
bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP)
bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
void initializeRISCVOptWInstrsPass(PassRegistry &)
void initializeRISCVCodeGenPreparePass(PassRegistry &)
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createRISCVExpandPseudoPass()
FunctionPass * createRISCVPreRAExpandPseudoPass()
FunctionPass * createRISCVInitUndefPass()
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI)
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
char & RISCVInitUndefID