LLVM 17.0.0git
Classes | Namespaces | Macros | Enumerations | Functions
RISCVBaseInfo.h File Reference
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/RISCVISAInfo.h"
#include "RISCVGenSearchableTables.inc"
Include dependency graph for RISCVBaseInfo.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct  llvm::RISCVSysReg::SysReg
 
struct  llvm::RISCVInsnOpcode::RISCVOpcode
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::RISCVII
 
namespace  llvm::RISCVOp
 
namespace  llvm::RISCVFenceField
 
namespace  llvm::RISCVFPRndMode
 
namespace  llvm::RISCVLoadFPImm
 
namespace  llvm::RISCVSysReg
 
namespace  llvm::RISCVInsnOpcode
 
namespace  llvm::RISCVABI
 
namespace  llvm::RISCVFeatures
 
namespace  llvm::RISCVVType
 
namespace  llvm::RISCVRVC
 

Macros

#define GET_SysRegsList_DECL
 
#define GET_RISCVOpcodesList_DECL
 

Enumerations

enum  {
  llvm::RISCVII::InstFormatPseudo = 0 , llvm::RISCVII::InstFormatR = 1 , llvm::RISCVII::InstFormatR4 = 2 , llvm::RISCVII::InstFormatI = 3 ,
  llvm::RISCVII::InstFormatS = 4 , llvm::RISCVII::InstFormatB = 5 , llvm::RISCVII::InstFormatU = 6 , llvm::RISCVII::InstFormatJ = 7 ,
  llvm::RISCVII::InstFormatCR = 8 , llvm::RISCVII::InstFormatCI = 9 , llvm::RISCVII::InstFormatCSS = 10 , llvm::RISCVII::InstFormatCIW = 11 ,
  llvm::RISCVII::InstFormatCL = 12 , llvm::RISCVII::InstFormatCS = 13 , llvm::RISCVII::InstFormatCA = 14 , llvm::RISCVII::InstFormatCB = 15 ,
  llvm::RISCVII::InstFormatCJ = 16 , llvm::RISCVII::InstFormatCU = 17 , llvm::RISCVII::InstFormatCLB = 18 , llvm::RISCVII::InstFormatCLH = 19 ,
  llvm::RISCVII::InstFormatCSB = 20 , llvm::RISCVII::InstFormatCSH = 21 , llvm::RISCVII::InstFormatOther = 22 , llvm::RISCVII::InstFormatMask = 31 ,
  llvm::RISCVII::InstFormatShift = 0 , llvm::RISCVII::ConstraintShift = InstFormatShift + 5 , llvm::RISCVII::ConstraintMask = 0b111 << ConstraintShift , llvm::RISCVII::VLMulShift = ConstraintShift + 3 ,
  llvm::RISCVII::VLMulMask = 0b111 << VLMulShift , llvm::RISCVII::HasDummyMaskOpShift = VLMulShift + 3 , llvm::RISCVII::HasDummyMaskOpMask = 1 << HasDummyMaskOpShift , llvm::RISCVII::ForceTailAgnosticShift = HasDummyMaskOpShift + 1 ,
  llvm::RISCVII::ForceTailAgnosticMask = 1 << ForceTailAgnosticShift , llvm::RISCVII::HasMergeOpShift = ForceTailAgnosticShift + 1 , llvm::RISCVII::HasMergeOpMask = 1 << HasMergeOpShift , llvm::RISCVII::HasSEWOpShift = HasMergeOpShift + 1 ,
  llvm::RISCVII::HasSEWOpMask = 1 << HasSEWOpShift , llvm::RISCVII::HasVLOpShift = HasSEWOpShift + 1 , llvm::RISCVII::HasVLOpMask = 1 << HasVLOpShift , llvm::RISCVII::HasVecPolicyOpShift = HasVLOpShift + 1 ,
  llvm::RISCVII::HasVecPolicyOpMask = 1 << HasVecPolicyOpShift , llvm::RISCVII::IsRVVWideningReductionShift = HasVecPolicyOpShift + 1 , llvm::RISCVII::IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift , llvm::RISCVII::UsesMaskPolicyShift = IsRVVWideningReductionShift + 1 ,
  llvm::RISCVII::UsesMaskPolicyMask = 1 << UsesMaskPolicyShift , llvm::RISCVII::IsSignExtendingOpWShift = UsesMaskPolicyShift + 1 , llvm::RISCVII::IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift
}
 
enum  llvm::RISCVII::VConstraintType { llvm::RISCVII::NoConstraint = 0 , llvm::RISCVII::VS2Constraint = 0b001 , llvm::RISCVII::VS1Constraint = 0b010 , llvm::RISCVII::VMConstraint = 0b100 }
 
enum  llvm::RISCVII::VLMUL : uint8_t {
  llvm::RISCVII::LMUL_1 = 0 , llvm::RISCVII::LMUL_2 , llvm::RISCVII::LMUL_4 , llvm::RISCVII::LMUL_8 ,
  llvm::RISCVII::LMUL_RESERVED , llvm::RISCVII::LMUL_F8 , llvm::RISCVII::LMUL_F4 , llvm::RISCVII::LMUL_F2
}
 
enum  { llvm::RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED = 0 , llvm::RISCVII::TAIL_AGNOSTIC = 1 , llvm::RISCVII::MASK_AGNOSTIC = 2 }
 
enum  {
  llvm::RISCVII::MO_None = 0 , llvm::RISCVII::MO_CALL = 1 , llvm::RISCVII::MO_PLT = 2 , llvm::RISCVII::MO_LO = 3 ,
  llvm::RISCVII::MO_HI = 4 , llvm::RISCVII::MO_PCREL_LO = 5 , llvm::RISCVII::MO_PCREL_HI = 6 , llvm::RISCVII::MO_GOT_HI = 7 ,
  llvm::RISCVII::MO_TPREL_LO = 8 , llvm::RISCVII::MO_TPREL_HI = 9 , llvm::RISCVII::MO_TPREL_ADD = 10 , llvm::RISCVII::MO_TLS_GOT_HI = 11 ,
  llvm::RISCVII::MO_TLS_GD_HI = 12 , llvm::RISCVII::MO_DIRECT_FLAG_MASK = 15
}
 
enum  llvm::RISCVOp::OperandType : unsigned {
  llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET , llvm::RISCVOp::OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM , llvm::RISCVOp::OPERAND_UIMM2_LSB0 , llvm::RISCVOp::OPERAND_UIMM3 ,
  llvm::RISCVOp::OPERAND_UIMM4 , llvm::RISCVOp::OPERAND_UIMM5 , llvm::RISCVOp::OPERAND_UIMM7 , llvm::RISCVOp::OPERAND_UIMM7_LSB00 ,
  llvm::RISCVOp::OPERAND_UIMM8_LSB00 , llvm::RISCVOp::OPERAND_UIMM8_LSB000 , llvm::RISCVOp::OPERAND_UIMM9_LSB000 , llvm::RISCVOp::OPERAND_UIMM10_LSB00_NONZERO ,
  llvm::RISCVOp::OPERAND_UIMM12 , llvm::RISCVOp::OPERAND_ZERO , llvm::RISCVOp::OPERAND_SIMM5 , llvm::RISCVOp::OPERAND_SIMM5_PLUS1 ,
  llvm::RISCVOp::OPERAND_SIMM6 , llvm::RISCVOp::OPERAND_SIMM6_NONZERO , llvm::RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO , llvm::RISCVOp::OPERAND_SIMM12 ,
  llvm::RISCVOp::OPERAND_SIMM12_LSB00000 , llvm::RISCVOp::OPERAND_UIMM20 , llvm::RISCVOp::OPERAND_UIMMLOG2XLEN , llvm::RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO ,
  llvm::RISCVOp::OPERAND_CLUI_IMM , llvm::RISCVOp::OPERAND_VTYPEI10 , llvm::RISCVOp::OPERAND_VTYPEI11 , llvm::RISCVOp::OPERAND_RVKRNUM ,
  llvm::RISCVOp::OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM , llvm::RISCVOp::OPERAND_AVL
}
 
enum  llvm::RISCVFenceField::FenceField { llvm::RISCVFenceField::I = 8 , llvm::RISCVFenceField::O = 4 , llvm::RISCVFenceField::R = 2 , llvm::RISCVFenceField::W = 1 }
 
enum  llvm::RISCVFPRndMode::RoundingMode {
  llvm::RISCVFPRndMode::RNE = 0 , llvm::RISCVFPRndMode::RTZ = 1 , llvm::RISCVFPRndMode::RDN = 2 , llvm::RISCVFPRndMode::RUP = 3 ,
  llvm::RISCVFPRndMode::RMM = 4 , llvm::RISCVFPRndMode::DYN = 7 , llvm::RISCVFPRndMode::Invalid
}
 
enum  llvm::RISCVABI::ABI {
  llvm::RISCVABI::ABI_ILP32 , llvm::RISCVABI::ABI_ILP32F , llvm::RISCVABI::ABI_ILP32D , llvm::RISCVABI::ABI_ILP32E ,
  llvm::RISCVABI::ABI_LP64 , llvm::RISCVABI::ABI_LP64F , llvm::RISCVABI::ABI_LP64D , llvm::RISCVABI::ABI_Unknown
}
 

Functions

static unsigned llvm::RISCVII::getFormat (uint64_t TSFlags)
 
static VConstraintType llvm::RISCVII::getConstraint (uint64_t TSFlags)
 
static VLMUL llvm::RISCVII::getLMul (uint64_t TSFlags)
 
static bool llvm::RISCVII::hasDummyMaskOp (uint64_t TSFlags)
 
static bool llvm::RISCVII::doesForceTailAgnostic (uint64_t TSFlags)
 
static bool llvm::RISCVII::hasMergeOp (uint64_t TSFlags)
 
static bool llvm::RISCVII::hasSEWOp (uint64_t TSFlags)
 
static bool llvm::RISCVII::hasVLOp (uint64_t TSFlags)
 
static bool llvm::RISCVII::hasVecPolicyOp (uint64_t TSFlags)
 
static bool llvm::RISCVII::isRVVWideningReduction (uint64_t TSFlags)
 
static bool llvm::RISCVII::usesMaskPolicy (uint64_t TSFlags)
 
static unsigned llvm::RISCVII::getMergeOpNum (const MCInstrDesc &Desc)
 
static unsigned llvm::RISCVII::getVLOpNum (const MCInstrDesc &Desc)
 
static unsigned llvm::RISCVII::getSEWOpNum (const MCInstrDesc &Desc)
 
static unsigned llvm::RISCVII::getVecPolicyOpNum (const MCInstrDesc &Desc)
 
static StringRef llvm::RISCVFPRndMode::roundingModeToString (RoundingMode RndMode)
 
static RoundingMode llvm::RISCVFPRndMode::stringToRoundingMode (StringRef Str)
 
static bool llvm::RISCVFPRndMode::isValidRoundingMode (unsigned Mode)
 
float llvm::RISCVLoadFPImm::getFPImm (unsigned Imm)
 
int llvm::RISCVLoadFPImm::getLoadFPImm (APFloat FPImm)
 getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
 
ABI llvm::RISCVABI::computeTargetABI (const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
 
ABI llvm::RISCVABI::getTargetABI (StringRef ABIName)
 
MCRegister llvm::RISCVABI::getBPReg ()
 
MCRegister llvm::RISCVABI::getSCSPReg ()
 
void llvm::RISCVFeatures::validate (const Triple &TT, const FeatureBitset &FeatureBits)
 
llvm::Expected< std::unique_ptr< RISCVISAInfo > > llvm::RISCVFeatures::parseFeatureBits (bool IsRV64, const FeatureBitset &FeatureBits)
 
static bool llvm::RISCVVType::isValidSEW (unsigned SEW)
 
static bool llvm::RISCVVType::isValidLMUL (unsigned LMUL, bool Fractional)
 
unsigned llvm::RISCVVType::encodeVTYPE (RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
 
static RISCVII::VLMUL llvm::RISCVVType::getVLMUL (unsigned VType)
 
std::pair< unsigned, bool > llvm::RISCVVType::decodeVLMUL (RISCVII::VLMUL VLMUL)
 
static RISCVII::VLMUL llvm::RISCVVType::encodeLMUL (unsigned LMUL, bool Fractional)
 
static unsigned llvm::RISCVVType::decodeVSEW (unsigned VSEW)
 
static unsigned llvm::RISCVVType::encodeSEW (unsigned SEW)
 
static unsigned llvm::RISCVVType::getSEW (unsigned VType)
 
static bool llvm::RISCVVType::isTailAgnostic (unsigned VType)
 
static bool llvm::RISCVVType::isMaskAgnostic (unsigned VType)
 
void llvm::RISCVVType::printVType (unsigned VType, raw_ostream &OS)
 
unsigned llvm::RISCVVType::getSEWLMULRatio (unsigned SEW, RISCVII::VLMUL VLMul)
 
bool llvm::RISCVRVC::compress (MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
 
bool llvm::RISCVRVC::uncompress (MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
 

Macro Definition Documentation

◆ GET_RISCVOpcodesList_DECL

#define GET_RISCVOpcodesList_DECL

Definition at line 397 of file RISCVBaseInfo.h.

◆ GET_SysRegsList_DECL

#define GET_SysRegsList_DECL

Definition at line 387 of file RISCVBaseInfo.h.

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