LLVM 23.0.0git
RISCVMoveMerger.cpp
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1//===-- RISCVMoveMerger.cpp - RISC-V move merge pass ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that performs move related peephole optimizations
10// as Zcmp has specified. This pass should be run after register allocation.
11//
12// This pass also supports Xqccmp, which has identical instructions.
13//
14//===----------------------------------------------------------------------===//
15
16#include "RISCVInstrInfo.h"
17#include "RISCVSubtarget.h"
18
19using namespace llvm;
20
21#define RISCV_MOVE_MERGE_NAME "RISC-V Zcmp move merging pass"
22
23namespace {
24struct RISCVMoveMerge : public MachineFunctionPass {
25 static char ID;
26
27 RISCVMoveMerge() : MachineFunctionPass(ID) {}
28
29 const RISCVSubtarget *ST;
30 const RISCVInstrInfo *TII;
31 const TargetRegisterInfo *TRI;
32
33 // Track which register units have been modified and used.
34 LiveRegUnits ModifiedRegUnits, UsedRegUnits;
35
36 bool isGPRPairCopyCandidate(const DestSourcePair &RegPair, bool EvenRegPair);
37
38 bool isCandidateToMergeMVA01S(const DestSourcePair &RegPair);
39 bool isCandidateToMergeMVSA01(const DestSourcePair &RegPair);
40
41 bool isPLIPairCandidate(const MachineInstr &MI, bool EvenRegPair);
42
43 // Merge the two instructions indicated into a single pair instruction.
44 MachineBasicBlock::iterator
45 mergeGPRPairInsns(MachineBasicBlock::iterator I,
46 MachineBasicBlock::iterator Paired, bool RegPairIsEven);
47 MachineBasicBlock::iterator
48 mergePairedInsns(MachineBasicBlock::iterator I,
49 MachineBasicBlock::iterator Paired, bool MoveFromSToA);
50 MachineBasicBlock::iterator mergePLIPair(MachineBasicBlock::iterator I,
51 MachineBasicBlock::iterator Paired,
52 bool RegPairIsEven);
53
54 MachineBasicBlock::iterator
55 findMatchingGPRPairCopy(MachineBasicBlock::iterator &MBBI, bool EvenRegPair,
56 const DestSourcePair &RegPair);
57 // Look for C.MV instruction that can be combined with
58 // the given instruction into CM.MVA01S or CM.MVSA01. Return the matching
59 // instruction if one exists.
60 MachineBasicBlock::iterator
61 findMatchingSACopy(MachineBasicBlock::iterator &MBBI, bool MoveFromSToA,
62 const DestSourcePair &RegPair);
63 MachineBasicBlock::iterator findMatchingPLI(MachineBasicBlock::iterator &MBBI,
64 bool EvenRegPair);
65 bool mergeMovePairs(MachineBasicBlock &MBB);
66 bool runOnMachineFunction(MachineFunction &Fn) override;
67
68 StringRef getPassName() const override { return RISCV_MOVE_MERGE_NAME; }
69};
70
71char RISCVMoveMerge::ID = 0;
72
73} // end of anonymous namespace
74
75INITIALIZE_PASS(RISCVMoveMerge, "riscv-move-merge", RISCV_MOVE_MERGE_NAME,
76 false, false)
77
78static unsigned getGPRPairCopyOpcode(const RISCVSubtarget &ST) {
79 if (ST.hasStdExtZdinx())
80 return RISCV::FSGNJ_D_IN32X;
81
82 if (ST.hasStdExtP())
83 return RISCV::PADD_DW;
84
85 llvm_unreachable("Unhandled subtarget with paired move.");
86}
87
88static unsigned getCM_MVOpcode(const RISCVSubtarget &ST, bool MoveFromSToA) {
89 if (ST.hasStdExtZcmp())
90 return MoveFromSToA ? RISCV::CM_MVA01S : RISCV::CM_MVSA01;
91
92 if (ST.hasVendorXqccmp())
93 return MoveFromSToA ? RISCV::QC_CM_MVA01S : RISCV::QC_CM_MVSA01;
94
95 llvm_unreachable("Unhandled subtarget with paired move.");
96}
97
98// Returns 0 if Opc has no paired form.
99static unsigned getPairedPLIOpcode(unsigned Opc) {
100 switch (Opc) {
101 case RISCV::PLI_B:
102 return RISCV::PLI_DB;
103 case RISCV::PLI_H:
104 return RISCV::PLI_DH;
105 case RISCV::PLUI_H:
106 return RISCV::PLUI_DH;
107 default:
108 return 0;
109 }
110}
111
112bool RISCVMoveMerge::isGPRPairCopyCandidate(const DestSourcePair &RegPair,
113 bool EvenRegPair) {
114 Register Destination = RegPair.Destination->getReg();
115 Register Source = RegPair.Source->getReg();
116
117 if (Source == Destination)
118 return false;
119
120 if ((!ST->hasStdExtZdinx() && !ST->hasStdExtP()) || ST->is64Bit())
121 return false;
122
123 unsigned SubIdx = EvenRegPair ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
124
125 Register SrcPair =
126 TRI->getMatchingSuperReg(Source, SubIdx, &RISCV::GPRPairRegClass);
127 Register DestPair =
128 TRI->getMatchingSuperReg(Destination, SubIdx, &RISCV::GPRPairRegClass);
129
130 return SrcPair.isValid() && DestPair.isValid();
131}
132
133// Check if registers meet CM.MVA01S constraints.
134bool RISCVMoveMerge::isCandidateToMergeMVA01S(const DestSourcePair &RegPair) {
135 Register Destination = RegPair.Destination->getReg();
136 Register Source = RegPair.Source->getReg();
137 // If destination is not a0 or a1.
138 if ((ST->hasStdExtZcmp() || ST->hasVendorXqccmp()) &&
139 (Destination == RISCV::X10 || Destination == RISCV::X11) &&
140 RISCV::SR07RegClass.contains(Source))
141 return true;
142 return false;
143}
144
145// Check if registers meet CM.MVSA01 constraints.
146bool RISCVMoveMerge::isCandidateToMergeMVSA01(const DestSourcePair &RegPair) {
147 Register Destination = RegPair.Destination->getReg();
148 Register Source = RegPair.Source->getReg();
149 // If Source is s0 - s7.
150 if ((ST->hasStdExtZcmp() || ST->hasVendorXqccmp()) &&
151 (Source == RISCV::X10 || Source == RISCV::X11) &&
152 RISCV::SR07RegClass.contains(Destination))
153 return true;
154 return false;
155}
156
157// Check if MI is a single-reg pli/plui whose destination is a half of a
158// GPRPair.
159bool RISCVMoveMerge::isPLIPairCandidate(const MachineInstr &MI,
160 bool EvenRegPair) {
161 if (!ST->hasStdExtP() || ST->is64Bit())
162 return false;
163 if (!getPairedPLIOpcode(MI.getOpcode()))
164 return false;
165 unsigned SubIdx = EvenRegPair ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
166 return TRI
167 ->getMatchingSuperReg(MI.getOperand(0).getReg(), SubIdx,
168 &RISCV::GPRPairRegClass)
169 .isValid();
170}
171
172MachineBasicBlock::iterator
173RISCVMoveMerge::mergeGPRPairInsns(MachineBasicBlock::iterator I,
174 MachineBasicBlock::iterator Paired,
175 bool RegPairIsEven) {
176 MachineBasicBlock::iterator E = I->getParent()->end();
177 MachineBasicBlock::iterator NextI = next_nodbg(I, E);
178 DestSourcePair FirstPair = *TII->isCopyInstrImpl(*I);
179 DestSourcePair SecondPair = *TII->isCopyInstrImpl(*Paired);
180
181 if (NextI == Paired)
182 NextI = next_nodbg(NextI, E);
183 DebugLoc DL = I->getDebugLoc();
184
185 // Make a copy of the second instruction to update the kill
186 // flag.
187 MachineOperand PairedSource = *SecondPair.Source;
188
189 unsigned Opcode = getGPRPairCopyOpcode(*ST);
190 for (auto It = std::next(I); It != Paired && PairedSource.isKill(); ++It)
191 if (It->readsRegister(PairedSource.getReg(), TRI))
192 PairedSource.setIsKill(false);
193
194 Register SrcReg1, SrcReg2, DestReg;
195 unsigned GPRPairIdx =
196 RegPairIsEven ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
197 SrcReg1 = TRI->getMatchingSuperReg(FirstPair.Source->getReg(), GPRPairIdx,
198 &RISCV::GPRPairRegClass);
199 SrcReg2 = ST->hasStdExtZdinx() ? SrcReg1 : Register(RISCV::X0_Pair);
200 DestReg = TRI->getMatchingSuperReg(FirstPair.Destination->getReg(),
201 GPRPairIdx, &RISCV::GPRPairRegClass);
202
203 BuildMI(*I->getParent(), I, DL, TII->get(Opcode), DestReg)
204 .addReg(SrcReg1, getKillRegState(PairedSource.isKill() &&
205 FirstPair.Source->isKill()))
206 .addReg(SrcReg2, getKillRegState(PairedSource.isKill() &&
207 FirstPair.Source->isKill()));
208
209 I->eraseFromParent();
210 Paired->eraseFromParent();
211 return NextI;
212}
213
214MachineBasicBlock::iterator
215RISCVMoveMerge::mergePairedInsns(MachineBasicBlock::iterator I,
216 MachineBasicBlock::iterator Paired,
217 bool MoveFromSToA) {
218 const MachineOperand *Sreg1, *Sreg2;
219 MachineBasicBlock::iterator E = I->getParent()->end();
220 MachineBasicBlock::iterator NextI = next_nodbg(I, E);
221 DestSourcePair FirstPair = *TII->isCopyInstrImpl(*I);
222 DestSourcePair PairedRegs = *TII->isCopyInstrImpl(*Paired);
223
224 if (NextI == Paired)
225 NextI = next_nodbg(NextI, E);
226 DebugLoc DL = I->getDebugLoc();
227
228 // Make a copy so we can update the kill flag in the MoveFromSToA case. The
229 // copied operand needs to be scoped outside the if since we make a pointer
230 // to it.
231 MachineOperand PairedSource = *PairedRegs.Source;
232
233 // The order of S-reg depends on which instruction holds A0, instead of
234 // the order of register pair.
235 // e,g.
236 // mv a1, s1
237 // mv a0, s2 => cm.mva01s s2,s1
238 //
239 // mv a0, s2
240 // mv a1, s1 => cm.mva01s s2,s1
241 unsigned Opcode = getCM_MVOpcode(*ST, MoveFromSToA);
242 if (MoveFromSToA) {
243 // We are moving one of the copies earlier so its kill flag may become
244 // invalid. Clear the copied kill flag if there are any reads of the
245 // register between the new location and the old location.
246 for (auto It = std::next(I); It != Paired && PairedSource.isKill(); ++It)
247 if (It->readsRegister(PairedSource.getReg(), TRI))
248 PairedSource.setIsKill(false);
249
250 Sreg1 = FirstPair.Source;
251 Sreg2 = &PairedSource;
252 if (FirstPair.Destination->getReg() != RISCV::X10)
253 std::swap(Sreg1, Sreg2);
254 } else {
255 Sreg1 = FirstPair.Destination;
256 Sreg2 = PairedRegs.Destination;
257 if (FirstPair.Source->getReg() != RISCV::X10)
258 std::swap(Sreg1, Sreg2);
259 }
260
261 BuildMI(*I->getParent(), I, DL, TII->get(Opcode)).add(*Sreg1).add(*Sreg2);
262
263 I->eraseFromParent();
264 Paired->eraseFromParent();
265 return NextI;
266}
267
268MachineBasicBlock::iterator
269RISCVMoveMerge::mergePLIPair(MachineBasicBlock::iterator I,
270 MachineBasicBlock::iterator Paired,
271 bool RegPairIsEven) {
272 MachineBasicBlock::iterator E = I->getParent()->end();
273 MachineBasicBlock::iterator NextI = next_nodbg(I, E);
274
275 if (NextI == Paired)
276 NextI = next_nodbg(NextI, E);
277 DebugLoc DL = I->getDebugLoc();
278
279 unsigned Opcode = getPairedPLIOpcode(I->getOpcode());
280 unsigned GPRPairIdx =
281 RegPairIsEven ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
282 Register DestReg = TRI->getMatchingSuperReg(
283 I->getOperand(0).getReg(), GPRPairIdx, &RISCV::GPRPairRegClass);
284
285 BuildMI(*I->getParent(), I, DL, TII->get(Opcode), DestReg)
286 .addImm(I->getOperand(1).getImm());
287
288 I->eraseFromParent();
289 Paired->eraseFromParent();
290 return NextI;
291}
292
293MachineBasicBlock::iterator
294RISCVMoveMerge::findMatchingGPRPairCopy(MachineBasicBlock::iterator &MBBI,
295 bool EvenRegPair,
296 const DestSourcePair &RegPair) {
297 MachineBasicBlock::iterator E = MBBI->getParent()->end();
298 ModifiedRegUnits.clear();
299 UsedRegUnits.clear();
300 unsigned RegPairIdx = EvenRegPair ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
301 unsigned SecondPairIdx =
302 !EvenRegPair ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
303
304 // Get the expected source/destination registers of the matching lane.
305 Register SrcGPRPair = TRI->getMatchingSuperReg(
306 RegPair.Source->getReg(), RegPairIdx, &RISCV::GPRPairRegClass);
307 Register DestGPRPair = TRI->getMatchingSuperReg(
308 RegPair.Destination->getReg(), RegPairIdx, &RISCV::GPRPairRegClass);
309 Register ExpectedSourceReg = TRI->getSubReg(SrcGPRPair, SecondPairIdx);
310 Register ExpectedDestReg = TRI->getSubReg(DestGPRPair, SecondPairIdx);
311
312 for (MachineBasicBlock::iterator I = next_nodbg(MBBI, E); I != E;
313 I = next_nodbg(I, E)) {
314
315 MachineInstr &MI = *I;
316
317 if (auto SecondPair = TII->isCopyInstrImpl(MI)) {
318 Register SourceReg = SecondPair->Source->getReg();
319 Register DestReg = SecondPair->Destination->getReg();
320
321 if (RegPair.Destination->getReg() == DestReg ||
322 RegPair.Source->getReg() == SourceReg)
323 return E;
324
325 // Check if the second pair's registers match the other lane of the
326 // GPRPairs.
327 if (SourceReg == ExpectedSourceReg && DestReg == ExpectedDestReg)
328 return I;
329 }
330 // Update modified / used register units.
331 LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits, TRI);
332 // Once expected lane registers are clobbered/read in-between, we can stop
333 // scanning since the pair cannot be legally merged anymore.
334 if (!ModifiedRegUnits.available(ExpectedDestReg) ||
335 !UsedRegUnits.available(ExpectedDestReg) ||
336 !ModifiedRegUnits.available(ExpectedSourceReg))
337 return E;
338 }
339 return E;
340}
341
342MachineBasicBlock::iterator
343RISCVMoveMerge::findMatchingSACopy(MachineBasicBlock::iterator &MBBI,
344 bool MoveFromSToA,
345 const DestSourcePair &RegPair) {
346 MachineBasicBlock::iterator E = MBBI->getParent()->end();
347
348 // Track which register units have been modified and used between the first
349 // insn and the second insn.
350 ModifiedRegUnits.clear();
351 UsedRegUnits.clear();
352
353 for (MachineBasicBlock::iterator I = next_nodbg(MBBI, E); I != E;
354 I = next_nodbg(I, E)) {
355
356 MachineInstr &MI = *I;
357
358 if (auto SecondPair = TII->isCopyInstrImpl(MI)) {
359 Register SourceReg = SecondPair->Source->getReg();
360 Register DestReg = SecondPair->Destination->getReg();
361
362 bool IsCandidate = MoveFromSToA ? isCandidateToMergeMVA01S(*SecondPair)
363 : isCandidateToMergeMVSA01(*SecondPair);
364 if (IsCandidate) {
365 // Second destination must be different.
366 if (RegPair.Destination->getReg() == DestReg)
367 return E;
368
369 // For AtoS the source must also be different.
370 if (!MoveFromSToA && RegPair.Source->getReg() == SourceReg)
371 return E;
372
373 // If paired destination register was modified or used, the source reg
374 // was modified, there is no possibility of finding matching
375 // instruction so exit early.
376 if (!ModifiedRegUnits.available(DestReg) ||
377 !UsedRegUnits.available(DestReg) ||
378 !ModifiedRegUnits.available(SourceReg))
379 return E;
380
381 return I;
382 }
383 }
384 // Update modified / used register units.
385 LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits, TRI);
386 }
387 return E;
388}
389
390// Look for a same-opcode pli/plui writing the other lane of the same GPRPair
391// with the same immediate. Return the matching instruction if one exists.
392MachineBasicBlock::iterator
393RISCVMoveMerge::findMatchingPLI(MachineBasicBlock::iterator &MBBI,
394 bool EvenRegPair) {
395 MachineBasicBlock::iterator E = MBBI->getParent()->end();
396 ModifiedRegUnits.clear();
397 UsedRegUnits.clear();
398 unsigned Opc = MBBI->getOpcode();
399 Register FirstDestReg = MBBI->getOperand(0).getReg();
400 int64_t FirstImm = MBBI->getOperand(1).getImm();
401 unsigned RegPairIdx = EvenRegPair ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
402 unsigned SecondPairIdx =
403 !EvenRegPair ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
404
405 // Get the expected destination register of the matching lane.
406 Register DestGPRPair = TRI->getMatchingSuperReg(FirstDestReg, RegPairIdx,
407 &RISCV::GPRPairRegClass);
408 Register ExpectedDestReg = TRI->getSubReg(DestGPRPair, SecondPairIdx);
409
410 for (MachineBasicBlock::iterator I = next_nodbg(MBBI, E); I != E;
411 I = next_nodbg(I, E)) {
412
413 MachineInstr &MI = *I;
414
415 if (MI.getOpcode() == Opc) {
416 Register DestReg = MI.getOperand(0).getReg();
417 int64_t Imm = MI.getOperand(1).getImm();
418
419 if (FirstDestReg == DestReg)
420 return E;
421
422 // Check if the second PLI matches the other lane and immediate.
423 if (DestReg == ExpectedDestReg && Imm == FirstImm)
424 return I;
425 }
426 // Update modified / used register units.
427 LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits, TRI);
428 // Once the expected lane register is clobbered/read in-between, we can
429 // stop scanning since the pair cannot be legally merged anymore.
430 if (!ModifiedRegUnits.available(ExpectedDestReg) ||
431 !UsedRegUnits.available(ExpectedDestReg))
432 return E;
433 }
434 return E;
435}
436
437// Finds instructions, which could be represented as C.MV instructions and
438// merged into CM.MVA01S or CM.MVSA01.
439bool RISCVMoveMerge::mergeMovePairs(MachineBasicBlock &MBB) {
440 bool Modified = false;
441
442 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
443 MBBI != E;) {
444 // Try merging a pair of single-reg PLI/PLUI into a paired form.
445 bool IsPLIEven = isPLIPairCandidate(*MBBI, /*EvenRegPair=*/true);
446 bool IsPLIOdd = isPLIPairCandidate(*MBBI, /*EvenRegPair=*/false);
447 if (IsPLIEven != IsPLIOdd) {
448 MachineBasicBlock::iterator Paired = findMatchingPLI(MBBI, IsPLIEven);
449 if (Paired != E) {
450 MBBI = mergePLIPair(MBBI, Paired, IsPLIEven);
451 Modified = true;
452 continue;
453 }
454 }
455
456 // Check if the instruction can be compressed to C.MV instruction. If it
457 // can, return Dest/Src register pair.
458 auto RegPair = TII->isCopyInstrImpl(*MBBI);
459 if (RegPair.has_value()) {
460 bool MoveFromSToA = isCandidateToMergeMVA01S(*RegPair);
461 bool MoveFromAToS = isCandidateToMergeMVSA01(*RegPair);
462 bool IsEven = isGPRPairCopyCandidate(*RegPair, /*EvenRegPair=*/true);
463 bool IsOdd = isGPRPairCopyCandidate(*RegPair, /*EvenRegPair=*/false);
464 if (!MoveFromSToA && !MoveFromAToS && !IsEven && !IsOdd) {
465 ++MBBI;
466 continue;
467 }
468
469 MachineBasicBlock::iterator Paired = E;
470 if (MoveFromSToA || MoveFromAToS) {
471 Paired = findMatchingSACopy(MBBI, MoveFromSToA, *RegPair);
472 if (Paired != E) {
473 MBBI = mergePairedInsns(MBBI, Paired, MoveFromSToA);
474 Modified = true;
475 continue;
476 }
477 }
478 if (IsEven != IsOdd) {
479 Paired = findMatchingGPRPairCopy(MBBI, IsEven, *RegPair);
480 if (Paired != E) {
481 MBBI = mergeGPRPairInsns(MBBI, Paired, IsEven);
482 Modified = true;
483 continue;
484 }
485 }
486 }
487 ++MBBI;
488 }
489 return Modified;
490}
491
492bool RISCVMoveMerge::runOnMachineFunction(MachineFunction &Fn) {
493 if (skipFunction(Fn.getFunction()))
494 return false;
495
496 ST = &Fn.getSubtarget<RISCVSubtarget>();
497 bool HasGPRPairCopy =
498 !ST->is64Bit() && (ST->hasStdExtZdinx() || ST->hasStdExtP());
499 if (!ST->hasStdExtZcmp() && !ST->hasVendorXqccmp() && !HasGPRPairCopy)
500 return false;
501
502 TII = ST->getInstrInfo();
503 TRI = ST->getRegisterInfo();
504 // Resize the modified and used register unit trackers. We do this once
505 // per function and then clear the register units each time we optimize a
506 // move.
507 ModifiedRegUnits.init(*TRI);
508 UsedRegUnits.init(*TRI);
509 bool Modified = false;
510 for (auto &MBB : Fn)
511 Modified |= mergeMovePairs(MBB);
512 return Modified;
513}
514
515/// createRISCVMoveMergePass - returns an instance of the
516/// move merge pass.
517FunctionPass *llvm::createRISCVMoveMergePass() { return new RISCVMoveMerge(); }
const
aarch64 promote const
Definition AArch64PromoteConstant.cpp:228
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
I
#define I(x, y, z)
Definition MD5.cpp:57
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2127
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
if
if(PassOpts->AAPipeline)
Definition PassBuilderBindings.cpp:64
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
getCM_MVOpcode
static unsigned getCM_MVOpcode(const RISCVSubtarget &ST, bool MoveFromSToA)
Definition RISCVMoveMerger.cpp:88
RISCV_MOVE_MERGE_NAME
#define RISCV_MOVE_MERGE_NAME
Definition RISCVMoveMerger.cpp:21
getPairedPLIOpcode
static unsigned getPairedPLIOpcode(unsigned Opc)
Definition RISCVMoveMerger.cpp:99
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::LiveRegUnits
A set of register units used to track register liveness.
Definition LiveRegUnits.h:31
llvm::LiveRegUnits::accumulateUsedDefed
static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
For a machine instruction MI, adds all register units used in UsedRegUnits and defined or clobbered i...
Definition LiveRegUnits.h:48
llvm::LiveRegUnits::available
bool available(MCRegister Reg) const
Returns true if no part of physical register Reg is live.
Definition LiveRegUnits.h:117
llvm::LiveRegUnits::init
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
Definition LiveRegUnits.h:74
llvm::LiveRegUnits::clear
void clear()
Clears the set.
Definition LiveRegUnits.h:81
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition MachineBasicBlock.h:324
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:342
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:788
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition MachineFunction.h:749
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:73
llvm::MachineInstr::eraseFromParent
LLVM_ABI MachineInstrBundleIterator< MachineInstr > eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition MachineInstr.cpp:796
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition MachineOperand.h:523
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition MachineOperand.h:372
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition RISCVSubtarget.h:147
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition RISCVSubtarget.h:146
llvm::Register::isValid
constexpr bool isValid() const
Definition Register.h:112
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:244
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::dwarf_linker::DebugSectionKind::DebugLoc
@ DebugLoc
Definition DWARFLinkerBase.h:34
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::next_nodbg
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
Definition MachineBasicBlock.h:1506
llvm::createRISCVMoveMergePass
FunctionPass * createRISCVMoveMergePass()
createRISCVMoveMergePass - returns an instance of the move merge pass.
Definition RISCVMoveMerger.cpp:517
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition BitVector.h:862
llvm::DestSourcePair::Source
const MachineOperand * Source
Definition TargetInstrInfo.h:78
llvm::DestSourcePair::Destination
const MachineOperand * Destination
Definition TargetInstrInfo.h:77
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