25#define DEBUG_TYPE "riscv-merge-base-offset"
26#define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
52 MachineFunctionProperties::Property::IsSSA);
69char RISCVMergeBaseOffsetOpt::ID = 0;
91 if (
Hi.getOpcode() != RISCV::LUI &&
Hi.getOpcode() != RISCV::AUIPC)
95 unsigned ExpectedFlags =
103 Register HiDestReg =
Hi.getOperand(0).getReg();
104 if (!
MRI->hasOneUse(HiDestReg))
107 Lo = &*
MRI->use_instr_begin(HiDestReg);
108 if (
Lo->getOpcode() != RISCV::ADDI)
112 if (
Hi.getOpcode() == RISCV::LUI) {
117 assert(
Hi.getOpcode() == RISCV::AUIPC);
143 if (
Hi.getOpcode() != RISCV::AUIPC)
146 MRI->replaceRegWith(
Tail.getOperand(0).getReg(),
Lo.getOperand(0).getReg());
147 Tail.eraseFromParent();
149 <<
" " <<
Hi <<
" " <<
Lo;);
176 assert((TailAdd.
getOpcode() == RISCV::ADD) &&
"Expected ADD instruction!");
182 if (!
MRI->hasOneUse(Reg))
186 if (OffsetTail.
getOpcode() == RISCV::ADDI ||
187 OffsetTail.
getOpcode() == RISCV::ADDIW) {
193 int64_t OffLo = AddiImmOp.
getImm();
197 if (OffsetLui.
getOpcode() != RISCV::LUI ||
201 int64_t
Offset = SignExtend64<32>(LuiImmOp.
getImm() << 12);
204 if (!
ST->is64Bit() || OffsetTail.
getOpcode() == RISCV::ADDIW)
210 <<
" " << OffsetLui);
215 }
else if (OffsetTail.
getOpcode() == RISCV::LUI) {
243 TailShXAdd.
getOpcode() == RISCV::SH2ADD ||
244 TailShXAdd.
getOpcode() == RISCV::SH3ADD) &&
245 "Expected SHXADD instruction!");
254 if (!
MRI->hasOneUse(Rs1))
258 if (OffsetTail.
getOpcode() != RISCV::ADDI)
271 case RISCV::SH1ADD: ShAmt = 1;
break;
272 case RISCV::SH2ADD: ShAmt = 2;
break;
273 case RISCV::SH3ADD: ShAmt = 3;
break;
284bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(
MachineInstr &
Hi,
291 if (!
MRI->hasOneUse(DestReg))
296 switch (
Tail.getOpcode()) {
298 LLVM_DEBUG(
dbgs() <<
"Don't know how to get offset from this instr:"
307 if (
MRI->hasOneUse(TailDestReg)) {
309 if (TailTail.
getOpcode() == RISCV::ADDI) {
313 Tail.eraseFromParent();
331 return foldLargeOffset(
Hi,
Lo,
Tail, DestReg);
338 return foldShiftedOffset(
Hi,
Lo,
Tail, DestReg);
360 std::optional<int64_t> CommonOffset;
362 switch (
UseMI.getOpcode()) {
383 if (
UseMI.getOperand(1).isFI())
389 "Expected base address use");
392 if (CommonOffset &&
Offset != CommonOffset)
403 int64_t NewOffset =
Hi.getOperand(1).getOffset() + *CommonOffset;
406 NewOffset = SignExtend64<32>(NewOffset);
408 if (!isInt<32>(NewOffset))
411 Hi.getOperand(1).setOffset(NewOffset);
413 if (
Hi.getOpcode() != RISCV::AUIPC)
419 UseMI.removeOperand(2);
420 UseMI.addOperand(ImmOp);
423 UseMI.getOperand(1).setReg(
Hi.getOperand(0).getReg());
426 Lo.eraseFromParent();
430bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(
MachineFunction &Fn) {
436 bool MadeChange =
false;
442 if (!detectFoldable(
Hi,
Lo))
444 MadeChange |= detectAndFoldOffset(
Hi, *
Lo);
445 MadeChange |= foldIntoMemoryOps(
Hi, *
Lo);
454 return new RISCVMergeBaseOffsetOpt();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
#define RISCV_MERGE_BASE_OFFSET_NAME
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setOffset(int64_t Offset)
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.