34#define DEBUG_TYPE "riscv-insert-vsetvli"
35#define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass"
39 cl::desc(
"Disable looking through phis when inserting vsetvlis."));
43 cl::desc(
"Enable strict assertion checking for the dataflow algorithm"));
56 return MI.getOpcode() == RISCV::PseudoVSETVLI ||
57 MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
58 MI.getOpcode() == RISCV::PseudoVSETIVLI;
64 if (
MI.getOpcode() != RISCV::PseudoVSETVLIX0)
66 assert(RISCV::X0 ==
MI.getOperand(1).getReg());
67 return RISCV::X0 ==
MI.getOperand(0).getReg();
72 RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
79 switch (getRVVMCOpcode(
MI.getOpcode())) {
89 switch (getRVVMCOpcode(
MI.getOpcode())) {
92 case RISCV::VSLIDEDOWN_VX:
93 case RISCV::VSLIDEDOWN_VI:
94 case RISCV::VSLIDEUP_VX:
95 case RISCV::VSLIDEUP_VI:
102static std::optional<unsigned> getEEWForLoadStore(
const MachineInstr &
MI) {
103 switch (getRVVMCOpcode(
MI.getOpcode())) {
112 case RISCV::VLSE16_V:
114 case RISCV::VSSE16_V:
117 case RISCV::VLSE32_V:
119 case RISCV::VSSE32_V:
122 case RISCV::VLSE64_V:
124 case RISCV::VSSE64_V:
134 const unsigned Log2SEW =
MI.getOperand(getSEWOpNum(
MI)).getImm();
140struct DemandedFields {
145 bool VLZeroness =
false;
148 bool SEWLMULRatio =
false;
149 bool TailPolicy =
false;
150 bool MaskPolicy =
false;
153 bool usedVTYPE()
const {
154 return SEW ||
LMUL || SEWLMULRatio || TailPolicy || MaskPolicy;
159 return VLAny || VLZeroness;
177#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
187 OS <<
"VLAny=" << VLAny <<
", ";
188 OS <<
"VLZeroness=" << VLZeroness <<
", ";
189 OS <<
"SEW=" <<
SEW <<
", ";
190 OS <<
"LMUL=" <<
LMUL <<
", ";
191 OS <<
"SEWLMULRatio=" << SEWLMULRatio <<
", ";
192 OS <<
"TailPolicy=" << TailPolicy <<
", ";
193 OS <<
"MaskPolicy=" << MaskPolicy;
199#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
211static bool areCompatibleVTYPEs(
uint64_t VType1,
213 const DemandedFields &Used) {
222 if (
Used.SEWLMULRatio) {
227 if (Ratio1 != Ratio2)
231 if (
Used.TailPolicy &&
234 if (
Used.MaskPolicy &&
250 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.readsRegister(RISCV::VL))
252 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.readsRegister(RISCV::VTYPE))
263 Res.MaskPolicy =
false;
272 if (getEEWForLoadStore(
MI)) {
279 Res.TailPolicy =
false;
280 Res.MaskPolicy =
false;
287 if (isMaskRegOp(
MI)) {
293 if (isScalarMoveInstr(
MI)) {
295 Res.SEWLMULRatio =
false;
322 uint8_t SEWLMULRatioOnly : 1;
327 SEWLMULRatioOnly(
false) {}
329 static VSETVLIInfo getUnknown() {
336 void setUnknown() { State =
Unknown; }
337 bool isUnknown()
const {
return State ==
Unknown; }
344 void setAVLImm(
unsigned Imm) {
349 bool hasAVLImm()
const {
return State == AVLIsImm; }
350 bool hasAVLReg()
const {
return State == AVLIsReg; }
355 unsigned getAVLImm()
const {
360 unsigned getSEW()
const {
return SEW; }
365 return getAVLImm() > 0;
367 if (getAVLReg() == RISCV::X0)
370 MI &&
MI->getOpcode() == RISCV::ADDI &&
371 MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() &&
372 MI->getOperand(1).getReg() == RISCV::X0 &&
373 MI->getOperand(2).getImm() != 0)
380 bool hasEquallyZeroAVL(
const VSETVLIInfo &
Other,
382 if (hasSameAVL(
Other))
384 return (hasNonZeroAVL(
MRI) &&
Other.hasNonZeroAVL(
MRI));
387 bool hasSameAVL(
const VSETVLIInfo &
Other)
const {
388 if (hasAVLReg() &&
Other.hasAVLReg())
389 return getAVLReg() ==
Other.getAVLReg();
391 if (hasAVLImm() &&
Other.hasAVLImm())
392 return getAVLImm() ==
Other.getAVLImm();
399 "Can't set VTYPE for uninitialized or unknown");
407 "Can't set VTYPE for uninitialized or unknown");
416 "Can't encode VTYPE for uninitialized or unknown");
420 bool hasSEWLMULRatioOnly()
const {
return SEWLMULRatioOnly; }
422 bool hasSameVTYPE(
const VSETVLIInfo &
Other)
const {
424 "Can't compare invalid VSETVLIInfos");
426 "Can't compare VTYPE in unknown state");
427 assert(!SEWLMULRatioOnly && !
Other.SEWLMULRatioOnly &&
428 "Can't compare when only LMUL/SEW ratio is valid.");
429 return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
436 "Can't use VTYPE for uninitialized or unknown");
444 bool hasSameVLMAX(
const VSETVLIInfo &
Other)
const {
446 "Can't compare invalid VSETVLIInfos");
448 "Can't compare VTYPE in unknown state");
452 bool hasCompatibleVTYPE(
const DemandedFields &Used,
453 const VSETVLIInfo &Require)
const {
454 return areCompatibleVTYPEs(
encodeVTYPE(), Require.encodeVTYPE(), Used);
460 bool isCompatible(
const DemandedFields &Used,
const VSETVLIInfo &Require,
463 "Can't compare invalid VSETVLIInfos");
464 assert(!Require.SEWLMULRatioOnly &&
465 "Expected a valid VTYPE for instruction!");
467 if (isUnknown() || Require.isUnknown())
471 if (SEWLMULRatioOnly)
476 if (Require.hasAVLReg() && Require.AVLReg == RISCV::NoRegister)
477 if (SEW == Require.SEW)
480 if (
Used.VLAny && !hasSameAVL(Require))
483 if (
Used.VLZeroness && !hasEquallyZeroAVL(Require,
MRI))
486 return areCompatibleVTYPEs(
encodeVTYPE(), Require.encodeVTYPE(), Used);
492 return !
Other.isValid();
493 if (!
Other.isValid())
498 return Other.isUnknown();
499 if (
Other.isUnknown())
502 if (!hasSameAVL(
Other))
506 if (SEWLMULRatioOnly !=
Other.SEWLMULRatioOnly)
510 if (SEWLMULRatioOnly)
511 return hasSameVLMAX(
Other);
514 return hasSameVTYPE(
Other);
518 return !(*
this ==
Other);
525 if (!
Other.isValid())
533 if (isUnknown() ||
Other.isUnknown())
534 return VSETVLIInfo::getUnknown();
542 if (hasSameAVL(
Other) && hasSameVLMAX(
Other)) {
543 VSETVLIInfo MergeInfo = *
this;
544 MergeInfo.SEWLMULRatioOnly =
true;
549 return VSETVLIInfo::getUnknown();
552#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
564 OS <<
"Uninitialized";
570 OS <<
"AVLImm=" << (
unsigned)AVLImm;
572 <<
"VLMul=" << (
unsigned)VLMul <<
", "
573 <<
"SEW=" << (
unsigned)
SEW <<
", "
574 <<
"TailAgnostic=" << (
bool)TailAgnostic <<
", "
576 <<
"SEWLMULRatioOnly=" << (
bool)SEWLMULRatioOnly <<
"}";
581#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
603 bool InQueue =
false;
612 std::vector<BlockData> BlockInfo;
613 std::queue<const MachineBasicBlock *> WorkList;
631 bool needVSETVLI(
const MachineInstr &
MI,
const VSETVLIInfo &Require,
632 const VSETVLIInfo &CurInfo)
const;
633 bool needVSETVLIPHI(
const VSETVLIInfo &Require,
636 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo);
639 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo);
653char RISCVInsertVSETVLI::ID = 0;
674 "Invalid Policy Value");
712 int64_t Imm = VLOp.
getImm();
725 if (std::optional<unsigned> EEW = getEEWForLoadStore(
MI)) {
726 assert(
SEW == EEW &&
"Initial SEW doesn't match expected EEW");
735 const VSETVLIInfo &Info,
736 const VSETVLIInfo &PrevInfo) {
745 if (
MI.getOpcode() == RISCV::PseudoVSETIVLI) {
746 NewInfo.setAVLImm(
MI.getOperand(1).getImm());
748 assert(
MI.getOpcode() == RISCV::PseudoVSETVLI ||
749 MI.getOpcode() == RISCV::PseudoVSETVLIX0);
751 assert((AVLReg != RISCV::X0 ||
MI.getOperand(0).getReg() != RISCV::X0) &&
752 "Can't handle X0, X0 vsetvli yet");
753 NewInfo.setAVLReg(AVLReg);
755 NewInfo.setVTYPE(
MI.getOperand(2).getImm());
762 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo) {
764 if (PrevInfo.isValid() && !PrevInfo.isUnknown()) {
767 if (
Info.hasSameAVL(PrevInfo) &&
Info.hasSameVLMAX(PrevInfo)) {
779 if (
Info.hasSameVLMAX(PrevInfo) &&
Info.hasAVLReg() &&
780 Info.getAVLReg().isVirtual()) {
782 if (isVectorConfigInstr(*
DefMI)) {
784 if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
797 if (
Info.hasAVLImm()) {
806 if (AVLReg == RISCV::NoRegister) {
809 if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
810 Info.hasSameVLMAX(PrevInfo)) {
827 MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
833 unsigned Opcode = RISCV::PseudoVSETVLI;
834 if (AVLReg == RISCV::X0) {
835 DestReg =
MRI->createVirtualRegister(&RISCV::GPRRegClass);
836 Opcode = RISCV::PseudoVSETVLIX0;
846 return Fractional || LMul == 1;
852 const VSETVLIInfo &Require,
853 const VSETVLIInfo &CurInfo)
const {
854 assert(Require == computeInfoForInstr(
MI,
MI.getDesc().TSFlags,
MRI));
856 if (!CurInfo.isValid() || CurInfo.isUnknown() || CurInfo.hasSEWLMULRatioOnly())
859 DemandedFields
Used = getDemanded(
MI);
861 if (isScalarMoveInstr(
MI)) {
868 auto *VRegDef =
MRI->getVRegDef(
MI.getOperand(1).getReg());
869 if (VRegDef && VRegDef->isImplicitDef() &&
870 CurInfo.getSEW() >= Require.getSEW()) {
872 Used.TailPolicy =
false;
884 if (isVSlideInstr(
MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
886 auto *VRegDef =
MRI->getVRegDef(
MI.getOperand(1).getReg());
887 if (VRegDef && VRegDef->isImplicitDef()) {
889 Used.VLZeroness =
true;
891 Used.TailPolicy =
false;
895 if (CurInfo.isCompatible(Used, Require, *
MRI))
902 if (Require.hasAVLReg() && Require.getAVLReg().isVirtual() &&
903 CurInfo.hasCompatibleVTYPE(Used, Require)) {
905 if (isVectorConfigInstr(*
DefMI)) {
907 if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
919void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
const MachineInstr &
MI) {
924 const VSETVLIInfo NewInfo = computeInfoForInstr(
MI,
TSFlags,
MRI);
925 if (
Info.isValid() && !needVSETVLI(
MI, NewInfo, Info))
928 const VSETVLIInfo PrevInfo =
Info;
942 if (isScalarMoveInstr(
MI) && PrevInfo.isValid() &&
943 PrevInfo.hasEquallyZeroAVL(Info, *
MRI) &&
944 Info.hasSameVLMAX(PrevInfo)) {
945 if (PrevInfo.hasAVLImm())
946 Info.setAVLImm(PrevInfo.getAVLImm());
948 Info.setAVLReg(PrevInfo.getAVLReg());
956 if (!
Info.hasAVLReg() || !
Info.getAVLReg().isVirtual())
963 if (DefInfo.hasSameVLMAX(Info) &&
964 (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {
965 if (DefInfo.hasAVLImm())
966 Info.setAVLImm(DefInfo.getAVLImm());
968 Info.setAVLReg(DefInfo.getAVLReg());
976void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
const MachineInstr &
MI) {
977 if (isVectorConfigInstr(
MI)) {
984 Info.setAVLReg(
MI.getOperand(1).getReg());
990 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL) ||
991 MI.modifiesRegister(RISCV::VTYPE))
992 Info = VSETVLIInfo::getUnknown();
996 bool HadVectorOp =
false;
1016 BBInfo.InQueue =
false;
1020 VSETVLIInfo InInfo = BBInfo.
Pred;
1023 InInfo.setUnknown();
1026 InInfo = InInfo.
intersect(BlockInfo[
P->getNumber()].Exit);
1030 if (!InInfo.isValid())
1034 if (InInfo == BBInfo.
Pred)
1037 BBInfo.
Pred = InInfo;
1039 <<
" changed to " << BBInfo.
Pred <<
"\n");
1045 computeVLVTYPEChanges(
MBB);
1046 VSETVLIInfo TmpStatus = BBInfo.
Change;
1050 if (BBInfo.
Exit == TmpStatus)
1053 BBInfo.
Exit = TmpStatus;
1055 <<
" changed to " << BBInfo.
Exit <<
"\n");
1060 if (!BlockInfo[S->getNumber()].InQueue) {
1061 BlockInfo[S->getNumber()].InQueue =
true;
1069bool RISCVInsertVSETVLI::needVSETVLIPHI(
const VSETVLIInfo &Require,
1074 if (!Require.hasAVLReg())
1077 Register AVLReg = Require.getAVLReg();
1083 if (!
PHI ||
PHI->getOpcode() != RISCV::PHI ||
PHI->getParent() != &
MBB)
1086 for (
unsigned PHIOp = 1, NumOps =
PHI->getNumOperands(); PHIOp != NumOps;
1093 if (PBBInfo.
Exit.isUnknown() || !PBBInfo.
Exit.hasSameVTYPE(Require))
1104 if (!DefInfo.hasSameAVL(PBBInfo.
Exit) ||
1105 !DefInfo.hasSameVTYPE(PBBInfo.
Exit))
1118 bool PrefixTransparent =
true;
1120 const VSETVLIInfo PrevInfo = CurInfo;
1121 transferBefore(CurInfo,
MI);
1124 if (isVectorConfigInstr(
MI)) {
1126 assert(
MI.getOperand(3).getReg() == RISCV::VL &&
1127 MI.getOperand(4).getReg() == RISCV::VTYPE &&
1128 "Unexpected operands where VL and VTYPE should be");
1129 MI.getOperand(3).setIsDead(
false);
1130 MI.getOperand(4).setIsDead(
false);
1131 PrefixTransparent =
false;
1136 if (PrevInfo != CurInfo) {
1144 if (!PrefixTransparent || needVSETVLIPHI(CurInfo,
MBB))
1145 insertVSETVLI(
MBB,
MI, CurInfo, PrevInfo);
1146 PrefixTransparent =
false;
1153 VLOp.
setReg(RISCV::NoRegister);
1163 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL) ||
1164 MI.modifiesRegister(RISCV::VTYPE))
1165 PrefixTransparent =
false;
1167 transferAfter(CurInfo,
MI);
1173 const VSETVLIInfo &ExitInfo = BlockInfo[
MBB.
getNumber()].Exit;
1174 if (CurInfo.isValid() && ExitInfo.isValid() && !ExitInfo.isUnknown() &&
1175 CurInfo != ExitInfo) {
1187 if (CurInfo !=
Info.Exit) {
1194 "InsertVSETVLI dataflow invariant violated");
1200 if (!
Info.hasAVLImm())
1204 return RISCV::X0 ==
Info.getAVLReg();
1206 unsigned AVL =
Info.getAVLImm();
1208 unsigned AVLInBits = AVL *
SEW;
1215 return ST.getRealMinVLen() / LMul >= AVLInBits;
1216 return ST.getRealMinVLen() * LMul >= AVLInBits;
1232 VSETVLIInfo AvailableInfo;
1234 const VSETVLIInfo &PredInfo = BlockInfo[
P->getNumber()].Exit;
1235 if (PredInfo.isUnknown()) {
1236 if (UnavailablePred)
1238 UnavailablePred =
P;
1239 }
else if (!AvailableInfo.isValid()) {
1240 AvailableInfo = PredInfo;
1241 }
else if (AvailableInfo != PredInfo) {
1248 if (!UnavailablePred || !AvailableInfo.isValid())
1268 VSETVLIInfo CurInfo = AvailableInfo;
1269 int TransitionsRemoved = 0;
1271 const VSETVLIInfo LastInfo = CurInfo;
1272 const VSETVLIInfo LastOldInfo = OldInfo;
1273 transferBefore(CurInfo,
MI);
1274 transferBefore(OldInfo,
MI);
1275 if (CurInfo == LastInfo)
1276 TransitionsRemoved++;
1277 if (LastOldInfo == OldInfo)
1278 TransitionsRemoved--;
1279 transferAfter(CurInfo,
MI);
1280 transferAfter(OldInfo,
MI);
1281 if (CurInfo == OldInfo)
1285 if (CurInfo != OldInfo || TransitionsRemoved <= 0)
1292 auto OldExit = BlockInfo[UnavailablePred->
getNumber()].Exit;
1294 << UnavailablePred->
getName() <<
" with state "
1295 << AvailableInfo <<
"\n");
1296 BlockInfo[UnavailablePred->
getNumber()].Exit = AvailableInfo;
1302 insertVSETVLI(*UnavailablePred, InsertPt,
1304 AvailableInfo, OldExit);
1309 A.VLZeroness |=
B.VLZeroness;
1312 A.SEWLMULRatio |=
B.SEWLMULRatio;
1313 A.TailPolicy |=
B.TailPolicy;
1314 A.MaskPolicy |=
B.MaskPolicy;
1319 return RISCV::X0 == MO.
getReg();
1328 const DemandedFields &Used) {
1332 if (!isVLPreservingConfig(
MI)) {
1337 if (isVLPreservingConfig(PrevMI))
1342 if (Used.VLZeroness &&
1349 if (
MI.getOperand(1).isReg() &&
1350 RISCV::X0 !=
MI.getOperand(1).getReg())
1357 MI.getOperand(1).isReg())
1365 auto VType =
MI.getOperand(2).getImm();
1366 return areCompatibleVTYPEs(PriorVType, VType, Used);
1373 DemandedFields
Used;
1379 if (!isVectorConfigInstr(
MI)) {
1384 Register VRegDef =
MI.getOperand(0).getReg();
1385 if (VRegDef != RISCV::X0 &&
1386 !(VRegDef.
isVirtual() &&
MRI->use_nodbg_empty(VRegDef)))
1390 if (!
Used.usedVL() && !
Used.usedVTYPE()) {
1395 if (!isVLPreservingConfig(*NextMI)) {
1411 for (
auto *
MI : ToDelete)
1412 MI->eraseFromParent();
1419 Register VLOutput =
MI.getOperand(1).getReg();
1420 if (!
MRI->use_nodbg_empty(VLOutput))
1424 MI.getOperand(1).setReg(RISCV::X0);
1432 if (!
ST.hasVInstructions())
1437 TII =
ST.getInstrInfo();
1440 assert(BlockInfo.empty() &&
"Expect empty block infos");
1443 bool HaveVectorOp =
false;
1447 HaveVectorOp |= computeVLVTYPEChanges(
MBB);
1452 <<
" is " << BBInfo.
Exit <<
"\n");
1457 if (!HaveVectorOp) {
1466 WorkList.push(&
MBB);
1469 while (!WorkList.empty()) {
1472 computeIncomingVLVTYPE(
MBB);
1493 doLocalPostpass(
MBB);
1502 if (
MI.getOpcode() == RISCV::PseudoVSETVLI ||
1503 MI.getOpcode() == RISCV::PseudoVSETIVLI) {
1504 Register VRegDef =
MI.getOperand(0).getReg();
1505 if (VRegDef != RISCV::X0 &&
MRI->use_nodbg_empty(VRegDef))
1506 MI.getOperand(0).setReg(RISCV::X0);
1517 return HaveVectorOp;
1522 return new RISCVInsertVSETVLI();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_ATTRIBUTE_USED
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::optional< std::vector< StOtherPiece > > Other
const HexagonInstrInfo * TII
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI)
static bool isNonZeroAVL(const MachineOperand &MO)
#define RISCV_INSERT_VSETVLI_NAME
uint64_t const MachineRegisterInfo * MRI
static bool canMutatePriorConfig(const MachineInstr &PrevMI, const MachineInstr &MI, const DemandedFields &Used)
assert(RISCVVType::isValidSEW(SEW) &&"Unexpected SEW")
InstrInfo setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic)
static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL)
static void doUnion(DemandedFields &A, DemandedFields B)
static cl::opt< bool > UseStrictAsserts("riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden, cl::desc("Enable strict assertion checking for the dataflow algorithm"))
static cl::opt< bool > DisableInsertVSETVLPHIOpt("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis."))
static bool hasFixedResult(const VSETVLIInfo &Info, const RISCVSubtarget &ST)
Return true if the VL value configured must be equal to the requested one.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned succ_size() const
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
reverse_iterator rbegin()
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isImplicitDef() const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
This class implements an extremely fast bulk output stream that can only output to a stream.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static bool usesMaskPolicy(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isMaskAgnostic(unsigned VType)
static bool isValidSEW(unsigned SEW)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
bool isFaultFirstLoad(const MachineInstr &MI)
static constexpr int64_t VLMaxSentinel
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator!=(uint64_t V1, const APInt &V2)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Status intersect(const Status &S) const