34#define DEBUG_TYPE "riscv-insert-vsetvli"
35#define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass"
39 cl::desc(
"Disable looking through phis when inserting vsetvlis."));
43 cl::desc(
"Enable strict assertion checking for the dataflow algorithm"));
56 return MI.getOpcode() == RISCV::PseudoVSETVLI ||
57 MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
58 MI.getOpcode() == RISCV::PseudoVSETIVLI;
64 if (
MI.getOpcode() != RISCV::PseudoVSETVLIX0)
66 assert(RISCV::X0 ==
MI.getOperand(1).getReg());
67 return RISCV::X0 ==
MI.getOperand(0).getReg();
70static bool isFloatScalarMoveOrScalarSplatInstr(
const MachineInstr &
MI) {
106 case RISCV::VFMV_V_F:
115 case RISCV::VSLIDEDOWN_VX:
116 case RISCV::VSLIDEDOWN_VI:
117 case RISCV::VSLIDEUP_VX:
118 case RISCV::VSLIDEUP_VI:
125static std::optional<unsigned> getEEWForLoadStore(
const MachineInstr &
MI) {
135 case RISCV::VLSE16_V:
137 case RISCV::VSSE16_V:
140 case RISCV::VLSE32_V:
142 case RISCV::VSSE32_V:
145 case RISCV::VLSE64_V:
147 case RISCV::VSSE64_V:
157 const unsigned Log2SEW =
MI.getOperand(getSEWOpNum(
MI)).getImm();
170 if (!
MI.isRegTiedToUseOperand(0, &UseOpIdx))
179 if (UseMO.
getReg() == RISCV::NoRegister)
199struct DemandedFields {
204 bool VLZeroness =
false;
208 SEWGreaterThanOrEqual = 2,
210 SEWGreaterThanOrEqualAndLessThan64 =
217 bool SEWLMULRatio =
false;
218 bool TailPolicy =
false;
219 bool MaskPolicy =
false;
222 bool usedVTYPE()
const {
223 return SEW ||
LMUL || SEWLMULRatio || TailPolicy || MaskPolicy;
228 return VLAny || VLZeroness;
246#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
256 OS <<
"VLAny=" << VLAny <<
", ";
257 OS <<
"VLZeroness=" << VLZeroness <<
", ";
263 case SEWGreaterThanOrEqual:
264 OS <<
"SEWGreaterThanOrEqual";
266 case SEWGreaterThanOrEqualAndLessThan64:
267 OS <<
"SEWGreaterThanOrEqualAndLessThan64";
274 OS <<
"LMUL=" <<
LMUL <<
", ";
275 OS <<
"SEWLMULRatio=" << SEWLMULRatio <<
", ";
276 OS <<
"TailPolicy=" << TailPolicy <<
", ";
277 OS <<
"MaskPolicy=" << MaskPolicy;
283#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
295 const DemandedFields &Used) {
297 case DemandedFields::SEWNone:
299 case DemandedFields::SEWEqual:
303 case DemandedFields::SEWGreaterThanOrEqual:
307 case DemandedFields::SEWGreaterThanOrEqualAndLessThan64:
318 if (
Used.SEWLMULRatio) {
323 if (Ratio1 != Ratio2)
348 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.readsRegister(RISCV::VL))
350 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.readsRegister(RISCV::VTYPE))
361 Res.MaskPolicy =
false;
370 if (getEEWForLoadStore(
MI)) {
371 Res.SEW = DemandedFields::SEWNone;
377 Res.TailPolicy =
false;
378 Res.MaskPolicy =
false;
385 if (isMaskRegOp(
MI)) {
386 Res.SEW = DemandedFields::SEWNone;
391 if (isScalarInsertInstr(
MI)) {
393 Res.SEWLMULRatio =
false;
401 if (hasUndefinedMergeOp(
MI, *
MRI)) {
402 if (isFloatScalarMoveOrScalarSplatInstr(
MI) && !
ST->hasVInstructionsF64())
403 Res.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64;
405 Res.SEW = DemandedFields::SEWGreaterThanOrEqual;
406 Res.TailPolicy =
false;
411 if (isScalarExtractInstr(
MI)) {
414 Res.SEWLMULRatio =
false;
415 Res.TailPolicy =
false;
416 Res.MaskPolicy =
false;
440 uint8_t TailAgnostic : 1;
441 uint8_t MaskAgnostic : 1;
442 uint8_t SEWLMULRatioOnly : 1;
446 : AVLImm(0), TailAgnostic(
false), MaskAgnostic(
false),
447 SEWLMULRatioOnly(
false) {}
449 static VSETVLIInfo getUnknown() {
456 void setUnknown() { State =
Unknown; }
457 bool isUnknown()
const {
return State ==
Unknown; }
464 void setAVLImm(
unsigned Imm) {
469 bool hasAVLImm()
const {
return State == AVLIsImm; }
470 bool hasAVLReg()
const {
return State == AVLIsReg; }
475 unsigned getAVLImm()
const {
480 void setAVL(VSETVLIInfo Info) {
482 if (
Info.isUnknown())
484 else if (
Info.hasAVLReg())
485 setAVLReg(
Info.getAVLReg());
488 setAVLImm(
Info.getAVLImm());
492 unsigned getSEW()
const {
return SEW; }
494 bool getTailAgnostic()
const {
return TailAgnostic; }
495 bool getMaskAgnostic()
const {
return MaskAgnostic; }
499 return getAVLImm() > 0;
501 if (getAVLReg() == RISCV::X0)
504 MI &&
MI->getOpcode() == RISCV::ADDI &&
505 MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() &&
506 MI->getOperand(1).getReg() == RISCV::X0 &&
507 MI->getOperand(2).getImm() != 0)
514 bool hasEquallyZeroAVL(
const VSETVLIInfo &
Other,
516 if (hasSameAVL(
Other))
518 return (hasNonZeroAVL(
MRI) &&
Other.hasNonZeroAVL(
MRI));
521 bool hasSameAVL(
const VSETVLIInfo &
Other)
const {
522 if (hasAVLReg() &&
Other.hasAVLReg())
523 return getAVLReg() ==
Other.getAVLReg();
525 if (hasAVLImm() &&
Other.hasAVLImm())
526 return getAVLImm() ==
Other.getAVLImm();
531 void setVTYPE(
unsigned VType) {
533 "Can't set VTYPE for uninitialized or unknown");
541 "Can't set VTYPE for uninitialized or unknown");
552 "Can't encode VTYPE for uninitialized or unknown");
556 bool hasSEWLMULRatioOnly()
const {
return SEWLMULRatioOnly; }
558 bool hasSameVTYPE(
const VSETVLIInfo &
Other)
const {
560 "Can't compare invalid VSETVLIInfos");
562 "Can't compare VTYPE in unknown state");
563 assert(!SEWLMULRatioOnly && !
Other.SEWLMULRatioOnly &&
564 "Can't compare when only LMUL/SEW ratio is valid.");
565 return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
572 "Can't use VTYPE for uninitialized or unknown");
580 bool hasSameVLMAX(
const VSETVLIInfo &
Other)
const {
582 "Can't compare invalid VSETVLIInfos");
584 "Can't compare VTYPE in unknown state");
588 bool hasCompatibleVTYPE(
const DemandedFields &Used,
589 const VSETVLIInfo &Require)
const {
590 return areCompatibleVTYPEs(Require.encodeVTYPE(),
encodeVTYPE(), Used);
596 bool isCompatible(
const DemandedFields &Used,
const VSETVLIInfo &Require,
599 "Can't compare invalid VSETVLIInfos");
600 assert(!Require.SEWLMULRatioOnly &&
601 "Expected a valid VTYPE for instruction!");
603 if (isUnknown() || Require.isUnknown())
607 if (SEWLMULRatioOnly)
610 if (
Used.VLAny && !hasSameAVL(Require))
613 if (
Used.VLZeroness && !hasEquallyZeroAVL(Require,
MRI))
616 return hasCompatibleVTYPE(Used, Require);
622 return !
Other.isValid();
623 if (!
Other.isValid())
628 return Other.isUnknown();
629 if (
Other.isUnknown())
632 if (!hasSameAVL(
Other))
636 if (SEWLMULRatioOnly !=
Other.SEWLMULRatioOnly)
640 if (SEWLMULRatioOnly)
641 return hasSameVLMAX(
Other);
644 return hasSameVTYPE(
Other);
648 return !(*
this ==
Other);
655 if (!
Other.isValid())
663 if (isUnknown() ||
Other.isUnknown())
664 return VSETVLIInfo::getUnknown();
672 if (hasSameAVL(
Other) && hasSameVLMAX(
Other)) {
673 VSETVLIInfo MergeInfo = *
this;
674 MergeInfo.SEWLMULRatioOnly =
true;
679 return VSETVLIInfo::getUnknown();
682#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
694 OS <<
"Uninitialized";
700 OS <<
"AVLImm=" << (
unsigned)AVLImm;
702 <<
"VLMul=" << (
unsigned)VLMul <<
", "
703 <<
"SEW=" << (
unsigned)SEW <<
", "
704 <<
"TailAgnostic=" << (
bool)TailAgnostic <<
", "
705 <<
"MaskAgnostic=" << (
bool)MaskAgnostic <<
", "
706 <<
"SEWLMULRatioOnly=" << (
bool)SEWLMULRatioOnly <<
"}";
711#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
729 bool InQueue =
false;
739 std::vector<BlockData> BlockInfo;
740 std::queue<const MachineBasicBlock *> WorkList;
756 bool needVSETVLI(
const MachineInstr &
MI,
const VSETVLIInfo &Require,
757 const VSETVLIInfo &CurInfo)
const;
758 bool needVSETVLIPHI(
const VSETVLIInfo &Require,
761 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo);
764 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo);
766 void transferBefore(VSETVLIInfo &Info,
const MachineInstr &
MI)
const;
767 void transferAfter(VSETVLIInfo &Info,
const MachineInstr &
MI)
const;
769 VSETVLIInfo &Info)
const;
779char RISCVInsertVSETVLI::ID = 0;
788 if (
MI.getOpcode() == RISCV::PseudoVSETIVLI) {
789 NewInfo.setAVLImm(
MI.getOperand(1).getImm());
791 assert(
MI.getOpcode() == RISCV::PseudoVSETVLI ||
792 MI.getOpcode() == RISCV::PseudoVSETVLIX0);
794 assert((AVLReg != RISCV::X0 ||
MI.getOperand(0).getReg() != RISCV::X0) &&
795 "Can't handle X0, X0 vsetvli yet");
796 NewInfo.setAVLReg(AVLReg);
798 NewInfo.setVTYPE(
MI.getOperand(2).getImm());
805 VSETVLIInfo InstrInfo;
807 bool TailAgnostic =
true;
808 bool MaskAgnostic =
true;
809 if (!hasUndefinedMergeOp(
MI, *
MRI)) {
811 TailAgnostic =
false;
812 MaskAgnostic =
false;
819 "Invalid Policy Value");
835 unsigned Log2SEW =
MI.getOperand(getSEWOpNum(
MI)).getImm();
837 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
843 int64_t Imm = VLOp.
getImm();
846 InstrInfo.setAVLReg(RISCV::X0);
848 InstrInfo.setAVLImm(Imm);
850 InstrInfo.setAVLReg(VLOp.
getReg());
854 InstrInfo.setAVLReg(RISCV::NoRegister);
857 if (std::optional<unsigned> EEW = getEEWForLoadStore(
MI)) {
858 assert(SEW == EEW &&
"Initial SEW doesn't match expected EEW");
861 InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
867 if (InstrInfo.hasAVLReg() && InstrInfo.getAVLReg().isVirtual()) {
870 VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*
DefMI);
871 if (DefInstrInfo.hasSameVLMAX(InstrInfo) &&
872 (DefInstrInfo.hasAVLImm() || DefInstrInfo.getAVLReg() == RISCV::X0)) {
873 InstrInfo.setAVL(DefInstrInfo);
882 const VSETVLIInfo &Info,
883 const VSETVLIInfo &PrevInfo) {
890 const VSETVLIInfo &Info,
const VSETVLIInfo &PrevInfo) {
892 if (PrevInfo.isValid() && !PrevInfo.isUnknown()) {
895 if (
Info.hasSameAVL(PrevInfo) &&
Info.hasSameVLMAX(PrevInfo)) {
907 if (
Info.hasSameVLMAX(PrevInfo) &&
Info.hasAVLReg() &&
908 Info.getAVLReg().isVirtual()) {
910 if (isVectorConfigInstr(*
DefMI)) {
911 VSETVLIInfo DefInfo = getInfoForVSETVLI(*
DefMI);
912 if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
925 if (
Info.hasAVLImm()) {
934 if (AVLReg == RISCV::NoRegister) {
937 if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
938 Info.hasSameVLMAX(PrevInfo)) {
955 MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
961 unsigned Opcode = RISCV::PseudoVSETVLI;
962 if (AVLReg == RISCV::X0) {
963 DestReg =
MRI->createVirtualRegister(&RISCV::GPRRegClass);
964 Opcode = RISCV::PseudoVSETVLIX0;
974 return Fractional || LMul == 1;
980 const VSETVLIInfo &Require,
981 const VSETVLIInfo &CurInfo)
const {
984 if (!CurInfo.isValid() || CurInfo.isUnknown() || CurInfo.hasSEWLMULRatioOnly())
987 DemandedFields
Used = getDemanded(
MI,
MRI, ST);
997 if (isVSlideInstr(
MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
1000 Used.VLZeroness =
true;
1002 Used.TailPolicy =
false;
1010 if (isScalarSplatInstr(
MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
1013 Used.SEWLMULRatio =
false;
1015 if (isFloatScalarMoveOrScalarSplatInstr(
MI) && !
ST->hasVInstructionsF64())
1016 Used.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64;
1018 Used.SEW = DemandedFields::SEWGreaterThanOrEqual;
1019 Used.TailPolicy =
false;
1022 if (CurInfo.isCompatible(Used, Require, *
MRI))
1029 if (Require.hasAVLReg() && Require.getAVLReg().isVirtual() &&
1030 CurInfo.hasCompatibleVTYPE(Used, Require)) {
1032 if (isVectorConfigInstr(*
DefMI)) {
1033 VSETVLIInfo DefInfo = getInfoForVSETVLI(*
DefMI);
1034 if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
1043static VSETVLIInfo
adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
1044 DemandedFields &Demanded,
1050void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
1057 assert(NewInfo.isValid() && !NewInfo.isUnknown());
1058 if (
Info.isValid() && !needVSETVLI(
MI, NewInfo, Info))
1061 const VSETVLIInfo PrevInfo =
Info;
1062 if (
Info.hasSEWLMULRatioOnly() || !
Info.isValid() ||
Info.isUnknown())
1070 DemandedFields Demanded = getDemanded(
MI,
MRI, ST);
1071 const VSETVLIInfo IncomingInfo =
1074 if (Demanded.usedVL())
1075 Info.setAVL(IncomingInfo);
1078 ((Demanded.LMUL || Demanded.SEWLMULRatio) ? IncomingInfo : Info)
1080 ((Demanded.SEW || Demanded.SEWLMULRatio) ? IncomingInfo : Info).getSEW(),
1083 (Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic() ||
1084 IncomingInfo.getTailAgnostic(),
1085 (Demanded.MaskPolicy ? IncomingInfo : Info).getMaskAgnostic() ||
1086 IncomingInfo.getMaskAgnostic());
1090 DemandedFields &Demanded,
1092 VSETVLIInfo
Info = NewInfo;
1097 if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() &&
1098 !PrevInfo.isUnknown()) {
1100 PrevInfo.getSEW(), PrevInfo.getVLMUL(),
Info.getSEW()))
1101 Info.setVLMul(*NewVLMul);
1102 Demanded.LMUL =
true;
1113 if (Demanded.VLZeroness && !Demanded.VLAny && PrevInfo.isValid() &&
1114 PrevInfo.hasEquallyZeroAVL(
Info, *
MRI) &&
Info.hasSameVLMAX(PrevInfo)) {
1115 Info.setAVL(PrevInfo);
1116 Demanded.demandVL();
1125void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
1127 if (isVectorConfigInstr(
MI)) {
1128 Info = getInfoForVSETVLI(
MI);
1134 Info.setAVLReg(
MI.getOperand(1).getReg());
1140 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL) ||
1141 MI.modifiesRegister(RISCV::VTYPE))
1142 Info = VSETVLIInfo::getUnknown();
1146 VSETVLIInfo &Info)
const {
1147 bool HadVectorOp =
false;
1151 transferBefore(Info,
MI);
1156 transferAfter(Info,
MI);
1166 BBInfo.InQueue =
false;
1170 VSETVLIInfo InInfo = BBInfo.
Pred;
1173 InInfo.setUnknown();
1176 InInfo = InInfo.
intersect(BlockInfo[
P->getNumber()].Exit);
1180 if (!InInfo.isValid())
1184 if (InInfo == BBInfo.
Pred)
1187 BBInfo.
Pred = InInfo;
1189 <<
" changed to " << BBInfo.
Pred <<
"\n");
1195 VSETVLIInfo TmpStatus;
1196 computeVLVTYPEChanges(
MBB, TmpStatus);
1200 if (BBInfo.
Exit == TmpStatus)
1203 BBInfo.
Exit = TmpStatus;
1205 <<
" changed to " << BBInfo.
Exit <<
"\n");
1210 if (!BlockInfo[S->getNumber()].InQueue) {
1211 BlockInfo[S->getNumber()].InQueue =
true;
1219bool RISCVInsertVSETVLI::needVSETVLIPHI(
const VSETVLIInfo &Require,
1224 if (!Require.hasAVLReg())
1227 Register AVLReg = Require.getAVLReg();
1233 if (!
PHI ||
PHI->getOpcode() != RISCV::PHI ||
PHI->getParent() != &
MBB)
1236 for (
unsigned PHIOp = 1, NumOps =
PHI->getNumOperands(); PHIOp != NumOps;
1243 if (PBBInfo.
Exit.isUnknown() || !PBBInfo.
Exit.hasSameVTYPE(Require))
1253 VSETVLIInfo DefInfo = getInfoForVSETVLI(*
DefMI);
1254 if (!DefInfo.hasSameAVL(PBBInfo.
Exit) ||
1255 !DefInfo.hasSameVTYPE(PBBInfo.
Exit))
1268 bool PrefixTransparent =
true;
1270 const VSETVLIInfo PrevInfo = CurInfo;
1271 transferBefore(CurInfo,
MI);
1274 if (isVectorConfigInstr(
MI)) {
1276 assert(
MI.getOperand(3).getReg() == RISCV::VL &&
1277 MI.getOperand(4).getReg() == RISCV::VTYPE &&
1278 "Unexpected operands where VL and VTYPE should be");
1279 MI.getOperand(3).setIsDead(
false);
1280 MI.getOperand(4).setIsDead(
false);
1281 PrefixTransparent =
false;
1286 if (PrevInfo != CurInfo) {
1294 if (!PrefixTransparent || needVSETVLIPHI(CurInfo,
MBB))
1295 insertVSETVLI(
MBB,
MI, CurInfo, PrevInfo);
1296 PrefixTransparent =
false;
1303 VLOp.
setReg(RISCV::NoRegister);
1313 if (
MI.isCall() ||
MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL) ||
1314 MI.modifiesRegister(RISCV::VTYPE))
1315 PrefixTransparent =
false;
1317 transferAfter(CurInfo,
MI);
1323 const VSETVLIInfo &ExitInfo = BlockInfo[
MBB.
getNumber()].Exit;
1324 if (CurInfo.isValid() && ExitInfo.isValid() && !ExitInfo.isUnknown() &&
1325 CurInfo != ExitInfo) {
1337 if (CurInfo !=
Info.Exit) {
1344 "InsertVSETVLI dataflow invariant violated");
1358 VSETVLIInfo AvailableInfo;
1360 const VSETVLIInfo &PredInfo = BlockInfo[
P->getNumber()].Exit;
1361 if (PredInfo.isUnknown()) {
1362 if (UnavailablePred)
1364 UnavailablePred =
P;
1365 }
else if (!AvailableInfo.isValid()) {
1366 AvailableInfo = PredInfo;
1367 }
else if (AvailableInfo != PredInfo) {
1374 if (!UnavailablePred || !AvailableInfo.isValid())
1384 if (AvailableInfo.hasAVLReg() && RISCV::X0 != AvailableInfo.getAVLReg()) {
1390 if (AVLDefMI->
getParent() != UnavailablePred)
1392 for (
auto &TermMI : UnavailablePred->
terminators())
1393 if (&TermMI == AVLDefMI)
1406 VSETVLIInfo CurInfo = AvailableInfo;
1407 int TransitionsRemoved = 0;
1409 const VSETVLIInfo LastInfo = CurInfo;
1410 const VSETVLIInfo LastOldInfo = OldInfo;
1411 transferBefore(CurInfo,
MI);
1412 transferBefore(OldInfo,
MI);
1413 if (CurInfo == LastInfo)
1414 TransitionsRemoved++;
1415 if (LastOldInfo == OldInfo)
1416 TransitionsRemoved--;
1417 transferAfter(CurInfo,
MI);
1418 transferAfter(OldInfo,
MI);
1419 if (CurInfo == OldInfo)
1423 if (CurInfo != OldInfo || TransitionsRemoved <= 0)
1430 auto OldExit = BlockInfo[UnavailablePred->
getNumber()].Exit;
1432 << UnavailablePred->
getName() <<
" with state "
1433 << AvailableInfo <<
"\n");
1434 BlockInfo[UnavailablePred->
getNumber()].Exit = AvailableInfo;
1440 insertVSETVLI(*UnavailablePred, InsertPt,
1442 AvailableInfo, OldExit);
1447 A.VLZeroness |=
B.VLZeroness;
1448 A.SEW = std::max(
A.SEW,
B.SEW);
1450 A.SEWLMULRatio |=
B.SEWLMULRatio;
1451 A.TailPolicy |=
B.TailPolicy;
1452 A.MaskPolicy |=
B.MaskPolicy;
1457 return RISCV::X0 == MO.
getReg();
1466 const DemandedFields &Used) {
1470 if (!isVLPreservingConfig(
MI)) {
1476 if (Used.VLZeroness) {
1477 if (isVLPreservingConfig(PrevMI))
1486 if (
MI.getOperand(1).isReg() &&
1487 RISCV::X0 !=
MI.getOperand(1).getReg())
1495 auto VType =
MI.getOperand(2).getImm();
1496 return areCompatibleVTYPEs(PriorVType, VType, Used);
1503 DemandedFields
Used;
1509 if (!isVectorConfigInstr(
MI)) {
1514 Register VRegDef =
MI.getOperand(0).getReg();
1515 if (VRegDef != RISCV::X0 &&
1516 !(VRegDef.
isVirtual() &&
MRI->use_nodbg_empty(VRegDef)))
1520 if (!
Used.usedVL() && !
Used.usedVTYPE()) {
1525 if (!isVLPreservingConfig(*NextMI)) {
1527 MI.getOperand(0).setIsDead(
false);
1543 for (
auto *
MI : ToDelete)
1544 MI->eraseFromParent();
1551 Register VLOutput =
MI.getOperand(1).getReg();
1552 if (!
MRI->use_nodbg_empty(VLOutput))
1556 MI.getOperand(1).setReg(RISCV::X0);
1564 if (!
ST->hasVInstructions())
1569 TII =
ST->getInstrInfo();
1572 assert(BlockInfo.empty() &&
"Expect empty block infos");
1575 bool HaveVectorOp =
false;
1579 VSETVLIInfo TmpStatus;
1580 HaveVectorOp |= computeVLVTYPEChanges(
MBB, TmpStatus);
1583 BBInfo.
Exit = TmpStatus;
1585 <<
" is " << BBInfo.
Exit <<
"\n");
1590 if (!HaveVectorOp) {
1599 WorkList.push(&
MBB);
1602 while (!WorkList.empty()) {
1605 computeIncomingVLVTYPE(
MBB);
1626 doLocalPostpass(
MBB);
1634 return HaveVectorOp;
1639 return new RISCVInsertVSETVLI();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_ATTRIBUTE_USED
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::optional< std::vector< StOtherPiece > > Other
const HexagonInstrInfo * TII
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, const MachineRegisterInfo *MRI)
static bool isNonZeroAVL(const MachineOperand &MO)
#define RISCV_INSERT_VSETVLI_NAME
static bool canMutatePriorConfig(const MachineInstr &PrevMI, const MachineInstr &MI, const DemandedFields &Used)
static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL)
static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo, DemandedFields &Demanded, const MachineRegisterInfo *MRI)
static void doUnion(DemandedFields &A, DemandedFields B)
static cl::opt< bool > UseStrictAsserts("riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden, cl::desc("Enable strict assertion checking for the dataflow algorithm"))
static cl::opt< bool > DisableInsertVSETVLPHIOpt("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis."))
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static constexpr uint32_t Opcode
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned succ_size() const
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
iterator_range< iterator > terminators()
iterator_range< succ_iterator > successors()
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
reverse_iterator rbegin()
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isImplicitDef() const
const MachineBasicBlock * getParent() const
unsigned getNumOperands() const
Retuns the total number of operands.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isRegSequence() const
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
This class implements an extremely fast bulk output stream that can only output to a stream.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static bool usesMaskPolicy(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isMaskAgnostic(unsigned VType)
static bool isValidSEW(unsigned SEW)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
std::optional< RISCVII::VLMUL > getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW)
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)
bool isFaultFirstLoad(const MachineInstr &MI)
static constexpr int64_t VLMaxSentinel
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator!=(uint64_t V1, const APInt &V2)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Status intersect(const Status &S) const