LLVM 17.0.0git
Macros | Functions | Variables
RISCVInsertVSETVLI.cpp File Reference
#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include <queue>
Include dependency graph for RISCVInsertVSETVLI.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "riscv-insert-vsetvli"
 
#define RISCV_INSERT_VSETVLI_NAME   "RISC-V Insert VSETVLI pass"
 

Functions

 INITIALIZE_PASS (RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, false, false) static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI
 
 if (MI.isRegTiedToUseOperand(0, &UseOpIdx))
 
 assert (RISCVVType::isValidSEW(SEW) &&"Unexpected SEW")
 
 if (RISCVII::hasVLOp(TSFlags))
 
 if (std::optional< unsigned > EEW=getEEWForLoadStore(MI))
 
InstrInfo setVTYPE (VLMul, SEW, TailAgnostic, MaskAgnostic)
 
static VSETVLIInfo getInfoForVSETVLI (const MachineInstr &MI)
 
static bool hasFixedResult (const VSETVLIInfo &Info, const RISCVSubtarget &ST)
 Return true if the VL value configured must be equal to the requested one.
 
static void doUnion (DemandedFields &A, DemandedFields B)
 
static bool isNonZeroAVL (const MachineOperand &MO)
 
static bool canMutatePriorConfig (const MachineInstr &PrevMI, const MachineInstr &MI, const DemandedFields &Used)
 

Variables

static cl::opt< bool > DisableInsertVSETVLPHIOpt ("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis."))
 
static cl::opt< bool > UseStrictAsserts ("riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden, cl::desc("Enable strict assertion checking for the dataflow algorithm"))
 
uint64_t TSFlags
 
uint64_t const MachineRegisterInfo * MRI
 
bool TailAgnostic = true
 
bool MaskAgnostic = true
 
unsigned UseOpIdx
 
 else
 
RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags)
 
unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm()
 
unsigned SEW = Log2SEW ? 1 << Log2SEW : 8
 
return InstrInfo
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-insert-vsetvli"

Definition at line 34 of file RISCVInsertVSETVLI.cpp.

◆ RISCV_INSERT_VSETVLI_NAME

#define RISCV_INSERT_VSETVLI_NAME   "RISC-V Insert VSETVLI pass"

Definition at line 35 of file RISCVInsertVSETVLI.cpp.

Function Documentation

◆ assert()

assert ( RISCVVType::isValidSEW(SEW) &&"Unexpected SEW"  )

Referenced by getInfoForVSETVLI(), if(), and isNonZeroAVL().

◆ canMutatePriorConfig()

static bool canMutatePriorConfig ( const MachineInstr &  PrevMI,
const MachineInstr &  MI,
const DemandedFields &  Used 
)
static

Definition at line 1258 of file RISCVInsertVSETVLI.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), isNonZeroAVL(), and MI.

◆ doUnion()

static void doUnion ( DemandedFields &  A,
DemandedFields  B 
)
static

Definition at line 1239 of file RISCVInsertVSETVLI.cpp.

References A, and B.

◆ getInfoForVSETVLI()

static VSETVLIInfo getInfoForVSETVLI ( const MachineInstr &  MI)
static

Definition at line 783 of file RISCVInsertVSETVLI.cpp.

References assert(), and MI.

◆ hasFixedResult()

static bool hasFixedResult ( const VSETVLIInfo &  Info,
const RISCVSubtarget &  ST 
)
static

Return true if the VL value configured must be equal to the requested one.

Definition at line 1131 of file RISCVInsertVSETVLI.cpp.

References llvm::RISCVVType::decodeVLMUL(), Info, and SEW.

◆ if() [1/3]

if ( MI.  isRegTiedToUseOperand0, &UseOpIdx)

Definition at line 641 of file RISCVInsertVSETVLI.cpp.

References assert(), llvm::RISCVII::doesForceTailAgnostic(), llvm::MachineOperand::getReg(), llvm::RISCVII::hasVecPolicyOp(), llvm::MachineInstr::isImplicitDef(), llvm::RISCVII::MASK_AGNOSTIC, MaskAgnostic, MI, MRI, llvm::RISCVII::TAIL_AGNOSTIC, TailAgnostic, TSFlags, UseMI, UseOpIdx, and llvm::RISCVII::usesMaskPolicy().

◆ if() [2/3]

if ( RISCVII::hasVLOp(TSFlags)  )

Definition at line 686 of file RISCVInsertVSETVLI.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), InstrInfo, llvm::MachineOperand::isImm(), MI, and llvm::RISCV::VLMaxSentinel.

◆ if() [3/3]

if ( std::optional< unsigned >  EEW = getEEWForLoadStore(MI))

Definition at line 702 of file RISCVInsertVSETVLI.cpp.

References assert(), and SEW.

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( RISCVInsertVSETVLI  ,
DEBUG_TYPE  ,
RISCV_INSERT_VSETVLI_NAME  ,
false  ,
false   
) const &

◆ isNonZeroAVL()

static bool isNonZeroAVL ( const MachineOperand &  MO)
static

Definition at line 1249 of file RISCVInsertVSETVLI.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().

Referenced by canMutatePriorConfig().

◆ setVTYPE()

InstrInfo setVTYPE ( VLMul  ,
SEW  ,
TailAgnostic  ,
MaskAgnostic   
)

Variable Documentation

◆ DisableInsertVSETVLPHIOpt

cl::opt< bool > DisableInsertVSETVLPHIOpt("riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, cl::desc("Disable looking through phis when inserting vsetvlis.")) ( "riscv-disable-insert-vsetvl-phi-opt"  ,
cl::init(false)  ,
cl::Hidden  ,
cl::desc("Disable looking through phis when inserting vsetvlis.")   
)
static

◆ else

else
Initial value:
{
assert(!RISCVII::hasVecPolicyOp(TSFlags) && "Unexpected policy operand")
assert
assert(RISCVVType::isValidSEW(SEW) &&"Unexpected SEW")
TSFlags
uint64_t TSFlags
Definition: RISCVInsertVSETVLI.cpp:635
llvm::RISCVII::hasVecPolicyOp
static bool hasVecPolicyOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:174

Definition at line 671 of file RISCVInsertVSETVLI.cpp.

◆ InstrInfo

return InstrInfo

Definition at line 708 of file RISCVInsertVSETVLI.cpp.

Referenced by llvm::AArch64Subtarget::AArch64Subtarget(), llvm::ARCSubtarget::ARCSubtarget(), llvm::ARMSubtarget::ARMSubtarget(), llvm::createLanaiMCCodeEmitter(), llvm::CSKYSubtarget::CSKYSubtarget(), llvm::GCNSubtarget::GCNSubtarget(), llvm::PPCMCCodeEmitter::getDirectBrEncoding(), llvm::GCNSubtarget::getInstrInfo(), llvm::R600Subtarget::getInstrInfo(), llvm::ARCSubtarget::getInstrInfo(), llvm::BPFSubtarget::getInstrInfo(), llvm::CSKYSubtarget::getInstrInfo(), llvm::DirectXSubtarget::getInstrInfo(), llvm::HexagonSubtarget::getInstrInfo(), llvm::LoongArchSubtarget::getInstrInfo(), llvm::MipsSubtarget::getInstrInfo(), llvm::MSP430Subtarget::getInstrInfo(), llvm::NVPTXSubtarget::getInstrInfo(), llvm::RISCVSubtarget::getInstrInfo(), llvm::SparcSubtarget::getInstrInfo(), llvm::SPIRVSubtarget::getInstrInfo(), llvm::SystemZSubtarget::getInstrInfo(), llvm::VESubtarget::getInstrInfo(), llvm::WebAssemblySubtarget::getInstrInfo(), llvm::X86Subtarget::getInstrInfo(), llvm::XCoreSubtarget::getInstrInfo(), llvm::GCNSubtarget::getRegisterInfo(), llvm::R600Subtarget::getRegisterInfo(), llvm::ARCSubtarget::getRegisterInfo(), llvm::BPFSubtarget::getRegisterInfo(), llvm::MipsSubtarget::getRegisterInfo(), llvm::MSP430Subtarget::getRegisterInfo(), llvm::NVPTXSubtarget::getRegisterInfo(), llvm::SparcSubtarget::getRegisterInfo(), llvm::SPIRVSubtarget::getRegisterInfo(), llvm::SystemZSubtarget::getRegisterInfo(), llvm::VESubtarget::getRegisterInfo(), llvm::XCoreSubtarget::getRegisterInfo(), llvm::AMDGPU::getVOPDInstInfo(), llvm::HexagonSubtarget::HexagonSubtarget(), if(), llvm::GenericUniformityAnalysisImpl< ContextT >::initialize(), llvm::PPCMCCodeEmitter::isPrefixedInstruction(), llvm::LoongArchSubtarget::LoongArchSubtarget(), llvm::M68kSubtarget::M68kSubtarget(), llvm::MipsSubtarget::MipsSubtarget(), llvm::MSP430Subtarget::MSP430Subtarget(), llvm::PerTargetMIParsingState::parseInstrName(), llvm::PPCSubtarget::PPCSubtarget(), llvm::R600Subtarget::R600Subtarget(), llvm::PPCRegisterInfo::requiresFrameIndexScavenging(), llvm::RISCVSubtarget::RISCVSubtarget(), llvm::SparcSubtarget::SparcSubtarget(), llvm::SPIRVSubtarget::SPIRVSubtarget(), llvm::SystemZSubtarget::SystemZSubtarget(), llvm::VESubtarget::VESubtarget(), llvm::WebAssemblySubtarget::WebAssemblySubtarget(), and llvm::X86Subtarget::X86Subtarget().

◆ Log2SEW

unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm()

Definition at line 681 of file RISCVInsertVSETVLI.cpp.

Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), llvm::RISCVInstrInfo::createMIROperandComment(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), and llvm::RISCVInstrInfo::verifyInstruction().

◆ MaskAgnostic

MaskAgnostic = true

Definition at line 639 of file RISCVInsertVSETVLI.cpp.

Referenced by llvm::RISCVVType::encodeVTYPE(), and if().

◆ MRI

uint64_t const MachineRegisterInfo* MRI
Initial value:
{
VSETVLIInfo InstrInfo
InstrInfo
return InstrInfo
Definition: RISCVInsertVSETVLI.cpp:708

Definition at line 636 of file RISCVInsertVSETVLI.cpp.

Referenced by if().

◆ SEW

unsigned SEW = Log2SEW ? 1 << Log2SEW : 8

Definition at line 683 of file RISCVInsertVSETVLI.cpp.

Referenced by llvm::RISCVInstrInfo::createMIROperandComment(), llvm::RISCVVType::encodeSEW(), llvm::RISCVVType::encodeVTYPE(), llvm::RISCVVType::getSEWLMULRatio(), hasFixedResult(), if(), llvm::RISCVVType::isValidSEW(), lowerVectorIntrinsicScalars(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), and llvm::RISCVInstrInfo::verifyInstruction().

◆ TailAgnostic

TailAgnostic = true

Definition at line 639 of file RISCVInsertVSETVLI.cpp.

Referenced by llvm::RISCVVType::encodeVTYPE(), and if().

◆ TSFlags

uint64_t TSFlags

Definition at line 635 of file RISCVInsertVSETVLI.cpp.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::RISCVInstrInfo::createMIROperandComment(), decodeOperand_AVLdSt_Any(), llvm::RISCVII::doesForceTailAgnostic(), getBaseOffset(), llvm::X86II::getBaseOpcodeFor(), llvm::RISCVII::getConstraint(), llvm::getFMA3Group(), llvm::RISCVII::getFormat(), getImmFixupKind(), llvm::RISCVII::getLMul(), llvm::X86II::getMemoryOperandNo(), llvm::RISCVII::getSEWOpNum(), llvm::X86II::getSizeOfImm(), getThreeSrcCommuteCase(), llvm::RISCVII::getVLOpNum(), llvm::RISCVII::hasDummyMaskOp(), llvm::X86II::hasImm(), llvm::RISCVII::hasMergeOp(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::hasVLOp(), if(), isConvertibleToVMV_V_V(), isDispOrCDisp8(), llvm::R600InstrInfo::isExport(), llvm::X86II::isImmPCRel(), llvm::X86II::isImmSigned(), llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), llvm::X86II::isPrefix(), llvm::X86II::isPseudo(), isRIPRelative(), llvm::RISCVII::isRVVWideningReduction(), isSignExtendingOpW(), lowerRISCVVMachineInstrToMCInst(), llvm::X86_MC::needsAddressSizeOverride(), llvm::X86InstPrinterCommon::printInstFlags(), printMasking(), llvm::CSKYInstPrinter::printOperand(), llvm::SIInstrInfo::pseudoToMCOpcode(), llvm::RISCVII::usesMaskPolicy(), and llvm::RISCVInstrInfo::verifyInstruction().

◆ UseOpIdx

unsigned UseOpIdx

Definition at line 640 of file RISCVInsertVSETVLI.cpp.

Referenced by llvm::GCNSubtarget::adjustSchedDependency(), if(), llvm::MachineInstr::isRegTiedToDefOperand(), llvm::MachineInstr::isRegTiedToUseOperand(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), llvm::SIInstrInfo::verifyInstruction(), and llvm::RISCVInstrInfo::verifyInstruction().

◆ UseStrictAsserts

cl::opt< bool > UseStrictAsserts("riscv-insert-vsetvl-strict-asserts", cl::init(true), cl::Hidden, cl::desc("Enable strict assertion checking for the dataflow algorithm")) ( "riscv-insert-vsetvl-strict-asserts"  ,
cl::init(true)  ,
cl::Hidden  ,
cl::desc("Enable strict assertion checking for the dataflow algorithm")   
)
static

◆ VLMul

RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags)

Definition at line 679 of file RISCVInsertVSETVLI.cpp.

Referenced by llvm::RISCVVType::getSEWLMULRatio(), and llvm::RISCVDAGToDAGISel::selectVSETVLI().

Generated on Fri Mar 31 2023 22:31:48 for LLVM by doxygen 1.9.6