LLVM 18.0.0git
RISCVTargetParser.cpp
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1//===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise hardware features
10// for RISC-V CPUs.
11//
12//===----------------------------------------------------------------------===//
13
18
19namespace llvm {
20namespace RISCV {
21
22enum CPUKind : unsigned {
23#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
24#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
25#include "llvm/TargetParser/RISCVTargetParserDef.inc"
26};
27
28struct CPUInfo {
31 bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
32};
33
34constexpr CPUInfo RISCVCPUInfo[] = {
35#define PROC(ENUM, NAME, DEFAULT_MARCH) \
36 {NAME, DEFAULT_MARCH},
37#include "llvm/TargetParser/RISCVTargetParserDef.inc"
38};
39
41 for (auto &C : RISCVCPUInfo)
42 if (C.Name == CPU)
43 return &C;
44 return nullptr;
45}
46
47bool parseCPU(StringRef CPU, bool IsRV64) {
48 const CPUInfo *Info = getCPUInfoByName(CPU);
49
50 if (!Info)
51 return false;
52 return Info->is64Bit() == IsRV64;
53}
54
55bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) {
56 std::optional<CPUKind> Kind =
58#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
59 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
60 .Default(std::nullopt);
61
62 if (Kind.has_value())
63 return true;
64
65 // Fallback to parsing as a CPU.
66 return parseCPU(TuneCPU, IsRV64);
67}
68
70 const CPUInfo *Info = getCPUInfoByName(CPU);
71 if (!Info)
72 return "";
73 return Info->DefaultMarch;
74}
75
77 for (const auto &C : RISCVCPUInfo) {
78 if (IsRV64 == C.is64Bit())
79 Values.emplace_back(C.Name);
80 }
81}
82
84 for (const auto &C : RISCVCPUInfo) {
85 if (IsRV64 == C.is64Bit())
86 Values.emplace_back(C.Name);
87 }
88#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
89#include "llvm/TargetParser/RISCVTargetParserDef.inc"
90}
91
92} // namespace RISCV
93} // namespace llvm
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define TUNE_PROC(ENUM, NAME)
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:857
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:257
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
void fillValidTuneCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
static const CPUInfo * getCPUInfoByName(StringRef CPU)
constexpr CPUInfo RISCVCPUInfo[]
StringRef getMArchFromMcpu(StringRef CPU)
bool parseCPU(StringRef CPU, bool IsRV64)
bool parseTuneCPU(StringRef CPU, bool IsRV64)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18