RISCVTargetParser.cpp File Reference

#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/Triple.h"
#include "llvm/TargetParser/RISCVTargetParserDef.inc"

Go to the source code of this file.

Classes
struct	llvm::RISCV::CPUInfo

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::RISCV
namespace	llvm::RISCV::RISCVExtensionBitmaskTable
namespace	llvm::RISCVVType

Macros
#define	PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)    CK_##ENUM,
#define	TUNE_PROC(ENUM, NAME)   CK_##ENUM,
#define	PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)    {NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},
#define	TUNE_PROC(ENUM, NAME)   .Case(NAME, CK_##ENUM)
#define	TUNE_PROC(ENUM, NAME)   Values.emplace_back(StringRef(NAME));
#define	GET_RISCVExtensionBitmaskTable_IMPL

Enumerations
enum	llvm::RISCV::CPUKind : unsigned

Functions
static const CPUInfo *	llvm::RISCV::getCPUInfoByName (StringRef CPU)
bool	llvm::RISCV::hasFastScalarUnalignedAccess (StringRef CPU)
bool	llvm::RISCV::hasFastVectorUnalignedAccess (StringRef CPU)
bool	llvm::RISCV::parseCPU (StringRef CPU, bool IsRV64)
bool	llvm::RISCV::parseTuneCPU (StringRef CPU, bool IsRV64)
StringRef	llvm::RISCV::getMArchFromMcpu (StringRef CPU)
void	llvm::RISCV::fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
void	llvm::RISCV::fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
void	llvm::RISCV::getFeaturesForCPU (StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
unsigned	llvm::RISCVVType::encodeVTYPE (RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
std::pair< unsigned, bool >	llvm::RISCVVType::decodeVLMUL (RISCVII::VLMUL VLMUL)
void	llvm::RISCVVType::printVType (unsigned VType, raw_ostream &OS)
unsigned	llvm::RISCVVType::getSEWLMULRatio (unsigned SEW, RISCVII::VLMUL VLMul)
std::optional< RISCVII::VLMUL >	llvm::RISCVVType::getSameRatioLMUL (unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW)

Variables
constexpr CPUInfo	llvm::RISCV::RISCVCPUInfo []

Macro Definition Documentation

GET_RISCVExtensionBitmaskTable_IMPL

#define GET_RISCVExtensionBitmaskTable_IMPL

Definition at line 133 of file RISCVTargetParser.cpp.

PROC [1/2]

#define PROC	(		ENUM,
			NAME,
			DEFAULT_MARCH,
			FAST_SCALAR_UNALIGN,
			FAST_VECTOR_UNALIGN
	)		CK_##ENUM,

Definition at line 24 of file RISCVTargetParser.cpp.

PROC [2/2]

#define PROC	(		ENUM,
			NAME,
			DEFAULT_MARCH,
			FAST_SCALAR_UNALIGN,
			FAST_VECTOR_UNALIGN
	)		{NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},

Definition at line 24 of file RISCVTargetParser.cpp.

TUNE_PROC [1/3]

#define TUNE_PROC	(		ENUM,
			NAME
	)		CK_##ENUM,

Definition at line 27 of file RISCVTargetParser.cpp.

TUNE_PROC [2/3]

#define TUNE_PROC	(		ENUM,
			NAME
	)		.Case(NAME, CK_##ENUM)

Definition at line 27 of file RISCVTargetParser.cpp.

TUNE_PROC [3/3]

#define TUNE_PROC	(		ENUM,
			NAME
	)		Values.emplace_back(StringRef(NAME));

Definition at line 27 of file RISCVTargetParser.cpp.