LLVM  12.0.0git
RISCVInstrInfo.cpp
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1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstrInfo.h"
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
16 #include "RISCVTargetMachine.h"
17 #include "Utils/RISCVMatInt.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
26 
27 using namespace llvm;
28 
29 #define GEN_CHECK_COMPRESS_INSTR
30 #include "RISCVGenCompressInstEmitter.inc"
31 
32 #define GET_INSTRINFO_CTOR_DTOR
33 #include "RISCVGenInstrInfo.inc"
34 
36  : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
37  STI(STI) {}
38 
40  int &FrameIndex) const {
41  switch (MI.getOpcode()) {
42  default:
43  return 0;
44  case RISCV::LB:
45  case RISCV::LBU:
46  case RISCV::LH:
47  case RISCV::LHU:
48  case RISCV::LW:
49  case RISCV::FLW:
50  case RISCV::LWU:
51  case RISCV::LD:
52  case RISCV::FLD:
53  break;
54  }
55 
56  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
57  MI.getOperand(2).getImm() == 0) {
58  FrameIndex = MI.getOperand(1).getIndex();
59  return MI.getOperand(0).getReg();
60  }
61 
62  return 0;
63 }
64 
66  int &FrameIndex) const {
67  switch (MI.getOpcode()) {
68  default:
69  return 0;
70  case RISCV::SB:
71  case RISCV::SH:
72  case RISCV::SW:
73  case RISCV::FSW:
74  case RISCV::SD:
75  case RISCV::FSD:
76  break;
77  }
78 
79  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
80  MI.getOperand(2).getImm() == 0) {
81  FrameIndex = MI.getOperand(1).getIndex();
82  return MI.getOperand(0).getReg();
83  }
84 
85  return 0;
86 }
87 
90  const DebugLoc &DL, MCRegister DstReg,
91  MCRegister SrcReg, bool KillSrc) const {
92  if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
93  BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
94  .addReg(SrcReg, getKillRegState(KillSrc))
95  .addImm(0);
96  return;
97  }
98 
99  // FPR->FPR copies
100  unsigned Opc;
101  if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
102  Opc = RISCV::FSGNJ_S;
103  else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
104  Opc = RISCV::FSGNJ_D;
105  else
106  llvm_unreachable("Impossible reg-to-reg copy");
107 
108  BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
109  .addReg(SrcReg, getKillRegState(KillSrc))
110  .addReg(SrcReg, getKillRegState(KillSrc));
111 }
112 
115  Register SrcReg, bool IsKill, int FI,
116  const TargetRegisterClass *RC,
117  const TargetRegisterInfo *TRI) const {
118  DebugLoc DL;
119  if (I != MBB.end())
120  DL = I->getDebugLoc();
121 
122  unsigned Opcode;
123 
124  if (RISCV::GPRRegClass.hasSubClassEq(RC))
125  Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
126  RISCV::SW : RISCV::SD;
127  else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
128  Opcode = RISCV::FSW;
129  else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
130  Opcode = RISCV::FSD;
131  else
132  llvm_unreachable("Can't store this register to stack slot");
133 
134  BuildMI(MBB, I, DL, get(Opcode))
135  .addReg(SrcReg, getKillRegState(IsKill))
136  .addFrameIndex(FI)
137  .addImm(0);
138 }
139 
142  Register DstReg, int FI,
143  const TargetRegisterClass *RC,
144  const TargetRegisterInfo *TRI) const {
145  DebugLoc DL;
146  if (I != MBB.end())
147  DL = I->getDebugLoc();
148 
149  unsigned Opcode;
150 
151  if (RISCV::GPRRegClass.hasSubClassEq(RC))
152  Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
153  RISCV::LW : RISCV::LD;
154  else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
155  Opcode = RISCV::FLW;
156  else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
157  Opcode = RISCV::FLD;
158  else
159  llvm_unreachable("Can't load this register from stack slot");
160 
161  BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
162 }
163 
166  const DebugLoc &DL, Register DstReg, uint64_t Val,
167  MachineInstr::MIFlag Flag) const {
168  MachineFunction *MF = MBB.getParent();
170  bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
171  Register SrcReg = RISCV::X0;
172  Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
173  unsigned Num = 0;
174 
175  if (!IsRV64 && !isInt<32>(Val))
176  report_fatal_error("Should only materialize 32-bit constants for RV32");
177 
179  RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
180  assert(Seq.size() > 0);
181 
182  for (RISCVMatInt::Inst &Inst : Seq) {
183  // Write the final result to DstReg if it's the last instruction in the Seq.
184  // Otherwise, write the result to the temp register.
185  if (++Num == Seq.size())
186  Result = DstReg;
187 
188  if (Inst.Opc == RISCV::LUI) {
189  BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
190  .addImm(Inst.Imm)
191  .setMIFlag(Flag);
192  } else {
193  BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
194  .addReg(SrcReg, RegState::Kill)
195  .addImm(Inst.Imm)
196  .setMIFlag(Flag);
197  }
198  // Only the first instruction has X0 as its source.
199  SrcReg = Result;
200  }
201 }
202 
203 // The contents of values added to Cond are not examined outside of
204 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
205 // push BranchOpcode, Reg1, Reg2.
208  // Block ends with fall-through condbranch.
209  assert(LastInst.getDesc().isConditionalBranch() &&
210  "Unknown conditional branch");
211  Target = LastInst.getOperand(2).getMBB();
213  Cond.push_back(LastInst.getOperand(0));
214  Cond.push_back(LastInst.getOperand(1));
215 }
216 
217 static unsigned getOppositeBranchOpcode(int Opc) {
218  switch (Opc) {
219  default:
220  llvm_unreachable("Unrecognized conditional branch");
221  case RISCV::BEQ:
222  return RISCV::BNE;
223  case RISCV::BNE:
224  return RISCV::BEQ;
225  case RISCV::BLT:
226  return RISCV::BGE;
227  case RISCV::BGE:
228  return RISCV::BLT;
229  case RISCV::BLTU:
230  return RISCV::BGEU;
231  case RISCV::BGEU:
232  return RISCV::BLTU;
233  }
234 }
235 
237  MachineBasicBlock *&TBB,
238  MachineBasicBlock *&FBB,
240  bool AllowModify) const {
241  TBB = FBB = nullptr;
242  Cond.clear();
243 
244  // If the block has no terminators, it just falls into the block after it.
246  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
247  return false;
248 
249  // Count the number of terminators and find the first unconditional or
250  // indirect branch.
251  MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
252  int NumTerminators = 0;
253  for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
254  J++) {
255  NumTerminators++;
256  if (J->getDesc().isUnconditionalBranch() ||
257  J->getDesc().isIndirectBranch()) {
258  FirstUncondOrIndirectBr = J.getReverse();
259  }
260  }
261 
262  // If AllowModify is true, we can erase any terminators after
263  // FirstUncondOrIndirectBR.
264  if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
265  while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
266  std::next(FirstUncondOrIndirectBr)->eraseFromParent();
267  NumTerminators--;
268  }
269  I = FirstUncondOrIndirectBr;
270  }
271 
272  // We can't handle blocks that end in an indirect branch.
273  if (I->getDesc().isIndirectBranch())
274  return true;
275 
276  // We can't handle blocks with more than 2 terminators.
277  if (NumTerminators > 2)
278  return true;
279 
280  // Handle a single unconditional branch.
281  if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
282  TBB = I->getOperand(0).getMBB();
283  return false;
284  }
285 
286  // Handle a single conditional branch.
287  if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
288  parseCondBranch(*I, TBB, Cond);
289  return false;
290  }
291 
292  // Handle a conditional branch followed by an unconditional branch.
293  if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
294  I->getDesc().isUnconditionalBranch()) {
295  parseCondBranch(*std::prev(I), TBB, Cond);
296  FBB = I->getOperand(0).getMBB();
297  return false;
298  }
299 
300  // Otherwise, we can't handle this.
301  return true;
302 }
303 
305  int *BytesRemoved) const {
306  if (BytesRemoved)
307  *BytesRemoved = 0;
309  if (I == MBB.end())
310  return 0;
311 
312  if (!I->getDesc().isUnconditionalBranch() &&
313  !I->getDesc().isConditionalBranch())
314  return 0;
315 
316  // Remove the branch.
317  if (BytesRemoved)
318  *BytesRemoved += getInstSizeInBytes(*I);
319  I->eraseFromParent();
320 
321  I = MBB.end();
322 
323  if (I == MBB.begin())
324  return 1;
325  --I;
326  if (!I->getDesc().isConditionalBranch())
327  return 1;
328 
329  // Remove the branch.
330  if (BytesRemoved)
331  *BytesRemoved += getInstSizeInBytes(*I);
332  I->eraseFromParent();
333  return 2;
334 }
335 
336 // Inserts a branch into the end of the specific MachineBasicBlock, returning
337 // the number of instructions inserted.
340  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
341  if (BytesAdded)
342  *BytesAdded = 0;
343 
344  // Shouldn't be a fall through.
345  assert(TBB && "insertBranch must not be told to insert a fallthrough");
346  assert((Cond.size() == 3 || Cond.size() == 0) &&
347  "RISCV branch conditions have two components!");
348 
349  // Unconditional branch.
350  if (Cond.empty()) {
351  MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
352  if (BytesAdded)
353  *BytesAdded += getInstSizeInBytes(MI);
354  return 1;
355  }
356 
357  // Either a one or two-way conditional branch.
358  unsigned Opc = Cond[0].getImm();
359  MachineInstr &CondMI =
360  *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
361  if (BytesAdded)
362  *BytesAdded += getInstSizeInBytes(CondMI);
363 
364  // One-way conditional branch.
365  if (!FBB)
366  return 1;
367 
368  // Two-way conditional branch.
369  MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
370  if (BytesAdded)
371  *BytesAdded += getInstSizeInBytes(MI);
372  return 2;
373 }
374 
376  MachineBasicBlock &DestBB,
377  const DebugLoc &DL,
378  int64_t BrOffset,
379  RegScavenger *RS) const {
380  assert(RS && "RegScavenger required for long branching");
381  assert(MBB.empty() &&
382  "new block should be inserted for expanding unconditional branch");
383  assert(MBB.pred_size() == 1);
384 
385  MachineFunction *MF = MBB.getParent();
386  MachineRegisterInfo &MRI = MF->getRegInfo();
387  const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
388 
389  if (TM.isPositionIndependent())
390  report_fatal_error("Unable to insert indirect branch");
391 
392  if (!isInt<32>(BrOffset))
394  "Branch offsets outside of the signed 32-bit range not supported");
395 
396  // FIXME: A virtual register must be used initially, as the register
397  // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
398  // uses the same workaround).
399  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
400  auto II = MBB.end();
401 
402  MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
403  .addMBB(&DestBB, RISCVII::MO_HI);
404  BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
405  .addReg(ScratchReg, RegState::Kill)
406  .addMBB(&DestBB, RISCVII::MO_LO);
407 
408  RS->enterBasicBlockEnd(MBB);
409  unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
410  LuiMI.getIterator(), false, 0);
411  MRI.replaceRegWith(ScratchReg, Scav);
412  MRI.clearVirtRegs();
413  RS->setRegUsed(Scav);
414  return 8;
415 }
416 
419  assert((Cond.size() == 3) && "Invalid branch condition!");
420  Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
421  return false;
422 }
423 
426  assert(MI.getDesc().isBranch() && "Unexpected opcode!");
427  // The branch target is always the last operand.
428  int NumOp = MI.getNumExplicitOperands();
429  return MI.getOperand(NumOp - 1).getMBB();
430 }
431 
433  int64_t BrOffset) const {
434  // Ideally we could determine the supported branch offset from the
435  // RISCVII::FormMask, but this can't be used for Pseudo instructions like
436  // PseudoBR.
437  switch (BranchOp) {
438  default:
439  llvm_unreachable("Unexpected opcode!");
440  case RISCV::BEQ:
441  case RISCV::BNE:
442  case RISCV::BLT:
443  case RISCV::BGE:
444  case RISCV::BLTU:
445  case RISCV::BGEU:
446  return isIntN(13, BrOffset);
447  case RISCV::JAL:
448  case RISCV::PseudoBR:
449  return isIntN(21, BrOffset);
450  }
451 }
452 
454  unsigned Opcode = MI.getOpcode();
455 
456  switch (Opcode) {
457  default: {
458  if (MI.getParent() && MI.getParent()->getParent()) {
459  const auto MF = MI.getMF();
460  const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
461  const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
462  const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo();
463  const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>();
464  if (isCompressibleInst(MI, &ST, MRI, STI))
465  return 2;
466  }
467  return get(Opcode).getSize();
468  }
470  case TargetOpcode::IMPLICIT_DEF:
471  case TargetOpcode::KILL:
472  case TargetOpcode::DBG_VALUE:
473  return 0;
474  // These values are determined based on RISCVExpandAtomicPseudoInsts,
475  // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the
476  // pseudos are expanded.
477  case RISCV::PseudoCALLReg:
478  case RISCV::PseudoCALL:
479  case RISCV::PseudoJump:
480  case RISCV::PseudoTAIL:
481  case RISCV::PseudoLLA:
482  case RISCV::PseudoLA:
483  case RISCV::PseudoLA_TLS_IE:
484  case RISCV::PseudoLA_TLS_GD:
485  return 8;
486  case RISCV::PseudoAtomicLoadNand32:
487  case RISCV::PseudoAtomicLoadNand64:
488  return 20;
489  case RISCV::PseudoMaskedAtomicSwap32:
490  case RISCV::PseudoMaskedAtomicLoadAdd32:
491  case RISCV::PseudoMaskedAtomicLoadSub32:
492  return 28;
493  case RISCV::PseudoMaskedAtomicLoadNand32:
494  return 32;
495  case RISCV::PseudoMaskedAtomicLoadMax32:
496  case RISCV::PseudoMaskedAtomicLoadMin32:
497  return 44;
498  case RISCV::PseudoMaskedAtomicLoadUMax32:
499  case RISCV::PseudoMaskedAtomicLoadUMin32:
500  return 36;
501  case RISCV::PseudoCmpXchg32:
502  case RISCV::PseudoCmpXchg64:
503  return 16;
504  case RISCV::PseudoMaskedCmpXchg32:
505  return 32;
508  const MachineFunction &MF = *MI.getParent()->getParent();
509  const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
510  return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
511  *TM.getMCAsmInfo());
512  }
513  }
514 }
515 
517  const unsigned Opcode = MI.getOpcode();
518  switch(Opcode) {
519  default:
520  break;
521  case RISCV::ADDI:
522  case RISCV::ORI:
523  case RISCV::XORI:
524  return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
525  }
526  return MI.isAsCheapAsAMove();
527 }
528 
530  StringRef &ErrInfo) const {
531  const MCInstrInfo *MCII = STI.getInstrInfo();
532  MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
533 
534  for (auto &OI : enumerate(Desc.operands())) {
535  unsigned OpType = OI.value().OperandType;
536  if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
538  const MachineOperand &MO = MI.getOperand(OI.index());
539  if (MO.isImm()) {
540  int64_t Imm = MO.getImm();
541  bool Ok;
542  switch (OpType) {
543  default:
544  llvm_unreachable("Unexpected operand type");
546  Ok = isUInt<4>(Imm);
547  break;
549  Ok = isUInt<5>(Imm);
550  break;
552  Ok = isUInt<12>(Imm);
553  break;
555  Ok = isInt<12>(Imm);
556  break;
558  Ok = isShiftedInt<12, 1>(Imm);
559  break;
561  Ok = isUInt<20>(Imm);
562  break;
564  Ok = isShiftedInt<20, 1>(Imm);
565  break;
567  if (STI.getTargetTriple().isArch64Bit())
568  Ok = isUInt<6>(Imm);
569  else
570  Ok = isUInt<5>(Imm);
571  break;
572  }
573  if (!Ok) {
574  ErrInfo = "Invalid immediate";
575  return false;
576  }
577  }
578  }
579  }
580 
581  return true;
582 }
583 
584 // Return true if get the base operand, byte offset of an instruction and the
585 // memory width. Width is the size of memory that is being loaded/stored.
587  const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
588  unsigned &Width, const TargetRegisterInfo *TRI) const {
589  if (!LdSt.mayLoadOrStore())
590  return false;
591 
592  // Here we assume the standard RISC-V ISA, which uses a base+offset
593  // addressing mode. You'll need to relax these conditions to support custom
594  // load/stores instructions.
595  if (LdSt.getNumExplicitOperands() != 3)
596  return false;
597  if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
598  return false;
599 
600  if (!LdSt.hasOneMemOperand())
601  return false;
602 
603  Width = (*LdSt.memoperands_begin())->getSize();
604  BaseReg = &LdSt.getOperand(1);
605  Offset = LdSt.getOperand(2).getImm();
606  return true;
607 }
608 
610  const MachineInstr &MIa, const MachineInstr &MIb) const {
611  assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
612  assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
613 
616  return false;
617 
618  // Retrieve the base register, offset from the base register and width. Width
619  // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
620  // base registers are identical, and the offset of a lower memory access +
621  // the width doesn't overlap the offset of a higher memory access,
622  // then the memory accesses are different.
624  const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
625  int64_t OffsetA = 0, OffsetB = 0;
626  unsigned int WidthA = 0, WidthB = 0;
627  if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
628  getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
629  if (BaseOpA->isIdenticalTo(*BaseOpB)) {
630  int LowOffset = std::min(OffsetA, OffsetB);
631  int HighOffset = std::max(OffsetA, OffsetB);
632  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
633  if (LowOffset + LowWidth <= HighOffset)
634  return true;
635  }
636  }
637  return false;
638 }
639 
640 std::pair<unsigned, unsigned>
642  const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
643  return std::make_pair(TF & Mask, TF & ~Mask);
644 }
645 
648  using namespace RISCVII;
649  static const std::pair<unsigned, const char *> TargetFlags[] = {
650  {MO_CALL, "riscv-call"},
651  {MO_PLT, "riscv-plt"},
652  {MO_LO, "riscv-lo"},
653  {MO_HI, "riscv-hi"},
654  {MO_PCREL_LO, "riscv-pcrel-lo"},
655  {MO_PCREL_HI, "riscv-pcrel-hi"},
656  {MO_GOT_HI, "riscv-got-hi"},
657  {MO_TPREL_LO, "riscv-tprel-lo"},
658  {MO_TPREL_HI, "riscv-tprel-hi"},
659  {MO_TPREL_ADD, "riscv-tprel-add"},
660  {MO_TLS_GOT_HI, "riscv-tls-got-hi"},
661  {MO_TLS_GD_HI, "riscv-tls-gd-hi"}};
662  return makeArrayRef(TargetFlags);
663 }
665  MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
666  const Function &F = MF.getFunction();
667 
668  // Can F be deduplicated by the linker? If it can, don't outline from it.
669  if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
670  return false;
671 
672  // Don't outline from functions with section markings; the program could
673  // expect that all the code is in the named section.
674  if (F.hasSection())
675  return false;
676 
677  // It's safe to outline from MF.
678  return true;
679 }
680 
682  unsigned &Flags) const {
683  // More accurate safety checking is done in getOutliningCandidateInfo.
684  return true;
685 }
686 
687 // Enum values indicating how an outlined call should be constructed.
690 };
691 
693  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
694 
695  // First we need to filter out candidates where the X5 register (IE t0) can't
696  // be used to setup the function call.
697  auto CannotInsertCall = [](outliner::Candidate &C) {
698  const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
699 
700  C.initLRU(*TRI);
701  LiveRegUnits LRU = C.LRU;
702  return !LRU.available(RISCV::X5);
703  };
704 
705  RepeatedSequenceLocs.erase(std::remove_if(RepeatedSequenceLocs.begin(),
706  RepeatedSequenceLocs.end(),
707  CannotInsertCall),
708  RepeatedSequenceLocs.end());
709 
710  // If the sequence doesn't have enough candidates left, then we're done.
711  if (RepeatedSequenceLocs.size() < 2)
713 
714  unsigned SequenceSize = 0;
715 
716  auto I = RepeatedSequenceLocs[0].front();
717  auto E = std::next(RepeatedSequenceLocs[0].back());
718  for (; I != E; ++I)
719  SequenceSize += getInstSizeInBytes(*I);
720 
721  // call t0, function = 8 bytes.
722  unsigned CallOverhead = 8;
723  for (auto &C : RepeatedSequenceLocs)
724  C.setCallInfo(MachineOutlinerDefault, CallOverhead);
725 
726  // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
727  unsigned FrameOverhead = 4;
728  if (RepeatedSequenceLocs[0].getMF()->getSubtarget()
729  .getFeatureBits()[RISCV::FeatureStdExtC])
730  FrameOverhead = 2;
731 
732  return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
733  FrameOverhead, MachineOutlinerDefault);
734 }
735 
738  unsigned Flags) const {
739  MachineInstr &MI = *MBBI;
741  const TargetRegisterInfo *TRI =
743 
744  // Positions generally can't safely be outlined.
745  if (MI.isPosition()) {
746  // We can manually strip out CFI instructions later.
747  if (MI.isCFIInstruction())
749 
751  }
752 
753  // Don't trust the user to write safe inline assembly.
754  if (MI.isInlineAsm())
756 
757  // We can't outline branches to other basic blocks.
758  if (MI.isTerminator() && !MBB->succ_empty())
760 
761  // We need support for tail calls to outlined functions before return
762  // statements can be allowed.
763  if (MI.isReturn())
765 
766  // Don't allow modifying the X5 register which we use for return addresses for
767  // these outlined functions.
768  if (MI.modifiesRegister(RISCV::X5, TRI) ||
769  MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
771 
772  // Make sure the operands don't reference something unsafe.
773  for (const auto &MO : MI.operands())
774  if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI())
776 
777  // Don't allow instructions which won't be materialized to impact outlining
778  // analysis.
779  if (MI.isMetaInstruction())
781 
783 }
784 
787  const outliner::OutlinedFunction &OF) const {
788 
789  // Strip out any CFI instructions
790  bool Changed = true;
791  while (Changed) {
792  Changed = false;
793  auto I = MBB.begin();
794  auto E = MBB.end();
795  for (; I != E; ++I) {
796  if (I->isCFIInstruction()) {
797  I->removeFromParent();
798  Changed = true;
799  break;
800  }
801  }
802  }
803 
804  MBB.addLiveIn(RISCV::X5);
805 
806  // Add in a return instruction to the end of the outlined frame.
807  MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
808  .addReg(RISCV::X0, RegState::Define)
809  .addReg(RISCV::X5)
810  .addImm(0));
811 }
812 
815  MachineFunction &MF, const outliner::Candidate &C) const {
816 
817  // Add in a call instruction to the outlined function at the given location.
818  It = MBB.insert(It,
819  BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)
820  .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
822  return It;
823 }
uint64_t CallInst * C
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
MachineBasicBlock * getMBB() const
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:23
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:67
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool isCFIInstruction() const
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:187
bool isInlineAsm() const
const RISCVRegisterInfo * getRegisterInfo() const override
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:965
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
F(f)
bool isMetaInstruction() const
Return true if this instruction doesn&#39;t produce any output in the form of executable instructions...
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:559
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
An individual sequence of instructions to be replaced with a call to an outlined function.
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
return AArch64::GPR64RegClass contains(Reg)
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:290
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineBasicBlock & MBB
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:458
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:784
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:456
const char * getSymbolName() const
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:871
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:453
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:117
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Definition: Module.cpp:113
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
reverse_iterator rend()
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getKillRegState(bool B)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool isAsCheapAsAMove(const MachineInstr &MI) const override
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:138
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:750
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
SmallVector< MachineOperand, 4 > Cond
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool hasLinkOnceODRLinkage() const
Definition: GlobalValue.h:436
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
InstrType
Represents how an instruction should be mapped by the outliner.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This instruction implements an extending load to FP stack slots.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:156
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MCInstrDesc.h:300
The information necessary to create an outlined function for some class of candidate.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:660
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:305
self_iterator getIterator()
Definition: ilist_node.h:81
RISCVInstrInfo(RISCVSubtarget &STI)
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
On a symbol operand, this represents the hi part.
Definition: AVRInstrInfo.h:55
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:461
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:879
auto remove_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::remove_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1530
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:374
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:645
static unsigned getOppositeBranchOpcode(int Opc)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineOperand class - Representation of each machine instruction operand.
bool hasSection() const
Check if this global has a custom object file section.
Definition: GlobalObject.h:107
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:883
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
int64_t getImm() const
unsigned pred_size() const
const RISCVSubtarget & STI
Target - Wrapper for Target specific information.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:280
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:62
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res)
Definition: RISCVMatInt.cpp:19
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:62
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:59
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Generic base class for all target subtargets.
iterator_range< const_opInfo_iterator > operands() const
Definition: MCInstrDesc.h:227
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
size_t size() const
Definition: SmallVector.h:66
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:874
const RISCVInstrInfo * getInstrInfo() const override
MachineOutlinerConstructionID
bool isPosition() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Register getReg() const
getReg - Returns the register number.
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:33
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:466
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:95
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static bool is64Bit(const char *name)
The operation is expected to be selectable directly by the target, and no transformation is necessary...
Definition: LegalizerInfo.h:49
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
MachineBasicBlock MachineBasicBlock::iterator MBBI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:151
detail::enumerator< R > enumerate(R &&TheRange)
Given an input range, returns a new range whose values are are pair (A,B) such that A is the 0-based ...
Definition: STLExtras.h:1886
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL