LLVM 19.0.0git
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1//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file defines the interfaces that XCore uses to lower LLVM code into a
10// selection DAG.
17#include "XCore.h"
21namespace llvm {
23 // Forward delcarations
24 class XCoreSubtarget;
26 namespace XCoreISD {
27 enum NodeType : unsigned {
28 // Start the numbering where the builtin ops and target ops leave off.
31 // Branch and link (call)
34 // pc relative address
37 // dp relative address
40 // cp relative address
43 // Load word from stack
46 // Store word to stack
49 // Corresponds to retsp instruction
52 // Corresponds to LADD instruction
55 // Corresponds to LSUB instruction
58 // Corresponds to LMUL instruction
61 // Corresponds to MACCU instruction
64 // Corresponds to MACCS instruction
67 // Corresponds to CRC8 instruction
70 // Jumptable branch.
73 // Jumptable branch using long branches for each entry.
76 // Offset from frame pointer to the first (possible) on-stack argument
79 // Exception handler return. The stack is restored to the first
80 // followed by a jump to the second argument.
82 };
83 }
85 //===--------------------------------------------------------------------===//
86 // TargetLowering Implementation
87 //===--------------------------------------------------------------------===//
89 {
90 public:
91 explicit XCoreTargetLowering(const TargetMachine &TM,
92 const XCoreSubtarget &Subtarget);
95 bool isZExtFree(SDValue Val, EVT VT2) const override;
98 unsigned getJumpTableEncoding() const override;
99 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override {
100 return MVT::i32;
101 }
103 /// LowerOperation - Provide custom lowering hooks for some operations.
104 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
106 /// ReplaceNodeResults - Replace the results of node with an illegal result
107 /// type with new values built out of custom code.
108 ///
110 SelectionDAG &DAG) const override;
112 /// getTargetNodeName - This method returns the name of a target specific
113 // DAG node.
114 const char *getTargetNodeName(unsigned Opcode) const override;
118 MachineBasicBlock *MBB) const override;
120 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
121 Type *Ty, unsigned AS,
122 Instruction *I = nullptr) const override;
124 /// If a physical register, this returns the register that receives the
125 /// exception address on entry to an EH pad.
127 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
128 return XCore::R0;
129 }
131 /// If a physical register, this returns the register that receives the
132 /// exception typeid on entry to a landing pad.
134 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
135 return XCore::R1;
136 }
138 private:
139 const TargetMachine &TM;
140 const XCoreSubtarget &Subtarget;
142 // Lower Operand helpers
143 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
144 bool isVarArg,
146 const SDLoc &dl, SelectionDAG &DAG,
147 SmallVectorImpl<SDValue> &InVals) const;
148 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
149 CallingConv::ID CallConv, bool isVarArg,
150 bool isTailCall,
152 const SmallVectorImpl<SDValue> &OutVals,
154 const SDLoc &dl, SelectionDAG &DAG,
155 SmallVectorImpl<SDValue> &InVals) const;
156 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
157 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
158 SelectionDAG &DAG) const;
159 SDValue lowerLoadWordFromAlignedBasePlusOffset(const SDLoc &DL,
160 SDValue Chain, SDValue Base,
161 int64_t Offset,
162 SelectionDAG &DAG) const;
164 // Lower Operand specifics
165 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
166 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
167 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
173 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
174 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
175 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
176 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
177 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
178 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
179 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
180 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
181 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
182 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
183 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
185 // Inline asm support
186 std::pair<unsigned, const TargetRegisterClass *>
187 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
188 StringRef Constraint, MVT VT) const override;
190 // Expand specifics
191 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
192 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
194 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
196 void computeKnownBitsForTargetNode(const SDValue Op,
197 KnownBits &Known,
198 const APInt &DemandedElts,
199 const SelectionDAG &DAG,
200 unsigned Depth = 0) const override;
202 SDValue
203 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
205 const SDLoc &dl, SelectionDAG &DAG,
206 SmallVectorImpl<SDValue> &InVals) const override;
208 SDValue
210 SmallVectorImpl<SDValue> &InVals) const override;
212 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
214 const SmallVectorImpl<SDValue> &OutVals,
215 const SDLoc &dl, SelectionDAG &DAG) const override;
217 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
218 bool isVarArg,
219 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
220 LLVMContext &Context) const override;
221 };
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:77
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1425
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
#define N
Extended Value Type.
Definition: ValueTypes.h:34
This structure contains all information that is necessary for lowering calls.