LLVM  10.0.0svn
XCoreISelLowering.h
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1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that XCore uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
15 #define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
16 
17 #include "XCore.h"
20 
21 namespace llvm {
22 
23  // Forward delcarations
24  class XCoreSubtarget;
25  class XCoreTargetMachine;
26 
27  namespace XCoreISD {
28  enum NodeType : unsigned {
29  // Start the numbering where the builtin ops and target ops leave off.
31 
32  // Branch and link (call)
33  BL,
34 
35  // pc relative address
37 
38  // dp relative address
40 
41  // cp relative address
43 
44  // Load word from stack
46 
47  // Store word to stack
49 
50  // Corresponds to retsp instruction
52 
53  // Corresponds to LADD instruction
55 
56  // Corresponds to LSUB instruction
58 
59  // Corresponds to LMUL instruction
61 
62  // Corresponds to MACCU instruction
64 
65  // Corresponds to MACCS instruction
67 
68  // Corresponds to CRC8 instruction
70 
71  // Jumptable branch.
73 
74  // Jumptable branch using long branches for each entry.
76 
77  // Offset from frame pointer to the first (possible) on-stack argument
79 
80  // Exception handler return. The stack is restored to the first
81  // followed by a jump to the second argument.
83 
84  // Memory barrier.
86  };
87  }
88 
89  //===--------------------------------------------------------------------===//
90  // TargetLowering Implementation
91  //===--------------------------------------------------------------------===//
93  {
94  public:
95  explicit XCoreTargetLowering(const TargetMachine &TM,
96  const XCoreSubtarget &Subtarget);
97 
99  bool isZExtFree(SDValue Val, EVT VT2) const override;
100 
101 
102  unsigned getJumpTableEncoding() const override;
103  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override {
104  return MVT::i32;
105  }
106 
107  /// LowerOperation - Provide custom lowering hooks for some operations.
108  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
109 
110  /// ReplaceNodeResults - Replace the results of node with an illegal result
111  /// type with new values built out of custom code.
112  ///
113  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
114  SelectionDAG &DAG) const override;
115 
116  /// getTargetNodeName - This method returns the name of a target specific
117  // DAG node.
118  const char *getTargetNodeName(unsigned Opcode) const override;
119 
121  EmitInstrWithCustomInserter(MachineInstr &MI,
122  MachineBasicBlock *MBB) const override;
123 
124  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
125  Type *Ty, unsigned AS,
126  Instruction *I = nullptr) const override;
127 
128  /// If a physical register, this returns the register that receives the
129  /// exception address on entry to an EH pad.
130  unsigned
131  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
132  return XCore::R0;
133  }
134 
135  /// If a physical register, this returns the register that receives the
136  /// exception typeid on entry to a landing pad.
137  unsigned
138  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
139  return XCore::R1;
140  }
141 
142  private:
143  const TargetMachine &TM;
144  const XCoreSubtarget &Subtarget;
145 
146  // Lower Operand helpers
147  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
148  bool isVarArg,
150  const SDLoc &dl, SelectionDAG &DAG,
151  SmallVectorImpl<SDValue> &InVals) const;
152  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
153  CallingConv::ID CallConv, bool isVarArg,
154  bool isTailCall,
156  const SmallVectorImpl<SDValue> &OutVals,
158  const SDLoc &dl, SelectionDAG &DAG,
159  SmallVectorImpl<SDValue> &InVals) const;
160  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
161  SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
162  SelectionDAG &DAG) const;
163  SDValue lowerLoadWordFromAlignedBasePlusOffset(const SDLoc &DL,
164  SDValue Chain, SDValue Base,
165  int64_t Offset,
166  SelectionDAG &DAG) const;
167 
168  // Lower Operand specifics
169  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
170  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
171  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
172  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
173  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
174  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
175  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
176  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
177  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
178  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
179  SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
180  SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
181  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
182  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
184  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
186  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
188  SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
190 
191  MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
192 
193  // Inline asm support
194  std::pair<unsigned, const TargetRegisterClass *>
195  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
196  StringRef Constraint, MVT VT) const override;
197 
198  // Expand specifics
199  SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
200  SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
201 
202  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
203 
204  void computeKnownBitsForTargetNode(const SDValue Op,
205  KnownBits &Known,
206  const APInt &DemandedElts,
207  const SelectionDAG &DAG,
208  unsigned Depth = 0) const override;
209 
210  SDValue
211  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
213  const SDLoc &dl, SelectionDAG &DAG,
214  SmallVectorImpl<SDValue> &InVals) const override;
215 
216  SDValue
217  LowerCall(TargetLowering::CallLoweringInfo &CLI,
218  SmallVectorImpl<SDValue> &InVals) const override;
219 
220  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
222  const SmallVectorImpl<SDValue> &OutVals,
223  const SDLoc &dl, SelectionDAG &DAG) const override;
224 
225  bool
226  CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
227  bool isVarArg,
228  const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
229  LLVMContext &Context) const override;
230  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
231  return true;
232  }
233  };
234 }
235 
236 #endif
static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
This is an important base class in LLVM.
Definition: Constant.h:41
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
Flags
Flags values. These may be or&#39;d together.
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG, const X86Subtarget &Subtarget)
This file describes how to lower LLVM code to machine code.