28#define DEBUG_TYPE "riscv-vl-optimizer"
29#define PASS_NAME "RISC-V VL Optimizer"
60char RISCVVLOptimizer::ID = 0;
66 return new RISCVVLOptimizer();
72 return RISCV::VRRegClass.contains(R);
87 std::optional<std::pair<unsigned, bool>>
EMUL;
104 assert(
A.isKnown() &&
B.isKnown() &&
"Both operands must be known");
106 return A.Log2EEW ==
B.Log2EEW &&
A.EMUL->first ==
B.EMUL->first &&
107 A.EMUL->second ==
B.EMUL->second;
115 assert(
EMUL &&
"Expected EMUL to have value");
131namespace RISCVVType {
156static std::pair<unsigned, bool>
168 unsigned MISEW = 1 << MILog2SEW;
170 unsigned EEW = 1 << Log2EEW;
173 unsigned Num = EEW, Denom = MISEW;
174 int GCD = MILMULIsFractional ? std::gcd(Num, Denom * MILMUL)
175 : std::gcd(Num * MILMUL, Denom);
176 Num = MILMULIsFractional ? Num / GCD : Num * MILMUL / GCD;
177 Denom = MILMULIsFractional ? Denom * MILMUL / GCD : Denom / GCD;
178 return std::make_pair(Num > Denom ? Num : Denom, Denom > Num);
195 unsigned MISEW = 1 << MILog2SEW;
196 unsigned EEW = MISEW / Factor;
197 unsigned Log2EEW =
Log2_32(EEW);
211 return Desc.operands()[MO.
getOperandNo()].RegClass == RISCV::VMV0RegClassID;
219 RISCVVPseudosTable::getPseudoInfo(
MI.getOpcode());
220 assert(
RVV &&
"Could not find MI in PseudoTable");
234 if (HasPassthru && MO.
getOperandNo() ==
MI.getNumExplicitDefs() &&
235 (MO.
getReg() != RISCV::NoRegister))
246 switch (
RVV->BaseInstr) {
250 case RISCV::VSETIVLI:
264 case RISCV::VSSE16_V:
267 case RISCV::VSSE32_V:
270 case RISCV::VSSE64_V:
277 case RISCV::VLUXEI8_V:
278 case RISCV::VLOXEI8_V:
279 case RISCV::VSUXEI8_V:
280 case RISCV::VSOXEI8_V: {
285 case RISCV::VLUXEI16_V:
286 case RISCV::VLOXEI16_V:
287 case RISCV::VSUXEI16_V:
288 case RISCV::VSOXEI16_V: {
293 case RISCV::VLUXEI32_V:
294 case RISCV::VLOXEI32_V:
295 case RISCV::VSUXEI32_V:
296 case RISCV::VSOXEI32_V: {
301 case RISCV::VLUXEI64_V:
302 case RISCV::VLOXEI64_V:
303 case RISCV::VSUXEI64_V:
304 case RISCV::VSOXEI64_V: {
317 case RISCV::VRSUB_VI:
318 case RISCV::VRSUB_VX:
342 case RISCV::VMINU_VV:
343 case RISCV::VMINU_VX:
346 case RISCV::VMAXU_VV:
347 case RISCV::VMAXU_VX:
354 case RISCV::VMULH_VV:
355 case RISCV::VMULH_VX:
356 case RISCV::VMULHU_VV:
357 case RISCV::VMULHU_VX:
358 case RISCV::VMULHSU_VV:
359 case RISCV::VMULHSU_VX:
362 case RISCV::VDIVU_VV:
363 case RISCV::VDIVU_VX:
366 case RISCV::VREMU_VV:
367 case RISCV::VREMU_VX:
372 case RISCV::VMACC_VV:
373 case RISCV::VMACC_VX:
374 case RISCV::VNMSAC_VV:
375 case RISCV::VNMSAC_VX:
376 case RISCV::VMADD_VV:
377 case RISCV::VMADD_VX:
378 case RISCV::VNMSUB_VV:
379 case RISCV::VNMSUB_VX:
384 case RISCV::VMERGE_VIM:
385 case RISCV::VMERGE_VVM:
386 case RISCV::VMERGE_VXM:
387 case RISCV::VADC_VIM:
388 case RISCV::VADC_VVM:
389 case RISCV::VADC_VXM:
390 case RISCV::VSBC_VVM:
391 case RISCV::VSBC_VXM:
400 case RISCV::VSADDU_VI:
401 case RISCV::VSADDU_VV:
402 case RISCV::VSADDU_VX:
403 case RISCV::VSADD_VI:
404 case RISCV::VSADD_VV:
405 case RISCV::VSADD_VX:
406 case RISCV::VSSUBU_VV:
407 case RISCV::VSSUBU_VX:
408 case RISCV::VSSUB_VV:
409 case RISCV::VSSUB_VX:
410 case RISCV::VAADDU_VV:
411 case RISCV::VAADDU_VX:
412 case RISCV::VAADD_VV:
413 case RISCV::VAADD_VX:
414 case RISCV::VASUBU_VV:
415 case RISCV::VASUBU_VX:
416 case RISCV::VASUB_VV:
417 case RISCV::VASUB_VX:
421 case RISCV::VSMUL_VV:
422 case RISCV::VSMUL_VX:
425 case RISCV::VSSRL_VI:
426 case RISCV::VSSRL_VV:
427 case RISCV::VSSRL_VX:
428 case RISCV::VSSRA_VI:
429 case RISCV::VSSRA_VV:
430 case RISCV::VSSRA_VX:
437 case RISCV::VFMV_F_S:
438 case RISCV::VFMV_S_F:
441 case RISCV::VSLIDEUP_VI:
442 case RISCV::VSLIDEUP_VX:
443 case RISCV::VSLIDEDOWN_VI:
444 case RISCV::VSLIDEDOWN_VX:
445 case RISCV::VSLIDE1UP_VX:
446 case RISCV::VFSLIDE1UP_VF:
447 case RISCV::VSLIDE1DOWN_VX:
448 case RISCV::VFSLIDE1DOWN_VF:
451 case RISCV::VRGATHER_VI:
452 case RISCV::VRGATHER_VV:
453 case RISCV::VRGATHER_VX:
456 case RISCV::VCOMPRESS_VM:
460 case RISCV::VFADD_VF:
461 case RISCV::VFADD_VV:
462 case RISCV::VFSUB_VF:
463 case RISCV::VFSUB_VV:
464 case RISCV::VFRSUB_VF:
466 case RISCV::VFMUL_VF:
467 case RISCV::VFMUL_VV:
468 case RISCV::VFDIV_VF:
469 case RISCV::VFDIV_VV:
470 case RISCV::VFRDIV_VF:
472 case RISCV::VFSQRT_V:
474 case RISCV::VFRSQRT7_V:
476 case RISCV::VFREC7_V:
478 case RISCV::VFMIN_VF:
479 case RISCV::VFMIN_VV:
480 case RISCV::VFMAX_VF:
481 case RISCV::VFMAX_VV:
483 case RISCV::VFSGNJ_VF:
484 case RISCV::VFSGNJ_VV:
485 case RISCV::VFSGNJN_VV:
486 case RISCV::VFSGNJN_VF:
487 case RISCV::VFSGNJX_VF:
488 case RISCV::VFSGNJX_VV:
490 case RISCV::VFCLASS_V:
492 case RISCV::VFMV_V_F:
494 case RISCV::VFCVT_XU_F_V:
495 case RISCV::VFCVT_X_F_V:
496 case RISCV::VFCVT_RTZ_XU_F_V:
497 case RISCV::VFCVT_RTZ_X_F_V:
498 case RISCV::VFCVT_F_XU_V:
499 case RISCV::VFCVT_F_X_V:
501 case RISCV::VFMERGE_VFM:
506 case RISCV::VWADDU_VV:
507 case RISCV::VWADDU_VX:
508 case RISCV::VWSUBU_VV:
509 case RISCV::VWSUBU_VX:
510 case RISCV::VWADD_VV:
511 case RISCV::VWADD_VX:
512 case RISCV::VWSUB_VV:
513 case RISCV::VWSUB_VX:
514 case RISCV::VWSLL_VI:
517 case RISCV::VWMUL_VV:
518 case RISCV::VWMUL_VX:
519 case RISCV::VWMULSU_VV:
520 case RISCV::VWMULSU_VX:
521 case RISCV::VWMULU_VV:
522 case RISCV::VWMULU_VX:
528 case RISCV::VWMACCU_VV:
529 case RISCV::VWMACCU_VX:
530 case RISCV::VWMACC_VV:
531 case RISCV::VWMACC_VX:
532 case RISCV::VWMACCSU_VV:
533 case RISCV::VWMACCSU_VX:
534 case RISCV::VWMACCUS_VX:
536 case RISCV::VFWMACC_VF:
537 case RISCV::VFWMACC_VV:
538 case RISCV::VFWNMACC_VF:
539 case RISCV::VFWNMACC_VV:
540 case RISCV::VFWMSAC_VF:
541 case RISCV::VFWMSAC_VV:
542 case RISCV::VFWNMSAC_VF:
543 case RISCV::VFWNMSAC_VV:
546 case RISCV::VFWADD_VV:
547 case RISCV::VFWADD_VF:
548 case RISCV::VFWSUB_VV:
549 case RISCV::VFWSUB_VF:
551 case RISCV::VFWMUL_VF:
552 case RISCV::VFWMUL_VV:
554 case RISCV::VFWCVT_XU_F_V:
555 case RISCV::VFWCVT_X_F_V:
556 case RISCV::VFWCVT_RTZ_XU_F_V:
557 case RISCV::VFWCVT_RTZ_X_F_V:
558 case RISCV::VFWCVT_F_XU_V:
559 case RISCV::VFWCVT_F_X_V:
560 case RISCV::VFWCVT_F_F_V: {
561 unsigned Log2EEW = IsMODef ? MILog2SEW + 1 : MILog2SEW;
568 case RISCV::VWADDU_WV:
569 case RISCV::VWADDU_WX:
570 case RISCV::VWSUBU_WV:
571 case RISCV::VWSUBU_WX:
572 case RISCV::VWADD_WV:
573 case RISCV::VWADD_WX:
574 case RISCV::VWSUB_WV:
575 case RISCV::VWSUB_WX:
577 case RISCV::VFWADD_WF:
578 case RISCV::VFWADD_WV:
579 case RISCV::VFWSUB_WF:
580 case RISCV::VFWSUB_WV: {
582 bool TwoTimes = IsMODef || IsOp1;
583 unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW;
590 case RISCV::VZEXT_VF2:
591 case RISCV::VSEXT_VF2:
593 case RISCV::VZEXT_VF4:
594 case RISCV::VSEXT_VF4:
596 case RISCV::VZEXT_VF8:
597 case RISCV::VSEXT_VF8:
603 case RISCV::VNSRL_WX:
604 case RISCV::VNSRL_WI:
605 case RISCV::VNSRL_WV:
606 case RISCV::VNSRA_WI:
607 case RISCV::VNSRA_WV:
608 case RISCV::VNSRA_WX:
611 case RISCV::VNCLIPU_WI:
612 case RISCV::VNCLIPU_WV:
613 case RISCV::VNCLIPU_WX:
614 case RISCV::VNCLIP_WI:
615 case RISCV::VNCLIP_WV:
616 case RISCV::VNCLIP_WX:
618 case RISCV::VFNCVT_XU_F_W:
619 case RISCV::VFNCVT_X_F_W:
620 case RISCV::VFNCVT_RTZ_XU_F_W:
621 case RISCV::VFNCVT_RTZ_X_F_W:
622 case RISCV::VFNCVT_F_XU_W:
623 case RISCV::VFNCVT_F_X_W:
624 case RISCV::VFNCVT_F_F_W:
625 case RISCV::VFNCVT_ROD_F_F_W: {
627 bool TwoTimes = IsOp1;
628 unsigned Log2EEW = TwoTimes ? MILog2SEW + 1 : MILog2SEW;
643 case RISCV::VMAND_MM:
644 case RISCV::VMNAND_MM:
645 case RISCV::VMANDN_MM:
646 case RISCV::VMXOR_MM:
648 case RISCV::VMNOR_MM:
649 case RISCV::VMORN_MM:
650 case RISCV::VMXNOR_MM:
653 case RISCV::VMSOF_M: {
660 case RISCV::VIOTA_M: {
668 case RISCV::VMSEQ_VI:
669 case RISCV::VMSEQ_VV:
670 case RISCV::VMSEQ_VX:
671 case RISCV::VMSNE_VI:
672 case RISCV::VMSNE_VV:
673 case RISCV::VMSNE_VX:
674 case RISCV::VMSLTU_VV:
675 case RISCV::VMSLTU_VX:
676 case RISCV::VMSLT_VV:
677 case RISCV::VMSLT_VX:
678 case RISCV::VMSLEU_VV:
679 case RISCV::VMSLEU_VI:
680 case RISCV::VMSLEU_VX:
681 case RISCV::VMSLE_VV:
682 case RISCV::VMSLE_VI:
683 case RISCV::VMSLE_VX:
684 case RISCV::VMSGTU_VI:
685 case RISCV::VMSGTU_VX:
686 case RISCV::VMSGT_VI:
687 case RISCV::VMSGT_VX:
691 case RISCV::VMADC_VIM:
692 case RISCV::VMADC_VVM:
693 case RISCV::VMADC_VXM:
694 case RISCV::VMSBC_VVM:
695 case RISCV::VMSBC_VXM:
697 case RISCV::VMADC_VV:
698 case RISCV::VMADC_VI:
699 case RISCV::VMADC_VX:
700 case RISCV::VMSBC_VV:
701 case RISCV::VMSBC_VX:
704 case RISCV::VMFEQ_VF:
705 case RISCV::VMFEQ_VV:
706 case RISCV::VMFNE_VF:
707 case RISCV::VMFNE_VV:
708 case RISCV::VMFLT_VF:
709 case RISCV::VMFLT_VV:
710 case RISCV::VMFLE_VF:
711 case RISCV::VMFLE_VV:
712 case RISCV::VMFGT_VF:
713 case RISCV::VMFGE_VF: {
729 RISCVVPseudosTable::getPseudoInfo(
MI.getOpcode());
734 switch (
RVV->BaseInstr) {
741 case RISCV::VRSUB_VI:
742 case RISCV::VRSUB_VX:
764 case RISCV::VWADDU_VV:
765 case RISCV::VWADDU_VX:
766 case RISCV::VWSUBU_VV:
767 case RISCV::VWSUBU_VX:
768 case RISCV::VWADD_VV:
769 case RISCV::VWADD_VX:
770 case RISCV::VWSUB_VV:
771 case RISCV::VWSUB_VX:
772 case RISCV::VWADDU_WV:
773 case RISCV::VWADDU_WX:
774 case RISCV::VWSUBU_WV:
775 case RISCV::VWSUBU_WX:
776 case RISCV::VWADD_WV:
777 case RISCV::VWADD_WX:
778 case RISCV::VWSUB_WV:
779 case RISCV::VWSUB_WX:
781 case RISCV::VZEXT_VF2:
782 case RISCV::VSEXT_VF2:
783 case RISCV::VZEXT_VF4:
784 case RISCV::VSEXT_VF4:
785 case RISCV::VZEXT_VF8:
786 case RISCV::VSEXT_VF8:
789 case RISCV::VMADC_VV:
790 case RISCV::VMADC_VI:
791 case RISCV::VMADC_VX:
792 case RISCV::VMSBC_VV:
793 case RISCV::VMSBC_VX:
795 case RISCV::VNSRL_WX:
796 case RISCV::VNSRL_WI:
797 case RISCV::VNSRL_WV:
798 case RISCV::VNSRA_WI:
799 case RISCV::VNSRA_WV:
800 case RISCV::VNSRA_WX:
802 case RISCV::VMSEQ_VI:
803 case RISCV::VMSEQ_VV:
804 case RISCV::VMSEQ_VX:
805 case RISCV::VMSNE_VI:
806 case RISCV::VMSNE_VV:
807 case RISCV::VMSNE_VX:
808 case RISCV::VMSLTU_VV:
809 case RISCV::VMSLTU_VX:
810 case RISCV::VMSLT_VV:
811 case RISCV::VMSLT_VX:
812 case RISCV::VMSLEU_VV:
813 case RISCV::VMSLEU_VI:
814 case RISCV::VMSLEU_VX:
815 case RISCV::VMSLE_VV:
816 case RISCV::VMSLE_VI:
817 case RISCV::VMSLE_VX:
818 case RISCV::VMSGTU_VI:
819 case RISCV::VMSGTU_VX:
820 case RISCV::VMSGT_VI:
821 case RISCV::VMSGT_VX:
823 case RISCV::VMINU_VV:
824 case RISCV::VMINU_VX:
827 case RISCV::VMAXU_VV:
828 case RISCV::VMAXU_VX:
834 case RISCV::VMULH_VV:
835 case RISCV::VMULH_VX:
836 case RISCV::VMULHU_VV:
837 case RISCV::VMULHU_VX:
838 case RISCV::VMULHSU_VV:
839 case RISCV::VMULHSU_VX:
841 case RISCV::VDIVU_VV:
842 case RISCV::VDIVU_VX:
845 case RISCV::VREMU_VV:
846 case RISCV::VREMU_VX:
850 case RISCV::VWMUL_VV:
851 case RISCV::VWMUL_VX:
852 case RISCV::VWMULSU_VV:
853 case RISCV::VWMULSU_VX:
854 case RISCV::VWMULU_VV:
855 case RISCV::VWMULU_VX:
857 case RISCV::VMACC_VV:
858 case RISCV::VMACC_VX:
859 case RISCV::VNMSAC_VV:
860 case RISCV::VNMSAC_VX:
861 case RISCV::VMADD_VV:
862 case RISCV::VMADD_VX:
863 case RISCV::VNMSUB_VV:
864 case RISCV::VNMSUB_VX:
866 case RISCV::VWMACCU_VV:
867 case RISCV::VWMACCU_VX:
868 case RISCV::VWMACC_VV:
869 case RISCV::VWMACC_VX:
870 case RISCV::VWMACCSU_VV:
871 case RISCV::VWMACCSU_VX:
872 case RISCV::VWMACCUS_VX:
882 case RISCV::VWSLL_VI:
891 case RISCV::VMAND_MM:
892 case RISCV::VMNAND_MM:
893 case RISCV::VMANDN_MM:
894 case RISCV::VMXOR_MM:
896 case RISCV::VMNOR_MM:
897 case RISCV::VMORN_MM:
898 case RISCV::VMXNOR_MM:
914 RISCVVPseudosTable::getPseudoInfo(
MI->getOpcode());
919 switch (
RVV->BaseInstr) {
921 case RISCV::VREDAND_VS:
922 case RISCV::VREDMAX_VS:
923 case RISCV::VREDMAXU_VS:
924 case RISCV::VREDMIN_VS:
925 case RISCV::VREDMINU_VS:
926 case RISCV::VREDOR_VS:
927 case RISCV::VREDSUM_VS:
928 case RISCV::VREDXOR_VS:
929 case RISCV::VWREDSUM_VS:
930 case RISCV::VWREDSUMU_VS:
931 case RISCV::VFREDMAX_VS:
932 case RISCV::VFREDMIN_VS:
933 case RISCV::VFREDOSUM_VS:
934 case RISCV::VFREDUSUM_VS:
935 case RISCV::VFWREDOSUM_VS:
936 case RISCV::VFWREDUSUM_VS:
939 case RISCV::VFMV_F_S:
949 RISCVVPseudosTable::getPseudoInfo(
MI.getOpcode());
953 switch (
RVV->BaseInstr) {
956 case RISCV::VSLIDEDOWN_VI:
957 case RISCV::VSLIDEDOWN_VX:
958 case RISCV::VSLIDE1DOWN_VX:
959 case RISCV::VFSLIDE1DOWN_VF:
963 case RISCV::VRGATHER_VI:
964 case RISCV::VRGATHER_VV:
965 case RISCV::VRGATHER_VX:
966 case RISCV::VRGATHEREI16_VV:
978 if (
MI.getNumDefs() != 1)
993 unsigned PassthruOpIdx =
MI.getNumExplicitDefs();
995 MI.getOperand(PassthruOpIdx).getReg() != RISCV::NoRegister) {
997 dbgs() <<
" Not a candidate because it uses non-undef passthru"
998 " with non-VLMAX VL\n");
1006 LLVM_DEBUG(
dbgs() <<
" Not a candidate because VL is already 1\n");
1023 LLVM_DEBUG(
dbgs() <<
"Not a candidate due to unsupported instruction\n");
1027 LLVM_DEBUG(
dbgs() <<
"Found a candidate for VL reduction: " <<
MI <<
"\n");
1031bool RISCVVLOptimizer::checkUsers(
const MachineOperand *&CommonVL,
1037 bool CanReduceVL =
true;
1038 for (
auto &UserOp :
MRI->use_operands(
MI.getOperand(0).getReg())) {
1047 CanReduceVL =
false;
1052 LLVM_DEBUG(
dbgs() <<
" Abort because used by unsafe instruction\n");
1053 CanReduceVL =
false;
1058 if (UserOp.isTied()) {
1059 LLVM_DEBUG(
dbgs() <<
" Abort because user used as tied operand\n");
1060 CanReduceVL =
false;
1066 LLVM_DEBUG(
dbgs() <<
" Abort due to lack of VL or SEW, assume that"
1068 CanReduceVL =
false;
1077 "Did not expect X0 VL");
1085 LLVM_DEBUG(
dbgs() <<
" Abort because cannot determine a common VL\n");
1086 CanReduceVL =
false;
1096 "information for EMUL or EEW.\n");
1097 LLVM_DEBUG(
dbgs() <<
" ConsumerInfo is: " << ConsumerInfo <<
"\n");
1098 LLVM_DEBUG(
dbgs() <<
" ProducerInfo is: " << ProducerInfo <<
"\n");
1099 CanReduceVL =
false;
1106bool RISCVVLOptimizer::tryReduceVL(
MachineInstr &OrigMI) {
1108 Worklist.
insert(&OrigMI);
1110 bool MadeChange =
false;
1111 while (!Worklist.
empty()) {
1116 bool CanReduceVL =
true;
1118 CanReduceVL = checkUsers(CommonVL,
MI);
1120 if (!CanReduceVL || !CommonVL)
1124 "Expected VL to be an Imm or virtual Reg");
1134 if (CommonVL->
isImm()) {
1136 << CommonVL->
getImm() <<
" for " <<
MI <<
"\n");
1140 if (!MDT->dominates(VLMI, &
MI))
1143 dbgs() <<
" Reduce VL from " << VLOp <<
" to "
1145 <<
" for " <<
MI <<
"\n");
1154 for (
auto &
Op :
MI.operands()) {
1155 if (!
Op.isReg() || !
Op.isUse() || !
Op.getReg().isVirtual())
1178 MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
1181 if (!
ST.hasVInstructions())
1184 bool MadeChange =
false;
1191 MadeChange |= tryReduceVL(
MI);
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
#define LLVM_ATTRIBUTE_UNUSED
static bool isCandidate(const MachineInstr *MI, Register &DefedReg, Register FrameReg)
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static bool mayReadPastVL(const MachineInstr &MI)
Return true if MI may read elements past VL.
static OperandInfo getOperandInfo(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Return the OperandInfo for MO.
static LLVM_ATTRIBUTE_UNUSED raw_ostream & operator<<(raw_ostream &OS, const OperandInfo &OI)
static bool isVectorOpUsedAsScalarOp(MachineOperand &MO)
Return true if MO is a vector operand but is used as a scalar operand.
static bool isVectorRegClass(Register R, const MachineRegisterInfo *MRI)
Return true if R is a physical or virtual vector register, false otherwise.
static bool isSupportedInstr(const MachineInstr &MI)
Return true if this optimization should consider MI for VL reduction.
static OperandInfo getIntegerExtensionOperandInfo(unsigned Factor, const MachineInstr &MI, const MachineOperand &MO)
Dest has EEW=SEW and EMUL=LMUL.
static bool isMaskOperand(const MachineInstr &MI, const MachineOperand &MO, const MachineRegisterInfo *MRI)
Check whether MO is a mask operand of MI.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesCFG()
This function should be called by the pass, iff they do not:
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
reverse_iterator rbegin()
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
const MachineBasicBlock * getParent() const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
A vector that has set insertion semantics.
bool empty() const
Determine if the SetVector is empty or not.
bool insert(const value_type &X)
Insert a new element into the SetVector.
value_type pop_back_val()
StringRef - Represent a constant reference to a string, i.e.
const uint8_t TSFlags
Configurable target specific flags.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
static bool isVRegClass(uint64_t TSFlags)
static std::pair< unsigned, bool > getEMULEqualsEEWDivSEWTimesLMUL(unsigned Log2EEW, const MachineInstr &MI)
Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags o...
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
static RISCVII::VLMUL twoTimesVLMUL(RISCVII::VLMUL VLMul)
Return the RISCVII::VLMUL that is two times VLMul.
bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS)
Given two VL operands, do we know that LHS <= RHS?
static constexpr int64_t VLMaxSentinel
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
FunctionPass * createRISCVVLOptimizerPass()
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Represents the EMUL and EEW of a MachineOperand.
OperandInfo(std::pair< unsigned, bool > EMUL, unsigned Log2EEW)
void print(raw_ostream &OS) const
static bool EMULAndEEWAreEqual(const OperandInfo &A, const OperandInfo &B)
OperandInfo(RISCVII::VLMUL EMUL, unsigned Log2EEW)
std::optional< std::pair< unsigned, bool > > EMUL
enum OperandInfo::State S
Description of the encoding of one expression Op.