LLVM 24.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandCCOpToCMov(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI);
51 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI, unsigned Opcode);
53 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI);
57 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61 bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MBBI);
63 bool expandPseudoClearFPR64(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator MBBI);
65#ifndef NDEBUG
66 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
67 unsigned Size = 0;
68 for (auto &MBB : MF)
69 for (auto &MI : MBB)
70 Size += TII->getInstSizeInBytes(MI);
71 return Size;
72 }
73#endif
74};
75
76char RISCVExpandPseudo::ID = 0;
77
78bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
79 STI = &MF.getSubtarget<RISCVSubtarget>();
80 TII = STI->getInstrInfo();
81
82#ifndef NDEBUG
83 const unsigned OldSize = getInstSizeInBytes(MF);
84#endif
85
86 bool Modified = false;
87 for (auto &MBB : MF)
88 Modified |= expandMBB(MBB);
89
90#ifndef NDEBUG
91 const unsigned NewSize = getInstSizeInBytes(MF);
92 assert(OldSize >= NewSize);
93#endif
94 return Modified;
95}
96
97bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
98 bool Modified = false;
99
100 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
101 while (MBBI != E) {
102 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
103 Modified |= expandMI(MBB, MBBI, NMBBI);
104 MBBI = NMBBI;
105 }
106
107 return Modified;
108}
109
110bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MBBI,
112 MachineBasicBlock::iterator &NextMBBI) {
113 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
114 // expanded instructions for each pseudo is correct in the Size field of the
115 // tablegen definition for the pseudo.
116 switch (MBBI->getOpcode()) {
117 case RISCV::PseudoMV_FPR16INX:
118 return expandMV_FPR16INX(MBB, MBBI);
119 case RISCV::PseudoMV_FPR32INX:
120 return expandMV_FPR32INX(MBB, MBBI);
121 case RISCV::PseudoRV32ZdinxSD:
122 return expandRV32ZdinxStore(MBB, MBBI);
123 case RISCV::PseudoRV32ZdinxLD:
124 return expandRV32ZdinxLoad(MBB, MBBI);
125 case RISCV::PseudoCCMOVGPRNoX0:
126 case RISCV::PseudoCCMOVGPR:
127 case RISCV::PseudoCCADD:
128 case RISCV::PseudoCCSUB:
129 case RISCV::PseudoCCAND:
130 case RISCV::PseudoCCOR:
131 case RISCV::PseudoCCXOR:
132 case RISCV::PseudoCCMAX:
133 case RISCV::PseudoCCMAXU:
134 case RISCV::PseudoCCMIN:
135 case RISCV::PseudoCCMINU:
136 case RISCV::PseudoCCMUL:
137 case RISCV::PseudoCCLUI:
138 case RISCV::PseudoCCQC_E_LB:
139 case RISCV::PseudoCCQC_E_LH:
140 case RISCV::PseudoCCQC_E_LW:
141 case RISCV::PseudoCCQC_E_LHU:
142 case RISCV::PseudoCCQC_E_LBU:
143 case RISCV::PseudoCCLB:
144 case RISCV::PseudoCCLH:
145 case RISCV::PseudoCCLW:
146 case RISCV::PseudoCCLHU:
147 case RISCV::PseudoCCLBU:
148 case RISCV::PseudoCCLWU:
149 case RISCV::PseudoCCLD:
150 case RISCV::PseudoCCQC_LI:
151 case RISCV::PseudoCCQC_E_LI:
152 case RISCV::PseudoCCADDW:
153 case RISCV::PseudoCCSUBW:
154 case RISCV::PseudoCCSLL:
155 case RISCV::PseudoCCSRL:
156 case RISCV::PseudoCCSRA:
157 case RISCV::PseudoCCADDI:
158 case RISCV::PseudoCCSLLI:
159 case RISCV::PseudoCCSRLI:
160 case RISCV::PseudoCCSRAI:
161 case RISCV::PseudoCCANDI:
162 case RISCV::PseudoCCORI:
163 case RISCV::PseudoCCXORI:
164 case RISCV::PseudoCCSLLW:
165 case RISCV::PseudoCCSRLW:
166 case RISCV::PseudoCCSRAW:
167 case RISCV::PseudoCCADDIW:
168 case RISCV::PseudoCCSLLIW:
169 case RISCV::PseudoCCSRLIW:
170 case RISCV::PseudoCCSRAIW:
171 case RISCV::PseudoCCANDN:
172 case RISCV::PseudoCCORN:
173 case RISCV::PseudoCCXNOR:
174 case RISCV::PseudoCCNDS_BFOS:
175 case RISCV::PseudoCCNDS_BFOZ:
176 return expandCCOp(MBB, MBBI, NextMBBI);
177 case RISCV::PseudoVMCLR_M_B1:
178 case RISCV::PseudoVMCLR_M_B2:
179 case RISCV::PseudoVMCLR_M_B4:
180 case RISCV::PseudoVMCLR_M_B8:
181 case RISCV::PseudoVMCLR_M_B16:
182 case RISCV::PseudoVMCLR_M_B32:
183 case RISCV::PseudoVMCLR_M_B64:
184 // vmclr.m vd => vmxor.mm vd, vd, vd
185 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
186 case RISCV::PseudoVMSET_M_B1:
187 case RISCV::PseudoVMSET_M_B2:
188 case RISCV::PseudoVMSET_M_B4:
189 case RISCV::PseudoVMSET_M_B8:
190 case RISCV::PseudoVMSET_M_B16:
191 case RISCV::PseudoVMSET_M_B32:
192 case RISCV::PseudoVMSET_M_B64:
193 // vmset.m vd => vmxnor.mm vd, vd, vd
194 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
195 case RISCV::PseudoReadVLENBViaVSETVLIX0:
196 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
197 case RISCV::PseudoClearFPR64:
198 return expandPseudoClearFPR64(MBB, MBBI);
199 }
200
201 return false;
202}
203
204bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
205 MachineBasicBlock::iterator MBBI,
206 MachineBasicBlock::iterator &NextMBBI) {
207 // First try expanding to a Conditional Move rather than a branch+mv
208 if (expandCCOpToCMov(MBB, MBBI))
209 return true;
210
211 MachineFunction *MF = MBB.getParent();
212 MachineInstr &MI = *MBBI;
213 DebugLoc DL = MI.getDebugLoc();
214
215 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
216 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
217
218 MF->insert(++MBB.getIterator(), TrueBB);
219 MF->insert(++TrueBB->getIterator(), MergeBB);
220
221 // We want to copy the "true" value only when the branch is executed.
222 // The SDNodeXform is responsible for the inversion.
223 unsigned BranchOpCode =
224 MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
225
226 // Insert branch instruction.
227 BuildMI(MBB, MBBI, DL, TII->get(BranchOpCode))
228 .add(MI.getOperand(MI.getNumExplicitOperands() - 2))
229 .add(MI.getOperand(MI.getNumExplicitOperands() - 1))
230 .addMBB(MergeBB);
231
232 Register DestReg = MI.getOperand(0).getReg();
233 assert(MI.getOperand(1).getReg() == DestReg);
234
235 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
236 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
237 // Add MV.
238 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
239 .add(MI.getOperand(2))
240 .addImm(0);
241 } else {
242 unsigned NewOpc;
243 // clang-format off
244 switch (MI.getOpcode()) {
245 default:
246 llvm_unreachable("Unexpected opcode!");
247 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
248 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
249 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
250 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
251 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
252 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
253 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
254 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
255 case RISCV::PseudoCCMAX: NewOpc = RISCV::MAX; break;
256 case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
257 case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
258 case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
259 case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
260 case RISCV::PseudoCCLUI: NewOpc = RISCV::LUI; break;
261 case RISCV::PseudoCCQC_E_LB: NewOpc = RISCV::QC_E_LB; break;
262 case RISCV::PseudoCCQC_E_LH: NewOpc = RISCV::QC_E_LH; break;
263 case RISCV::PseudoCCQC_E_LW: NewOpc = RISCV::QC_E_LW; break;
264 case RISCV::PseudoCCQC_E_LHU: NewOpc = RISCV::QC_E_LHU; break;
265 case RISCV::PseudoCCQC_E_LBU: NewOpc = RISCV::QC_E_LBU; break;
266 case RISCV::PseudoCCLB: NewOpc = RISCV::LB; break;
267 case RISCV::PseudoCCLH: NewOpc = RISCV::LH; break;
268 case RISCV::PseudoCCLW: NewOpc = RISCV::LW; break;
269 case RISCV::PseudoCCLHU: NewOpc = RISCV::LHU; break;
270 case RISCV::PseudoCCLBU: NewOpc = RISCV::LBU; break;
271 case RISCV::PseudoCCLWU: NewOpc = RISCV::LWU; break;
272 case RISCV::PseudoCCLD: NewOpc = RISCV::LD; break;
273 case RISCV::PseudoCCQC_LI: NewOpc = RISCV::QC_LI; break;
274 case RISCV::PseudoCCQC_E_LI: NewOpc = RISCV::QC_E_LI; break;
275 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
276 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
277 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
278 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
279 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
280 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
281 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
282 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
283 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
284 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
285 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
286 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
287 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
288 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
289 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
290 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
291 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
292 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
293 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
294 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
295 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
296 }
297 // clang-format on
298
299 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
300 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
301 .add(MI.getOperand(2))
302 .add(MI.getOperand(3))
303 .add(MI.getOperand(4));
304 } else if (NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI ||
305 NewOpc == RISCV::QC_E_LI) {
306 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg).add(MI.getOperand(2));
307 } else {
308 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
309 .add(MI.getOperand(2))
310 .add(MI.getOperand(3));
311 }
312 }
313
314 TrueBB->addSuccessor(MergeBB);
315
316 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
317 MergeBB->transferSuccessors(&MBB);
318
319 MBB.addSuccessor(TrueBB);
320 MBB.addSuccessor(MergeBB);
321
322 NextMBBI = MBB.end();
323 MI.eraseFromParent();
324
325 // Make sure live-ins are correctly attached to this new basic block.
326 LivePhysRegs LiveRegs;
327 computeAndAddLiveIns(LiveRegs, *TrueBB);
328 computeAndAddLiveIns(LiveRegs, *MergeBB);
329
330 return true;
331}
332
333bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
334 MachineBasicBlock::iterator MBBI) {
335 MachineInstr &MI = *MBBI;
336 DebugLoc DL = MI.getDebugLoc();
337
338 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
339 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
340 return false;
341
342 if (!STI->hasVendorXqcicm())
343 return false;
344
345 MachineOperand &LHS = MI.getOperand(MI.getNumExplicitOperands() - 2);
346 MachineOperand &RHS = MI.getOperand(MI.getNumExplicitOperands() - 1);
347
348 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
349 if (LHS.getReg() == RISCV::X0 || MI.getOperand(1).getReg() == RISCV::X0 ||
350 MI.getOperand(2).getReg() == RISCV::X0)
351 return false;
352
353 // Use branch opcode to select appropriate Xqcicm instruction
354 unsigned BCC = MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
355 std::optional<unsigned> CMovRegOpcode;
356 bool IsSigned = true;
357 unsigned CMovImmOpcode;
358 switch (BCC) {
359 default:
360 return false; // Unhandled branch opcodes
361 case RISCV::BNE:
362 CMovRegOpcode = RISCV::QC_MVEQ;
363 CMovImmOpcode = RISCV::QC_MVEQI;
364 break;
365 case RISCV::BEQ:
366 CMovRegOpcode = RISCV::QC_MVNE;
367 CMovImmOpcode = RISCV::QC_MVNEI;
368 break;
369 case RISCV::BGE:
370 CMovRegOpcode = RISCV::QC_MVLT;
371 CMovImmOpcode = RISCV::QC_MVLTI;
372 break;
373 case RISCV::BLT:
374 CMovRegOpcode = RISCV::QC_MVGE;
375 CMovImmOpcode = RISCV::QC_MVGEI;
376 break;
377 case RISCV::BGEU:
378 CMovRegOpcode = RISCV::QC_MVLTU;
379 CMovImmOpcode = RISCV::QC_MVLTUI;
380 break;
381 case RISCV::BLTU:
382 CMovRegOpcode = RISCV::QC_MVGEU;
383 CMovImmOpcode = RISCV::QC_MVGEUI;
384 break;
385 case RISCV::QC_BEQI:
386 CMovImmOpcode = RISCV::QC_MVNEI;
387 break;
388 case RISCV::QC_BNEI:
389 CMovImmOpcode = RISCV::QC_MVEQI;
390 break;
391 case RISCV::QC_BLTI:
392 CMovImmOpcode = RISCV::QC_MVGEI;
393 break;
394 case RISCV::QC_BGEI:
395 CMovImmOpcode = RISCV::QC_MVLTI;
396 break;
397 case RISCV::QC_BLTUI:
398 CMovImmOpcode = RISCV::QC_MVGEUI;
399 IsSigned = false;
400 break;
401 case RISCV::QC_BGEUI:
402 CMovImmOpcode = RISCV::QC_MVLTUI;
403 IsSigned = false;
404 break;
405 }
406
407 if (RHS.isImm()) {
408 if ((!isInt<5>(RHS.getImm()) || !IsSigned) &&
409 (!isUInt<5>(RHS.getImm()) || IsSigned))
410 return false;
411
412 // $dst = PseudoCCMOVGPR $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
413 // $dst = PseudoCCMOVGPRNoX0 $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
414 // =>
415 // $dst = QC_MVccI $falsev (=$dst), $lhs, $rhs_imm, $truev
416 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
417 .addDef(MI.getOperand(0).getReg())
418 .addReg(MI.getOperand(1).getReg())
419 .addReg(LHS.getReg())
420 .add(RHS)
421 .addReg(MI.getOperand(2).getReg());
422
423 MI.eraseFromParent();
424 return true;
425 }
426
427 if (RHS.getReg() == RISCV::X0) {
428 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, X0
429 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, X0
430 // =>
431 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
432 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
433 .addDef(MI.getOperand(0).getReg())
434 .addReg(MI.getOperand(1).getReg())
435 .addReg(LHS.getReg())
436 .addImm(0)
437 .addReg(MI.getOperand(2).getReg());
438
439 MI.eraseFromParent();
440 return true;
441 }
442
443 if (!CMovRegOpcode)
444 return false;
445
446 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, $rhs
447 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, $rhs
448 // =>
449 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
450 BuildMI(MBB, MBBI, DL, TII->get(*CMovRegOpcode))
451 .addDef(MI.getOperand(0).getReg())
452 .addReg(MI.getOperand(1).getReg())
453 .addReg(LHS.getReg())
454 .addReg(RHS.getReg())
455 .addReg(MI.getOperand(2).getReg());
456 MI.eraseFromParent();
457 return true;
458}
459
460bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MBBI,
462 unsigned Opcode) {
463 DebugLoc DL = MBBI->getDebugLoc();
464 Register DstReg = MBBI->getOperand(0).getReg();
465 const MCInstrDesc &Desc = TII->get(Opcode);
466 BuildMI(MBB, MBBI, DL, Desc, DstReg)
467 .addReg(DstReg, RegState::Undef)
468 .addReg(DstReg, RegState::Undef);
469 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
470 return true;
471}
472
473bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
474 MachineBasicBlock::iterator MBBI) {
475 DebugLoc DL = MBBI->getDebugLoc();
476 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
477 Register DstReg = TRI->getMatchingSuperReg(
478 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
479 Register SrcReg = TRI->getMatchingSuperReg(
480 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
481
482 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
483 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
484 .addImm(0);
485
486 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
487 return true;
488}
489
490bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
491 MachineBasicBlock::iterator MBBI) {
492 DebugLoc DL = MBBI->getDebugLoc();
493 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
494 Register DstReg = TRI->getMatchingSuperReg(
495 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
496 Register SrcReg = TRI->getMatchingSuperReg(
497 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
498
499 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
500 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
501 .addImm(0);
502
503 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
504 return true;
505}
506
507// This function expands the PseudoRV32ZdinxSD for storing a double-precision
508// floating-point value into memory by generating an equivalent instruction
509// sequence for RV32.
510bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
511 MachineBasicBlock::iterator MBBI) {
512 DebugLoc DL = MBBI->getDebugLoc();
513 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
514 Register Lo =
515 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
516 Register Hi =
517 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
518 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
519 Hi = RISCV::X0;
520
521 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
522 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
523 .addReg(MBBI->getOperand(1).getReg())
524 .add(MBBI->getOperand(2));
525
526 MachineInstrBuilder MIBHi;
527 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
528 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
529 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
530 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
531 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
532 .add(MBBI->getOperand(1))
533 .add(MBBI->getOperand(2));
534 } else {
535 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
536 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
537 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
538 .add(MBBI->getOperand(1))
539 .addImm(MBBI->getOperand(2).getImm() + 4);
540 }
541
542 MachineFunction *MF = MBB.getParent();
543 SmallVector<MachineMemOperand *> NewLoMMOs;
544 SmallVector<MachineMemOperand *> NewHiMMOs;
545 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
546 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
547 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
548 }
549 MIBLo.setMemRefs(NewLoMMOs);
550 MIBHi.setMemRefs(NewHiMMOs);
551
552 MBBI->eraseFromParent();
553 return true;
554}
555
556// This function expands PseudoRV32ZdinxLoad for loading a double-precision
557// floating-point value from memory into an equivalent instruction sequence for
558// RV32.
559bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
560 MachineBasicBlock::iterator MBBI) {
561 DebugLoc DL = MBBI->getDebugLoc();
562 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
563 Register Lo =
564 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
565 Register Hi =
566 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
567 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
568
569 MachineInstrBuilder MIBLo, MIBHi;
570
571 // If the register of operand 1 is equal to the Lo register, then swap the
572 // order of loading the Lo and Hi statements.
573 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
574 // Order: Lo, Hi
575 if (!IsOp1EqualToLo) {
576 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
577 .addReg(MBBI->getOperand(1).getReg())
578 .add(MBBI->getOperand(2));
579 }
580
581 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
582 auto Offset = MBBI->getOperand(2).getOffset();
583 assert(Offset % 8 == 0);
584 MBBI->getOperand(2).setOffset(Offset + 4);
585 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
586 .addReg(MBBI->getOperand(1).getReg())
587 .add(MBBI->getOperand(2));
588 MBBI->getOperand(2).setOffset(Offset);
589 } else {
590 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
591 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
592 .addReg(MBBI->getOperand(1).getReg())
593 .addImm(MBBI->getOperand(2).getImm() + 4);
594 }
595
596 // Order: Hi, Lo
597 if (IsOp1EqualToLo) {
598 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
599 .addReg(MBBI->getOperand(1).getReg())
600 .add(MBBI->getOperand(2));
601 }
602
603 MachineFunction *MF = MBB.getParent();
604 SmallVector<MachineMemOperand *> NewLoMMOs;
605 SmallVector<MachineMemOperand *> NewHiMMOs;
606 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
607 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
608 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
609 }
610 MIBLo.setMemRefs(NewLoMMOs);
611 MIBHi.setMemRefs(NewHiMMOs);
612
613 MBBI->eraseFromParent();
614 return true;
615}
616
617bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
618 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
619 DebugLoc DL = MBBI->getDebugLoc();
620 Register Dst = MBBI->getOperand(0).getReg();
621 unsigned Mul = MBBI->getOperand(1).getImm();
622 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
623 unsigned VTypeImm = RISCVVType::encodeVTYPE(
624 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
625
626 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
627 .addReg(Dst, RegState::Define)
628 .addReg(RISCV::X0, RegState::Kill)
629 .addImm(VTypeImm);
630
631 MBBI->eraseFromParent();
632 return true;
633}
634
635bool RISCVExpandPseudo::expandPseudoClearFPR64(
636 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
637 const DebugLoc &DL = MBBI->getDebugLoc();
638 Register Dst = MBBI->getOperand(0).getReg();
639
640 if (STI->is64Bit()) {
641 BuildMI(MBB, MBBI, DL, TII->get(RISCV::FMV_D_X), Dst).addReg(RISCV::X0);
642 } else {
643 BuildMI(MBB, MBBI, DL, TII->get(RISCV::FCVT_D_W), Dst)
644 .addReg(RISCV::X0)
645 .addImm(RISCVFPRndMode::RNE);
646 }
647
648 MBBI->eraseFromParent();
649 return true;
650}
651
652class RISCVPreRAExpandPseudo : public MachineFunctionPass {
653public:
654 const RISCVSubtarget *STI;
655 const RISCVInstrInfo *TII;
656 static char ID;
657
658 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
659
660 bool runOnMachineFunction(MachineFunction &MF) override;
661
662 void getAnalysisUsage(AnalysisUsage &AU) const override {
663 AU.setPreservesCFG();
664 MachineFunctionPass::getAnalysisUsage(AU);
665 }
666 StringRef getPassName() const override {
667 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
668 }
669
670private:
671 bool expandMBB(MachineBasicBlock &MBB);
672 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
673 MachineBasicBlock::iterator &NextMBBI);
674 bool expandAuipcInstPair(MachineBasicBlock &MBB,
675 MachineBasicBlock::iterator MBBI,
676 MachineBasicBlock::iterator &NextMBBI,
677 unsigned FlagsHi, unsigned SecondOpcode);
678 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
679 MachineBasicBlock::iterator MBBI,
680 MachineBasicBlock::iterator &NextMBBI);
681 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
682 MachineBasicBlock::iterator MBBI,
683 MachineBasicBlock::iterator &NextMBBI);
684 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
685 MachineBasicBlock::iterator MBBI,
686 MachineBasicBlock::iterator &NextMBBI);
687 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
688 MachineBasicBlock::iterator MBBI,
689 MachineBasicBlock::iterator &NextMBBI);
690 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
691 MachineBasicBlock::iterator MBBI,
692 MachineBasicBlock::iterator &NextMBBI);
693
694#ifndef NDEBUG
695 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
696 unsigned Size = 0;
697 for (auto &MBB : MF)
698 for (auto &MI : MBB)
699 Size += TII->getInstSizeInBytes(MI);
700 return Size;
701 }
702#endif
703};
704
705char RISCVPreRAExpandPseudo::ID = 0;
706
707bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
708 STI = &MF.getSubtarget<RISCVSubtarget>();
709 TII = STI->getInstrInfo();
710
711#ifndef NDEBUG
712 const unsigned OldSize = getInstSizeInBytes(MF);
713#endif
714
715 bool Modified = false;
716 for (auto &MBB : MF)
717 Modified |= expandMBB(MBB);
718
719#ifndef NDEBUG
720 const unsigned NewSize = getInstSizeInBytes(MF);
721 assert(OldSize >= NewSize);
722#endif
723 return Modified;
724}
725
726bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
727 bool Modified = false;
728
729 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
730 while (MBBI != E) {
731 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
732 Modified |= expandMI(MBB, MBBI, NMBBI);
733 MBBI = NMBBI;
734 }
735
736 return Modified;
737}
738
739bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
740 MachineBasicBlock::iterator MBBI,
741 MachineBasicBlock::iterator &NextMBBI) {
742
743 switch (MBBI->getOpcode()) {
744 case RISCV::PseudoLLA:
745 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
746 case RISCV::PseudoLGA:
747 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
748 case RISCV::PseudoLA_TLS_IE:
749 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
750 case RISCV::PseudoLA_TLS_GD:
751 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
752 case RISCV::PseudoLA_TLSDESC:
753 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
754 }
755 return false;
756}
757
758bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
759 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
760 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
761 unsigned SecondOpcode) {
762 MachineFunction *MF = MBB.getParent();
763 MachineInstr &MI = *MBBI;
764 DebugLoc DL = MI.getDebugLoc();
765
766 Register DestReg = MI.getOperand(0).getReg();
767 Register ScratchReg =
768 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
769
770 MachineOperand &Symbol = MI.getOperand(1);
771 Symbol.setTargetFlags(FlagsHi);
772 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
773
774 MachineInstr *MIAUIPC =
775 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
776 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
777
778 MachineInstr *SecondMI =
779 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
780 .addReg(ScratchReg)
781 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
782
783 if (MI.hasOneMemOperand())
784 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
785
786 MI.eraseFromParent();
787 return true;
788}
789
790bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
791 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
792 MachineBasicBlock::iterator &NextMBBI) {
793 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
794 RISCV::ADDI);
795}
796
797bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
798 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
799 MachineBasicBlock::iterator &NextMBBI) {
800 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
801 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
802 SecondOpcode);
803}
804
805bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
806 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
807 MachineBasicBlock::iterator &NextMBBI) {
808 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
809 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
810 SecondOpcode);
811}
812
813bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
814 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
815 MachineBasicBlock::iterator &NextMBBI) {
816 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
817 RISCV::ADDI);
818}
819
820bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
821 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
822 MachineBasicBlock::iterator &NextMBBI) {
823 MachineFunction *MF = MBB.getParent();
824 MachineInstr &MI = *MBBI;
825 DebugLoc DL = MI.getDebugLoc();
826
827 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
828 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
829
830 Register FinalReg = MI.getOperand(0).getReg();
831 Register DestReg =
832 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
833 Register ScratchReg =
834 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
835
836 MachineOperand &Symbol = MI.getOperand(1);
837 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
838 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
839
840 MachineInstr *MIAUIPC =
841 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
842 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
843
844 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
845 .addReg(ScratchReg)
846 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
847
848 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
849 .addReg(ScratchReg)
850 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
851
852 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
853 .addReg(DestReg)
854 .addImm(0)
855 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
856
857 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
858 .addReg(RISCV::X10)
859 .addReg(RISCV::X4);
860
861 MI.eraseFromParent();
862 return true;
863}
864
865} // end of anonymous namespace
866
867INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
868 RISCV_EXPAND_PSEUDO_NAME, false, false)
869
870INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
871 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
872
873namespace llvm {
874
875FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
876FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
877
878} // end of namespace llvm
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2132
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:26
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition SystemZLongBranch.cpp:211
RHS
Value * RHS
Definition X86PartialReduction.cpp:81
LHS
Value * LHS
Definition X86PartialReduction.cpp:80
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:75
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:275
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:126
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
LLVM_ABI MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition MCContext.cpp:400
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:199
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:947
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:825
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1158
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:343
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:136
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:789
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:581
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition MachineFunction.h:736
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:799
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:544
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1027
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:310
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition MachineInstrBuilder.h:373
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:248
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:218
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineInstr::setPreInstrSymbol
LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition MachineInstr.cpp:476
llvm::MachineInstr::addMemOperand
LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition MachineInstr.cpp:381
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:154
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition RISCVSubtarget.h:148
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition RISCVSubtarget.h:147
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:423
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1236
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:72
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
INITIALIZE_PASS
TargetPassConfig.
Definition TargetPassConfig.cpp:394
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:186
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:366
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:578
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:166
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:65
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:57
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:26
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190
llvm::computeAndAddLiveIns
LLVM_ABI void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:875
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:876
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