LLVM 24.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains one of the four passes that expand pseudo instructions
10// into target instructions. This pass is run very late, but before atomic
11// instructions are expanded.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVExpandPseudoBase.h"
17#include "RISCVInstrInfo.h"
18#include "RISCVSubtarget.h"
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22
23using namespace llvm;
24
25#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
26
27namespace {
28
29class RISCVExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
30 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
31 MachineBasicBlock::iterator &NextMBBI) const override;
32
33 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
34 MachineBasicBlock::iterator &NextMBBI) const;
35
36 bool expandCCOpToCMov(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator MBBI) const;
38
39 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MBBI,
41 unsigned Opcode) const;
42
43 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MBBI) const;
45
46 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MBBI) const;
48
49 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI) const;
51
52 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI) const;
54
55 bool
56 expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator MBBI) const;
58
59 bool expandPseudoClearFPR64(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI) const;
61};
62
63class RISCVExpandPseudoLegacy : public MachineFunctionPass {
64public:
65 static char ID;
66
67 RISCVExpandPseudoLegacy() : MachineFunctionPass(ID) {}
68
69 bool runOnMachineFunction(MachineFunction &MF) override {
70 return RISCVExpandPseudoImpl().run(MF);
71 }
72
73 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
74};
75
76} // anonymous namespace
77
78bool RISCVExpandPseudoImpl::expandMI(
79 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
80 MachineBasicBlock::iterator &NextMBBI) const {
81 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
82 // expanded instructions for each pseudo is correct in the Size field of the
83 // tablegen definition for the pseudo.
84 switch (MBBI->getOpcode()) {
85 case RISCV::PseudoMV_FPR16INX:
86 return expandMV_FPR16INX(MBB, MBBI);
87 case RISCV::PseudoMV_FPR32INX:
88 return expandMV_FPR32INX(MBB, MBBI);
89 case RISCV::PseudoRV32ZdinxSD:
90 return expandRV32ZdinxStore(MBB, MBBI);
91 case RISCV::PseudoRV32ZdinxLD:
92 return expandRV32ZdinxLoad(MBB, MBBI);
93 case RISCV::PseudoCCMOVGPRNoX0:
94 case RISCV::PseudoCCMOVGPR:
95 case RISCV::PseudoCCADD:
96 case RISCV::PseudoCCSUB:
97 case RISCV::PseudoCCAND:
98 case RISCV::PseudoCCOR:
99 case RISCV::PseudoCCXOR:
100 case RISCV::PseudoCCMAX:
101 case RISCV::PseudoCCMAXU:
102 case RISCV::PseudoCCMIN:
103 case RISCV::PseudoCCMINU:
104 case RISCV::PseudoCCMUL:
105 case RISCV::PseudoCCLUI:
106 case RISCV::PseudoCCQC_E_LB:
107 case RISCV::PseudoCCQC_E_LH:
108 case RISCV::PseudoCCQC_E_LW:
109 case RISCV::PseudoCCQC_E_LHU:
110 case RISCV::PseudoCCQC_E_LBU:
111 case RISCV::PseudoCCLB:
112 case RISCV::PseudoCCLH:
113 case RISCV::PseudoCCLW:
114 case RISCV::PseudoCCLHU:
115 case RISCV::PseudoCCLBU:
116 case RISCV::PseudoCCLWU:
117 case RISCV::PseudoCCLD:
118 case RISCV::PseudoCCQC_LI:
119 case RISCV::PseudoCCQC_E_LI:
120 case RISCV::PseudoCCADDW:
121 case RISCV::PseudoCCSUBW:
122 case RISCV::PseudoCCSLL:
123 case RISCV::PseudoCCSRL:
124 case RISCV::PseudoCCSRA:
125 case RISCV::PseudoCCADDI:
126 case RISCV::PseudoCCSLLI:
127 case RISCV::PseudoCCSRLI:
128 case RISCV::PseudoCCSRAI:
129 case RISCV::PseudoCCANDI:
130 case RISCV::PseudoCCORI:
131 case RISCV::PseudoCCXORI:
132 case RISCV::PseudoCCSLLW:
133 case RISCV::PseudoCCSRLW:
134 case RISCV::PseudoCCSRAW:
135 case RISCV::PseudoCCADDIW:
136 case RISCV::PseudoCCSLLIW:
137 case RISCV::PseudoCCSRLIW:
138 case RISCV::PseudoCCSRAIW:
139 case RISCV::PseudoCCANDN:
140 case RISCV::PseudoCCORN:
141 case RISCV::PseudoCCXNOR:
142 case RISCV::PseudoCCNDS_BFOS:
143 case RISCV::PseudoCCNDS_BFOZ:
144 return expandCCOp(MBB, MBBI, NextMBBI);
145 case RISCV::PseudoVMCLR_M_B1:
146 case RISCV::PseudoVMCLR_M_B2:
147 case RISCV::PseudoVMCLR_M_B4:
148 case RISCV::PseudoVMCLR_M_B8:
149 case RISCV::PseudoVMCLR_M_B16:
150 case RISCV::PseudoVMCLR_M_B32:
151 case RISCV::PseudoVMCLR_M_B64:
152 // vmclr.m vd => vmxor.mm vd, vd, vd
153 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
154 case RISCV::PseudoVMSET_M_B1:
155 case RISCV::PseudoVMSET_M_B2:
156 case RISCV::PseudoVMSET_M_B4:
157 case RISCV::PseudoVMSET_M_B8:
158 case RISCV::PseudoVMSET_M_B16:
159 case RISCV::PseudoVMSET_M_B32:
160 case RISCV::PseudoVMSET_M_B64:
161 // vmset.m vd => vmxnor.mm vd, vd, vd
162 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
163 case RISCV::PseudoReadVLENBViaVSETVLIX0:
164 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
165 case RISCV::PseudoClearFPR64:
166 return expandPseudoClearFPR64(MBB, MBBI);
167 }
168
169 return false;
170}
171
172bool RISCVExpandPseudoImpl::expandCCOp(
173 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
174 MachineBasicBlock::iterator &NextMBBI) const {
175 // First try expanding to a Conditional Move rather than a branch+mv
176 if (expandCCOpToCMov(MBB, MBBI))
177 return true;
178
179 MachineFunction *MF = MBB.getParent();
180 MachineInstr &MI = *MBBI;
181 DebugLoc DL = MI.getDebugLoc();
182
183 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
184 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
185
186 MF->insert(++MBB.getIterator(), TrueBB);
187 MF->insert(++TrueBB->getIterator(), MergeBB);
188
189 // We want to copy the "true" value only when the branch is executed.
190 // The SDNodeXform is responsible for the inversion.
191 unsigned BranchOpCode =
192 MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
193
194 // Insert branch instruction.
195 BuildMI(MBB, MBBI, DL, TII->get(BranchOpCode))
196 .add(MI.getOperand(MI.getNumExplicitOperands() - 2))
197 .add(MI.getOperand(MI.getNumExplicitOperands() - 1))
198 .addMBB(MergeBB);
199
200 Register DestReg = MI.getOperand(0).getReg();
201 assert(MI.getOperand(1).getReg() == DestReg);
202
203 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
204 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
205 // Add MV.
206 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
207 .add(MI.getOperand(2))
208 .addImm(0);
209 } else {
210 unsigned NewOpc;
211 // clang-format off
212 switch (MI.getOpcode()) {
213 default:
214 llvm_unreachable("Unexpected opcode!");
215 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
216 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
217 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
218 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
219 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
220 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
221 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
222 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
223 case RISCV::PseudoCCMAX: NewOpc = RISCV::MAX; break;
224 case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
225 case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
226 case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
227 case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
228 case RISCV::PseudoCCLUI: NewOpc = RISCV::LUI; break;
229 case RISCV::PseudoCCQC_E_LB: NewOpc = RISCV::QC_E_LB; break;
230 case RISCV::PseudoCCQC_E_LH: NewOpc = RISCV::QC_E_LH; break;
231 case RISCV::PseudoCCQC_E_LW: NewOpc = RISCV::QC_E_LW; break;
232 case RISCV::PseudoCCQC_E_LHU: NewOpc = RISCV::QC_E_LHU; break;
233 case RISCV::PseudoCCQC_E_LBU: NewOpc = RISCV::QC_E_LBU; break;
234 case RISCV::PseudoCCLB: NewOpc = RISCV::LB; break;
235 case RISCV::PseudoCCLH: NewOpc = RISCV::LH; break;
236 case RISCV::PseudoCCLW: NewOpc = RISCV::LW; break;
237 case RISCV::PseudoCCLHU: NewOpc = RISCV::LHU; break;
238 case RISCV::PseudoCCLBU: NewOpc = RISCV::LBU; break;
239 case RISCV::PseudoCCLWU: NewOpc = RISCV::LWU; break;
240 case RISCV::PseudoCCLD: NewOpc = RISCV::LD; break;
241 case RISCV::PseudoCCQC_LI: NewOpc = RISCV::QC_LI; break;
242 case RISCV::PseudoCCQC_E_LI: NewOpc = RISCV::QC_E_LI; break;
243 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
244 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
245 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
246 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
247 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
248 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
249 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
250 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
251 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
252 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
253 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
254 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
255 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
256 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
257 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
258 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
259 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
260 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
261 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
262 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
263 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
264 }
265 // clang-format on
266
267 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
268 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
269 .add(MI.getOperand(2))
270 .add(MI.getOperand(3))
271 .add(MI.getOperand(4));
272 } else if (NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI ||
273 NewOpc == RISCV::QC_E_LI) {
274 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg).add(MI.getOperand(2));
275 } else {
276 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
277 .add(MI.getOperand(2))
278 .add(MI.getOperand(3));
279 }
280 }
281
282 TrueBB->addSuccessor(MergeBB);
283
284 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
285 MergeBB->transferSuccessors(&MBB);
286
287 MBB.addSuccessor(TrueBB);
288 MBB.addSuccessor(MergeBB);
289
290 NextMBBI = MBB.end();
291 MI.eraseFromParent();
292
293 // Make sure live-ins are correctly attached to this new basic block.
294 LivePhysRegs LiveRegs;
295 computeAndAddLiveIns(LiveRegs, *TrueBB);
296 computeAndAddLiveIns(LiveRegs, *MergeBB);
297
298 return true;
299}
300
301bool RISCVExpandPseudoImpl::expandCCOpToCMov(
302 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
303 MachineInstr &MI = *MBBI;
304 DebugLoc DL = MI.getDebugLoc();
305
306 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
307 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
308 return false;
309
310 if (!STI->hasVendorXqcicm())
311 return false;
312
313 MachineOperand &LHS = MI.getOperand(MI.getNumExplicitOperands() - 2);
314 MachineOperand &RHS = MI.getOperand(MI.getNumExplicitOperands() - 1);
315
316 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
317 if (LHS.getReg() == RISCV::X0 || MI.getOperand(1).getReg() == RISCV::X0 ||
318 MI.getOperand(2).getReg() == RISCV::X0)
319 return false;
320
321 // Use branch opcode to select appropriate Xqcicm instruction
322 unsigned BCC = MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
323 std::optional<unsigned> CMovRegOpcode;
324 bool IsSigned = true;
325 unsigned CMovImmOpcode;
326 switch (BCC) {
327 default:
328 return false; // Unhandled branch opcodes
329 case RISCV::BNE:
330 CMovRegOpcode = RISCV::QC_MVEQ;
331 CMovImmOpcode = RISCV::QC_MVEQI;
332 break;
333 case RISCV::BEQ:
334 CMovRegOpcode = RISCV::QC_MVNE;
335 CMovImmOpcode = RISCV::QC_MVNEI;
336 break;
337 case RISCV::BGE:
338 CMovRegOpcode = RISCV::QC_MVLT;
339 CMovImmOpcode = RISCV::QC_MVLTI;
340 break;
341 case RISCV::BLT:
342 CMovRegOpcode = RISCV::QC_MVGE;
343 CMovImmOpcode = RISCV::QC_MVGEI;
344 break;
345 case RISCV::BGEU:
346 CMovRegOpcode = RISCV::QC_MVLTU;
347 CMovImmOpcode = RISCV::QC_MVLTUI;
348 break;
349 case RISCV::BLTU:
350 CMovRegOpcode = RISCV::QC_MVGEU;
351 CMovImmOpcode = RISCV::QC_MVGEUI;
352 break;
353 case RISCV::QC_BEQI:
354 CMovImmOpcode = RISCV::QC_MVNEI;
355 break;
356 case RISCV::QC_BNEI:
357 CMovImmOpcode = RISCV::QC_MVEQI;
358 break;
359 case RISCV::QC_BLTI:
360 CMovImmOpcode = RISCV::QC_MVGEI;
361 break;
362 case RISCV::QC_BGEI:
363 CMovImmOpcode = RISCV::QC_MVLTI;
364 break;
365 case RISCV::QC_BLTUI:
366 CMovImmOpcode = RISCV::QC_MVGEUI;
367 IsSigned = false;
368 break;
369 case RISCV::QC_BGEUI:
370 CMovImmOpcode = RISCV::QC_MVLTUI;
371 IsSigned = false;
372 break;
373 }
374
375 if (RHS.isImm()) {
376 if ((!isInt<5>(RHS.getImm()) || !IsSigned) &&
377 (!isUInt<5>(RHS.getImm()) || IsSigned))
378 return false;
379
380 // $dst = PseudoCCMOVGPR $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
381 // $dst = PseudoCCMOVGPRNoX0 $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
382 // =>
383 // $dst = QC_MVccI $falsev (=$dst), $lhs, $rhs_imm, $truev
384 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
385 .addDef(MI.getOperand(0).getReg())
386 .addReg(MI.getOperand(1).getReg())
387 .addReg(LHS.getReg())
388 .add(RHS)
389 .addReg(MI.getOperand(2).getReg());
390
391 MI.eraseFromParent();
392 return true;
393 }
394
395 if (RHS.getReg() == RISCV::X0) {
396 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, X0
397 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, X0
398 // =>
399 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
400 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
401 .addDef(MI.getOperand(0).getReg())
402 .addReg(MI.getOperand(1).getReg())
403 .addReg(LHS.getReg())
404 .addImm(0)
405 .addReg(MI.getOperand(2).getReg());
406
407 MI.eraseFromParent();
408 return true;
409 }
410
411 if (!CMovRegOpcode)
412 return false;
413
414 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, $rhs
415 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, $rhs
416 // =>
417 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
418 BuildMI(MBB, MBBI, DL, TII->get(*CMovRegOpcode))
419 .addDef(MI.getOperand(0).getReg())
420 .addReg(MI.getOperand(1).getReg())
421 .addReg(LHS.getReg())
422 .addReg(RHS.getReg())
423 .addReg(MI.getOperand(2).getReg());
424 MI.eraseFromParent();
425 return true;
426}
427
428bool RISCVExpandPseudoImpl::expandVMSET_VMCLR(MachineBasicBlock &MBB,
429 MachineBasicBlock::iterator MBBI,
430 unsigned Opcode) const {
431 DebugLoc DL = MBBI->getDebugLoc();
432 Register DstReg = MBBI->getOperand(0).getReg();
433 const MCInstrDesc &Desc = TII->get(Opcode);
434 BuildMI(MBB, MBBI, DL, Desc, DstReg)
435 .addReg(DstReg, RegState::Undef)
436 .addReg(DstReg, RegState::Undef);
437 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
438 return true;
439}
440
441bool RISCVExpandPseudoImpl::expandMV_FPR16INX(
442 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
443 DebugLoc DL = MBBI->getDebugLoc();
444 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
445 Register DstReg = TRI->getMatchingSuperReg(
446 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
447 Register SrcReg = TRI->getMatchingSuperReg(
448 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
449
450 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
451 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
452 .addImm(0);
453
454 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
455 return true;
456}
457
458bool RISCVExpandPseudoImpl::expandMV_FPR32INX(
459 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
460 DebugLoc DL = MBBI->getDebugLoc();
461 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
462 Register DstReg = TRI->getMatchingSuperReg(
463 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
464 Register SrcReg = TRI->getMatchingSuperReg(
465 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
466
467 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
468 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
469 .addImm(0);
470
471 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
472 return true;
473}
474
475// This function expands the PseudoRV32ZdinxSD for storing a double-precision
476// floating-point value into memory by generating an equivalent instruction
477// sequence for RV32.
478bool RISCVExpandPseudoImpl::expandRV32ZdinxStore(
479 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
480 DebugLoc DL = MBBI->getDebugLoc();
481 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
482 Register Lo =
483 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
484 Register Hi =
485 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
486 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
487 Hi = RISCV::X0;
488
489 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
490 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
491 .addReg(MBBI->getOperand(1).getReg())
492 .add(MBBI->getOperand(2));
493
494 MachineInstrBuilder MIBHi;
495 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
496 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
497 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
498 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
499 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
500 .add(MBBI->getOperand(1))
501 .add(MBBI->getOperand(2));
502 } else {
503 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
504 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
505 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
506 .add(MBBI->getOperand(1))
507 .addImm(MBBI->getOperand(2).getImm() + 4);
508 }
509
510 MachineFunction *MF = MBB.getParent();
511 SmallVector<MachineMemOperand *> NewLoMMOs;
512 SmallVector<MachineMemOperand *> NewHiMMOs;
513 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
514 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
515 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
516 }
517 MIBLo.setMemRefs(NewLoMMOs);
518 MIBHi.setMemRefs(NewHiMMOs);
519
520 MBBI->eraseFromParent();
521 return true;
522}
523
524// This function expands PseudoRV32ZdinxLoad for loading a double-precision
525// floating-point value from memory into an equivalent instruction sequence for
526// RV32.
527bool RISCVExpandPseudoImpl::expandRV32ZdinxLoad(
528 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
529 DebugLoc DL = MBBI->getDebugLoc();
530 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
531 Register Lo =
532 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
533 Register Hi =
534 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
535 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
536
537 MachineInstrBuilder MIBLo, MIBHi;
538
539 // If the register of operand 1 is equal to the Lo register, then swap the
540 // order of loading the Lo and Hi statements.
541 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
542 // Order: Lo, Hi
543 if (!IsOp1EqualToLo) {
544 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
545 .addReg(MBBI->getOperand(1).getReg())
546 .add(MBBI->getOperand(2));
547 }
548
549 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
550 auto Offset = MBBI->getOperand(2).getOffset();
551 assert(Offset % 8 == 0);
552 MBBI->getOperand(2).setOffset(Offset + 4);
553 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
554 .addReg(MBBI->getOperand(1).getReg())
555 .add(MBBI->getOperand(2));
556 MBBI->getOperand(2).setOffset(Offset);
557 } else {
558 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
559 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
560 .addReg(MBBI->getOperand(1).getReg())
561 .addImm(MBBI->getOperand(2).getImm() + 4);
562 }
563
564 // Order: Hi, Lo
565 if (IsOp1EqualToLo) {
566 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
567 .addReg(MBBI->getOperand(1).getReg())
568 .add(MBBI->getOperand(2));
569 }
570
571 MachineFunction *MF = MBB.getParent();
572 SmallVector<MachineMemOperand *> NewLoMMOs;
573 SmallVector<MachineMemOperand *> NewHiMMOs;
574 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
575 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
576 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
577 }
578 MIBLo.setMemRefs(NewLoMMOs);
579 MIBHi.setMemRefs(NewHiMMOs);
580
581 MBBI->eraseFromParent();
582 return true;
583}
584
585bool RISCVExpandPseudoImpl::expandPseudoReadVLENBViaVSETVLIX0(
586 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
587 DebugLoc DL = MBBI->getDebugLoc();
588 Register Dst = MBBI->getOperand(0).getReg();
589 unsigned Mul = MBBI->getOperand(1).getImm();
590 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
591 unsigned VTypeImm = RISCVVType::encodeVTYPE(
592 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
593
594 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
595 .addReg(Dst, RegState::Define)
596 .addReg(RISCV::X0, RegState::Kill)
597 .addImm(VTypeImm);
598
599 MBBI->eraseFromParent();
600 return true;
601}
602
603bool RISCVExpandPseudoImpl::expandPseudoClearFPR64(
604 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
605 const DebugLoc &DL = MBBI->getDebugLoc();
606 Register Dst = MBBI->getOperand(0).getReg();
607
608 if (STI->is64Bit()) {
609 BuildMI(MBB, MBBI, DL, TII->get(RISCV::FMV_D_X), Dst).addReg(RISCV::X0);
610 } else {
611 BuildMI(MBB, MBBI, DL, TII->get(RISCV::FCVT_D_W), Dst)
612 .addReg(RISCV::X0)
613 .addImm(RISCVFPRndMode::RNE);
614 }
615
616 MBBI->eraseFromParent();
617 return true;
618}
619
620char RISCVExpandPseudoLegacy::ID = 0;
621
622INITIALIZE_PASS(RISCVExpandPseudoLegacy, "riscv-expand-pseudo",
623 RISCV_EXPAND_PSEUDO_NAME, false, false)
624
625FunctionPass *llvm::createRISCVExpandPseudoLegacyPass() {
626 return new RISCVExpandPseudoLegacy();
627}
628
629PreservedAnalyses
630RISCVExpandPseudoPass::run(MachineFunction &MF,
631 MachineFunctionAnalysisManager &MFAM) {
632 bool Changed = RISCVExpandPseudoImpl().run(MF);
633 if (!Changed)
634 return PreservedAnalyses::all();
635 return getMachineFunctionPassPreservedAnalyses();
636}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:865
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2131
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:25
RHS
Value * RHS
Definition X86PartialReduction.cpp:83
LHS
Value * LHS
Definition X86PartialReduction.cpp:82
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:77
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:950
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition MachineBasicBlock.h:255
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:828
llvm::MachineBasicBlock::eraseFromParent
LLVM_ABI void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition MachineBasicBlock.cpp:1527
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition MachineBasicBlock.h:325
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1162
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:343
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, LLT MemTy, Align BaseAlignment, const MMOMetadata &Metadata=MMOMetadata(), SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:580
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:544
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1027
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:310
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:248
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:218
llvm::PreservedAnalyses::all
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition Analysis.h:118
llvm::RISCVExpandPseudoPass::run
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Definition RISCVExpandPseudoInsts.cpp:630
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:423
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
Changed
Changed
Definition ObjCARCOpts.cpp:2366
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:186
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:366
llvm::dwarf_linker::DebugSectionKind::DebugLoc
@ DebugLoc
Definition DWARFLinkerBase.h:35
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:578
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:166
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::MachineFunctionAnalysisManager
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
Definition MachineFunctionAnalysisManager.h:24
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:26
llvm::getMachineFunctionPassPreservedAnalyses
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
Definition MachinePassManager.cpp:162
llvm::createRISCVExpandPseudoLegacyPass
FunctionPass * createRISCVExpandPseudoLegacyPass()
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190
llvm::SmallVector
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition SmallVector.h:1162
llvm::computeAndAddLiveIns
LLVM_ABI void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
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