LLVM 23.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandCCOpToCMov(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI);
51 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI, unsigned Opcode);
53 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI);
57 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61 bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MBBI);
63#ifndef NDEBUG
64 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
65 unsigned Size = 0;
66 for (auto &MBB : MF)
67 for (auto &MI : MBB)
68 Size += TII->getInstSizeInBytes(MI);
69 return Size;
70 }
71#endif
72};
73
74char RISCVExpandPseudo::ID = 0;
75
76bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
77 STI = &MF.getSubtarget<RISCVSubtarget>();
78 TII = STI->getInstrInfo();
79
80#ifndef NDEBUG
81 const unsigned OldSize = getInstSizeInBytes(MF);
82#endif
83
84 bool Modified = false;
85 for (auto &MBB : MF)
86 Modified |= expandMBB(MBB);
87
88#ifndef NDEBUG
89 const unsigned NewSize = getInstSizeInBytes(MF);
90 assert(OldSize >= NewSize);
91#endif
92 return Modified;
93}
94
95bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
96 bool Modified = false;
97
98 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
99 while (MBBI != E) {
100 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
101 Modified |= expandMI(MBB, MBBI, NMBBI);
102 MBBI = NMBBI;
103 }
104
105 return Modified;
106}
107
108bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MBBI,
110 MachineBasicBlock::iterator &NextMBBI) {
111 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
112 // expanded instructions for each pseudo is correct in the Size field of the
113 // tablegen definition for the pseudo.
114 switch (MBBI->getOpcode()) {
115 case RISCV::PseudoMV_FPR16INX:
116 return expandMV_FPR16INX(MBB, MBBI);
117 case RISCV::PseudoMV_FPR32INX:
118 return expandMV_FPR32INX(MBB, MBBI);
119 case RISCV::PseudoRV32ZdinxSD:
120 return expandRV32ZdinxStore(MBB, MBBI);
121 case RISCV::PseudoRV32ZdinxLD:
122 return expandRV32ZdinxLoad(MBB, MBBI);
123 case RISCV::PseudoCCMOVGPRNoX0:
124 case RISCV::PseudoCCMOVGPR:
125 case RISCV::PseudoCCADD:
126 case RISCV::PseudoCCSUB:
127 case RISCV::PseudoCCAND:
128 case RISCV::PseudoCCOR:
129 case RISCV::PseudoCCXOR:
130 case RISCV::PseudoCCMAX:
131 case RISCV::PseudoCCMAXU:
132 case RISCV::PseudoCCMIN:
133 case RISCV::PseudoCCMINU:
134 case RISCV::PseudoCCMUL:
135 case RISCV::PseudoCCLUI:
136 case RISCV::PseudoCCQC_E_LB:
137 case RISCV::PseudoCCQC_E_LH:
138 case RISCV::PseudoCCQC_E_LW:
139 case RISCV::PseudoCCQC_E_LHU:
140 case RISCV::PseudoCCQC_E_LBU:
141 case RISCV::PseudoCCLB:
142 case RISCV::PseudoCCLH:
143 case RISCV::PseudoCCLW:
144 case RISCV::PseudoCCLHU:
145 case RISCV::PseudoCCLBU:
146 case RISCV::PseudoCCLWU:
147 case RISCV::PseudoCCLD:
148 case RISCV::PseudoCCQC_LI:
149 case RISCV::PseudoCCQC_E_LI:
150 case RISCV::PseudoCCADDW:
151 case RISCV::PseudoCCSUBW:
152 case RISCV::PseudoCCSLL:
153 case RISCV::PseudoCCSRL:
154 case RISCV::PseudoCCSRA:
155 case RISCV::PseudoCCADDI:
156 case RISCV::PseudoCCSLLI:
157 case RISCV::PseudoCCSRLI:
158 case RISCV::PseudoCCSRAI:
159 case RISCV::PseudoCCANDI:
160 case RISCV::PseudoCCORI:
161 case RISCV::PseudoCCXORI:
162 case RISCV::PseudoCCSLLW:
163 case RISCV::PseudoCCSRLW:
164 case RISCV::PseudoCCSRAW:
165 case RISCV::PseudoCCADDIW:
166 case RISCV::PseudoCCSLLIW:
167 case RISCV::PseudoCCSRLIW:
168 case RISCV::PseudoCCSRAIW:
169 case RISCV::PseudoCCANDN:
170 case RISCV::PseudoCCORN:
171 case RISCV::PseudoCCXNOR:
172 case RISCV::PseudoCCNDS_BFOS:
173 case RISCV::PseudoCCNDS_BFOZ:
174 return expandCCOp(MBB, MBBI, NextMBBI);
175 case RISCV::PseudoVMCLR_M_B1:
176 case RISCV::PseudoVMCLR_M_B2:
177 case RISCV::PseudoVMCLR_M_B4:
178 case RISCV::PseudoVMCLR_M_B8:
179 case RISCV::PseudoVMCLR_M_B16:
180 case RISCV::PseudoVMCLR_M_B32:
181 case RISCV::PseudoVMCLR_M_B64:
182 // vmclr.m vd => vmxor.mm vd, vd, vd
183 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
184 case RISCV::PseudoVMSET_M_B1:
185 case RISCV::PseudoVMSET_M_B2:
186 case RISCV::PseudoVMSET_M_B4:
187 case RISCV::PseudoVMSET_M_B8:
188 case RISCV::PseudoVMSET_M_B16:
189 case RISCV::PseudoVMSET_M_B32:
190 case RISCV::PseudoVMSET_M_B64:
191 // vmset.m vd => vmxnor.mm vd, vd, vd
192 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
193 case RISCV::PseudoReadVLENBViaVSETVLIX0:
194 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
195 }
196
197 return false;
198}
199
200bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MBBI,
202 MachineBasicBlock::iterator &NextMBBI) {
203 // First try expanding to a Conditional Move rather than a branch+mv
204 if (expandCCOpToCMov(MBB, MBBI))
205 return true;
206
207 MachineFunction *MF = MBB.getParent();
208 MachineInstr &MI = *MBBI;
209 DebugLoc DL = MI.getDebugLoc();
210
211 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
212 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
213
214 MF->insert(++MBB.getIterator(), TrueBB);
215 MF->insert(++TrueBB->getIterator(), MergeBB);
216
217 // We want to copy the "true" value only when the branch is executed.
218 // The SDNodeXform is responsible for the inversion.
219 unsigned BranchOpCode =
220 MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
221
222 // Insert branch instruction.
223 BuildMI(MBB, MBBI, DL, TII->get(BranchOpCode))
224 .add(MI.getOperand(MI.getNumExplicitOperands() - 2))
225 .add(MI.getOperand(MI.getNumExplicitOperands() - 1))
226 .addMBB(MergeBB);
227
228 Register DestReg = MI.getOperand(0).getReg();
229 assert(MI.getOperand(1).getReg() == DestReg);
230
231 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
232 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
233 // Add MV.
234 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
235 .add(MI.getOperand(2))
236 .addImm(0);
237 } else {
238 unsigned NewOpc;
239 // clang-format off
240 switch (MI.getOpcode()) {
241 default:
242 llvm_unreachable("Unexpected opcode!");
243 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
244 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
245 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
246 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
247 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
248 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
249 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
250 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
251 case RISCV::PseudoCCMAX: NewOpc = RISCV::MAX; break;
252 case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
253 case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
254 case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
255 case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
256 case RISCV::PseudoCCLUI: NewOpc = RISCV::LUI; break;
257 case RISCV::PseudoCCQC_E_LB: NewOpc = RISCV::QC_E_LB; break;
258 case RISCV::PseudoCCQC_E_LH: NewOpc = RISCV::QC_E_LH; break;
259 case RISCV::PseudoCCQC_E_LW: NewOpc = RISCV::QC_E_LW; break;
260 case RISCV::PseudoCCQC_E_LHU: NewOpc = RISCV::QC_E_LHU; break;
261 case RISCV::PseudoCCQC_E_LBU: NewOpc = RISCV::QC_E_LBU; break;
262 case RISCV::PseudoCCLB: NewOpc = RISCV::LB; break;
263 case RISCV::PseudoCCLH: NewOpc = RISCV::LH; break;
264 case RISCV::PseudoCCLW: NewOpc = RISCV::LW; break;
265 case RISCV::PseudoCCLHU: NewOpc = RISCV::LHU; break;
266 case RISCV::PseudoCCLBU: NewOpc = RISCV::LBU; break;
267 case RISCV::PseudoCCLWU: NewOpc = RISCV::LWU; break;
268 case RISCV::PseudoCCLD: NewOpc = RISCV::LD; break;
269 case RISCV::PseudoCCQC_LI: NewOpc = RISCV::QC_LI; break;
270 case RISCV::PseudoCCQC_E_LI: NewOpc = RISCV::QC_E_LI; break;
271 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
272 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
273 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
274 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
275 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
276 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
277 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
278 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
279 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
280 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
281 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
282 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
283 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
284 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
285 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
286 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
287 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
288 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
289 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
290 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
291 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
292 }
293 // clang-format on
294
295 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
296 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
297 .add(MI.getOperand(2))
298 .add(MI.getOperand(3))
299 .add(MI.getOperand(4));
300 } else if (NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI ||
301 NewOpc == RISCV::QC_E_LI) {
302 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg).add(MI.getOperand(2));
303 } else {
304 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
305 .add(MI.getOperand(2))
306 .add(MI.getOperand(3));
307 }
308 }
309
310 TrueBB->addSuccessor(MergeBB);
311
312 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
313 MergeBB->transferSuccessors(&MBB);
314
315 MBB.addSuccessor(TrueBB);
316 MBB.addSuccessor(MergeBB);
317
318 NextMBBI = MBB.end();
319 MI.eraseFromParent();
320
321 // Make sure live-ins are correctly attached to this new basic block.
322 LivePhysRegs LiveRegs;
323 computeAndAddLiveIns(LiveRegs, *TrueBB);
324 computeAndAddLiveIns(LiveRegs, *MergeBB);
325
326 return true;
327}
328
329bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
330 MachineBasicBlock::iterator MBBI) {
331 MachineInstr &MI = *MBBI;
332 DebugLoc DL = MI.getDebugLoc();
333
334 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
335 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
336 return false;
337
338 if (!STI->hasVendorXqcicm())
339 return false;
340
341 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
342 if (MI.getOperand(MI.getNumExplicitOperands() - 2).getReg() == RISCV::X0 ||
343 MI.getOperand(1).getReg() == RISCV::X0 ||
344 MI.getOperand(2).getReg() == RISCV::X0)
345 return false;
346
347 // Use branch opcode to select appropriate Xqcicm instruction
348 unsigned BCC = MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
349 unsigned CMovOpcode, CMovIOpcode;
350 switch (BCC) {
351 default:
352 return false; // Unhandled branch opcodes
353 case RISCV::BNE:
354 CMovOpcode = RISCV::QC_MVEQ;
355 CMovIOpcode = RISCV::QC_MVEQI;
356 break;
357 case RISCV::BEQ:
358 CMovOpcode = RISCV::QC_MVNE;
359 CMovIOpcode = RISCV::QC_MVNEI;
360 break;
361 case RISCV::BGE:
362 CMovOpcode = RISCV::QC_MVLT;
363 CMovIOpcode = RISCV::QC_MVLTI;
364 break;
365 case RISCV::BLT:
366 CMovOpcode = RISCV::QC_MVGE;
367 CMovIOpcode = RISCV::QC_MVGEI;
368 break;
369 case RISCV::BGEU:
370 CMovOpcode = RISCV::QC_MVLTU;
371 CMovIOpcode = RISCV::QC_MVLTUI;
372 break;
373 case RISCV::BLTU:
374 CMovOpcode = RISCV::QC_MVGEU;
375 CMovIOpcode = RISCV::QC_MVGEUI;
376 break;
377 }
378
379 if (MI.getOperand(MI.getNumExplicitOperands() - 1).getReg() == RISCV::X0) {
380 // $dst = PseudoCCMOVGPR $lhs, X0, $cc, $falsev (=$dst), $truev
381 // $dst = PseudoCCMOVGPRNoX0 $lhs, X0, $cc, $falsev (=$dst), $truev
382 // =>
383 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
384 BuildMI(MBB, MBBI, DL, TII->get(CMovIOpcode))
385 .addDef(MI.getOperand(0).getReg())
386 .addReg(MI.getOperand(1).getReg())
387 .addReg(MI.getOperand(MI.getNumExplicitOperands() - 2).getReg())
388 .addImm(0)
389 .addReg(MI.getOperand(2).getReg());
390
391 MI.eraseFromParent();
392 return true;
393 }
394
395 // $dst = PseudoCCMOVGPR $lhs, $rhs, $cc, $falsev (=$dst), $truev
396 // $dst = PseudoCCMOVGPRNoX0 $lhs, $rhs, $cc, $falsev (=$dst), $truev
397 // =>
398 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
399 BuildMI(MBB, MBBI, DL, TII->get(CMovOpcode))
400 .addDef(MI.getOperand(0).getReg())
401 .addReg(MI.getOperand(1).getReg())
402 .addReg(MI.getOperand(MI.getNumExplicitOperands() - 2).getReg())
403 .addReg(MI.getOperand(MI.getNumExplicitOperands() - 1).getReg())
404 .addReg(MI.getOperand(2).getReg());
405 MI.eraseFromParent();
406 return true;
407}
408
409bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
410 MachineBasicBlock::iterator MBBI,
411 unsigned Opcode) {
412 DebugLoc DL = MBBI->getDebugLoc();
413 Register DstReg = MBBI->getOperand(0).getReg();
414 const MCInstrDesc &Desc = TII->get(Opcode);
415 BuildMI(MBB, MBBI, DL, Desc, DstReg)
416 .addReg(DstReg, RegState::Undef)
417 .addReg(DstReg, RegState::Undef);
418 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
419 return true;
420}
421
422bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
423 MachineBasicBlock::iterator MBBI) {
424 DebugLoc DL = MBBI->getDebugLoc();
425 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
426 Register DstReg = TRI->getMatchingSuperReg(
427 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
428 Register SrcReg = TRI->getMatchingSuperReg(
429 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
430
431 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
432 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
433 .addImm(0);
434
435 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
436 return true;
437}
438
439bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
440 MachineBasicBlock::iterator MBBI) {
441 DebugLoc DL = MBBI->getDebugLoc();
442 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
443 Register DstReg = TRI->getMatchingSuperReg(
444 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
445 Register SrcReg = TRI->getMatchingSuperReg(
446 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
447
448 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
449 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
450 .addImm(0);
451
452 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
453 return true;
454}
455
456// This function expands the PseudoRV32ZdinxSD for storing a double-precision
457// floating-point value into memory by generating an equivalent instruction
458// sequence for RV32.
459bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
460 MachineBasicBlock::iterator MBBI) {
461 DebugLoc DL = MBBI->getDebugLoc();
462 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
463 Register Lo =
464 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
465 Register Hi =
466 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
467 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
468 Hi = RISCV::X0;
469
470 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
471 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
472 .addReg(MBBI->getOperand(1).getReg())
473 .add(MBBI->getOperand(2));
474
475 MachineInstrBuilder MIBHi;
476 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
477 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
478 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
479 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
480 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
481 .add(MBBI->getOperand(1))
482 .add(MBBI->getOperand(2));
483 } else {
484 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
485 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
486 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
487 .add(MBBI->getOperand(1))
488 .addImm(MBBI->getOperand(2).getImm() + 4);
489 }
490
491 MachineFunction *MF = MBB.getParent();
492 SmallVector<MachineMemOperand *> NewLoMMOs;
493 SmallVector<MachineMemOperand *> NewHiMMOs;
494 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
495 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
496 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
497 }
498 MIBLo.setMemRefs(NewLoMMOs);
499 MIBHi.setMemRefs(NewHiMMOs);
500
501 MBBI->eraseFromParent();
502 return true;
503}
504
505// This function expands PseudoRV32ZdinxLoad for loading a double-precision
506// floating-point value from memory into an equivalent instruction sequence for
507// RV32.
508bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
509 MachineBasicBlock::iterator MBBI) {
510 DebugLoc DL = MBBI->getDebugLoc();
511 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
512 Register Lo =
513 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
514 Register Hi =
515 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
516 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
517
518 MachineInstrBuilder MIBLo, MIBHi;
519
520 // If the register of operand 1 is equal to the Lo register, then swap the
521 // order of loading the Lo and Hi statements.
522 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
523 // Order: Lo, Hi
524 if (!IsOp1EqualToLo) {
525 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
526 .addReg(MBBI->getOperand(1).getReg())
527 .add(MBBI->getOperand(2));
528 }
529
530 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
531 auto Offset = MBBI->getOperand(2).getOffset();
532 assert(Offset % 8 == 0);
533 MBBI->getOperand(2).setOffset(Offset + 4);
534 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
535 .addReg(MBBI->getOperand(1).getReg())
536 .add(MBBI->getOperand(2));
537 MBBI->getOperand(2).setOffset(Offset);
538 } else {
539 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
540 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
541 .addReg(MBBI->getOperand(1).getReg())
542 .addImm(MBBI->getOperand(2).getImm() + 4);
543 }
544
545 // Order: Hi, Lo
546 if (IsOp1EqualToLo) {
547 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
548 .addReg(MBBI->getOperand(1).getReg())
549 .add(MBBI->getOperand(2));
550 }
551
552 MachineFunction *MF = MBB.getParent();
553 SmallVector<MachineMemOperand *> NewLoMMOs;
554 SmallVector<MachineMemOperand *> NewHiMMOs;
555 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
556 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
557 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
558 }
559 MIBLo.setMemRefs(NewLoMMOs);
560 MIBHi.setMemRefs(NewHiMMOs);
561
562 MBBI->eraseFromParent();
563 return true;
564}
565
566bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
567 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
568 DebugLoc DL = MBBI->getDebugLoc();
569 Register Dst = MBBI->getOperand(0).getReg();
570 unsigned Mul = MBBI->getOperand(1).getImm();
571 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
572 unsigned VTypeImm = RISCVVType::encodeVTYPE(
573 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
574
575 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
576 .addReg(Dst, RegState::Define)
577 .addReg(RISCV::X0, RegState::Kill)
578 .addImm(VTypeImm);
579
580 MBBI->eraseFromParent();
581 return true;
582}
583
584class RISCVPreRAExpandPseudo : public MachineFunctionPass {
585public:
586 const RISCVSubtarget *STI;
587 const RISCVInstrInfo *TII;
588 static char ID;
589
590 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
591
592 bool runOnMachineFunction(MachineFunction &MF) override;
593
594 void getAnalysisUsage(AnalysisUsage &AU) const override {
595 AU.setPreservesCFG();
596 MachineFunctionPass::getAnalysisUsage(AU);
597 }
598 StringRef getPassName() const override {
599 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
600 }
601
602private:
603 bool expandMBB(MachineBasicBlock &MBB);
604 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
605 MachineBasicBlock::iterator &NextMBBI);
606 bool expandAuipcInstPair(MachineBasicBlock &MBB,
607 MachineBasicBlock::iterator MBBI,
608 MachineBasicBlock::iterator &NextMBBI,
609 unsigned FlagsHi, unsigned SecondOpcode);
610 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
611 MachineBasicBlock::iterator MBBI,
612 MachineBasicBlock::iterator &NextMBBI);
613 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
614 MachineBasicBlock::iterator MBBI,
615 MachineBasicBlock::iterator &NextMBBI);
616 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
617 MachineBasicBlock::iterator MBBI,
618 MachineBasicBlock::iterator &NextMBBI);
619 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
620 MachineBasicBlock::iterator MBBI,
621 MachineBasicBlock::iterator &NextMBBI);
622 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
623 MachineBasicBlock::iterator MBBI,
624 MachineBasicBlock::iterator &NextMBBI);
625
626#ifndef NDEBUG
627 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
628 unsigned Size = 0;
629 for (auto &MBB : MF)
630 for (auto &MI : MBB)
631 Size += TII->getInstSizeInBytes(MI);
632 return Size;
633 }
634#endif
635};
636
637char RISCVPreRAExpandPseudo::ID = 0;
638
639bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
640 STI = &MF.getSubtarget<RISCVSubtarget>();
641 TII = STI->getInstrInfo();
642
643#ifndef NDEBUG
644 const unsigned OldSize = getInstSizeInBytes(MF);
645#endif
646
647 bool Modified = false;
648 for (auto &MBB : MF)
649 Modified |= expandMBB(MBB);
650
651#ifndef NDEBUG
652 const unsigned NewSize = getInstSizeInBytes(MF);
653 assert(OldSize >= NewSize);
654#endif
655 return Modified;
656}
657
658bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
659 bool Modified = false;
660
661 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
662 while (MBBI != E) {
663 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
664 Modified |= expandMI(MBB, MBBI, NMBBI);
665 MBBI = NMBBI;
666 }
667
668 return Modified;
669}
670
671bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
672 MachineBasicBlock::iterator MBBI,
673 MachineBasicBlock::iterator &NextMBBI) {
674
675 switch (MBBI->getOpcode()) {
676 case RISCV::PseudoLLA:
677 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
678 case RISCV::PseudoLGA:
679 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
680 case RISCV::PseudoLA_TLS_IE:
681 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
682 case RISCV::PseudoLA_TLS_GD:
683 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
684 case RISCV::PseudoLA_TLSDESC:
685 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
686 }
687 return false;
688}
689
690bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
691 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
692 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
693 unsigned SecondOpcode) {
694 MachineFunction *MF = MBB.getParent();
695 MachineInstr &MI = *MBBI;
696 DebugLoc DL = MI.getDebugLoc();
697
698 Register DestReg = MI.getOperand(0).getReg();
699 Register ScratchReg =
700 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
701
702 MachineOperand &Symbol = MI.getOperand(1);
703 Symbol.setTargetFlags(FlagsHi);
704 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
705
706 MachineInstr *MIAUIPC =
707 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
708 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
709
710 MachineInstr *SecondMI =
711 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
712 .addReg(ScratchReg)
713 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
714
715 if (MI.hasOneMemOperand())
716 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
717
718 MI.eraseFromParent();
719 return true;
720}
721
722bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
723 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
724 MachineBasicBlock::iterator &NextMBBI) {
725 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
726 RISCV::ADDI);
727}
728
729bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
730 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
731 MachineBasicBlock::iterator &NextMBBI) {
732 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
733 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
734 SecondOpcode);
735}
736
737bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
738 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
739 MachineBasicBlock::iterator &NextMBBI) {
740 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
741 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
742 SecondOpcode);
743}
744
745bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
746 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
747 MachineBasicBlock::iterator &NextMBBI) {
748 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
749 RISCV::ADDI);
750}
751
752bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
753 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
754 MachineBasicBlock::iterator &NextMBBI) {
755 MachineFunction *MF = MBB.getParent();
756 MachineInstr &MI = *MBBI;
757 DebugLoc DL = MI.getDebugLoc();
758
759 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
760 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
761
762 Register FinalReg = MI.getOperand(0).getReg();
763 Register DestReg =
764 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
765 Register ScratchReg =
766 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
767
768 MachineOperand &Symbol = MI.getOperand(1);
769 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
770 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
771
772 MachineInstr *MIAUIPC =
773 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
774 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
775
776 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
777 .addReg(ScratchReg)
778 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
779
780 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
781 .addReg(ScratchReg)
782 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
783
784 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
785 .addReg(DestReg)
786 .addImm(0)
787 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
788
789 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
790 .addReg(RISCV::X10)
791 .addReg(RISCV::X4);
792
793 MI.eraseFromParent();
794 return true;
795}
796
797} // end of anonymous namespace
798
799INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
800 RISCV_EXPAND_PSEUDO_NAME, false, false)
801
802INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
803 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
804
805namespace llvm {
806
807FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
808FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
809
810} // end of namespace llvm
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2120
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:26
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition SystemZLongBranch.cpp:211
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:75
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:270
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:123
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
LLVM_ABI MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition MCContext.cpp:395
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:199
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:942
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:823
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1172
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:349
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:188
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:776
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:544
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition MachineFunction.h:733
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:786
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:507
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1021
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:310
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition MachineInstrBuilder.h:373
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:248
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:218
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:72
llvm::MachineInstr::setPreInstrSymbol
LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition MachineInstr.cpp:480
llvm::MachineInstr::addMemOperand
LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition MachineInstr.cpp:385
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:154
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition RISCVSubtarget.h:143
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition RISCVSubtarget.h:142
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:419
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1205
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:242
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
INITIALIZE_PASS
TargetPassConfig.
Definition TargetPassConfig.cpp:391
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:139
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:366
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition Types.h:26
llvm::Offset
@ Offset
Definition DWP.cpp:532
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:165
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:65
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:57
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:23
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:807
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:808
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