LLVM 20.0.0git
TargetPassConfig.cpp
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1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines interfaces to access the target independent code
10// generation passes provided by the LLVM backend.
11//
12//===---------------------------------------------------------------------===//
13
15#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/StringRef.h"
27#include "llvm/CodeGen/Passes.h"
32#include "llvm/IR/Verifier.h"
34#include "llvm/MC/MCAsmInfo.h"
36#include "llvm/Pass.h"
40#include "llvm/Support/Debug.h"
52#include <cassert>
53#include <optional>
54#include <string>
55
56using namespace llvm;
57
58static cl::opt<bool>
59 EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
60 cl::desc("Enable interprocedural register allocation "
61 "to reduce load/store at procedure calls."));
63 cl::desc("Disable Post Regalloc Scheduler"));
64static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
65 cl::desc("Disable branch folding"));
66static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
67 cl::desc("Disable tail duplication"));
68static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
69 cl::desc("Disable pre-register allocation tail duplication"));
70static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
71 cl::Hidden, cl::desc("Disable probability-driven block placement"));
72static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
73 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
74static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
75 cl::desc("Disable Stack Slot Coloring"));
76static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
77 cl::desc("Disable Machine Dead Code Elimination"));
79 cl::desc("Disable Early If-conversion"));
80static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
81 cl::desc("Disable Machine LICM"));
82static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
83 cl::desc("Disable Machine Common Subexpression Elimination"));
85 "optimize-regalloc", cl::Hidden,
86 cl::desc("Enable optimized register allocation compilation path."));
87static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
89 cl::desc("Disable Machine LICM"));
90static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
91 cl::desc("Disable Machine Sinking"));
92static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
94 cl::desc("Disable PostRA Machine Sinking"));
95static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
96 cl::desc("Disable Loop Strength Reduction Pass"));
97static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
98 cl::Hidden, cl::desc("Disable ConstantHoisting"));
99static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
100 cl::desc("Disable Codegen Prepare"));
101static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
102 cl::desc("Disable Copy Propagation pass"));
103static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
104 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
106 "disable-atexit-based-global-dtor-lowering", cl::Hidden,
107 cl::desc("For MachO, disable atexit()-based global destructor lowering"));
109 "enable-implicit-null-checks",
110 cl::desc("Fold null checks into faulting memory operations"),
111 cl::init(false), cl::Hidden);
112static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
113 cl::desc("Disable MergeICmps Pass"),
114 cl::init(false), cl::Hidden);
115static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
116 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
117static cl::opt<bool>
118 PrintISelInput("print-isel-input", cl::Hidden,
119 cl::desc("Print LLVM IR input to isel pass"));
121 VerifyMachineCode("verify-machineinstrs", cl::Hidden,
122 cl::desc("Verify generated machine code"));
124 DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden,
125 cl::desc("Debugify MIR before and Strip debug after "
126 "each pass except those known to be unsafe "
127 "when debug info is present"));
129 "debugify-check-and-strip-all-safe", cl::Hidden,
130 cl::desc(
131 "Debugify MIR before, by checking and stripping the debug info after, "
132 "each pass except those known to be unsafe when debug info is "
133 "present"));
134// Enable or disable the MachineOutliner.
136 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
137 cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault),
138 cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always",
139 "Run on all functions guaranteed to be beneficial"),
140 clEnumValN(RunOutliner::NeverOutline, "never",
141 "Disable all outlining"),
142 // Sentinel value for unspecified option.
143 clEnumValN(RunOutliner::AlwaysOutline, "", "")));
144// Disable the pass to fix unwind information. Whether the pass is included in
145// the pipeline is controlled via the target options, this option serves as
146// manual override.
147static cl::opt<bool> DisableCFIFixup("disable-cfi-fixup", cl::Hidden,
148 cl::desc("Disable the CFI fixup pass"));
149// Enable or disable FastISel. Both options are needed, because
150// FastISel is enabled by default with -fast, and we wish to be
151// able to enable or disable fast-isel independently from -O0.
154 cl::desc("Enable the \"fast\" instruction selector"));
155
157 "global-isel", cl::Hidden,
158 cl::desc("Enable the \"global\" instruction selector"));
159
160// FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
161// first...
162static cl::opt<bool>
163 PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
164 cl::desc("Print machine instrs after ISel"));
165
167 "global-isel-abort", cl::Hidden,
168 cl::desc("Enable abort calls when \"global\" instruction selection "
169 "fails to lower/select an instruction"),
171 clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
172 clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
173 clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",
174 "Disable the abort but emit a diagnostic on failure")));
175
176// Disable MIRProfileLoader before RegAlloc. This is for for debugging and
177// tuning purpose.
179 "disable-ra-fsprofile-loader", cl::init(false), cl::Hidden,
180 cl::desc("Disable MIRProfileLoader before RegAlloc"));
181// Disable MIRProfileLoader before BloackPlacement. This is for for debugging
182// and tuning purpose.
184 "disable-layout-fsprofile-loader", cl::init(false), cl::Hidden,
185 cl::desc("Disable MIRProfileLoader before BlockPlacement"));
186// Specify FSProfile file name.
188 FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"),
189 cl::desc("Flow Sensitive profile file name."), cl::Hidden);
190// Specify Remapping file for FSProfile.
192 "fs-remapping-file", cl::init(""), cl::value_desc("filename"),
193 cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden);
194
195// Temporary option to allow experimenting with MachineScheduler as a post-RA
196// scheduler. Targets can "properly" enable this with
197// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
198// Targets can return true in targetSchedulesPostRAScheduling() and
199// insert a PostRA scheduling pass wherever it wants.
201 "misched-postra", cl::Hidden,
202 cl::desc(
203 "Run MachineScheduler post regalloc (independent of preRA sched)"));
204
205// Experimental option to run live interval analysis early.
206static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
207 cl::desc("Run live interval analysis earlier in the pipeline"));
208
210 "disable-replace-with-vec-lib", cl::Hidden,
211 cl::desc("Disable replace with vector math call pass"));
212
213/// Option names for limiting the codegen pipeline.
214/// Those are used in error reporting and we didn't want
215/// to duplicate their names all over the place.
216static const char StartAfterOptName[] = "start-after";
217static const char StartBeforeOptName[] = "start-before";
218static const char StopAfterOptName[] = "stop-after";
219static const char StopBeforeOptName[] = "stop-before";
220
223 cl::desc("Resume compilation after a specific pass"),
224 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
225
228 cl::desc("Resume compilation before a specific pass"),
229 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
230
233 cl::desc("Stop compilation after a specific pass"),
234 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
235
238 cl::desc("Stop compilation before a specific pass"),
239 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
240
241/// Enable the machine function splitter pass.
243 "enable-split-machine-functions", cl::Hidden,
244 cl::desc("Split out cold blocks from machine functions based on profile "
245 "information."));
246
247/// Disable the expand reductions pass for testing.
249 "disable-expand-reductions", cl::init(false), cl::Hidden,
250 cl::desc("Disable the expand reduction intrinsics pass from running"));
251
252/// Disable the select optimization pass.
254 "disable-select-optimize", cl::init(true), cl::Hidden,
255 cl::desc("Disable the select-optimization pass from running"));
256
257/// Enable garbage-collecting empty basic blocks.
258static cl::opt<bool>
259 GCEmptyBlocks("gc-empty-basic-blocks", cl::init(false), cl::Hidden,
260 cl::desc("Enable garbage-collecting empty basic blocks"));
261
262/// Allow standard passes to be disabled by command line options. This supports
263/// simple binary flags that either suppress the pass or do nothing.
264/// i.e. -disable-mypass=false has no effect.
265/// These should be converted to boolOrDefault in order to use applyOverride.
267 bool Override) {
268 if (Override)
269 return IdentifyingPassPtr();
270 return PassID;
271}
272
273/// Allow standard passes to be disabled by the command line, regardless of who
274/// is adding the pass.
275///
276/// StandardID is the pass identified in the standard pass pipeline and provided
277/// to addPass(). It may be a target-specific ID in the case that the target
278/// directly adds its own pass, but in that case we harmlessly fall through.
279///
280/// TargetID is the pass that the target has configured to override StandardID.
281///
282/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
283/// pass to run. This allows multiple options to control a single pass depending
284/// on where in the pipeline that pass is added.
286 IdentifyingPassPtr TargetID) {
287 if (StandardID == &PostRASchedulerID)
288 return applyDisable(TargetID, DisablePostRASched);
289
290 if (StandardID == &BranchFolderPassID)
291 return applyDisable(TargetID, DisableBranchFold);
292
293 if (StandardID == &TailDuplicateID)
294 return applyDisable(TargetID, DisableTailDuplicate);
295
296 if (StandardID == &EarlyTailDuplicateID)
297 return applyDisable(TargetID, DisableEarlyTailDup);
298
299 if (StandardID == &MachineBlockPlacementID)
300 return applyDisable(TargetID, DisableBlockPlacement);
301
302 if (StandardID == &StackSlotColoringID)
303 return applyDisable(TargetID, DisableSSC);
304
305 if (StandardID == &DeadMachineInstructionElimID)
306 return applyDisable(TargetID, DisableMachineDCE);
307
308 if (StandardID == &EarlyIfConverterID)
309 return applyDisable(TargetID, DisableEarlyIfConversion);
310
311 if (StandardID == &EarlyMachineLICMID)
312 return applyDisable(TargetID, DisableMachineLICM);
313
314 if (StandardID == &MachineCSEID)
315 return applyDisable(TargetID, DisableMachineCSE);
316
317 if (StandardID == &MachineLICMID)
318 return applyDisable(TargetID, DisablePostRAMachineLICM);
319
320 if (StandardID == &MachineSinkingID)
321 return applyDisable(TargetID, DisableMachineSink);
322
323 if (StandardID == &PostRAMachineSinkingID)
324 return applyDisable(TargetID, DisablePostRAMachineSink);
325
326 if (StandardID == &MachineCopyPropagationID)
327 return applyDisable(TargetID, DisableCopyProp);
328
329 return TargetID;
330}
331
332// Find the FSProfile file name. The internal option takes the precedence
333// before getting from TargetMachine.
334static std::string getFSProfileFile(const TargetMachine *TM) {
335 if (!FSProfileFile.empty())
336 return FSProfileFile.getValue();
337 const std::optional<PGOOptions> &PGOOpt = TM->getPGOOption();
338 if (PGOOpt == std::nullopt || PGOOpt->Action != PGOOptions::SampleUse)
339 return std::string();
340 return PGOOpt->ProfileFile;
341}
342
343// Find the Profile remapping file name. The internal option takes the
344// precedence before getting from TargetMachine.
345static std::string getFSRemappingFile(const TargetMachine *TM) {
346 if (!FSRemappingFile.empty())
347 return FSRemappingFile.getValue();
348 const std::optional<PGOOptions> &PGOOpt = TM->getPGOOption();
349 if (PGOOpt == std::nullopt || PGOOpt->Action != PGOOptions::SampleUse)
350 return std::string();
351 return PGOOpt->ProfileRemappingFile;
352}
353
354//===---------------------------------------------------------------------===//
355/// TargetPassConfig
356//===---------------------------------------------------------------------===//
357
358INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
359 "Target Pass Configuration", false, false)
361
362namespace {
363
367
368 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
369 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID) {}
370
372 assert(InsertedPassID.isValid() && "Illegal Pass ID!");
373 if (InsertedPassID.isInstance())
374 return InsertedPassID.getInstance();
375 Pass *NP = Pass::createPass(InsertedPassID.getID());
376 assert(NP && "Pass ID not registered");
377 return NP;
378 }
379};
380
381} // end anonymous namespace
382
383namespace llvm {
384
386
388public:
389 // List of passes explicitly substituted by this target. Normally this is
390 // empty, but it is a convenient way to suppress or replace specific passes
391 // that are part of a standard pass pipeline without overridding the entire
392 // pipeline. This mechanism allows target options to inherit a standard pass's
393 // user interface. For example, a target may disable a standard pass by
394 // default by substituting a pass ID of zero, and the user may still enable
395 // that standard pass with an explicit command line option.
397
398 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
399 /// is inserted after each instance of the first one.
401};
402
403} // end namespace llvm
404
405// Out of line virtual method.
407 delete Impl;
408}
409
411 if (PassName.empty())
412 return nullptr;
413
415 const PassInfo *PI = PR.getPassInfo(PassName);
416 if (!PI)
418 Twine("\" pass is not registered."));
419 return PI;
420}
421
423 const PassInfo *PI = getPassInfo(PassName);
424 return PI ? PI->getTypeInfo() : nullptr;
425}
426
427static std::pair<StringRef, unsigned>
429 StringRef Name, InstanceNumStr;
430 std::tie(Name, InstanceNumStr) = PassName.split(',');
431
432 unsigned InstanceNum = 0;
433 if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
434 report_fatal_error("invalid pass instance specifier " + PassName);
435
436 return std::make_pair(Name, InstanceNum);
437}
438
439void TargetPassConfig::setStartStopPasses() {
440 StringRef StartBeforeName;
441 std::tie(StartBeforeName, StartBeforeInstanceNum) =
443
444 StringRef StartAfterName;
445 std::tie(StartAfterName, StartAfterInstanceNum) =
447
448 StringRef StopBeforeName;
449 std::tie(StopBeforeName, StopBeforeInstanceNum)
451
452 StringRef StopAfterName;
453 std::tie(StopAfterName, StopAfterInstanceNum)
455
456 StartBefore = getPassIDFromName(StartBeforeName);
457 StartAfter = getPassIDFromName(StartAfterName);
458 StopBefore = getPassIDFromName(StopBeforeName);
459 StopAfter = getPassIDFromName(StopAfterName);
460 if (StartBefore && StartAfter)
462 Twine(StartAfterOptName) + Twine(" specified!"));
463 if (StopBefore && StopAfter)
465 Twine(StopAfterOptName) + Twine(" specified!"));
466 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
467}
468
471
472#define SET_OPTION(Option) \
473 if (Option.getNumOccurrences()) \
474 Opt.Option = Option;
475
487
488#define SET_BOOLEAN_OPTION(Option) Opt.Option = Option;
489
508
509 return Opt;
510}
511
513 LLVMTargetMachine &LLVMTM) {
514
515 // Register a callback for disabling passes.
517
518#define DISABLE_PASS(Option, Name) \
519 if (Option && P.contains(#Name)) \
520 return false;
521 DISABLE_PASS(DisableBlockPlacement, MachineBlockPlacementPass)
522 DISABLE_PASS(DisableBranchFold, BranchFolderPass)
523 DISABLE_PASS(DisableCopyProp, MachineCopyPropagationPass)
524 DISABLE_PASS(DisableEarlyIfConversion, EarlyIfConverterPass)
525 DISABLE_PASS(DisableEarlyTailDup, EarlyTailDuplicatePass)
526 DISABLE_PASS(DisableMachineCSE, MachineCSEPass)
528 DISABLE_PASS(DisableMachineLICM, EarlyMachineLICMPass)
529 DISABLE_PASS(DisableMachineSink, MachineSinkingPass)
530 DISABLE_PASS(DisablePostRAMachineLICM, MachineLICMPass)
531 DISABLE_PASS(DisablePostRAMachineSink, PostRAMachineSinkingPass)
532 DISABLE_PASS(DisablePostRASched, PostRASchedulerPass)
533 DISABLE_PASS(DisableSSC, StackSlotColoringPass)
534 DISABLE_PASS(DisableTailDuplicate, TailDuplicatePass)
535
536 return true;
537 });
538}
539
542 auto [StartBefore, StartBeforeInstanceNum] =
544 auto [StartAfter, StartAfterInstanceNum] =
546 auto [StopBefore, StopBeforeInstanceNum] =
548 auto [StopAfter, StopAfterInstanceNum] =
550
551 if (!StartBefore.empty() && !StartAfter.empty())
552 return make_error<StringError>(
553 Twine(StartBeforeOptName) + " and " + StartAfterOptName + " specified!",
554 std::make_error_code(std::errc::invalid_argument));
555 if (!StopBefore.empty() && !StopAfter.empty())
556 return make_error<StringError>(
557 Twine(StopBeforeOptName) + " and " + StopAfterOptName + " specified!",
558 std::make_error_code(std::errc::invalid_argument));
559
560 StartStopInfo Result;
561 Result.StartPass = StartBefore.empty() ? StartAfter : StartBefore;
562 Result.StopPass = StopBefore.empty() ? StopAfter : StopBefore;
563 Result.StartInstanceNum =
564 StartBefore.empty() ? StartAfterInstanceNum : StartBeforeInstanceNum;
565 Result.StopInstanceNum =
566 StopBefore.empty() ? StopAfterInstanceNum : StopBeforeInstanceNum;
567 Result.StartAfter = !StartAfter.empty();
568 Result.StopAfter = !StopAfter.empty();
569 Result.StartInstanceNum += Result.StartInstanceNum == 0;
570 Result.StopInstanceNum += Result.StopInstanceNum == 0;
571 return Result;
572}
573
574// Out of line constructor provides default values for pass options and
575// registers all common codegen passes.
577 : ImmutablePass(ID), PM(&pm), TM(&TM) {
578 Impl = new PassConfigImpl();
579
580 // Register all target independent codegen passes to activate their PassIDs,
581 // including this pass itself.
583
584 // Also register alias analysis passes required by codegen passes.
587
588 if (EnableIPRA.getNumOccurrences())
590 else {
591 // If not explicitly specified, use target default.
593 }
594
597
598 if (EnableGlobalISelAbort.getNumOccurrences())
600
601 setStartStopPasses();
602}
603
605 return TM->getOptLevel();
606}
607
608/// Insert InsertedPassID pass after TargetPassID.
610 IdentifyingPassPtr InsertedPassID) {
611 assert(((!InsertedPassID.isInstance() &&
612 TargetPassID != InsertedPassID.getID()) ||
613 (InsertedPassID.isInstance() &&
614 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
615 "Insert a pass after itself!");
616 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID);
617}
618
619/// createPassConfig - Create a pass configuration object to be used by
620/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
621///
622/// Targets may override this to extend TargetPassConfig.
624 return new TargetPassConfig(*this, PM);
625}
626
628 : ImmutablePass(ID) {
629 report_fatal_error("Trying to construct TargetPassConfig without a target "
630 "machine. Scheduling a CodeGen pass without a target "
631 "triple set?");
632}
633
635 return StopBeforeOpt.empty() && StopAfterOpt.empty();
636}
637
639 return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
641}
642
645 return std::string();
646 std::string Res;
647 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
649 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
651 bool IsFirst = true;
652 for (int Idx = 0; Idx < 4; ++Idx)
653 if (!PassNames[Idx]->empty()) {
654 if (!IsFirst)
655 Res += " and ";
656 IsFirst = false;
657 Res += OptNames[Idx];
658 }
659 return Res;
660}
661
662// Helper to verify the analysis is really immutable.
663void TargetPassConfig::setOpt(bool &Opt, bool Val) {
664 assert(!Initialized && "PassConfig is immutable");
665 Opt = Val;
666}
667
669 IdentifyingPassPtr TargetID) {
670 Impl->TargetPasses[StandardID] = TargetID;
671}
672
675 I = Impl->TargetPasses.find(ID);
676 if (I == Impl->TargetPasses.end())
677 return ID;
678 return I->second;
679}
680
683 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
684 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
685 FinalPtr.getID() != ID;
686}
687
688/// Add a pass to the PassManager if that pass is supposed to be run. If the
689/// Started/Stopped flags indicate either that the compilation should start at
690/// a later pass or that it should stop after an earlier pass, then do not add
691/// the pass. Finally, compare the current pass against the StartAfter
692/// and StopAfter options and change the Started/Stopped flags accordingly.
694 assert(!Initialized && "PassConfig is immutable");
695
696 // Cache the Pass ID here in case the pass manager finds this pass is
697 // redundant with ones already scheduled / available, and deletes it.
698 // Fundamentally, once we add the pass to the manager, we no longer own it
699 // and shouldn't reference it.
700 AnalysisID PassID = P->getPassID();
701
702 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
703 Started = true;
704 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
705 Stopped = true;
706 if (Started && !Stopped) {
707 if (AddingMachinePasses) {
708 // Construct banner message before PM->add() as that may delete the pass.
709 std::string Banner =
710 std::string("After ") + std::string(P->getPassName());
712 PM->add(P);
713 addMachinePostPasses(Banner);
714 } else {
715 PM->add(P);
716 }
717
718 // Add the passes after the pass P if there is any.
719 for (const auto &IP : Impl->InsertedPasses)
720 if (IP.TargetPassID == PassID)
721 addPass(IP.getInsertedPass());
722 } else {
723 delete P;
724 }
725
726 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
727 Stopped = true;
728
729 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
730 Started = true;
731 if (Stopped && !Started)
732 report_fatal_error("Cannot stop compilation after pass that is not run");
733}
734
735/// Add a CodeGen pass at this point in the pipeline after checking for target
736/// and command line overrides.
737///
738/// addPass cannot return a pointer to the pass instance because is internal the
739/// PassManager and the instance we create here may already be freed.
741 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
742 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
743 if (!FinalPtr.isValid())
744 return nullptr;
745
746 Pass *P;
747 if (FinalPtr.isInstance())
748 P = FinalPtr.getInstance();
749 else {
750 P = Pass::createPass(FinalPtr.getID());
751 if (!P)
752 llvm_unreachable("Pass ID not registered");
753 }
754 AnalysisID FinalID = P->getPassID();
755 addPass(P); // Ends the lifetime of P.
756
757 return FinalID;
758}
759
760void TargetPassConfig::printAndVerify(const std::string &Banner) {
761 addPrintPass(Banner);
762 addVerifyPass(Banner);
763}
764
765void TargetPassConfig::addPrintPass(const std::string &Banner) {
766 if (PrintAfterISel)
768}
769
770void TargetPassConfig::addVerifyPass(const std::string &Banner) {
772#ifdef EXPENSIVE_CHECKS
775#endif
776 if (Verify)
777 PM->add(createMachineVerifierPass(Banner));
778}
779
782}
783
785 PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
786}
787
790}
791
793 if (AllowDebugify && DebugifyIsSafe &&
797}
798
799void TargetPassConfig::addMachinePostPasses(const std::string &Banner) {
800 if (DebugifyIsSafe) {
804 } else if (DebugifyAndStripAll == cl::BOU_TRUE)
806 }
807 addVerifyPass(Banner);
808}
809
810/// Add common target configurable passes that perform LLVM IR to IR transforms
811/// following machine independent optimization.
813 // Before running any passes, run the verifier to determine if the input
814 // coming from the front-end and/or optimizer is valid.
815 if (!DisableVerify)
817
819 // Basic AliasAnalysis support.
820 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
821 // BasicAliasAnalysis wins if they disagree. This is intended to help
822 // support "obvious" type-punning idioms.
826
827 // Run loop strength reduction before anything else.
828 if (!DisableLSR) {
833 if (PrintLSR)
835 "\n\n*** Code after LSR ***\n"));
836 }
837
838 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
839 // loads and compares. ExpandMemCmpPass then tries to expand those calls
840 // into optimally-sized loads and compares. The transforms are enabled by a
841 // target lowering hook.
845 }
846
847 // Run GC lowering passes for builtin collectors
848 // TODO: add a pass insertion point here
851
852 // For MachO, lower @llvm.global_dtors into @llvm.global_ctors with
853 // __cxa_atexit() calls to avoid emitting the deprecated __mod_term_func.
857
858 // Make sure that no unreachable blocks are instruction selected.
860
861 // Prepare expensive constants for SelectionDAG.
864
867
870
871 // Instrument function entry after all inlining.
873
874 // Add scalarization of target's unsupported masked memory intrinsics pass.
875 // the unsupported intrinsic will be replaced with a chain of basic blocks,
876 // that stores/loads element one-by-one if the appropriate mask bit is set.
878
879 // Expand reduction intrinsics into shuffle sequences if the target wants to.
880 // Allow disabling it for testing purposes.
883
886
887 // Convert conditional moves to conditional jumps when profitable.
890}
891
892/// Turn exception handling constructs into something the code generators can
893/// handle.
895 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
896 assert(MCAI && "No MCAsmInfo");
897 switch (MCAI->getExceptionHandlingType()) {
899 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
900 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
901 // catch info can get misplaced when a selector ends up more than one block
902 // removed from the parent invoke(s). This could happen when a landing
903 // pad is shared by multiple invokes and is also a target of a normal
904 // edge from elsewhere.
906 [[fallthrough]];
912 break;
914 // We support using both GCC-style and MSVC-style exceptions on Windows, so
915 // add both preparation passes. Each pass will only actually run if it
916 // recognizes the personality function.
919 break;
921 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
922 // on catchpads and cleanuppads because it does not outline them into
923 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
924 // should remove PHIs there.
925 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/true));
927 break;
930
931 // The lower invoke pass may create unreachable code. Remove it.
933 break;
934 }
935}
936
937/// Add pass to prepare the LLVM IR for code generation. This should be done
938/// before exception handling preparation passes.
942}
943
944/// Add common passes that perform LLVM IR to IR transforms in preparation for
945/// instruction selection.
947 addPreISel();
948
949 // Force codegen to run according to the callgraph.
952
955
957
958 // Add both the safe stack and the stack protection passes: each of them will
959 // only protect functions that have corresponding attributes.
962
963 if (PrintISelInput)
965 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
966
967 // All passes which modify the LLVM IR are now complete; run the verifier
968 // to ensure that the IR is valid.
969 if (!DisableVerify)
971}
972
974 // Enable FastISel with -fast-isel, but allow that to be overridden.
976
977 // Determine an instruction selector.
978 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
979 SelectorType Selector;
980
982 Selector = SelectorType::FastISel;
986 Selector = SelectorType::GlobalISel;
987 else if (TM->getOptLevel() == CodeGenOptLevel::None &&
989 Selector = SelectorType::FastISel;
990 else
991 Selector = SelectorType::SelectionDAG;
992
993 // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
994 if (Selector == SelectorType::FastISel) {
995 TM->setFastISel(true);
996 TM->setGlobalISel(false);
997 } else if (Selector == SelectorType::GlobalISel) {
998 TM->setFastISel(false);
999 TM->setGlobalISel(true);
1000 }
1001
1002 // FIXME: Injecting into the DAGISel pipeline seems to cause issues with
1003 // analyses needing to be re-run. This can result in being unable to
1004 // schedule passes (particularly with 'Function Alias Analysis
1005 // Results'). It's not entirely clear why but AFAICT this seems to be
1006 // due to one FunctionPassManager not being able to use analyses from a
1007 // previous one. As we're injecting a ModulePass we break the usual
1008 // pass manager into two. GlobalISel with the fallback path disabled
1009 // and -run-pass seem to be unaffected. The majority of GlobalISel
1010 // testing uses -run-pass so this probably isn't too bad.
1011 SaveAndRestore SavedDebugifyIsSafe(DebugifyIsSafe);
1012 if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
1013 DebugifyIsSafe = false;
1014
1015 // Add instruction selector passes.
1016 if (Selector == SelectorType::GlobalISel) {
1017 SaveAndRestore SavedAddingMachinePasses(AddingMachinePasses, true);
1018 if (addIRTranslator())
1019 return true;
1020
1022
1024 return true;
1025
1026 // Before running the register bank selector, ask the target if it
1027 // wants to run some passes.
1029
1030 if (addRegBankSelect())
1031 return true;
1032
1034
1036 return true;
1037
1038 // Pass to reset the MachineFunction if the ISel failed.
1041
1042 // Provide a fallback path when we do not want to abort on
1043 // not-yet-supported input.
1045 return true;
1046
1047 } else if (addInstSelector())
1048 return true;
1049
1050 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
1051 // FinalizeISel.
1053
1054 // Print the instruction selected machine code...
1055 printAndVerify("After Instruction Selection");
1056
1057 return false;
1058}
1059
1061 if (TM->useEmulatedTLS())
1063
1068 addIRPasses();
1072
1073 return addCoreISelPasses();
1074}
1075
1076/// -regalloc=... command line option.
1077static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
1081 cl::desc("Register allocator to use"));
1082
1083/// Add the complete set of target-independent postISel code generator passes.
1084///
1085/// This can be read as the standard order of major LLVM CodeGen stages. Stages
1086/// with nontrivial configuration or multiple passes are broken out below in
1087/// add%Stage routines.
1088///
1089/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
1090/// addPre/Post methods with empty header implementations allow injecting
1091/// target-specific fixups just before or after major stages. Additionally,
1092/// targets have the flexibility to change pass order within a stage by
1093/// overriding default implementation of add%Stage routines below. Each
1094/// technique has maintainability tradeoffs because alternate pass orders are
1095/// not well supported. addPre/Post works better if the target pass is easily
1096/// tied to a common pass. But if it has subtle dependencies on multiple passes,
1097/// the target should override the stage instead.
1098///
1099/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
1100/// before/after any target-independent pass. But it's currently overkill.
1102 AddingMachinePasses = true;
1103
1104 // Add passes that optimize machine instructions in SSA form.
1107 } else {
1108 // If the target requests it, assign local variables to stack slots relative
1109 // to one another and simplify frame index references where possible.
1111 }
1112
1113 if (TM->Options.EnableIPRA)
1115
1116 // Run pre-ra passes.
1118
1119 // Debugifying the register allocator passes seems to provoke some
1120 // non-determinism that affects CodeGen and there doesn't seem to be a point
1121 // where it becomes safe again so stop debugifying here.
1122 DebugifyIsSafe = false;
1123
1124 // Add a FSDiscriminator pass right before RA, so that we could get
1125 // more precise SampleFDO profile for RA.
1129 const std::string ProfileFile = getFSProfileFile(TM);
1130 if (!ProfileFile.empty() && !DisableRAFSProfileLoader)
1133 nullptr));
1134 }
1135
1136 // Run register allocation and passes that are tightly coupled with it,
1137 // including phi elimination and scheduling.
1138 if (getOptimizeRegAlloc())
1140 else
1142
1143 // Run post-ra passes.
1145
1147
1149
1150 // Insert prolog/epilog code. Eliminate abstract frame index references...
1154 }
1155
1156 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
1157 // do so if it hasn't been disabled, substituted, or overridden.
1160
1161 /// Add passes that optimize machine instructions after register allocation.
1164
1165 // Expand pseudo instructions before second scheduling pass.
1167
1168 // Run pre-sched2 passes.
1169 addPreSched2();
1170
1173
1174 // Second pass scheduler.
1175 // Let Target optionally insert this pass by itself at some other
1176 // point.
1179 if (MISchedPostRA)
1181 else
1183 }
1184
1185 // GC
1186 addGCPasses();
1187
1188 // Basic block placement.
1191
1192 // Insert before XRay Instrumentation.
1194
1197
1199
1200 if (TM->Options.EnableIPRA)
1201 // Collect register usage information and produce a register mask of
1202 // clobbered registers, to be used to optimize call sites.
1204
1205 // FIXME: Some backends are incompatible with running the verifier after
1206 // addPreEmitPass. Maybe only pass "false" here for those targets?
1208
1212
1216 bool RunOnAllFunctions =
1218 bool AddOutliner =
1219 RunOnAllFunctions || TM->Options.SupportsDefaultOutlining;
1220 if (AddOutliner)
1221 addPass(createMachineOutlinerPass(RunOnAllFunctions));
1222 }
1223
1224 if (GCEmptyBlocks)
1226
1230
1231 bool NeedsBBSections =
1233 // Machine function splitter uses the basic block sections feature. Both
1234 // cannot be enabled at the same time. We do not apply machine function
1235 // splitter if -basic-block-sections is requested.
1236 if (!NeedsBBSections && (TM->Options.EnableMachineFunctionSplitter ||
1238 const std::string ProfileFile = getFSProfileFile(TM);
1239 if (!ProfileFile.empty()) {
1242 ProfileFile, getFSRemappingFile(TM),
1244 } else {
1245 // Sample profile is given, but FSDiscriminator is not
1246 // enabled, this may result in performance regression.
1248 << "Using AutoFDO without FSDiscriminator for MFS may regress "
1249 "performance.\n";
1250 }
1251 }
1253 }
1254 // We run the BasicBlockSections pass if either we need BB sections or BB
1255 // address map (or both).
1256 if (NeedsBBSections || TM->Options.BBAddrMap) {
1261 }
1263 }
1264
1266
1269
1271
1272 // Add passes that directly emit MI after all other MI passes.
1274
1275 AddingMachinePasses = false;
1276}
1277
1278/// Add passes that optimize machine instructions in SSA form.
1280 // Pre-ra tail duplication.
1282
1283 // Optimize PHIs before DCE: removing dead PHI cycles may make more
1284 // instructions dead.
1286
1287 // This pass merges large allocas. StackSlotColoring is a different pass
1288 // which merges spill slots.
1290
1291 // If the target requests it, assign local variables to stack slots relative
1292 // to one another and simplify frame index references where possible.
1294
1295 // With optimization, dead code should already be eliminated. However
1296 // there is one known exception: lowered code for arguments that are only
1297 // used by tail calls, where the tail calls reuse the incoming stack
1298 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1300
1301 // Allow targets to insert passes that improve instruction level parallelism,
1302 // like if-conversion. Such passes will typically need dominator trees and
1303 // loop info, just like LICM and CSE below.
1304 addILPOpts();
1305
1308
1310
1312 // Clean-up the dead code that may have been generated by peephole
1313 // rewriting.
1315}
1316
1317//===---------------------------------------------------------------------===//
1318/// Register Allocation Pass Configuration
1319//===---------------------------------------------------------------------===//
1320
1322 switch (OptimizeRegAlloc) {
1323 case cl::BOU_UNSET:
1325 case cl::BOU_TRUE: return true;
1326 case cl::BOU_FALSE: return false;
1327 }
1328 llvm_unreachable("Invalid optimize-regalloc state");
1329}
1330
1331/// A dummy default pass factory indicates whether the register allocator is
1332/// overridden on the command line.
1334
1335static RegisterRegAlloc
1337 "pick register allocator based on -O option",
1339
1343}
1344
1345/// Instantiate the default register allocator pass for this target for either
1346/// the optimized or unoptimized allocation path. This will be added to the pass
1347/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1348/// in the optimized case.
1349///
1350/// A target that uses the standard regalloc pass order for fast or optimized
1351/// allocation may still override this for per-target regalloc
1352/// selection. But -regalloc=... always takes precedence.
1354 if (Optimized)
1356 else
1358}
1359
1360/// Find and instantiate the register allocation pass requested by this target
1361/// at the current optimization level. Different register allocators are
1362/// defined as separate passes because they may require different analysis.
1363///
1364/// This helper ensures that the regalloc= option is always available,
1365/// even for targets that override the default allocator.
1366///
1367/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1368/// this can be folded into addPass.
1370 // Initialize the global default.
1373
1375 if (Ctor != useDefaultRegisterAllocator)
1376 return Ctor();
1377
1378 // With no -regalloc= override, ask the target for a regalloc pass.
1379 return createTargetRegisterAllocator(Optimized);
1380}
1381
1383 return RegAlloc !=
1385}
1386
1390 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1391
1393
1394 // Allow targets to change the register assignments after
1395 // fast register allocation.
1397 return true;
1398}
1399
1401 // Add the selected register allocation pass.
1403
1404 // Allow targets to change the register assignments before rewriting.
1405 addPreRewrite();
1406
1407 // Finally rewrite virtual registers.
1409
1410 // Regalloc scoring for ML-driven eviction - noop except when learning a new
1411 // eviction policy.
1413 return true;
1414}
1415
1416/// Return true if the default global register allocator is in use and
1417/// has not be overriden on the command line with '-regalloc=...'
1419 return RegAlloc.getNumOccurrences() == 0;
1420}
1421
1422/// Add the minimum set of target-independent passes that are required for
1423/// register allocation. No coalescing or scheduling.
1427
1429}
1430
1431/// Add standard target-independent passes that are tightly coupled with
1432/// optimized register allocation, including coalescing, machine instruction
1433/// scheduling, and register allocation itself.
1436
1438
1440
1441 // LiveVariables currently requires pure SSA form.
1442 //
1443 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1444 // LiveVariables can be removed completely, and LiveIntervals can be directly
1445 // computed. (We still either need to regenerate kill flags after regalloc, or
1446 // preferably fix the scavenger to not depend on them).
1447 // FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
1448 // When LiveVariables is removed this has to be removed/moved either.
1449 // Explicit addition of UnreachableMachineBlockElim allows stopping before or
1450 // after it with -stop-before/-stop-after.
1453
1454 // Edge splitting is smarter with machine loop info.
1457
1458 // Eventually, we want to run LiveIntervals before PHI elimination.
1461
1464
1465 // The machine scheduler may accidentally create disconnected components
1466 // when moving subregister definitions around, avoid this by splitting them to
1467 // separate vregs before. Splitting can also improve reg. allocation quality.
1469
1470 // PreRA instruction scheduling.
1472
1474 // Perform stack slot coloring and post-ra machine LICM.
1476
1477 // Allow targets to expand pseudo instructions depending on the choice of
1478 // registers before MachineCopyPropagation.
1480
1481 // Copy propagate to forward register uses and try to eliminate COPYs that
1482 // were not coalesced.
1484
1485 // Run post-ra machine LICM to hoist reloads / remats.
1486 //
1487 // FIXME: can this move into MachineLateOptimization?
1489 }
1490}
1491
1492//===---------------------------------------------------------------------===//
1493/// Post RegAlloc Pass Configuration
1494//===---------------------------------------------------------------------===//
1495
1496/// Add passes that optimize machine instructions after register allocation.
1498 // Cleanup of redundant immediate/address loads.
1500
1501 // Branch folding must be run after regalloc and prolog/epilog insertion.
1503
1504 // Tail duplication.
1505 // Note that duplicating tail just increases code size and degrades
1506 // performance for targets that require Structured Control Flow.
1507 // In addition it can also make CFG irreducible. Thus we disable it.
1508 if (!TM->requiresStructuredCFG())
1510
1511 // Copy propagation.
1513}
1514
1515/// Add standard GC passes.
1518 return true;
1519}
1520
1521/// Add standard basic block placement passes.
1526 const std::string ProfileFile = getFSProfileFile(TM);
1527 if (!ProfileFile.empty() && !DisableLayoutFSProfileLoader)
1530 nullptr));
1531 }
1533 // Run a separate pass to collect block placement statistics.
1536 }
1537}
1538
1539//===---------------------------------------------------------------------===//
1540/// GlobalISel Configuration
1541//===---------------------------------------------------------------------===//
1544}
1545
1548}
1549
1551 return true;
1552}
1553
1554std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1555 return std::make_unique<CSEConfigBase>();
1556}
This is the interface for LLVM's primary stateless and local alias analysis.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:686
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
std::string Name
This file contains an interface for creating legacy passes to print out IR in various granularities.
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
ppc ctr loops PowerPC CTR Loops Verify
PassInstrumentationCallbacks PIC
This file defines the Pass Instrumentation classes that provide instrumentation points into the pass ...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file provides utility classes that use RAII to save and restore values.
This is the interface for a metadata-based scoped no-alias analysis.
This file defines the SmallVector class.
static const char StopAfterOptName[]
static cl::opt< bool > DisableExpandReductions("disable-expand-reductions", cl::init(false), cl::Hidden, cl::desc("Disable the expand reduction intrinsics pass from running"))
Disable the expand reductions pass for testing.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
static cl::opt< cl::boolOrDefault > DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before and Strip debug after " "each pass except those known to be unsafe " "when debug info is present"))
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
static cl::opt< bool > DisableAtExitBasedGlobalDtorLowering("disable-atexit-based-global-dtor-lowering", cl::Hidden, cl::desc("For MachO, disable atexit()-based global destructor lowering"))
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
static std::string getFSRemappingFile(const TargetMachine *TM)
static const char StopBeforeOptName[]
static AnalysisID getPassIDFromName(StringRef PassName)
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
static cl::opt< bool > DisableReplaceWithVecLib("disable-replace-with-vec-lib", cl::Hidden, cl::desc("Disable replace with vector math call pass"))
static cl::opt< bool > EnableMachineFunctionSplitter("enable-split-machine-functions", cl::Hidden, cl::desc("Split out cold blocks from machine functions based on profile " "information."))
Enable the machine function splitter pass.
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
static cl::opt< bool > PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden, cl::desc("Print machine instrs after ISel"))
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"))
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
#define SET_BOOLEAN_OPTION(Option)
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
static cl::opt< bool > DisableRAFSProfileLoader("disable-ra-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before RegAlloc"))
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static void initializeDefaultRegisterAllocatorOnce()
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
static cl::opt< bool > DisableSelectOptimize("disable-select-optimize", cl::init(true), cl::Hidden, cl::desc("Disable the select-optimization pass from running"))
Disable the select optimization pass.
static cl::opt< std::string > FSRemappingFile("fs-remapping-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden)
static cl::opt< bool > DisableCFIFixup("disable-cfi-fixup", cl::Hidden, cl::desc("Disable the CFI fixup pass"))
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static const char StartBeforeOptName[]
static const PassInfo * getPassInfo(StringRef PassName)
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \"global\" instruction selector"))
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
static const char StartAfterOptName[]
Option names for limiting the codegen pipeline.
static cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
static std::string getFSProfileFile(const TargetMachine *TM)
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
static cl::opt< bool > GCEmptyBlocks("gc-empty-basic-blocks", cl::init(false), cl::Hidden, cl::desc("Enable garbage-collecting empty basic blocks"))
Enable garbage-collecting empty basic blocks.
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector"))
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
#define DISABLE_PASS(Option, Name)
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
static cl::opt< bool > DisableLayoutFSProfileLoader("disable-layout-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before BlockPlacement"))
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault), cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(RunOutliner::NeverOutline, "never", "Disable all outlining"), clEnumValN(RunOutliner::AlwaysOutline, "", "")))
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
static cl::opt< std::string > FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile file name."), cl::Hidden)
static cl::opt< cl::boolOrDefault > DebugifyCheckAndStripAll("debugify-check-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before, by checking and stripping the debug info after, " "each pass except those known to be unsafe when debug info is " "present"))
#define SET_OPTION(Option)
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
This is the interface for a metadata-based TBAA.
Defines the virtual file system interface vfs::FileSystem.
static const char PassName[]
Definition: Any.h:28
This pass is required by interprocedural register allocation.
Tagged union holding either a T or a Error.
Definition: Error.h:481
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:310
Discriminated union of Pass ID types.
AnalysisID getID() const
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:281
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:740
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
PassInfo class - An instance of this class exists for every pass known by the system,...
Definition: PassInfo.h:30
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass... TODO : Rename
Definition: PassInfo.h:63
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
void registerShouldRunOptionalPassCallback(CallableT C)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:200
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:113
RegisterPassParser class - Handle the addition of new machine passes.
static void setDefault(FunctionPassCtor C)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:226
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:950
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:455
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const Triple & getTargetTriple() const
void setFastISel(bool Enable)
const MemoryBuffer * getBBSectionsFuncListBuf() const
Get the list of functions and basic block ids that need unique sections.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
bool requiresStructuredCFG() const
void setGlobalISel(bool Enable)
TargetIRAnalysis getTargetIRAnalysis() const
Get a TargetIRAnalysis appropriate for the target.
TargetOptions Options
void setO0WantsFastISel(bool Enable)
llvm::BasicBlockSection getBBSectionsType() const
If basic blocks should be emitted into their own section, corresponding to -fbasic-block-sections.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
unsigned EnableCFIFixup
Enable the CFIFixup pass.
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
unsigned EnableMachineFunctionSplitter
Enables the MachineFunctionSplitter pass.
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
Target-Independent Code Generator Pass Configuration Options.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
bool requiresCodeGenSCCOrder() const
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
LLVMTargetMachine * TM
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
bool EnableLoopTermFold
Enable LoopTermFold immediately after LSR.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
static Expected< StartStopInfo > getStartStopInfo(PassInstrumentationCallbacks &PIC)
Returns pass name in -stop-before or -stop-after NOTE: New pass manager migration only.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
CodeGenOptLevel getOptLevel() const
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
void setOpt(bool &Opt, bool Val)
virtual void addBlockPlacement()
Add standard basic block placement passes.
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
virtual void addPostBBSections()
This pass may be implemented by targets that want to run passes immediately after basic block section...
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
bool isCustomizedRegAlloc()
Return true if register allocator is specified by -regalloc=override.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
virtual bool addRegAssignAndRewriteOptimized()
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
static std::string getLimitedCodeGenPipelineReason()
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options that ...
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
bool addCoreISelPasses()
Add the actual instruction selection passes.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:732
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
static raw_ostream & warning()
Convenience method for printing "warning: " to stderr.
Definition: WithColor.cpp:85
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ ValueOptional
Definition: CommandLine.h:130
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:711
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
char & FEntryInserterID
This pass inserts FEntry calls.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
FunctionPass * createSjLjEHPreparePass(const TargetMachine *TM)
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
FunctionPass * createTLSVariableHoistPass()
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
char & InitUndefID
Definition: InitUndef.cpp:98
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
MachineFunctionPass * createBasicBlockPathCloningPass()
FunctionPass * createConstantHoistingPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:974
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
@ SjLj
setjmp/longjmp based exceptions
@ ZOS
z/OS MVS Exception Handling.
@ None
No exception support.
@ AIX
AIX Exception Handling.
@ DwarfCFI
DWARF-like instruction based exceptions.
@ WinEH
Windows Exception Handling.
@ Wasm
WebAssembly Exception Handling.
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly's exception handling s...
char & FixupStatepointCallerSavedID
The pass fixups statepoint machine instruction to replace usage of caller saved registers with stack ...
MachineFunctionPass * createBasicBlockSectionsPass()
createBasicBlockSections Pass - This pass assigns sections to machine basic blocks and is enabled wit...
FunctionPass * createPostInlineEntryExitInstrumenterPass()
MachineFunctionPass * createPrologEpilogInserterPass()
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
MachineFunctionPass * createGCEmptyBasicBlocksPass()
createGCEmptyBasicblocksPass - Empty basic blocks (basic blocks without real code) appear as the resu...
FunctionPass * createCallBrPass()
ModulePass * createStripDebugMachineModulePass(bool OnlyDebugified)
Creates MIR Strip Debug pass.
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
FunctionPass * createScalarizeMaskedMemIntrinLegacyPass()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
Pass * createLoopTermFoldPass()
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
char & LiveDebugValuesID
LiveDebugValues pass.
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
FunctionPass * createExpandLargeFpConvertPass()
ImmutablePass * createBasicBlockSectionsProfileReaderWrapperPass(const MemoryBuffer *Buf)
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
cl::opt< bool > EnableFSDiscriminator
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
MachineFunctionPass * createStackFrameLayoutAnalysisPass()
StackFramePrinter pass - This pass prints out the machine function's stack frame to the given stream ...
FunctionPass * createMIRAddFSDiscriminatorsPass(sampleprof::FSDiscriminatorPass P)
Add Flow Sensitive Discriminators.
char & MachineSanitizerBinaryMetadataID
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
void initializeAAResultsWrapperPassPass(PassRegistry &)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:288
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
ImmutablePass * createScopedNoAliasAAWrapperPass()
FunctionPass * createExpandMemCmpLegacyPass()
ModulePass * createLowerGlobalDtorsLegacyPass()
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:85
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
FunctionPass * createCodeGenPrepareLegacyPass()
createCodeGenPrepareLegacyPass - Transform the code to expose more pattern matching during instructio...
char & RemoveRedundantDebugValuesID
RemoveRedundantDebugValues pass.
FunctionPass * createBasicAAWrapperPass()
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
FunctionPass * createDwarfEHPass(CodeGenOptLevel OptLevel)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation.
FunctionPass * createRegAllocScoringPass()
When learning an eviction policy, extract score(reward) information, otherwise this does nothing.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
const void * AnalysisID
Definition: Pass.h:50
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createExpandLargeDivRemPass()
Pass * createMergeICmpsLegacyPass()
Definition: MergeICmps.cpp:913
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
ModulePass * createCheckDebugMachineModulePass()
Creates MIR Check Debug pass.
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
ImmutablePass * createTypeBasedAAWrapperPass()
FunctionPass * createMIRProfileLoaderPass(std::string File, std::string RemappingFile, sampleprof::FSDiscriminatorPass P, IntrusiveRefCntPtr< vfs::FileSystem > FS)
Read Flow Sensitive Profile.
FunctionPass * createCFIFixup()
Creates CFI Fixup pass.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:165
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:7563
void initializeBasicAAWrapperPassPass(PassRegistry &)
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
Pass * createLoopStrengthReducePass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createExpandReductionsPass()
This pass expands the reduction intrinsics into sequences of shuffles.
MachineFunctionPass * createMachineFunctionSplitterPass()
createMachineFunctionSplitterPass - This pass splits machine functions using profile information.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
FunctionPass * createReplaceWithVeclibLegacyPass()
char & FinalizeISelID
This pass expands pseudo-instructions, reserves registers and adjusts machine frame information.
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
FunctionPass * createPartiallyInlineLibCallsPass()
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Pass * createCanonicalizeFreezeInLoopsPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Pass * createObjCARCContractPass()
ModulePass * createDebugifyMachineModulePass()
Creates MIR Debugify pass.
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed.
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:20
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
CGPassBuilderOption getCGPassBuilderOption()
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
A utility class that uses RAII to save and restore the value of a variable.
The llvm::once_flag structure.
Definition: Threading.h:68