59 cl::desc(
"Enable interprocedural register allocation "
60 "to reduce load/store at procedure calls."));
62 cl::desc(
"Disable Post Regalloc Scheduler"));
66 cl::desc(
"Disable tail duplication"));
68 cl::desc(
"Disable pre-register allocation tail duplication"));
74 cl::desc(
"Disable Stack Slot Coloring"));
76 cl::desc(
"Disable Machine Dead Code Elimination"));
78 cl::desc(
"Disable Early If-conversion"));
82 cl::desc(
"Disable Machine Common Subexpression Elimination"));
85 cl::desc(
"Enable optimized register allocation compilation path."));
90 cl::desc(
"Disable Machine Sinking"));
93 cl::desc(
"Disable PostRA Machine Sinking"));
95 cl::desc(
"Disable Loop Strength Reduction Pass"));
99 cl::desc(
"Disable Codegen Prepare"));
101 cl::desc(
"Disable Copy Propagation pass"));
105 "disable-atexit-based-global-dtor-lowering",
cl::Hidden,
106 cl::desc(
"For MachO, disable atexit()-based global destructor lowering"));
108 "enable-implicit-null-checks",
109 cl::desc(
"Fold null checks into faulting memory operations"),
112 cl::desc(
"Disable MergeICmps Pass"),
115 cl::desc(
"Print LLVM IR produced by the loop-reduce pass"));
117 cl::desc(
"Print LLVM IR input to isel pass"));
119 cl::desc(
"Dump garbage collector data"));
122 cl::desc(
"Verify generated machine code"));
125 cl::desc(
"Debugify MIR before and Strip debug after "
126 "each pass except those known to be unsafe "
127 "when debug info is present"));
129 "debugify-check-and-strip-all-safe",
cl::Hidden,
131 "Debugify MIR before, by checking and stripping the debug info after, "
132 "each pass except those known to be unsafe when debug info is "
136 "enable-machine-outliner",
cl::desc(
"Enable the machine outliner"),
139 "Run on all functions guaranteed to be beneficial"),
140 clEnumValN(RunOutliner::NeverOutline,
"never",
141 "Disable all outlining"),
143 clEnumValN(RunOutliner::AlwaysOutline,
"",
"")));
148 cl::desc(
"Disable the CFI fixup pass"));
154 cl::desc(
"Enable the \"fast\" instruction selector"));
158 cl::desc(
"Enable the \"global\" instruction selector"));
164 cl::desc(
"Print machine instrs after ISel"));
168 cl::desc(
"Enable abort calls when \"global\" instruction selection "
169 "fails to lower/select an instruction"),
171 clEnumValN(GlobalISelAbortMode::Disable,
"0",
"Disable the abort"),
172 clEnumValN(GlobalISelAbortMode::Enable,
"1",
"Enable the abort"),
173 clEnumValN(GlobalISelAbortMode::DisableWithDiag,
"2",
174 "Disable the abort but emit a diagnostic on failure")));
180 cl::desc(
"Disable MIRProfileLoader before RegAlloc"));
185 cl::desc(
"Disable MIRProfileLoader before BlockPlacement"));
203 "Run MachineScheduler post regalloc (independent of preRA sched)"));
207 cl::desc(
"Run live interval analysis earlier in the pipeline"));
219 cl::desc(
"Resume compilation after a specific pass"),
224 cl::desc(
"Resume compilation before a specific pass"),
229 cl::desc(
"Stop compilation after a specific pass"),
234 cl::desc(
"Stop compilation before a specific pass"),
240 cl::desc(
"Split out cold blocks from machine functions based on profile "
246 cl::desc(
"Disable the expand reduction intrinsics pass from running"));
251 cl::desc(
"Disable the select-optimization pass from running"));
256 cl::desc(
"Enable garbage-collecting empty basic blocks"));
333 const std::optional<PGOOptions> &PGOOpt =
TM->getPGOOption();
335 return std::string();
336 return PGOOpt->ProfileFile;
344 const std::optional<PGOOptions> &PGOOpt =
TM->getPGOOption();
346 return std::string();
347 return PGOOpt->ProfileRemappingFile;
355 "Target Pass Configuration",
false,
false)
365 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID) {}
372 assert(NP &&
"Pass ID not registered");
414 Twine(
"\" pass is not registered."));
423static std::pair<StringRef, unsigned>
428 unsigned InstanceNum = 0;
432 return std::make_pair(
Name, InstanceNum);
435void TargetPassConfig::setStartStopPasses() {
437 std::tie(StartBeforeName, StartBeforeInstanceNum) =
441 std::tie(StartAfterName, StartAfterInstanceNum) =
445 std::tie(StopBeforeName, StopBeforeInstanceNum)
449 std::tie(StopAfterName, StopAfterInstanceNum)
456 if (StartBefore && StartAfter)
459 if (StopBefore && StopAfter)
462 Started = (StartAfter ==
nullptr) && (StartBefore ==
nullptr);
468#define SET_OPTION(Option) \
469 if (Option.getNumOccurrences()) \
479#define SET_BOOLEAN_OPTION(Option) Opt.Option = Option;
506 unsigned StartBeforeInstanceNum = 0;
507 unsigned StartAfterInstanceNum = 0;
508 unsigned StopBeforeInstanceNum = 0;
509 unsigned StopAfterInstanceNum = 0;
511 std::tie(StartBefore, StartBeforeInstanceNum) =
513 std::tie(StartAfter, StartAfterInstanceNum) =
515 std::tie(StopBefore, StopBeforeInstanceNum) =
517 std::tie(StopAfter, StopAfterInstanceNum) =
524 std::tie(StartBefore, std::ignore) =
526 std::tie(StartAfter, std::ignore) =
528 std::tie(StopBefore, std::ignore) =
530 std::tie(StopAfter, std::ignore) =
532 if (!StartBefore.
empty() && !StartAfter.
empty())
535 if (!StopBefore.
empty() && !StopAfter.
empty())
540 [=, EnableCurrent = StartBefore.
empty() && StartAfter.
empty(),
541 EnableNext = std::optional<bool>(), StartBeforeCount = 0u,
542 StartAfterCount = 0u, StopBeforeCount = 0u,
544 bool StartBeforePass = !StartBefore.empty() && P.contains(StartBefore);
545 bool StartAfterPass = !StartAfter.empty() && P.contains(StartAfter);
546 bool StopBeforePass = !StopBefore.empty() && P.contains(StopBefore);
547 bool StopAfterPass = !StopAfter.empty() && P.contains(StopAfter);
551 EnableCurrent = *EnableNext;
557 if (StartAfterPass && StartAfterCount++ == StartAfterInstanceNum) {
558 assert(!EnableNext &&
"Error: assign to EnableNext more than once");
561 if (StopAfterPass && StopAfterCount++ == StopAfterInstanceNum) {
562 assert(!EnableNext &&
"Error: assign to EnableNext more than once");
566 if (StartBeforePass && StartBeforeCount++ == StartBeforeInstanceNum)
567 EnableCurrent =
true;
568 if (StopBeforePass && StopBeforeCount++ == StopBeforeInstanceNum)
569 EnableCurrent =
false;
570 return EnableCurrent;
580#define DISABLE_PASS(Option, Name) \
581 if (Option && P.contains(#Name)) \
631 setStartStopPasses();
642 TargetPassID != InsertedPassID.
getID()) ||
645 "Insert a pass after itself!");
660 "machine. Scheduling a CodeGen pass without a target "
676 return std::string();
684 if (!PassNames[
Idx]->empty()) {
688 Res += OptNames[
Idx];
733 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
735 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
737 if (Started && !Stopped) {
738 if (AddingMachinePasses) {
741 std::string(
"After ") + std::string(
P->getPassName());
751 if (IP.TargetPassID == PassID)
757 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
760 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
762 if (Stopped && !Started)
803#ifdef EXPENSIVE_CHECKS
824 if (AllowDebugify && DebugifyIsSafe &&
831 if (DebugifyIsSafe) {
864 "\n\n*** Code after LSR ***\n"));
928 assert(MCAI &&
"No MCAsmInfo");
993 dbgs(),
"\n\n*** Final LLVM Code input to ISel ***\n"));
1007 SelectorType Selector;
1010 Selector = SelectorType::FastISel;
1014 Selector = SelectorType::GlobalISel;
1017 Selector = SelectorType::FastISel;
1019 Selector = SelectorType::SelectionDAG;
1022 if (Selector == SelectorType::FastISel) {
1025 }
else if (Selector == SelectorType::GlobalISel) {
1041 DebugifyIsSafe =
false;
1044 if (Selector == SelectorType::GlobalISel) {
1045 SaveAndRestore SavedAddingMachinePasses(AddingMachinePasses,
true);
1109 cl::desc(
"Register allocator to use"));
1130 AddingMachinePasses =
true;
1150 DebugifyIsSafe =
false;
1247 bool RunOnAllFunctions =
1276 if (!ProfileFile.empty()) {
1285 <<
"Using AutoFDO without FSDiscriminator for MFS may regress "
1302 AddingMachinePasses =
false;
1364 "pick register allocator based on -O option",
1417 report_fatal_error(
"Must use fast (default) register allocator for unoptimized regalloc.");
1446 return RegAlloc.getNumOccurrences() == 0;
1580 return std::make_unique<CSEConfigBase>();
This is the interface for LLVM's primary stateless and local alias analysis.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file contains an interface for creating legacy passes to print out IR in various granularities.
ppc ctr loops PowerPC CTR Loops Verify
const char LLVMTargetMachineRef TM
PassInstrumentationCallbacks PIC
This file defines the Pass Instrumentation classes that provide instrumentation points into the pass ...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file provides utility classes that use RAII to save and restore values.
This is the interface for a metadata-based scoped no-alias analysis.
This file defines the SmallVector class.
static const char StopAfterOptName[]
static cl::opt< bool > DisableExpandReductions("disable-expand-reductions", cl::init(false), cl::Hidden, cl::desc("Disable the expand reduction intrinsics pass from running"))
Disable the expand reductions pass for testing.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
static cl::opt< cl::boolOrDefault > DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before and Strip debug after " "each pass except those known to be unsafe " "when debug info is present"))
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
static cl::opt< bool > DisableAtExitBasedGlobalDtorLowering("disable-atexit-based-global-dtor-lowering", cl::Hidden, cl::desc("For MachO, disable atexit()-based global destructor lowering"))
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
static void registerPartialPipelineCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &LLVMTM)
static std::string getFSRemappingFile(const TargetMachine *TM)
static const char StopBeforeOptName[]
static AnalysisID getPassIDFromName(StringRef PassName)
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
static cl::opt< bool > EnableMachineFunctionSplitter("enable-split-machine-functions", cl::Hidden, cl::desc("Split out cold blocks from machine functions based on profile " "information."))
Enable the machine function splitter pass.
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
static cl::opt< bool > PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden, cl::desc("Print machine instrs after ISel"))
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"))
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
#define SET_BOOLEAN_OPTION(Option)
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
static cl::opt< bool > DisableRAFSProfileLoader("disable-ra-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before RegAlloc"))
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static void initializeDefaultRegisterAllocatorOnce()
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
static cl::opt< bool > DisableSelectOptimize("disable-select-optimize", cl::init(true), cl::Hidden, cl::desc("Disable the select-optimization pass from running"))
Disable the select optimization pass.
static cl::opt< std::string > FSRemappingFile("fs-remapping-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden)
static cl::opt< bool > DisableCFIFixup("disable-cfi-fixup", cl::Hidden, cl::desc("Disable the CFI fixup pass"))
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static const char StartBeforeOptName[]
static const PassInfo * getPassInfo(StringRef PassName)
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \"global\" instruction selector"))
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
static const char StartAfterOptName[]
Option names for limiting the codegen pipeline.
static cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
static std::string getFSProfileFile(const TargetMachine *TM)
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
static cl::opt< bool > GCEmptyBlocks("gc-empty-basic-blocks", cl::init(false), cl::Hidden, cl::desc("Enable garbage-collecting empty basic blocks"))
Enable garbage-collecting empty basic blocks.
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector"))
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
#define DISABLE_PASS(Option, Name)
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
static cl::opt< bool > DisableLayoutFSProfileLoader("disable-layout-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before BlockPlacement"))
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault), cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(RunOutliner::NeverOutline, "never", "Disable all outlining"), clEnumValN(RunOutliner::AlwaysOutline, "", "")))
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
static cl::opt< std::string > FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile file name."), cl::Hidden)
static cl::opt< cl::boolOrDefault > DebugifyCheckAndStripAll("debugify-check-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before, by checking and stripping the debug info after, " "each pass except those known to be unsafe when debug info is " "present"))
#define SET_OPTION(Option)
Target-Independent Code Generator Pass Configuration Options pass.
This is the interface for a metadata-based TBAA.
Defines the virtual file system interface vfs::FileSystem.
static const char PassName[]
This pass is required by interprocedural register allocation.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionPass class - This class is used to implement most global optimizations.
Discriminated union of Pass ID types.
Pass * getInstance() const
ImmutablePass class - This class is used to provide information that does not need to be run.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
virtual std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef)
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
PassInfo class - An instance of this class exists for every pass known by the system,...
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass... TODO : Rename
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
void registerShouldRunOptionalPassCallback(CallableT C)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
Pass interface - Implemented by all 'passes'.
static Pass * createPass(AnalysisID ID)
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
RegisterPassParser class - Handle the addition of new machine passes.
static FunctionPassCtor getDefault()
static void setDefault(FunctionPassCtor C)
FunctionPass *(*)() FunctionPassCtor
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
constexpr bool empty() const
empty - Check if the string is empty.
Primary interface to the complete machine description for the target machine.
const Triple & getTargetTriple() const
void setFastISel(bool Enable)
const MemoryBuffer * getBBSectionsFuncListBuf() const
Get the list of functions and basic block ids that need unique sections.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
bool requiresStructuredCFG() const
void setGlobalISel(bool Enable)
TargetIRAnalysis getTargetIRAnalysis() const
Get a TargetIRAnalysis appropriate for the target.
bool getO0WantsFastISel()
void setO0WantsFastISel(bool Enable)
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
llvm::BasicBlockSection getBBSectionsType() const
If basic blocks should be emitted into their own section, corresponding to -fbasic-block-sections.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
unsigned EnableCFIFixup
Enable the CFIFixup pass.
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
unsigned EnableMachineFunctionSplitter
Enables the MachineFunctionSplitter pass.
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
Target-Independent Code Generator Pass Configuration Options.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
bool requiresCodeGenSCCOrder() const
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
~TargetPassConfig() override
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
CodeGenOptLevel getOptLevel() const
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
void setOpt(bool &Opt, bool Val)
virtual void addBlockPlacement()
Add standard basic block placement passes.
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
virtual void addPostBBSections()
This pass may be implemented by targets that want to run passes immediately after basic block section...
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
bool isCustomizedRegAlloc()
Return true if register allocator is specified by -regalloc=override.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
virtual bool addRegAssignAndRewriteOptimized()
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
bool addCoreISelPasses()
Add the actual instruction selection passes.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static raw_ostream & warning()
Convenience method for printing "warning: " to stderr.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
char & FEntryInserterID
This pass inserts FEntry calls.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
FunctionPass * createSjLjEHPreparePass(const TargetMachine *TM)
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
FunctionPass * createTLSVariableHoistPass()
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
MachineFunctionPass * createBasicBlockPathCloningPass()
FunctionPass * createConstantHoistingPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
@ SjLj
setjmp/longjmp based exceptions
@ None
No exception support.
@ AIX
AIX Exception Handling.
@ DwarfCFI
DWARF-like instruction based exceptions.
@ WinEH
Windows Exception Handling.
@ Wasm
WebAssembly Exception Handling.
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly's exception handling s...
char & FixupStatepointCallerSavedID
The pass fixups statepoint machine instruction to replace usage of caller saved registers with stack ...
FunctionPass * createExpandVectorPredicationPass()
This pass expands the vector predication intrinsics into unpredicated instructions with selects or ju...
MachineFunctionPass * createBasicBlockSectionsPass()
createBasicBlockSections Pass - This pass assigns sections to machine basic blocks and is enabled wit...
MachineFunctionPass * createPrologEpilogInserterPass()
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
MachineFunctionPass * createGCEmptyBasicBlocksPass()
createGCEmptyBasicblocksPass - Empty basic blocks (basic blocks without real code) appear as the resu...
ModulePass * createStripDebugMachineModulePass(bool OnlyDebugified)
Creates MIR Strip Debug pass.
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
FunctionPass * createScalarizeMaskedMemIntrinLegacyPass()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
char & LiveDebugValuesID
LiveDebugValues pass.
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
FunctionPass * createExpandLargeFpConvertPass()
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
cl::opt< bool > EnableFSDiscriminator
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
MachineFunctionPass * createStackFrameLayoutAnalysisPass()
StackFramePrinter pass - This pass prints out the machine function's stack frame to the given stream ...
FunctionPass * createMIRAddFSDiscriminatorsPass(sampleprof::FSDiscriminatorPass P)
Add Flow Sensitive Discriminators.
char & MachineSanitizerBinaryMetadataID
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
void initializeAAResultsWrapperPassPass(PassRegistry &)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
ImmutablePass * createScopedNoAliasAAWrapperPass()
ModulePass * createLowerGlobalDtorsLegacyPass()
FunctionPass * createLowerInvokePass()
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
FunctionPass * createExpandMemCmpPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
char & RemoveRedundantDebugValuesID
RemoveRedundantDebugValues pass.
FunctionPass * createBasicAAWrapperPass()
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
FunctionPass * createDwarfEHPass(CodeGenOptLevel OptLevel)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation.
FunctionPass * createRegAllocScoringPass()
When learning an eviction policy, extract score(reward) information, otherwise this does nothing.
CodeGenOptLevel
Code generation optimization level.
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createExpandLargeDivRemPass()
Pass * createMergeICmpsLegacyPass()
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
ModulePass * createCheckDebugMachineModulePass()
Creates MIR Check Debug pass.
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
ImmutablePass * createTypeBasedAAWrapperPass()
FunctionPass * createMIRProfileLoaderPass(std::string File, std::string RemappingFile, sampleprof::FSDiscriminatorPass P, IntrusiveRefCntPtr< vfs::FileSystem > FS)
Read Flow Sensitive Profile.
FunctionPass * createCFIFixup()
Creates CFI Fixup pass.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
FunctionPass * createVerifierPass(bool FatalErrors=true)
void initializeBasicAAWrapperPassPass(PassRegistry &)
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
Pass * createLoopStrengthReducePass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createExpandReductionsPass()
This pass expands the reduction intrinsics into sequences of shuffles.
MachineFunctionPass * createMachineFunctionSplitterPass()
createMachineFunctionSplitterPass - This pass splits machine functions using profile information.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created.
char & VirtRegRewriterID
VirtRegRewriter pass.
FunctionPass * createReplaceWithVeclibLegacyPass()
FunctionPass * createLowerConstantIntrinsicsPass()
ImmutablePass * createBasicBlockSectionsProfileReaderPass(const MemoryBuffer *Buf)
char & FinalizeISelID
This pass expands pseudo-instructions, reserves registers and adjusts machine frame information.
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
FunctionPass * createPartiallyInlineLibCallsPass()
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Pass * createCanonicalizeFreezeInLoopsPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
ModulePass * createDebugifyMachineModulePass()
Creates MIR Debugify pass.
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed.
FunctionPass * createCallBrPass()
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
CGPassBuilderOption getCGPassBuilderOption()
IdentifyingPassPtr InsertedPassID
Pass * getInsertedPass() const
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
A utility class that uses RAII to save and restore the value of a variable.
The llvm::once_flag structure.