LLVM  10.0.0svn
TargetPassConfig.cpp
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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines interfaces to access the target independent code
10 // generation passes provided by the LLVM backend.
11 //
12 //===---------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/Verifier.h"
33 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Threading.h"
44 #include "llvm/Transforms/Scalar.h"
45 #include "llvm/Transforms/Utils.h"
47 #include <cassert>
48 #include <string>
49 
50 using namespace llvm;
51 
52 static cl::opt<bool>
53  EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
54  cl::desc("Enable interprocedural register allocation "
55  "to reduce load/store at procedure calls."));
56 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
57  cl::desc("Disable Post Regalloc Scheduler"));
58 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
59  cl::desc("Disable branch folding"));
60 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
61  cl::desc("Disable tail duplication"));
62 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
63  cl::desc("Disable pre-register allocation tail duplication"));
64 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
65  cl::Hidden, cl::desc("Disable probability-driven block placement"));
66 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
67  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
68 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
69  cl::desc("Disable Stack Slot Coloring"));
70 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
71  cl::desc("Disable Machine Dead Code Elimination"));
72 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
73  cl::desc("Disable Early If-conversion"));
74 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
75  cl::desc("Disable Machine LICM"));
76 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
77  cl::desc("Disable Machine Common Subexpression Elimination"));
79  "optimize-regalloc", cl::Hidden,
80  cl::desc("Enable optimized register allocation compilation path."));
81 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
82  cl::Hidden,
83  cl::desc("Disable Machine LICM"));
84 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
85  cl::desc("Disable Machine Sinking"));
86 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
87  cl::Hidden,
88  cl::desc("Disable PostRA Machine Sinking"));
89 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
90  cl::desc("Disable Loop Strength Reduction Pass"));
91 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
92  cl::Hidden, cl::desc("Disable ConstantHoisting"));
93 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
94  cl::desc("Disable Codegen Prepare"));
95 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
96  cl::desc("Disable Copy Propagation pass"));
97 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
98  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
100  "enable-implicit-null-checks",
101  cl::desc("Fold null checks into faulting memory operations"),
102  cl::init(false), cl::Hidden);
103 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
104  cl::desc("Disable MergeICmps Pass"),
105  cl::init(false), cl::Hidden);
106 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
107  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
108 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
109  cl::desc("Print LLVM IR input to isel pass"));
110 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
111  cl::desc("Dump garbage collector data"));
113  VerifyMachineCode("verify-machineinstrs", cl::Hidden,
114  cl::desc("Verify generated machine code"),
117 // Enable or disable the MachineOutliner.
119  "enable-machine-outliner", cl::desc("Enable the machine outliner"),
120  cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
122  "Run on all functions guaranteed to be beneficial"),
123  clEnumValN(NeverOutline, "never", "Disable all outlining"),
124  // Sentinel value for unspecified option.
125  clEnumValN(AlwaysOutline, "", "")));
126 // Enable or disable FastISel. Both options are needed, because
127 // FastISel is enabled by default with -fast, and we wish to be
128 // able to enable or disable fast-isel independently from -O0.
130 EnableFastISelOption("fast-isel", cl::Hidden,
131  cl::desc("Enable the \"fast\" instruction selector"));
132 
134  "global-isel", cl::Hidden,
135  cl::desc("Enable the \"global\" instruction selector"));
136 
138  "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
139  cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
140 
142  "global-isel-abort", cl::Hidden,
143  cl::desc("Enable abort calls when \"global\" instruction selection "
144  "fails to lower/select an instruction"),
145  cl::values(
146  clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
147  clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
149  "Disable the abort but emit a diagnostic on failure")));
150 
151 // Temporary option to allow experimenting with MachineScheduler as a post-RA
152 // scheduler. Targets can "properly" enable this with
153 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
154 // Targets can return true in targetSchedulesPostRAScheduling() and
155 // insert a PostRA scheduling pass wherever it wants.
157  "misched-postra", cl::Hidden,
158  cl::desc(
159  "Run MachineScheduler post regalloc (independent of preRA sched)"));
160 
161 // Experimental option to run live interval analysis early.
162 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
163  cl::desc("Run live interval analysis earlier in the pipeline"));
164 
165 // Experimental option to use CFL-AA in codegen
168  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
169  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
170  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
172  "Enable unification-based CFL-AA"),
174  "Enable inclusion-based CFL-AA"),
175  clEnumValN(CFLAAType::Both, "both",
176  "Enable both variants of CFL-AA")));
177 
178 /// Option names for limiting the codegen pipeline.
179 /// Those are used in error reporting and we didn't want
180 /// to duplicate their names all over the place.
181 static const char *StartAfterOptName = "start-after";
182 static const char *StartBeforeOptName = "start-before";
183 static const char *StopAfterOptName = "stop-after";
184 static const char *StopBeforeOptName = "stop-before";
185 
187  StartAfterOpt(StringRef(StartAfterOptName),
188  cl::desc("Resume compilation after a specific pass"),
189  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
190 
192  StartBeforeOpt(StringRef(StartBeforeOptName),
193  cl::desc("Resume compilation before a specific pass"),
194  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
195 
197  StopAfterOpt(StringRef(StopAfterOptName),
198  cl::desc("Stop compilation after a specific pass"),
199  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
200 
202  StopBeforeOpt(StringRef(StopBeforeOptName),
203  cl::desc("Stop compilation before a specific pass"),
204  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
205 
206 /// Allow standard passes to be disabled by command line options. This supports
207 /// simple binary flags that either suppress the pass or do nothing.
208 /// i.e. -disable-mypass=false has no effect.
209 /// These should be converted to boolOrDefault in order to use applyOverride.
211  bool Override) {
212  if (Override)
213  return IdentifyingPassPtr();
214  return PassID;
215 }
216 
217 /// Allow standard passes to be disabled by the command line, regardless of who
218 /// is adding the pass.
219 ///
220 /// StandardID is the pass identified in the standard pass pipeline and provided
221 /// to addPass(). It may be a target-specific ID in the case that the target
222 /// directly adds its own pass, but in that case we harmlessly fall through.
223 ///
224 /// TargetID is the pass that the target has configured to override StandardID.
225 ///
226 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
227 /// pass to run. This allows multiple options to control a single pass depending
228 /// on where in the pipeline that pass is added.
230  IdentifyingPassPtr TargetID) {
231  if (StandardID == &PostRASchedulerID)
232  return applyDisable(TargetID, DisablePostRASched);
233 
234  if (StandardID == &BranchFolderPassID)
235  return applyDisable(TargetID, DisableBranchFold);
236 
237  if (StandardID == &TailDuplicateID)
238  return applyDisable(TargetID, DisableTailDuplicate);
239 
240  if (StandardID == &EarlyTailDuplicateID)
241  return applyDisable(TargetID, DisableEarlyTailDup);
242 
243  if (StandardID == &MachineBlockPlacementID)
244  return applyDisable(TargetID, DisableBlockPlacement);
245 
246  if (StandardID == &StackSlotColoringID)
247  return applyDisable(TargetID, DisableSSC);
248 
249  if (StandardID == &DeadMachineInstructionElimID)
250  return applyDisable(TargetID, DisableMachineDCE);
251 
252  if (StandardID == &EarlyIfConverterID)
253  return applyDisable(TargetID, DisableEarlyIfConversion);
254 
255  if (StandardID == &EarlyMachineLICMID)
256  return applyDisable(TargetID, DisableMachineLICM);
257 
258  if (StandardID == &MachineCSEID)
259  return applyDisable(TargetID, DisableMachineCSE);
260 
261  if (StandardID == &MachineLICMID)
262  return applyDisable(TargetID, DisablePostRAMachineLICM);
263 
264  if (StandardID == &MachineSinkingID)
265  return applyDisable(TargetID, DisableMachineSink);
266 
267  if (StandardID == &PostRAMachineSinkingID)
268  return applyDisable(TargetID, DisablePostRAMachineSink);
269 
270  if (StandardID == &MachineCopyPropagationID)
271  return applyDisable(TargetID, DisableCopyProp);
272 
273  return TargetID;
274 }
275 
276 //===---------------------------------------------------------------------===//
277 /// TargetPassConfig
278 //===---------------------------------------------------------------------===//
279 
280 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
281  "Target Pass Configuration", false, false)
282 char TargetPassConfig::ID = 0;
283 
284 namespace {
285 
286 struct InsertedPass {
291 
292  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
293  bool VerifyAfter, bool PrintAfter)
294  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
295  VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
296 
298  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
299  if (InsertedPassID.isInstance())
300  return InsertedPassID.getInstance();
301  Pass *NP = Pass::createPass(InsertedPassID.getID());
302  assert(NP && "Pass ID not registered");
303  return NP;
304  }
305 };
306 
307 } // end anonymous namespace
308 
309 namespace llvm {
310 
312 public:
313  // List of passes explicitly substituted by this target. Normally this is
314  // empty, but it is a convenient way to suppress or replace specific passes
315  // that are part of a standard pass pipeline without overridding the entire
316  // pipeline. This mechanism allows target options to inherit a standard pass's
317  // user interface. For example, a target may disable a standard pass by
318  // default by substituting a pass ID of zero, and the user may still enable
319  // that standard pass with an explicit command line option.
321 
322  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
323  /// is inserted after each instance of the first one.
325 };
326 
327 } // end namespace llvm
328 
329 // Out of line virtual method.
331  delete Impl;
332 }
333 
334 static const PassInfo *getPassInfo(StringRef PassName) {
335  if (PassName.empty())
336  return nullptr;
337 
339  const PassInfo *PI = PR.getPassInfo(PassName);
340  if (!PI)
341  report_fatal_error(Twine('\"') + Twine(PassName) +
342  Twine("\" pass is not registered."));
343  return PI;
344 }
345 
347  const PassInfo *PI = getPassInfo(PassName);
348  return PI ? PI->getTypeInfo() : nullptr;
349 }
350 
351 static std::pair<StringRef, unsigned>
353  StringRef Name, InstanceNumStr;
354  std::tie(Name, InstanceNumStr) = PassName.split(',');
355 
356  unsigned InstanceNum = 0;
357  if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
358  report_fatal_error("invalid pass instance specifier " + PassName);
359 
360  return std::make_pair(Name, InstanceNum);
361 }
362 
363 void TargetPassConfig::setStartStopPasses() {
364  StringRef StartBeforeName;
365  std::tie(StartBeforeName, StartBeforeInstanceNum) =
367 
368  StringRef StartAfterName;
369  std::tie(StartAfterName, StartAfterInstanceNum) =
371 
372  StringRef StopBeforeName;
373  std::tie(StopBeforeName, StopBeforeInstanceNum)
375 
376  StringRef StopAfterName;
377  std::tie(StopAfterName, StopAfterInstanceNum)
379 
380  StartBefore = getPassIDFromName(StartBeforeName);
381  StartAfter = getPassIDFromName(StartAfterName);
382  StopBefore = getPassIDFromName(StopBeforeName);
383  StopAfter = getPassIDFromName(StopAfterName);
384  if (StartBefore && StartAfter)
385  report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
386  Twine(StartAfterOptName) + Twine(" specified!"));
387  if (StopBefore && StopAfter)
388  report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
389  Twine(StopAfterOptName) + Twine(" specified!"));
390  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
391 }
392 
393 // Out of line constructor provides default values for pass options and
394 // registers all common codegen passes.
396  : ImmutablePass(ID), PM(&pm), TM(&TM) {
397  Impl = new PassConfigImpl();
398 
399  // Register all target independent codegen passes to activate their PassIDs,
400  // including this pass itself.
402 
403  // Also register alias analysis passes required by codegen passes.
406 
407  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
408  TM.Options.PrintMachineCode = true;
409 
410  if (EnableIPRA.getNumOccurrences())
412  else {
413  // If not explicitly specified, use target default.
414  TM.Options.EnableIPRA |= TM.useIPRA();
415  }
416 
417  if (TM.Options.EnableIPRA)
419 
420  if (EnableGlobalISelAbort.getNumOccurrences())
421  TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
422 
423  setStartStopPasses();
424 }
425 
427  return TM->getOptLevel();
428 }
429 
430 /// Insert InsertedPassID pass after TargetPassID.
432  IdentifyingPassPtr InsertedPassID,
433  bool VerifyAfter, bool PrintAfter) {
434  assert(((!InsertedPassID.isInstance() &&
435  TargetPassID != InsertedPassID.getID()) ||
436  (InsertedPassID.isInstance() &&
437  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
438  "Insert a pass after itself!");
439  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
440  PrintAfter);
441 }
442 
443 /// createPassConfig - Create a pass configuration object to be used by
444 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
445 ///
446 /// Targets may override this to extend TargetPassConfig.
448  return new TargetPassConfig(*this, PM);
449 }
450 
452  : ImmutablePass(ID) {
453  report_fatal_error("Trying to construct TargetPassConfig without a target "
454  "machine. Scheduling a CodeGen pass without a target "
455  "triple set?");
456 }
457 
459  return StopBeforeOpt.empty() && StopAfterOpt.empty();
460 }
461 
463  return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
465 }
466 
467 std::string
470  return std::string();
471  std::string Res;
472  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
474  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
475  StopAfterOptName, StopBeforeOptName};
476  bool IsFirst = true;
477  for (int Idx = 0; Idx < 4; ++Idx)
478  if (!PassNames[Idx]->empty()) {
479  if (!IsFirst)
480  Res += Separator;
481  IsFirst = false;
482  Res += OptNames[Idx];
483  }
484  return Res;
485 }
486 
487 // Helper to verify the analysis is really immutable.
488 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
489  assert(!Initialized && "PassConfig is immutable");
490  Opt = Val;
491 }
492 
494  IdentifyingPassPtr TargetID) {
495  Impl->TargetPasses[StandardID] = TargetID;
496 }
497 
500  I = Impl->TargetPasses.find(ID);
501  if (I == Impl->TargetPasses.end())
502  return ID;
503  return I->second;
504 }
505 
508  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
509  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
510  FinalPtr.getID() != ID;
511 }
512 
513 /// Add a pass to the PassManager if that pass is supposed to be run. If the
514 /// Started/Stopped flags indicate either that the compilation should start at
515 /// a later pass or that it should stop after an earlier pass, then do not add
516 /// the pass. Finally, compare the current pass against the StartAfter
517 /// and StopAfter options and change the Started/Stopped flags accordingly.
518 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
519  assert(!Initialized && "PassConfig is immutable");
520 
521  // Cache the Pass ID here in case the pass manager finds this pass is
522  // redundant with ones already scheduled / available, and deletes it.
523  // Fundamentally, once we add the pass to the manager, we no longer own it
524  // and shouldn't reference it.
525  AnalysisID PassID = P->getPassID();
526 
527  if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
528  Started = true;
529  if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
530  Stopped = true;
531  if (Started && !Stopped) {
532  std::string Banner;
533  // Construct banner message before PM->add() as that may delete the pass.
534  if (AddingMachinePasses && (printAfter || verifyAfter))
535  Banner = std::string("After ") + std::string(P->getPassName());
536  PM->add(P);
537  if (AddingMachinePasses) {
538  if (printAfter)
539  addPrintPass(Banner);
540  if (verifyAfter)
541  addVerifyPass(Banner);
542  }
543 
544  // Add the passes after the pass P if there is any.
545  for (auto IP : Impl->InsertedPasses) {
546  if (IP.TargetPassID == PassID)
547  addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
548  }
549  } else {
550  delete P;
551  }
552 
553  if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
554  Stopped = true;
555 
556  if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
557  Started = true;
558  if (Stopped && !Started)
559  report_fatal_error("Cannot stop compilation after pass that is not run");
560 }
561 
562 /// Add a CodeGen pass at this point in the pipeline after checking for target
563 /// and command line overrides.
564 ///
565 /// addPass cannot return a pointer to the pass instance because is internal the
566 /// PassManager and the instance we create here may already be freed.
568  bool printAfter) {
569  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
570  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
571  if (!FinalPtr.isValid())
572  return nullptr;
573 
574  Pass *P;
575  if (FinalPtr.isInstance())
576  P = FinalPtr.getInstance();
577  else {
578  P = Pass::createPass(FinalPtr.getID());
579  if (!P)
580  llvm_unreachable("Pass ID not registered");
581  }
582  AnalysisID FinalID = P->getPassID();
583  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
584 
585  return FinalID;
586 }
587 
588 void TargetPassConfig::printAndVerify(const std::string &Banner) {
589  addPrintPass(Banner);
590  addVerifyPass(Banner);
591 }
592 
593 void TargetPassConfig::addPrintPass(const std::string &Banner) {
594  if (TM->shouldPrintMachineCode())
595  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
596 }
597 
598 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
600 #ifdef EXPENSIVE_CHECKS
602  Verify = TM->isMachineVerifierClean();
603 #endif
604  if (Verify)
605  PM->add(createMachineVerifierPass(Banner));
606 }
607 
608 /// Add common target configurable passes that perform LLVM IR to IR transforms
609 /// following machine independent optimization.
611  switch (UseCFLAA) {
614  break;
615  case CFLAAType::Andersen:
617  break;
618  case CFLAAType::Both:
621  break;
622  default:
623  break;
624  }
625 
626  // Basic AliasAnalysis support.
627  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
628  // BasicAliasAnalysis wins if they disagree. This is intended to help
629  // support "obvious" type-punning idioms.
633 
634  // Before running any passes, run the verifier to determine if the input
635  // coming from the front-end and/or optimizer is valid.
636  if (!DisableVerify)
638 
639  // Run loop strength reduction before anything else.
640  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
642  if (PrintLSR)
643  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
644  }
645 
646  if (getOptLevel() != CodeGenOpt::None) {
647  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
648  // loads and compares. ExpandMemCmpPass then tries to expand those calls
649  // into optimally-sized loads and compares. The transforms are enabled by a
650  // target lowering hook.
651  if (!DisableMergeICmps)
654  }
655 
656  // Run GC lowering passes for builtin collectors
657  // TODO: add a pass insertion point here
661 
662  // Make sure that no unreachable blocks are instruction selected.
664 
665  // Prepare expensive constants for SelectionDAG.
668 
671 
672  // Instrument function entry and exit, e.g. with calls to mcount().
674 
675  // Add scalarization of target's unsupported masked memory intrinsics pass.
676  // the unsupported intrinsic will be replaced with a chain of basic blocks,
677  // that stores/loads element one-by-one if the appropriate mask bit is set.
679 
680  // Expand reduction intrinsics into shuffle sequences if the target wants to.
682 }
683 
684 /// Turn exception handling constructs into something the code generators can
685 /// handle.
687  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
688  assert(MCAI && "No MCAsmInfo");
689  switch (MCAI->getExceptionHandlingType()) {
691  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
692  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
693  // catch info can get misplaced when a selector ends up more than one block
694  // removed from the parent invoke(s). This could happen when a landing
695  // pad is shared by multiple invokes and is also a target of a normal
696  // edge from elsewhere.
702  break;
704  // We support using both GCC-style and MSVC-style exceptions on Windows, so
705  // add both preparation passes. Each pass will only actually run if it
706  // recognizes the personality function.
709  break;
711  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
712  // on catchpads and cleanuppads because it does not outline them into
713  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
714  // should remove PHIs there.
715  addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
717  break;
720 
721  // The lower invoke pass may create unreachable code. Remove it.
723  break;
724  }
725 }
726 
727 /// Add pass to prepare the LLVM IR for code generation. This should be done
728 /// before exception handling preparation passes.
733 }
734 
735 /// Add common passes that perform LLVM IR to IR transforms in preparation for
736 /// instruction selection.
738  addPreISel();
739 
740  // Force codegen to run according to the callgraph.
742  addPass(new DummyCGSCCPass);
743 
744  // Add both the safe stack and the stack protection passes: each of them will
745  // only protect functions that have corresponding attributes.
748 
749  if (PrintISelInput)
751  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
752 
753  // All passes which modify the LLVM IR are now complete; run the verifier
754  // to ensure that the IR is valid.
755  if (!DisableVerify)
757 }
758 
760  // Enable FastISel with -fast-isel, but allow that to be overridden.
761  TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
762 
763  // Determine an instruction selector.
764  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
765  SelectorType Selector;
766 
767  if (EnableFastISelOption == cl::BOU_TRUE)
768  Selector = SelectorType::FastISel;
769  else if (EnableGlobalISelOption == cl::BOU_TRUE ||
771  EnableGlobalISelOption != cl::BOU_FALSE))
772  Selector = SelectorType::GlobalISel;
773  else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
774  Selector = SelectorType::FastISel;
775  else
776  Selector = SelectorType::SelectionDAG;
777 
778  // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
779  if (Selector == SelectorType::FastISel) {
780  TM->setFastISel(true);
781  TM->setGlobalISel(false);
782  } else if (Selector == SelectorType::GlobalISel) {
783  TM->setFastISel(false);
784  TM->setGlobalISel(true);
785  }
786 
787  // Add instruction selector passes.
788  if (Selector == SelectorType::GlobalISel) {
789  SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
790  if (addIRTranslator())
791  return true;
792 
794 
795  if (addLegalizeMachineIR())
796  return true;
797 
798  // Before running the register bank selector, ask the target if it
799  // wants to run some passes.
801 
802  if (addRegBankSelect())
803  return true;
804 
806 
808  return true;
809 
810  // Pass to reset the MachineFunction if the ISel failed.
813 
814  // Provide a fallback path when we do not want to abort on
815  // not-yet-supported input.
817  return true;
818 
819  } else if (addInstSelector())
820  return true;
821 
822  // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
823  // FinalizeISel.
825 
826  // Print the instruction selected machine code...
827  printAndVerify("After Instruction Selection");
828 
829  return false;
830 }
831 
833  if (TM->useEmulatedTLS())
835 
838  addIRPasses();
841  addISelPrepare();
842 
843  return addCoreISelPasses();
844 }
845 
846 /// -regalloc=... command line option.
847 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
851  cl::desc("Register allocator to use"));
852 
853 /// Add the complete set of target-independent postISel code generator passes.
854 ///
855 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
856 /// with nontrivial configuration or multiple passes are broken out below in
857 /// add%Stage routines.
858 ///
859 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
860 /// addPre/Post methods with empty header implementations allow injecting
861 /// target-specific fixups just before or after major stages. Additionally,
862 /// targets have the flexibility to change pass order within a stage by
863 /// overriding default implementation of add%Stage routines below. Each
864 /// technique has maintainability tradeoffs because alternate pass orders are
865 /// not well supported. addPre/Post works better if the target pass is easily
866 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
867 /// the target should override the stage instead.
868 ///
869 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
870 /// before/after any target-independent pass. But it's currently overkill.
872  AddingMachinePasses = true;
873 
874  // Insert a machine instr printer pass after the specified pass.
875  StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
876  if (!PrintMachineInstrsPassName.equals("") &&
877  !PrintMachineInstrsPassName.equals("option-unspecified")) {
878  if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
880  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
881  assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
882  const char *TID = (const char *)(TPI->getTypeInfo());
883  const char *IID = (const char *)(IPI->getTypeInfo());
884  insertPass(TID, IID);
885  }
886  }
887 
888  // Add passes that optimize machine instructions in SSA form.
889  if (getOptLevel() != CodeGenOpt::None) {
891  } else {
892  // If the target requests it, assign local variables to stack slots relative
893  // to one another and simplify frame index references where possible.
895  }
896 
897  if (TM->Options.EnableIPRA)
899 
900  // Run pre-ra passes.
901  addPreRegAlloc();
902 
903  // Run register allocation and passes that are tightly coupled with it,
904  // including phi elimination and scheduling.
905  if (getOptimizeRegAlloc())
907  else
908  addFastRegAlloc();
909 
910  // Run post-ra passes.
911  addPostRegAlloc();
912 
913  // Insert prolog/epilog code. Eliminate abstract frame index references...
914  if (getOptLevel() != CodeGenOpt::None) {
917  }
918 
919  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
920  // do so if it hasn't been disabled, substituted, or overridden.
923 
924  /// Add passes that optimize machine instructions after register allocation.
925  if (getOptLevel() != CodeGenOpt::None)
927 
928  // Expand pseudo instructions before second scheduling pass.
930 
931  // Run pre-sched2 passes.
932  addPreSched2();
933 
936 
937  // Second pass scheduler.
938  // Let Target optionally insert this pass by itself at some other
939  // point.
940  if (getOptLevel() != CodeGenOpt::None &&
942  if (MISchedPostRA)
944  else
946  }
947 
948  // GC
949  if (addGCPasses()) {
950  if (PrintGCInfo)
951  addPass(createGCInfoPrinter(dbgs()), false, false);
952  }
953 
954  // Basic block placement.
955  if (getOptLevel() != CodeGenOpt::None)
957 
958  addPreEmitPass();
959 
960  if (TM->Options.EnableIPRA)
961  // Collect register usage information and produce a register mask of
962  // clobbered registers, to be used to optimize call sites.
964 
965  addPass(&FuncletLayoutID, false);
966 
967  addPass(&StackMapLivenessID, false);
968  addPass(&LiveDebugValuesID, false);
969 
970  // Insert before XRay Instrumentation.
971  addPass(&FEntryInserterID, false);
972 
974  addPass(&PatchableFunctionID, false);
975 
977  EnableMachineOutliner != NeverOutline) {
978  bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
979  bool AddOutliner = RunOnAllFunctions ||
981  if (AddOutliner)
982  addPass(createMachineOutlinerPass(RunOnAllFunctions));
983  }
984 
985  // Add passes that directly emit MI after all other MI passes.
986  addPreEmitPass2();
987 
988  AddingMachinePasses = false;
989 }
990 
991 /// Add passes that optimize machine instructions in SSA form.
993  // Pre-ra tail duplication.
995 
996  // Optimize PHIs before DCE: removing dead PHI cycles may make more
997  // instructions dead.
998  addPass(&OptimizePHIsID, false);
999 
1000  // This pass merges large allocas. StackSlotColoring is a different pass
1001  // which merges spill slots.
1002  addPass(&StackColoringID, false);
1003 
1004  // If the target requests it, assign local variables to stack slots relative
1005  // to one another and simplify frame index references where possible.
1007 
1008  // With optimization, dead code should already be eliminated. However
1009  // there is one known exception: lowered code for arguments that are only
1010  // used by tail calls, where the tail calls reuse the incoming stack
1011  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1013 
1014  // Allow targets to insert passes that improve instruction level parallelism,
1015  // like if-conversion. Such passes will typically need dominator trees and
1016  // loop info, just like LICM and CSE below.
1017  addILPOpts();
1018 
1019  addPass(&EarlyMachineLICMID, false);
1020  addPass(&MachineCSEID, false);
1021 
1023 
1025  // Clean-up the dead code that may have been generated by peephole
1026  // rewriting.
1028 }
1029 
1030 //===---------------------------------------------------------------------===//
1031 /// Register Allocation Pass Configuration
1032 //===---------------------------------------------------------------------===//
1033 
1035  switch (OptimizeRegAlloc) {
1036  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1037  case cl::BOU_TRUE: return true;
1038  case cl::BOU_FALSE: return false;
1039  }
1040  llvm_unreachable("Invalid optimize-regalloc state");
1041 }
1042 
1043 /// A dummy default pass factory indicates whether the register allocator is
1044 /// overridden on the command line.
1046 
1047 static RegisterRegAlloc
1048 defaultRegAlloc("default",
1049  "pick register allocator based on -O option",
1051 
1054  RegisterRegAlloc::setDefault(RegAlloc);
1055 }
1056 
1057 /// Instantiate the default register allocator pass for this target for either
1058 /// the optimized or unoptimized allocation path. This will be added to the pass
1059 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1060 /// in the optimized case.
1061 ///
1062 /// A target that uses the standard regalloc pass order for fast or optimized
1063 /// allocation may still override this for per-target regalloc
1064 /// selection. But -regalloc=... always takes precedence.
1066  if (Optimized)
1068  else
1069  return createFastRegisterAllocator();
1070 }
1071 
1072 /// Find and instantiate the register allocation pass requested by this target
1073 /// at the current optimization level. Different register allocators are
1074 /// defined as separate passes because they may require different analysis.
1075 ///
1076 /// This helper ensures that the regalloc= option is always available,
1077 /// even for targets that override the default allocator.
1078 ///
1079 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1080 /// this can be folded into addPass.
1082  // Initialize the global default.
1083  llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1085 
1086  RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1087  if (Ctor != useDefaultRegisterAllocator)
1088  return Ctor();
1089 
1090  // With no -regalloc= override, ask the target for a regalloc pass.
1091  return createTargetRegisterAllocator(Optimized);
1092 }
1093 
1095  if (RegAlloc != &useDefaultRegisterAllocator &&
1096  RegAlloc != &createFastRegisterAllocator)
1097  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1098 
1099  addPass(createRegAllocPass(false));
1100  return true;
1101 }
1102 
1104  // Add the selected register allocation pass.
1105  addPass(createRegAllocPass(true));
1106 
1107  // Allow targets to change the register assignments before rewriting.
1108  addPreRewrite();
1109 
1110  // Finally rewrite virtual registers.
1112  // Perform stack slot coloring and post-ra machine LICM.
1113  //
1114  // FIXME: Re-enable coloring with register when it's capable of adding
1115  // kill markers.
1117 
1118  return true;
1119 }
1120 
1121 /// Return true if the default global register allocator is in use and
1122 /// has not be overriden on the command line with '-regalloc=...'
1124  return RegAlloc.getNumOccurrences() == 0;
1125 }
1126 
1127 /// Add the minimum set of target-independent passes that are required for
1128 /// register allocation. No coalescing or scheduling.
1130  addPass(&PHIEliminationID, false);
1132 
1134 }
1135 
1136 /// Add standard target-independent passes that are tightly coupled with
1137 /// optimized register allocation, including coalescing, machine instruction
1138 /// scheduling, and register allocation itself.
1140  addPass(&DetectDeadLanesID, false);
1141 
1142  addPass(&ProcessImplicitDefsID, false);
1143 
1144  // LiveVariables currently requires pure SSA form.
1145  //
1146  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1147  // LiveVariables can be removed completely, and LiveIntervals can be directly
1148  // computed. (We still either need to regenerate kill flags after regalloc, or
1149  // preferably fix the scavenger to not depend on them).
1150  addPass(&LiveVariablesID, false);
1151 
1152  // Edge splitting is smarter with machine loop info.
1153  addPass(&MachineLoopInfoID, false);
1154  addPass(&PHIEliminationID, false);
1155 
1156  // Eventually, we want to run LiveIntervals before PHI elimination.
1157  if (EarlyLiveIntervals)
1158  addPass(&LiveIntervalsID, false);
1159 
1162 
1163  // The machine scheduler may accidentally create disconnected components
1164  // when moving subregister definitions around, avoid this by splitting them to
1165  // separate vregs before. Splitting can also improve reg. allocation quality.
1167 
1168  // PreRA instruction scheduling.
1170 
1171  if (addRegAssignmentOptimized()) {
1172  // Allow targets to expand pseudo instructions depending on the choice of
1173  // registers before MachineCopyPropagation.
1174  addPostRewrite();
1175 
1176  // Copy propagate to forward register uses and try to eliminate COPYs that
1177  // were not coalesced.
1179 
1180  // Run post-ra machine LICM to hoist reloads / remats.
1181  //
1182  // FIXME: can this move into MachineLateOptimization?
1184  }
1185 }
1186 
1187 //===---------------------------------------------------------------------===//
1188 /// Post RegAlloc Pass Configuration
1189 //===---------------------------------------------------------------------===//
1190 
1191 /// Add passes that optimize machine instructions after register allocation.
1193  // Branch folding must be run after regalloc and prolog/epilog insertion.
1195 
1196  // Tail duplication.
1197  // Note that duplicating tail just increases code size and degrades
1198  // performance for targets that require Structured Control Flow.
1199  // In addition it can also make CFG irreducible. Thus we disable it.
1200  if (!TM->requiresStructuredCFG())
1202 
1203  // Copy propagation.
1205 }
1206 
1207 /// Add standard GC passes.
1210  return true;
1211 }
1212 
1213 /// Add standard basic block placement passes.
1216  // Run a separate pass to collect block placement statistics.
1219  }
1220 }
1221 
1222 //===---------------------------------------------------------------------===//
1223 /// GlobalISel Configuration
1224 //===---------------------------------------------------------------------===//
1227 }
1228 
1231 }
1232 
1234  return true;
1235 }
1236 
1237 std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1238  return std::make_unique<CSEConfigBase>();
1239 }
Pass interface - Implemented by all &#39;passes&#39;.
Definition: Pass.h:80
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass&#39; corresponding PassInfo, indexed by the pass&#39; type identifier (&MyPass::...
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
Pass * createLoopStrengthReducePass()
This is the interface for LLVM&#39;s inclusion-based alias analysis implemented with CFL graph reachabili...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
char & FEntryInserterID
This pass inserts FEntry calls.
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers...
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
setjmp/longjmp based exceptions
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & FuncletLayoutID
This pass lays out funclets contiguously.
bool requiresStructuredCFG() const
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
This is the interface for a metadata-based scoped no-alias analysis.
FunctionPass * createExpandMemCmpPass()
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:5530
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
void setO0WantsFastISel(bool Enable)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
bool requiresCodeGenSCCOrder() const
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
RegisterPassParser class - Handle the addition of new machine passes.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
static void initializeDefaultRegisterAllocatorOnce()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:79
void setRequiresCodeGenSCCOrder(bool Enable=true)
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
ImmutablePass * createScopedNoAliasAAWrapperPass()
CodeGenOpt::Level getOptLevel() const
static const char * StopBeforeOptName
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
static cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
FunctionPass * createScalarizeMaskedMemIntrinPass()
createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather and scatter intrinsics with s...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Pass * createMergeICmpsLegacyPass()
Definition: MergeICmps.cpp:930
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:86
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:902
static const PassInfo * getPassInfo(StringRef PassName)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
MachineFunctionPass * createPrologEpilogInserterPass()
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:140
Target-Independent Code Generator Pass Configuration Options.
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
void initializeAAResultsWrapperPassPass(PassRegistry &)
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform...
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
FunctionPass * createPartiallyInlineLibCallsPass()
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
ppc ctr loops PowerPC CTR Loops Verify
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:151
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(TargetDefault), cl::values(clEnumValN(AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(NeverOutline, "never", "Disable all outlining"), clEnumValN(AlwaysOutline, "", "")))
AnalysisID getID() const
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
LLVMTargetMachine * TM
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:71
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly&#39;s exception handling s...
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
static const char * StartBeforeOptName
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:102
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:91
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::ZeroOrMore)
WebAssembly Exception Handling.
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
This is the interface for LLVM&#39;s unification-based alias analysis implemented with CFL graph reachabi...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
This pass is required by interprocedural register allocation.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
bool addCoreISelPasses()
Add the actual instruction selection passes.
This is the interface for a metadata-based TBAA.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \lobal\instruction selector"))
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:99
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:652
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
TargetIRAnalysis getTargetIRAnalysis()
Get a TargetIRAnalysis appropriate for the target.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
int getNumOccurrences() const
Definition: CommandLine.h:393
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
char & LiveDebugValuesID
LiveDebugValues pass.
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
virtual bool addRegAssignmentOptimized()
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
std::once_flag once_flag
Definition: Threading.h:72
void pm(uint64_t &Value)
Adjusts a program memory address.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:30
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:197
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:492
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:255
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:710
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
void setFastISel(bool Enable)
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
FunctionPass * createLowerConstantIntrinsicsPass()
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter, bool PrintAfter)
const void * AnalysisID
Definition: Pass.h:48
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
FunctionPass * createBasicAAWrapperPass()
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \lobal\instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
std::string getLimitedCodeGenPipelineReason(const char *Separator="/") const
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options...
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
static const char * StartAfterOptName
Option names for limiting the codegen pipeline.
FunctionPass * createPostInlineEntryExitInstrumenterPass()
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
A utility class that uses RAII to save and restore the value of a variable.
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:627
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:174
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
TargetOptions Options
virtual void addBlockPlacement()
Add standard basic block placement passes.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
No exception support.
Windows Exception Handling.
#define I(x, y, z)
Definition: MD5.cpp:58
char & FinalizeISelID
This pass expands pseudo-instructions, reserves registers and adjusts machine frame information...
void setGlobalISel(bool Enable)
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
virtual bool addRegAssignmentFast()
Add core register alloator passes which do the actual register assignment and rewriting.
void setOpt(bool &Opt, bool Val)
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
ImmutablePass * createCFLSteensAAWrapperPass()
ImmutablePass * createTypeBasedAAWrapperPass()
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
bool shouldPrintMachineCode() const
static void setDefault(FunctionPassCtor C)
This file defines passes to print out IR in various granularities.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:232
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:21
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
static const char * StopAfterOptName
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:211
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set...
This file provides utility classes that use RAII to save and restore values.
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:593
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \ast\instruction selector"))
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
static AnalysisID getPassIDFromName(StringRef PassName)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:249
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
This is the interface for LLVM&#39;s primary stateless and local alias analysis.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
This pass exposes codegen information to IR-level passes.
DWARF-like instruction based exceptions.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
ImmutablePass * createCFLAndersAAWrapperPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
void initializeBasicAAWrapperPassPass(PassRegistry &)
FunctionPass * createConstantHoistingPass()
FunctionPass * createDwarfEHPass()
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...