LLVM  12.0.0git
FixupStatepointCallerSaved.cpp
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1 //===-- FixupStatepointCallerSaved.cpp - Fixup caller saved registers ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// Statepoint instruction in deopt parameters contains values which are
12 /// meaningful to the runtime and should be able to be read at the moment the
13 /// call returns. So we can say that we need to encode the fact that these
14 /// values are "late read" by runtime. If we could express this notion for
15 /// register allocator it would produce the right form for us.
16 /// The need to fixup (i.e this pass) is specifically handling the fact that
17 /// we cannot describe such a late read for the register allocator.
18 /// Register allocator may put the value on a register clobbered by the call.
19 /// This pass forces the spill of such registers and replaces corresponding
20 /// statepoint operands to added spill slots.
21 ///
22 //===----------------------------------------------------------------------===//
23 
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/IR/Statepoint.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/Support/Debug.h"
36 
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "fixup-statepoint-caller-saved"
40 STATISTIC(NumSpilledRegisters, "Number of spilled register");
41 STATISTIC(NumSpillSlotsAllocated, "Number of spill slots allocated");
42 STATISTIC(NumSpillSlotsExtended, "Number of spill slots extended");
43 
45  "fixup-scs-extend-slot-size", cl::Hidden, cl::init(false),
46  cl::desc("Allow spill in spill slot of greater size than register size"),
47  cl::Hidden);
48 
50  "fixup-allow-gcptr-in-csr", cl::Hidden, cl::init(false),
51  cl::desc("Allow passing GC Pointer arguments in callee saved registers"));
52 
54  "fixup-scs-enable-copy-propagation", cl::Hidden, cl::init(true),
55  cl::desc("Enable simple copy propagation during register reloading"));
56 
57 // This is purely debugging option.
58 // It may be handy for investigating statepoint spilling issues.
60  "fixup-max-csr-statepoints", cl::Hidden,
61  cl::desc("Max number of statepoints allowed to pass GC Ptrs in registers"));
62 
63 namespace {
64 
65 class FixupStatepointCallerSaved : public MachineFunctionPass {
66 public:
67  static char ID;
68 
69  FixupStatepointCallerSaved() : MachineFunctionPass(ID) {
71  }
72 
73  void getAnalysisUsage(AnalysisUsage &AU) const override {
74  AU.setPreservesCFG();
76  }
77 
78  StringRef getPassName() const override {
79  return "Fixup Statepoint Caller Saved";
80  }
81 
82  bool runOnMachineFunction(MachineFunction &MF) override;
83 };
84 
85 } // End anonymous namespace.
86 
89 
90 INITIALIZE_PASS_BEGIN(FixupStatepointCallerSaved, DEBUG_TYPE,
91  "Fixup Statepoint Caller Saved", false, false)
92 INITIALIZE_PASS_END(FixupStatepointCallerSaved, DEBUG_TYPE,
93  "Fixup Statepoint Caller Saved", false, false)
94 
95 // Utility function to get size of the register.
97  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
98  return TRI.getSpillSize(*RC);
99 }
100 
101 // Try to eliminate redundant copy to register which we're going to
102 // spill, i.e. try to change:
103 // X = COPY Y
104 // SPILL X
105 // to
106 // SPILL Y
107 // If there are no uses of X between copy and STATEPOINT, that COPY
108 // may be eliminated.
109 // Reg - register we're about to spill
110 // RI - On entry points to statepoint.
111 // On successful copy propagation set to new spill point.
112 // IsKill - set to true if COPY is Kill (there are no uses of Y)
113 // Returns either found source copy register or original one.
116  bool &IsKill, const TargetInstrInfo &TII,
117  const TargetRegisterInfo &TRI) {
118  // First check if statepoint itself uses Reg in non-meta operands.
119  int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI);
120  if (Idx >= 0 && (unsigned)Idx < StatepointOpers(&*RI).getNumDeoptArgsIdx()) {
121  IsKill = false;
122  return Reg;
123  }
124 
125  if (!EnableCopyProp)
126  return Reg;
127 
128  MachineBasicBlock *MBB = RI->getParent();
130  MachineInstr *Def = nullptr, *Use = nullptr;
131  for (auto It = ++(RI.getReverse()); It != E; ++It) {
132  if (It->readsRegister(Reg, &TRI) && !Use)
133  Use = &*It;
134  if (It->modifiesRegister(Reg, &TRI)) {
135  Def = &*It;
136  break;
137  }
138  }
139 
140  if (!Def)
141  return Reg;
142 
143  auto DestSrc = TII.isCopyInstr(*Def);
144  if (!DestSrc || DestSrc->Destination->getReg() != Reg)
145  return Reg;
146 
147  Register SrcReg = DestSrc->Source->getReg();
148 
149  if (getRegisterSize(TRI, Reg) != getRegisterSize(TRI, SrcReg))
150  return Reg;
151 
152  LLVM_DEBUG(dbgs() << "spillRegisters: perform copy propagation "
153  << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI)
154  << "\n");
155 
156  // Insert spill immediately after Def
158  IsKill = DestSrc->Source->isKill();
159 
160  // There are no uses of original register between COPY and STATEPOINT.
161  // There can't be any after STATEPOINT, so we can eliminate Def.
162  if (!Use) {
163  LLVM_DEBUG(dbgs() << "spillRegisters: removing dead copy " << *Def);
164  Def->eraseFromParent();
165  }
166  return SrcReg;
167 }
168 
169 namespace {
170 // Pair {Register, FrameIndex}
171 using RegSlotPair = std::pair<Register, int>;
172 
173 // Keeps track of what reloads were inserted in MBB.
174 class RegReloadCache {
175  using ReloadSet = SmallSet<RegSlotPair, 8>;
177 
178 public:
179  RegReloadCache() = default;
180 
181  // Record reload of Reg from FI in block MBB
182  void recordReload(Register Reg, int FI, const MachineBasicBlock *MBB) {
183  RegSlotPair RSP(Reg, FI);
184  auto Res = Reloads[MBB].insert(RSP);
185  (void)Res;
186  assert(Res.second && "reload already exists");
187  }
188 
189  // Does basic block MBB contains reload of Reg from FI?
190  bool hasReload(Register Reg, int FI, const MachineBasicBlock *MBB) {
191  RegSlotPair RSP(Reg, FI);
192  return Reloads.count(MBB) && Reloads[MBB].count(RSP);
193  }
194 };
195 
196 // Cache used frame indexes during statepoint re-write to re-use them in
197 // processing next statepoint instruction.
198 // Two strategies. One is to preserve the size of spill slot while another one
199 // extends the size of spill slots to reduce the number of them, causing
200 // the less total frame size. But unspill will have "implicit" any extend.
201 class FrameIndexesCache {
202 private:
203  struct FrameIndexesPerSize {
204  // List of used frame indexes during processing previous statepoints.
205  SmallVector<int, 8> Slots;
206  // Current index of un-used yet frame index.
207  unsigned Index = 0;
208  };
209  MachineFrameInfo &MFI;
210  const TargetRegisterInfo &TRI;
211  // Map size to list of frame indexes of this size. If the mode is
212  // FixupSCSExtendSlotSize then the key 0 is used to keep all frame indexes.
213  // If the size of required spill slot is greater than in a cache then the
214  // size will be increased.
216 
217  // Keeps track of slots reserved for the shared landing pad processing.
218  // Initialized from GlobalIndices for the current EHPad.
219  SmallSet<int, 8> ReservedSlots;
220 
221  // Landing pad can be destination of several statepoints. Every register
222  // defined by such statepoints must be spilled to the same stack slot.
223  // This map keeps that information.
225  GlobalIndices;
226 
227  FrameIndexesPerSize &getCacheBucket(unsigned Size) {
228  // In FixupSCSExtendSlotSize mode the bucket with 0 index is used
229  // for all sizes.
230  return Cache[FixupSCSExtendSlotSize ? 0 : Size];
231  }
232 
233 public:
234  FrameIndexesCache(MachineFrameInfo &MFI, const TargetRegisterInfo &TRI)
235  : MFI(MFI), TRI(TRI) {}
236  // Reset the current state of used frame indexes. After invocation of
237  // this function all frame indexes are available for allocation with
238  // the exception of slots reserved for landing pad processing (if any).
239  void reset(const MachineBasicBlock *EHPad) {
240  for (auto &It : Cache)
241  It.second.Index = 0;
242 
243  ReservedSlots.clear();
244  if (EHPad && GlobalIndices.count(EHPad))
245  for (auto &RSP : GlobalIndices[EHPad])
246  ReservedSlots.insert(RSP.second);
247  }
248 
249  // Get frame index to spill the register.
250  int getFrameIndex(Register Reg, MachineBasicBlock *EHPad) {
251  // Check if slot for Reg is already reserved at EHPad.
252  auto It = GlobalIndices.find(EHPad);
253  if (It != GlobalIndices.end()) {
254  auto &Vec = It->second;
255  auto Idx = llvm::find_if(
256  Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; });
257  if (Idx != Vec.end()) {
258  int FI = Idx->second;
259  LLVM_DEBUG(dbgs() << "Found global FI " << FI << " for register "
260  << printReg(Reg, &TRI) << " at "
261  << printMBBReference(*EHPad) << "\n");
262  assert(ReservedSlots.count(FI) && "using unreserved slot");
263  return FI;
264  }
265  }
266 
267  unsigned Size = getRegisterSize(TRI, Reg);
268  FrameIndexesPerSize &Line = getCacheBucket(Size);
269  while (Line.Index < Line.Slots.size()) {
270  int FI = Line.Slots[Line.Index++];
271  if (ReservedSlots.count(FI))
272  continue;
273  // If all sizes are kept together we probably need to extend the
274  // spill slot size.
275  if (MFI.getObjectSize(FI) < Size) {
276  MFI.setObjectSize(FI, Size);
277  MFI.setObjectAlignment(FI, Align(Size));
278  NumSpillSlotsExtended++;
279  }
280  return FI;
281  }
282  int FI = MFI.CreateSpillStackObject(Size, Align(Size));
283  NumSpillSlotsAllocated++;
284  Line.Slots.push_back(FI);
285  ++Line.Index;
286 
287  // Remember assignment {Reg, FI} for EHPad
288  if (EHPad) {
289  GlobalIndices[EHPad].push_back(std::make_pair(Reg, FI));
290  LLVM_DEBUG(dbgs() << "Reserved FI " << FI << " for spilling reg "
291  << printReg(Reg, &TRI) << " at landing pad "
292  << printMBBReference(*EHPad) << "\n");
293  }
294 
295  return FI;
296  }
297 
298  // Sort all registers to spill in descendent order. In the
299  // FixupSCSExtendSlotSize mode it will minimize the total frame size.
300  // In non FixupSCSExtendSlotSize mode we can skip this step.
301  void sortRegisters(SmallVectorImpl<Register> &Regs) {
303  return;
304  llvm::sort(Regs, [&](Register &A, Register &B) {
305  return getRegisterSize(TRI, A) > getRegisterSize(TRI, B);
306  });
307  }
308 };
309 
310 // Describes the state of the current processing statepoint instruction.
311 class StatepointState {
312 private:
313  // statepoint instruction.
314  MachineInstr &MI;
315  MachineFunction &MF;
316  // If non-null then statepoint is invoke, and this points to the landing pad.
317  MachineBasicBlock *EHPad;
318  const TargetRegisterInfo &TRI;
319  const TargetInstrInfo &TII;
320  MachineFrameInfo &MFI;
321  // Mask with callee saved registers.
322  const uint32_t *Mask;
323  // Cache of frame indexes used on previous instruction processing.
324  FrameIndexesCache &CacheFI;
325  bool AllowGCPtrInCSR;
326  // Operands with physical registers requiring spilling.
327  SmallVector<unsigned, 8> OpsToSpill;
328  // Set of register to spill.
329  SmallVector<Register, 8> RegsToSpill;
330  // Set of registers to reload after statepoint.
331  SmallVector<Register, 8> RegsToReload;
332  // Map Register to Frame Slot index.
333  DenseMap<Register, int> RegToSlotIdx;
334 
335 public:
336  StatepointState(MachineInstr &MI, const uint32_t *Mask,
337  FrameIndexesCache &CacheFI, bool AllowGCPtrInCSR)
338  : MI(MI), MF(*MI.getMF()), TRI(*MF.getSubtarget().getRegisterInfo()),
339  TII(*MF.getSubtarget().getInstrInfo()), MFI(MF.getFrameInfo()),
340  Mask(Mask), CacheFI(CacheFI), AllowGCPtrInCSR(AllowGCPtrInCSR) {
341 
342  // Find statepoint's landing pad, if any.
343  EHPad = nullptr;
344  MachineBasicBlock *MBB = MI.getParent();
345  // Invoke statepoint must be last one in block.
346  bool Last = std::none_of(++MI.getIterator(), MBB->end().getInstrIterator(),
347  [](MachineInstr &I) {
348  return I.getOpcode() == TargetOpcode::STATEPOINT;
349  });
350 
351  if (!Last)
352  return;
353 
354  auto IsEHPad = [](MachineBasicBlock *B) { return B->isEHPad(); };
355 
356  assert(llvm::count_if(MBB->successors(), IsEHPad) < 2 && "multiple EHPads");
357 
358  auto It = llvm::find_if(MBB->successors(), IsEHPad);
359  if (It != MBB->succ_end())
360  EHPad = *It;
361  }
362 
363  MachineBasicBlock *getEHPad() const { return EHPad; }
364 
365  // Return true if register is callee saved.
366  bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; }
367 
368  // Iterates over statepoint meta args to find caller saver registers.
369  // Also cache the size of found registers.
370  // Returns true if caller save registers found.
371  bool findRegistersToSpill() {
372  SmallSet<Register, 8> GCRegs;
373  // All GC pointer operands assigned to registers produce new value.
374  // Since they're tied to their defs, it is enough to collect def registers.
375  for (const auto &Def : MI.defs())
376  GCRegs.insert(Def.getReg());
377 
378  SmallSet<Register, 8> VisitedRegs;
379  for (unsigned Idx = StatepointOpers(&MI).getVarIdx(),
380  EndIdx = MI.getNumOperands();
381  Idx < EndIdx; ++Idx) {
382  MachineOperand &MO = MI.getOperand(Idx);
383  if (!MO.isReg() || MO.isImplicit())
384  continue;
385  Register Reg = MO.getReg();
386  assert(Reg.isPhysical() && "Only physical regs are expected");
387 
388  if (isCalleeSaved(Reg) && (AllowGCPtrInCSR || !is_contained(GCRegs, Reg)))
389  continue;
390 
391  LLVM_DEBUG(dbgs() << "Will spill " << printReg(Reg, &TRI) << " at index "
392  << Idx << "\n");
393 
394  if (VisitedRegs.insert(Reg).second)
395  RegsToSpill.push_back(Reg);
396  OpsToSpill.push_back(Idx);
397  }
398  CacheFI.sortRegisters(RegsToSpill);
399  return !RegsToSpill.empty();
400  }
401 
402  // Spill all caller saved registers right before statepoint instruction.
403  // Remember frame index where register is spilled.
404  void spillRegisters() {
405  for (Register Reg : RegsToSpill) {
406  int FI = CacheFI.getFrameIndex(Reg, EHPad);
407  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
408 
409  NumSpilledRegisters++;
410  RegToSlotIdx[Reg] = FI;
411 
412  LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, &TRI) << " to FI " << FI
413  << "\n");
414 
415  // Perform trivial copy propagation
416  bool IsKill = true;
417  MachineBasicBlock::iterator InsertBefore(MI);
418  Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI);
419 
420  LLVM_DEBUG(dbgs() << "Insert spill before " << *InsertBefore);
421  TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI,
422  RC, &TRI);
423  }
424  }
425 
426  void insertReloadBefore(unsigned Reg, MachineBasicBlock::iterator It,
428  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
429  int FI = RegToSlotIdx[Reg];
430  if (It != MBB->end()) {
431  TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI);
432  return;
433  }
434 
435  // To insert reload at the end of MBB, insert it before last instruction
436  // and then swap them.
437  assert(MBB->begin() != MBB->end() && "Empty block");
438  --It;
439  TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI);
440  MachineInstr *Reload = It->getPrevNode();
441  int Dummy = 0;
442  (void)Dummy;
443  assert(TII.isLoadFromStackSlot(*Reload, Dummy) == Reg);
444  assert(Dummy == FI);
445  MBB->remove(Reload);
446  MBB->insertAfter(It, Reload);
447  }
448 
449  // Insert reloads of (relocated) registers spilled in statepoint.
450  void insertReloads(MachineInstr *NewStatepoint, RegReloadCache &RC) {
451  MachineBasicBlock *MBB = NewStatepoint->getParent();
452  auto InsertPoint = std::next(NewStatepoint->getIterator());
453 
454  for (auto Reg : RegsToReload) {
455  insertReloadBefore(Reg, InsertPoint, MBB);
456  LLVM_DEBUG(dbgs() << "Reloading " << printReg(Reg, &TRI) << " from FI "
457  << RegToSlotIdx[Reg] << " after statepoint\n");
458 
459  if (EHPad && !RC.hasReload(Reg, RegToSlotIdx[Reg], EHPad)) {
460  RC.recordReload(Reg, RegToSlotIdx[Reg], EHPad);
461  auto EHPadInsertPoint = EHPad->SkipPHIsLabelsAndDebug(EHPad->begin());
462  insertReloadBefore(Reg, EHPadInsertPoint, EHPad);
463  LLVM_DEBUG(dbgs() << "...also reload at EHPad "
464  << printMBBReference(*EHPad) << "\n");
465  }
466  }
467  }
468 
469  // Re-write statepoint machine instruction to replace caller saved operands
470  // with indirect memory location (frame index).
471  MachineInstr *rewriteStatepoint() {
472  MachineInstr *NewMI =
473  MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
474  MachineInstrBuilder MIB(MF, NewMI);
475 
476  unsigned NumOps = MI.getNumOperands();
477 
478  // New indices for the remaining defs.
479  SmallVector<unsigned, 8> NewIndices;
480  unsigned NumDefs = MI.getNumDefs();
481  for (unsigned I = 0; I < NumDefs; ++I) {
482  MachineOperand &DefMO = MI.getOperand(I);
483  assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand");
484  Register Reg = DefMO.getReg();
485  if (!AllowGCPtrInCSR) {
486  assert(is_contained(RegsToSpill, Reg));
487  RegsToReload.push_back(Reg);
488  } else {
489  if (isCalleeSaved(Reg)) {
490  NewIndices.push_back(NewMI->getNumOperands());
491  MIB.addReg(Reg, RegState::Define);
492  } else {
493  NewIndices.push_back(NumOps);
494  RegsToReload.push_back(Reg);
495  }
496  }
497  }
498 
499  // Add End marker.
500  OpsToSpill.push_back(MI.getNumOperands());
501  unsigned CurOpIdx = 0;
502 
503  for (unsigned I = NumDefs; I < MI.getNumOperands(); ++I) {
504  MachineOperand &MO = MI.getOperand(I);
505  if (I == OpsToSpill[CurOpIdx]) {
506  int FI = RegToSlotIdx[MO.getReg()];
507  MIB.addImm(StackMaps::IndirectMemRefOp);
508  MIB.addImm(getRegisterSize(TRI, MO.getReg()));
509  assert(MO.isReg() && "Should be register");
510  assert(MO.getReg().isPhysical() && "Should be physical register");
511  MIB.addFrameIndex(FI);
512  MIB.addImm(0);
513  ++CurOpIdx;
514  } else {
515  MIB.add(MO);
516  unsigned OldDef;
517  if (AllowGCPtrInCSR && MI.isRegTiedToDefOperand(I, &OldDef)) {
518  assert(OldDef < NumDefs);
519  assert(NewIndices[OldDef] < NumOps);
520  MIB->tieOperands(NewIndices[OldDef], MIB->getNumOperands() - 1);
521  }
522  }
523  }
524  assert(CurOpIdx == (OpsToSpill.size() - 1) && "Not all operands processed");
525  // Add mem operands.
526  NewMI->setMemRefs(MF, MI.memoperands());
527  for (auto It : RegToSlotIdx) {
528  Register R = It.first;
529  int FrameIndex = It.second;
530  auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
532  if (is_contained(RegsToReload, R))
534  auto *MMO =
535  MF.getMachineMemOperand(PtrInfo, Flags, getRegisterSize(TRI, R),
537  NewMI->addMemOperand(MF, MMO);
538  }
539 
540  // Insert new statepoint and erase old one.
541  MI.getParent()->insert(MI, NewMI);
542 
543  LLVM_DEBUG(dbgs() << "rewritten statepoint to : " << *NewMI << "\n");
544  MI.eraseFromParent();
545  return NewMI;
546  }
547 };
548 
549 class StatepointProcessor {
550 private:
551  MachineFunction &MF;
552  const TargetRegisterInfo &TRI;
553  FrameIndexesCache CacheFI;
554  RegReloadCache ReloadCache;
555 
556 public:
557  StatepointProcessor(MachineFunction &MF)
558  : MF(MF), TRI(*MF.getSubtarget().getRegisterInfo()),
559  CacheFI(MF.getFrameInfo(), TRI) {}
560 
561  bool process(MachineInstr &MI, bool AllowGCPtrInCSR) {
562  StatepointOpers SO(&MI);
563  uint64_t Flags = SO.getFlags();
564  // Do nothing for LiveIn, it supports all registers.
565  if (Flags & (uint64_t)StatepointFlags::DeoptLiveIn)
566  return false;
567  LLVM_DEBUG(dbgs() << "\nMBB " << MI.getParent()->getNumber() << " "
568  << MI.getParent()->getName() << " : process statepoint "
569  << MI);
570  CallingConv::ID CC = SO.getCallingConv();
571  const uint32_t *Mask = TRI.getCallPreservedMask(MF, CC);
572  StatepointState SS(MI, Mask, CacheFI, AllowGCPtrInCSR);
573  CacheFI.reset(SS.getEHPad());
574 
575  if (!SS.findRegistersToSpill())
576  return false;
577 
578  SS.spillRegisters();
579  auto *NewStatepoint = SS.rewriteStatepoint();
580  SS.insertReloads(NewStatepoint, ReloadCache);
581  return true;
582  }
583 };
584 } // namespace
585 
586 bool FixupStatepointCallerSaved::runOnMachineFunction(MachineFunction &MF) {
587  if (skipFunction(MF.getFunction()))
588  return false;
589 
590  const Function &F = MF.getFunction();
591  if (!F.hasGC())
592  return false;
593 
595  for (MachineBasicBlock &BB : MF)
596  for (MachineInstr &I : BB)
597  if (I.getOpcode() == TargetOpcode::STATEPOINT)
598  Statepoints.push_back(&I);
599 
600  if (Statepoints.empty())
601  return false;
602 
603  bool Changed = false;
604  StatepointProcessor SPP(MF);
605  unsigned NumStatepoints = 0;
606  bool AllowGCPtrInCSR = PassGCPtrInCSR;
607  for (MachineInstr *I : Statepoints) {
608  ++NumStatepoints;
609  if (MaxStatepointsWithRegs.getNumOccurrences() &&
610  NumStatepoints >= MaxStatepointsWithRegs)
611  AllowGCPtrInCSR = false;
612  Changed |= SPP.process(*I, AllowGCPtrInCSR);
613  }
614  return Changed;
615 }
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
char & FixupStatepointCallerSavedID
The pass fixups statepoint machine instruction to replace usage of caller saved registers with stack ...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Fixup Statepoint Caller Saved
auto count_if(R &&Range, UnaryPredicate P)
Wrapper function around std::count_if to count the number of times an element satisfying a given pred...
Definition: STLExtras.h:1588
unsigned Reg
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
F(f)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
INITIALIZE_PASS_BEGIN(FixupStatepointCallerSaved, DEBUG_TYPE, "Fixup Statepoint Caller Saved", false, false) INITIALIZE_PASS_END(FixupStatepointCallerSaved
iterator_range< succ_iterator > successors()
Function & getFunction()
Return the LLVM function that this machine code represents.
static cl::opt< bool > FixupSCSExtendSlotSize("fixup-scs-extend-slot-size", cl::Hidden, cl::init(false), cl::desc("Allow spill in spill slot of greater size than register size"), cl::Hidden)
MachineBasicBlock & MBB
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getVarIdx() const
Get starting index of non call related arguments (calling convention, statepoint flags,...
Definition: StackMaps.h:188
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:478
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1512
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void initializeFixupStatepointCallerSavedPass(PassRegistry &)
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
Fixup Statepoint Caller static false unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg)
static cl::opt< bool > PassGCPtrInCSR("fixup-allow-gcptr-in-csr", cl::Hidden, cl::init(false), cl::desc("Allow passing GC Pointer arguments in callee saved registers"))
void clear()
Definition: SmallSet.h:218
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
TargetInstrInfo - Interface to description of machine instruction set.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:427
MachineInstrBundleIterator< MachineInstr > iterator
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
static Register performCopyPropagation(Register Reg, MachineBasicBlock::iterator &RI, bool &IsKill, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI)
Represent the analysis usage information of a pass.
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1439
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
void setObjectSize(int ObjectIdx, int64_t Size)
Change the size of the specified stack object.
uint64_t Align
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
The memory access writes data.
static cl::opt< bool > EnableCopyProp("fixup-scs-enable-copy-propagation", cl::Hidden, cl::init(true), cl::desc("Enable simple copy propagation during register reloading"))
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
MachineOperand class - Representation of each machine instruction operand.
uint32_t Index
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static cl::opt< unsigned > MaxStatepointsWithRegs("fixup-max-csr-statepoints", cl::Hidden, cl::desc("Max number of statepoints allowed to pass GC Ptrs in registers"))
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
Flags
Flags values. These may be or'd together.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:284
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:62
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
#define I(x, y, z)
Definition: MD5.cpp:59
MI-level Statepoint operands.
Definition: StackMaps.h:158
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
size_t size() const
Definition: SmallVector.h:72
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
aarch64 promote const
Mark the deopt arguments associated with the statepoint as only being "live-in".
#define DEBUG_TYPE
Register definition.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
iterator SkipPHIsLabelsAndDebug(iterator I)
Return the first instruction in MBB after I that is not a PHI, label or debug.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1525
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
bool isImplicit() const
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1563