59#define DEBUG_TYPE "machinelicm"
63 cl::desc(
"MachineLICM should avoid speculation"),
68 cl::desc(
"MachineLICM should hoist even cheap instructions"),
84 cl::desc(
"Do not hoist instructions if target"
85 "block is N times hotter than the source."),
92 cl::desc(
"Disable hoisting instructions to"
96 "disable the feature"),
98 "enable the feature when using profile data"),
100 "enable the feature with/wo profile data")));
103 "Number of machine instructions hoisted out of loops");
105 "Number of instructions hoisted in low reg pressure situation");
107 "Number of high latency instructions hoisted");
109 "Number of hoisted machine instructions CSEed");
111 "Number of machine instructions hoisted out of loops post regalloc");
113 "Number of stores of const phys reg hoisted out of loops");
115 "Number of instructions not hoisted due to block frequency");
118 enum HoistResult { NotHoisted = 1, Hoisted = 2, ErasedMI = 4 };
127 bool PreRegAlloc =
false;
128 bool HasProfileData =
false;
137 bool Changed =
false;
138 bool FirstInLoop =
false;
153 ExitBlockMap[CurLoop] = ExitBlocks;
182 unsigned SpeculationState = SpeculateUnknown;
185 MachineLICMBase(
char &PassID,
bool PreRegAlloc)
206 ExitBlockMap.
clear();
211 struct CandidateInfo {
217 :
MI(mi),
Def(def), FI(fi) {}
259 void ExitScopeIfDone(
271 bool ConsiderUnseenAsDef);
274 bool ConsiderUnseenAsDef =
false);
279 std::vector<MachineInstr *> &PrevMIs);
283 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI);
292 void InitializeLoadsHoistableLoops();
300 class MachineLICM :
public MachineLICMBase {
303 MachineLICM() : MachineLICMBase(
ID,
false) {
308 class EarlyMachineLICM :
public MachineLICMBase {
311 EarlyMachineLICM() : MachineLICMBase(
ID,
true) {
319char EarlyMachineLICM::ID;
325 "Machine Loop Invariant Code Motion",
false,
false)
343 if (skipFunction(MF.getFunction()))
346 Changed = FirstInLoop =
false;
348 TII = ST.getInstrInfo();
349 TLI = ST.getTargetLowering();
350 TRI = ST.getRegisterInfo();
351 MFI = &MF.getFrameInfo();
352 MRI = &MF.getRegInfo();
353 SchedModel.
init(&ST);
355 PreRegAlloc =
MRI->isSSA();
356 HasProfileData = MF.getFunction().hasProfileData();
366 unsigned NumRPS =
TRI->getNumRegPressureSets();
367 RegPressure.resize(NumRPS);
368 std::fill(RegPressure.begin(), RegPressure.end(), 0);
370 for (
unsigned i = 0, e = NumRPS; i != e; ++i)
371 RegLimit[i] =
TRI->getRegPressureSetLimit(MF, i);
376 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
377 MLI = &getAnalysis<MachineLoopInfo>();
378 DT = &getAnalysis<MachineDominatorTree>();
379 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
382 InitializeLoadsHoistableLoops();
385 while (!Worklist.
empty()) {
390 HoistRegionPostRA(CurLoop, CurPreheader);
396 HoistOutOfLoop(
N, CurLoop, CurPreheader);
412 if (
MI->memoperands_empty())
415 if (!
MemOp->isStore() || !
MemOp->getPseudoValue())
418 dyn_cast<FixedStackPseudoSourceValue>(
MemOp->getPseudoValue())) {
419 if (
Value->getFrameIndex() == FI)
433 bool RuledOut =
false;
434 bool HasNonInvariantUse =
false;
439 int FI = MO.getIndex();
440 if (!StoredFIs.
count(FI) &&
444 HasNonInvariantUse =
true;
450 if (MO.isRegMask()) {
460 assert(
Reg.isPhysical() &&
"Not expecting virtual register!");
463 if (Reg && (PhysRegDefs.
test(Reg) || PhysRegClobbers.
test(Reg)))
466 HasNonInvariantUse =
true;
470 if (MO.isImplicit()) {
472 PhysRegClobbers.
set(*AI);
492 if (PhysRegDefs.
test(*AS))
493 PhysRegClobbers.
set(*AS);
498 PhysRegDefs.
set(*AS);
500 if (PhysRegClobbers.
test(Reg))
508 if (Def && !RuledOut) {
509 int FI = std::numeric_limits<int>::min();
510 if ((!HasNonInvariantUse && IsLICMCandidate(*
MI, CurLoop)) ||
518void MachineLICMBase::HoistRegionPostRA(
MachineLoop *CurLoop,
524 unsigned NumRegs =
TRI->getNumRegs();
537 if (
ML &&
ML->getHeader()->isEHPad())
continue;
542 for (
const auto &LI : BB->liveins()) {
544 PhysRegDefs.
set(*AI);
548 if (
const uint32_t *Mask = BB->getBeginClobberMask(
TRI))
551 SpeculationState = SpeculateUnknown;
553 ProcessMI(&
MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates,
560 if (TI != Preheader->
end()) {
580 for (CandidateInfo &Candidate : Candidates) {
581 if (Candidate.FI != std::numeric_limits<int>::min() &&
582 StoredFIs.
count(Candidate.FI))
585 unsigned Def = Candidate.Def;
586 if (!PhysRegClobbers.
test(Def) && !TermRegs.test(Def)) {
593 if (PhysRegDefs.
test(Reg) ||
594 PhysRegClobbers.
test(Reg)) {
602 HoistPostRA(
MI, Candidate.Def, CurLoop, CurPreheader);
611 if (!BB->isLiveIn(Reg))
617 if (
TRI->regsOverlap(Reg, MO.getReg()))
644 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
650 AddToLiveIns(Def, CurLoop);
660 if (SpeculationState != SpeculateUnknown)
661 return SpeculationState == SpeculateFalse;
668 if (!DT->
dominates(BB, CurrentLoopExitingBlock)) {
669 SpeculationState = SpeculateTrue;
674 SpeculationState = SpeculateFalse;
682bool MachineLICMBase::isTriviallyReMaterializable(
684 if (!
TII->isTriviallyReMaterializable(
MI))
688 if (MO.getReg().isVirtual())
713 if (OpenChildren[
Node])
717 ExitScope(
Node->getBlock());
720 if (!Parent || --OpenChildren[Parent] != 0)
744 while (!WorkList.
empty()) {
752 if (
ML &&
ML->getHeader()->isEHPad())
760 unsigned NumChildren =
Node->getNumChildren();
768 OpenChildren[
Node] = NumChildren;
774 ParentMap[Child] =
Node;
786 InitRegPressure(Preheader);
795 SpeculationState = SpeculateUnknown;
797 unsigned HoistRes = HoistResult::NotHoisted;
798 HoistRes =
Hoist(&
MI, Preheader, CurLoop);
799 if (HoistRes & HoistResult::NotHoisted) {
804 L =
L->getParentLoop())
807 while (!InnerLoopWorkList.
empty()) {
810 if (InnerLoopPreheader) {
811 HoistRes =
Hoist(&
MI, InnerLoopPreheader, InnerLoop);
812 if (HoistRes & HoistResult::Hoisted)
818 if (HoistRes & HoistResult::ErasedMI)
821 UpdateRegPressure(&
MI);
825 ExitScopeIfDone(
Node, OpenChildren, ParentMap);
851 UpdateRegPressure(&
MI,
true);
856 bool ConsiderUnseenAsDef) {
857 auto Cost = calcRegisterCost(
MI,
true, ConsiderUnseenAsDef);
858 for (
const auto &RPIdAndCost :
Cost) {
859 unsigned Class = RPIdAndCost.first;
860 if (
static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second)
874MachineLICMBase::calcRegisterCost(
const MachineInstr *
MI,
bool ConsiderSeen,
875 bool ConsiderUnseenAsDef) {
877 if (
MI->isImplicitDef())
879 for (
unsigned i = 0, e =
MI->getDesc().getNumOperands(); i != e; ++i) {
884 if (!
Reg.isVirtual())
888 bool isNew = ConsiderSeen ? RegSeen.
insert(Reg).second :
false;
894 RCCost =
W.RegWeight;
897 if (isNew && !isKill && ConsiderUnseenAsDef)
899 RCCost =
W.RegWeight;
900 else if (!isNew && isKill)
901 RCCost = -
W.RegWeight;
905 const int *PS =
TRI->getRegClassPressureSets(RC);
906 for (; *PS != -1; ++PS) {
907 if (!
Cost.contains(*PS))
919 assert(
MI.mayLoad() &&
"Expected MI that loads!");
923 if (
MI.memoperands_empty())
928 if (PSV->isGOT() || PSV->isConstantPool())
945 bool FoundCallerPresReg =
false;
946 if (!
MI.mayStore() ||
MI.hasUnmodeledSideEffects() ||
947 (
MI.getNumOperands() == 0))
960 if (!
TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *
MI.getMF()))
963 FoundCallerPresReg =
true;
964 }
else if (!MO.
isImm()) {
968 return FoundCallerPresReg;
986 Register CopySrcReg =
MI.getOperand(1).getReg();
990 if (!
TRI->isCallerPreservedPhysReg(CopySrcReg.
asMCReg(), *MF))
993 Register CopyDstReg =
MI.getOperand(0).getReg();
1008 bool DontMoveAcrossStore = !
HoistConstLoads || !AllowedToHoistLoads[CurLoop];
1009 if ((!
I.isSafeToMove(AA, DontMoveAcrossStore)) &&
1022 !IsGuaranteedToExecute(
I.getParent(), CurLoop)) {
1031 if (
I.isConvergent())
1034 if (!
TII->shouldHoist(
I, CurLoop))
1043 if (!IsLICMCandidate(
I, CurLoop)) {
1044 LLVM_DEBUG(
dbgs() <<
"LICM: Instruction not a LICM candidate\n");
1056 MI = Work.pop_back_val();
1059 if (!
Reg.isVirtual())
1063 if (
UseMI.isPHI()) {
1077 Work.push_back(&
UseMI);
1080 }
while (!Work.empty());
1086bool MachineLICMBase::HasHighOperandLatency(
MachineInstr &
MI,
unsigned DefIdx,
1089 if (
MRI->use_nodbg_empty(Reg))
1093 if (
UseMI.isCopyLike())
1097 for (
unsigned i = 0, e =
UseMI.getNumOperands(); i != e; ++i) {
1105 if (
TII->hasHighOperandLatency(SchedModel,
MRI,
MI, DefIdx,
UseMI, i))
1118bool MachineLICMBase::IsCheapInstruction(
MachineInstr &
MI)
const {
1122 bool isCheap =
false;
1123 unsigned NumDefs =
MI.getDesc().getNumDefs();
1124 for (
unsigned i = 0, e =
MI.getNumOperands(); NumDefs && i != e; ++i) {
1130 if (
Reg.isPhysical())
1133 if (!
TII->hasLowDefLatency(SchedModel,
MI, i))
1146 for (
const auto &RPIdAndCost :
Cost) {
1147 if (RPIdAndCost.second <= 0)
1150 unsigned Class = RPIdAndCost.first;
1151 int Limit = RegLimit[
Class];
1158 for (
const auto &RP : BackTrace)
1159 if (
static_cast<int>(RP[Class]) + RPIdAndCost.second >= Limit)
1169void MachineLICMBase::UpdateBackTraceRegPressure(
const MachineInstr *
MI) {
1172 auto Cost = calcRegisterCost(
MI,
false,
1176 for (
auto &RP : BackTrace)
1177 for (
const auto &RPIdAndCost :
Cost)
1178 RP[RPIdAndCost.first] += RPIdAndCost.second;
1185 if (
MI.isImplicitDef())
1203 bool CheapInstr = IsCheapInstruction(
MI);
1204 bool CreatesCopy = HasLoopPHIUse(&
MI, CurLoop);
1207 if (CheapInstr && CreatesCopy) {
1214 if (isTriviallyReMaterializable(
MI))
1219 for (
unsigned i = 0, e =
MI.getDesc().getNumOperands(); i != e; ++i) {
1224 if (!
Reg.isVirtual())
1226 if (MO.
isDef() && HasHighOperandLatency(
MI, i, Reg, CurLoop)) {
1239 auto Cost = calcRegisterCost(&
MI,
false,
1244 if (!CanCauseHighRegPressure(
Cost, CheapInstr)) {
1260 (!IsGuaranteedToExecute(
MI.getParent(), CurLoop) && !MayCSE(&
MI))) {
1268 if (
MI.isCopy() &&
MI.getOperand(0).isReg() &&
1269 (DefReg =
MI.getOperand(0).getReg()).isVirtual() &&
1270 MI.getOperand(1).isReg() &&
MI.getOperand(1).getReg().isVirtual() &&
1271 IsLoopInvariantInst(
MI, CurLoop) &&
1272 any_of(
MRI->use_nodbg_instructions(
MI.getOperand(0).getReg()),
1274 if (!CurLoop->contains(&UseMI))
1280 if (CanCauseHighRegPressure(Cost, false) &&
1281 !CurLoop->isLoopInvariant(UseMI, DefReg))
1290 if (!isTriviallyReMaterializable(
MI) &&
1291 !
MI.isDereferenceableInvariantLoad()) {
1305 if (
MI->canFoldAsLoad())
1311 if (!
MI->isDereferenceableInvariantLoad())
1315 unsigned LoadRegIndex;
1317 TII->getOpcodeAfterMemoryUnfold(
MI->getOpcode(),
1321 if (NewOpc == 0)
return nullptr;
1334 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1337 "Unfolded a load into multiple instructions!");
1344 if (!IsLoopInvariantInst(*NewMIs[0], CurLoop) ||
1345 !IsProfitableToHoist(*NewMIs[0], CurLoop)) {
1346 NewMIs[0]->eraseFromParent();
1347 NewMIs[1]->eraseFromParent();
1352 UpdateRegPressure(NewMIs[1]);
1357 if (
MI->shouldUpdateCallSiteInfo())
1360 MI->eraseFromParent();
1374void MachineLICMBase::InitializeLoadsHoistableLoops() {
1380 while (!Worklist.empty()) {
1381 auto *
L = Worklist.pop_back_val();
1382 AllowedToHoistLoads[
L] =
true;
1384 Worklist.insert(Worklist.end(),
L->getSubLoops().begin(),
1385 L->getSubLoops().end());
1398 if (!AllowedToHoistLoads[
Loop])
1400 for (
auto &
MI : *
MBB) {
1401 if (!
MI.mayStore() && !
MI.isCall() &&
1402 !(
MI.mayLoad() &&
MI.hasOrderedMemoryRef()))
1405 AllowedToHoistLoads[
L] =
false;
1416 std::vector<MachineInstr *> &PrevMIs) {
1418 if (
TII->produceSameValue(*
MI, *PrevMI, (PreRegAlloc ?
MRI :
nullptr)))
1428bool MachineLICMBase::EliminateCSE(
1430 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI) {
1433 if (
MI->isImplicitDef())
1438 if (
MI->mayLoad() && !
MI->isDereferenceableInvariantLoad())
1447 for (
unsigned i = 0, e =
MI->getNumOperands(); i != e; ++i) {
1452 MO.
getReg() == Dup->getOperand(i).getReg()) &&
1453 "Instructions with different phys regs are not identical!");
1460 for (
unsigned i = 0, e = Defs.
size(); i != e; ++i) {
1461 unsigned Idx = Defs[i];
1466 if (!
MRI->constrainRegClass(DupReg,
MRI->getRegClass(Reg))) {
1468 for (
unsigned j = 0;
j != i; ++
j)
1469 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1474 for (
unsigned Idx : Defs) {
1477 MRI->replaceRegWith(Reg, DupReg);
1478 MRI->clearKillFlags(DupReg);
1480 if (!
MRI->use_nodbg_empty(DupReg))
1481 Dup->getOperand(
Idx).setIsDead(
false);
1484 MI->eraseFromParent();
1494 if (
MI->mayLoad() && !
MI->isDereferenceableInvariantLoad())
1497 unsigned Opcode =
MI->getOpcode();
1498 for (
auto &Map : CSEMap) {
1502 Map.second.find(Opcode);
1505 if (CI ==
Map.second.end() ||
MI->isImplicitDef())
1507 if (LookForDuplicate(
MI, CI->second) !=
nullptr)
1525 isTgtHotterThanSrc(SrcBlock, Preheader)) {
1526 ++NumNotHoistedDueToHotness;
1527 return HoistResult::NotHoisted;
1530 bool HasExtractHoistableLoad =
false;
1531 if (!IsLoopInvariantInst(*
MI, CurLoop) ||
1532 !IsProfitableToHoist(*
MI, CurLoop)) {
1534 MI = ExtractHoistableLoad(
MI, CurLoop);
1536 return HoistResult::NotHoisted;
1537 HasExtractHoistableLoad =
true;
1548 dbgs() <<
"Hoisting " << *
MI;
1549 if (
MI->getParent()->getBasicBlock())
1559 InitCSEMap(Preheader);
1560 FirstInLoop =
false;
1564 unsigned Opcode =
MI->getOpcode();
1565 bool HasCSEDone =
false;
1566 for (
auto &Map : CSEMap) {
1570 Map.second.find(Opcode);
1571 if (CI !=
Map.second.end()) {
1572 if (EliminateCSE(
MI, CI)) {
1587 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
1591 UpdateBackTraceRegPressure(
MI);
1600 CSEMap[Preheader][Opcode].push_back(
MI);
1606 if (HasCSEDone || HasExtractHoistableLoad)
1607 return HoistResult::Hoisted | HoistResult::ErasedMI;
1608 return HoistResult::Hoisted;
1613MachineLICMBase::getCurPreheader(
MachineLoop *CurLoop,
1622 if (!CurPreheader) {
1624 if (!CurPreheader) {
1632 if (!CurPreheader) {
1638 return CurPreheader;
1653 double Ratio = (double)DstBF / SrcBF;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
This file implements the BitVector class.
COFF::MachineTypes Machine
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
const HexagonInstrInfo * TII
static bool isExitBlock(BasicBlock *BB, const SmallVectorImpl< BasicBlock * > &ExitBlocks)
Return true if the specified block is in the list.
Machine Loop Invariant Code false early machinelicm
static cl::opt< bool > HoistConstStores("hoist-const-stores", cl::desc("Hoist invariant stores"), cl::init(true), cl::Hidden)
static cl::opt< UseBFI > DisableHoistingToHotterBlocks("disable-hoisting-to-hotter-blocks", cl::desc("Disable hoisting instructions to" " hotter blocks"), cl::init(UseBFI::PGO), cl::Hidden, cl::values(clEnumValN(UseBFI::None, "none", "disable the feature"), clEnumValN(UseBFI::PGO, "pgo", "enable the feature when using profile data"), clEnumValN(UseBFI::All, "all", "enable the feature with/wo profile data")))
static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI)
Return true if this machine instruction loads from global offset table or constant pool.
static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI)
static cl::opt< bool > HoistConstLoads("hoist-const-loads", cl::desc("Hoist invariant loads"), cl::init(true), cl::Hidden)
Machine Loop Invariant Code Motion
static cl::opt< bool > AvoidSpeculation("avoid-speculation", cl::desc("MachineLICM should avoid speculation"), cl::init(true), cl::Hidden)
static bool InstructionStoresToFI(const MachineInstr *MI, int FI)
Return true if instruction stores to the specified frame.
static bool isCopyFeedingInvariantStore(const MachineInstr &MI, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
static cl::opt< bool > HoistCheapInsts("hoist-cheap-insts", cl::desc("MachineLICM should hoist even cheap instructions"), cl::init(false), cl::Hidden)
static bool isInvariantStore(const MachineInstr &MI, const TargetRegisterInfo *TRI, const MachineRegisterInfo *MRI)
static cl::opt< unsigned > BlockFrequencyRatioThreshold("block-freq-ratio-threshold", cl::desc("Do not hoist instructions if target" "block is N times hotter than the source."), cl::init(100), cl::Hidden)
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
TLS Variable Hoist
When an instruction is found to use only loop invariant operands that are safe to hoist,...
This file describes how to lower LLVM code to machine code.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
bool test(unsigned Idx) const
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
bool contains(const_arg_type_t< KeyT > Val) const
Return true if the specified key is in the map, false otherwise.
Base class for the actual dominator tree node.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
void getExitBlocks(SmallVectorImpl< BlockT * > &ExitBlocks) const
Return all of the successor blocks of this loop.
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
BlockT * getHeader() const
iterator_range< block_iterator > blocks() const
BlockT * getLoopPredecessor() const
If the given loop's header has exactly one unique predecessor outside the loop, return it.
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Represents a single loop in the control flow graph.
Describe properties that are true of each instruction in the target description file.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
unsigned pred_size() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
pred_iterator pred_begin()
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<> > *LiveInSets=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void eraseCallSiteInfo(const MachineInstr *MI)
Following functions update call site info.
Representation of each machine instruction.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
bool isLoopInvariant(MachineInstr &I, const Register ExcludeReg=0) const
Returns true if the instruction is loop invariant.
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual void releaseMemory()
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
TargetSubtargetInfo - Generic base class for all target subtargets.
LLVM Value Representation.
Reg
All possible values of the reg field in the ModR/M byte.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
initializer< Ty > init(const Ty &Val)
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void initializeMachineLICMPass(PassRegistry &)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
void initializeEarlyMachineLICMPass(PassRegistry &)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...