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AArch64Disassembler.cpp
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1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64Disassembler.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm-c/Disassembler.h"
19 #include "llvm/MC/MCDecoderOps.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrDesc.h"
23 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/TargetRegistry.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
29 #include <algorithm>
30 #include <memory>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "aarch64-disassembler"
35 
36 // Pull DecodeStatus and its enum values into the global namespace.
38 
39 // Forward declare these because the autogenerated code will reference them.
40 // Definitions are further down.
41 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
42  uint64_t Address,
43  const MCDisassembler *Decoder);
44 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
45  uint64_t Address,
46  const MCDisassembler *Decoder);
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
48  uint64_t Address,
49  const MCDisassembler *Decoder);
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
51  uint64_t Address,
52  const MCDisassembler *Decoder);
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
54  uint64_t Address,
55  const MCDisassembler *Decoder);
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
57  uint64_t Address,
58  const MCDisassembler *Decoder);
59 static DecodeStatus
60 DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
61  const MCDisassembler *Decoder);
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
63  uint64_t Address,
64  const MCDisassembler *Decoder);
65 static DecodeStatus
66 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
67  const MCDisassembler *Decoder);
68 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
69  uint64_t Address,
70  const MCDisassembler *Decoder);
71 static DecodeStatus
73  uint64_t Address, const void *Decoder);
74 static DecodeStatus
76  uint64_t Address,
77  const MCDisassembler *Decoder);
78 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
79  uint64_t Address,
80  const MCDisassembler *Decoder);
81 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
82  uint64_t Address,
83  const MCDisassembler *Decoder);
84 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
85  uint64_t Address,
86  const MCDisassembler *Decoder);
87 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
88  uint64_t Address,
89  const MCDisassembler *Decoder);
90 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
91  uint64_t Address,
92  const MCDisassembler *Decoder);
93 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
94  uint64_t Address,
95  const MCDisassembler *Decoder);
96 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
97  uint64_t Address,
98  const MCDisassembler *Decoder);
99 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
100  uint64_t Address,
101  const MCDisassembler *Decoder);
102 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
103  uint64_t Address,
104  const MCDisassembler *Decoder);
105 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
106  uint64_t Address,
107  const MCDisassembler *Decoder);
108 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
109  uint64_t Address,
110  const MCDisassembler *Decoder);
111 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
112  uint64_t Address,
113  const MCDisassembler *Decoder);
114 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
115  uint64_t Address,
116  const MCDisassembler *Decoder);
117 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
118  uint64_t Address,
119  const MCDisassembler *Decoder);
120 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
121  uint64_t Address,
122  const void *Decoder);
123 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
124  uint64_t Address,
125  const void *Decoder);
126 static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
127  uint64_t Address,
128  const void *Decoder);
129 static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
130  uint64_t Address,
131  const void *Decoder);
132 template <unsigned NumBitsForTile>
133 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
134  uint64_t Address,
135  const MCDisassembler *Decoder);
136 static DecodeStatus
137 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
138  uint64_t Address,
139  const MCDisassembler *Decoder);
140 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
141  uint64_t Address,
142  const MCDisassembler *Decoder);
143 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
144  uint64_t Address,
145  const MCDisassembler *Decoder);
146 static DecodeStatus
147 DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
148  const MCDisassembler *Decoder);
149 static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
150  uint64_t Address,
151  const void *Decoder);
152 static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
153  uint64_t Address,
154  const void *Decoder);
155 
156 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
157  uint64_t Address,
158  const MCDisassembler *Decoder);
159 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
160  uint64_t Address,
161  const MCDisassembler *Decoder);
162 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
163  uint64_t Address,
164  const MCDisassembler *Decoder);
165 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
166  uint64_t Address,
167  const MCDisassembler *Decoder);
168 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
169  uint64_t Address,
170  const MCDisassembler *Decoder);
171 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
172  uint64_t Address,
173  const MCDisassembler *Decoder);
174 static DecodeStatus
176  const MCDisassembler *Decoder);
178  uint64_t Address,
179  const MCDisassembler *Decoder);
180 static DecodeStatus
182  const MCDisassembler *Decoder);
184  uint64_t Address,
185  const MCDisassembler *Decoder);
186 static DecodeStatus
188  const MCDisassembler *Decoder);
190  uint64_t Address,
191  const MCDisassembler *Decoder);
193  uint64_t Address,
194  const MCDisassembler *Decoder);
196  uint64_t Address,
197  const MCDisassembler *Decoder);
199  uint64_t Address,
200  const MCDisassembler *Decoder);
202  uint64_t Address,
203  const MCDisassembler *Decoder);
205  uint64_t Address,
206  const MCDisassembler *Decoder);
208  uint64_t Address,
209  const MCDisassembler *Decoder);
211  uint64_t Address,
212  const MCDisassembler *Decoder);
214  uint64_t Address,
215  const MCDisassembler *Decoder);
216 static DecodeStatus
218  const MCDisassembler *Decoder);
220  uint64_t Address,
221  const MCDisassembler *Decoder);
222 
223 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
224  uint64_t Address,
225  const MCDisassembler *Decoder);
226 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
227  uint64_t Addr,
228  const MCDisassembler *Decoder);
229 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
230  uint64_t Addr,
231  const MCDisassembler *Decoder);
232 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
233  uint64_t Addr,
234  const MCDisassembler *Decoder);
235 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
236  uint64_t Addr,
237  const MCDisassembler *Decoder);
238 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
239  uint64_t Addr,
240  const MCDisassembler *Decoder);
241 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
242  uint64_t Addr,
243  const MCDisassembler *Decoder);
244 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
245  uint64_t Addr,
246  const MCDisassembler *Decoder);
247 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
248  uint64_t Addr,
249  const MCDisassembler *Decoder);
250 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
251  uint64_t Addr,
252  const MCDisassembler *Decoder);
253 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
254  uint64_t Addr,
255  const MCDisassembler *Decoder);
256 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
257  uint64_t Addr,
258  const MCDisassembler *Decoder);
259 static DecodeStatus
261  const MCDisassembler *Decoder);
262 static DecodeStatus
264  const MCDisassembler *Decoder);
266  uint64_t Addr,
267  const MCDisassembler *Decoder);
268 static DecodeStatus
270  const MCDisassembler *Decoder);
271 template <int Bits>
272 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
273  const MCDisassembler *Decoder);
274 template <int ElementWidth>
275 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
276  const MCDisassembler *Decoder);
277 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
278  uint64_t Addr,
279  const MCDisassembler *Decoder);
280 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
281  const MCDisassembler *Decoder);
283  uint64_t Addr,
284  const MCDisassembler *Decoder);
286  uint64_t Addr,
287  const MCDisassembler *Decoder);
289  uint64_t Address,
290  const MCDisassembler *Decoder);
291 
292 #include "AArch64GenDisassemblerTables.inc"
293 #include "AArch64GenInstrInfo.inc"
294 
295 #define Success MCDisassembler::Success
296 #define Fail MCDisassembler::Fail
297 #define SoftFail MCDisassembler::SoftFail
298 
300  const MCSubtargetInfo &STI,
301  MCContext &Ctx) {
302 
303  return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
304 }
305 
307  ArrayRef<uint8_t> Bytes,
308  uint64_t Address,
309  raw_ostream &CS) const {
310  CommentStream = &CS;
311 
312  Size = 0;
313  // We want to read exactly 4 bytes of data.
314  if (Bytes.size() < 4)
315  return Fail;
316  Size = 4;
317 
318  // Encoded as a small-endian 32-bit word in the stream.
319  uint32_t Insn =
320  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
321 
322  const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
323 
324  for (const auto *Table : Tables) {
325  DecodeStatus Result =
326  decodeInstruction(Table, MI, Insn, Address, this, STI);
327 
328  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
329 
330  // For Scalable Matrix Extension (SME) instructions that have an implicit
331  // operand for the accumulator (ZA) or implicit immediate zero which isn't
332  // encoded, manually insert operand.
333  for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
335  switch (Desc.OpInfo[i].RegClass) {
336  default:
337  break;
338  case AArch64::MPRRegClassID:
339  MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
340  break;
341  case AArch64::MPR8RegClassID:
342  MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
343  break;
344  case AArch64::ZTRRegClassID:
345  MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
346  break;
347  }
348  } else if (Desc.OpInfo[i].OperandType ==
350  MI.insert(MI.begin() + i, MCOperand::createImm(0));
351  }
352  }
353 
354  if (MI.getOpcode() == AArch64::LDR_ZA ||
355  MI.getOpcode() == AArch64::STR_ZA) {
356  // Spill and fill instructions have a single immediate used for both
357  // the vector select offset and optional memory offset. Replicate
358  // the decoded immediate.
359  const MCOperand &Imm4Op = MI.getOperand(2);
360  assert(Imm4Op.isImm() && "Unexpected operand type!");
361  MI.addOperand(Imm4Op);
362  }
363 
364  if (Result != MCDisassembler::Fail)
365  return Result;
366  }
367 
368  return MCDisassembler::Fail;
369 }
370 
372  uint64_t Address) const {
373  // AArch64 instructions are always 4 bytes wide, so there's no point
374  // in skipping any smaller number of bytes if an instruction can't
375  // be decoded.
376  return 4;
377 }
378 
379 static MCSymbolizer *
381  LLVMSymbolLookupCallback SymbolLookUp,
382  void *DisInfo, MCContext *Ctx,
383  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
384  return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
385  SymbolLookUp, DisInfo);
386 }
387 
401 
410 }
411 
412 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
413  uint64_t Addr,
414  const MCDisassembler *Decoder) {
415  if (RegNo > 31)
416  return Fail;
417 
418  unsigned Register =
419  AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
421  return Success;
422 }
423 
424 static DecodeStatus
426  const MCDisassembler *Decoder) {
427  if (RegNo > 15)
428  return Fail;
429  return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
430 }
431 
432 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
433  uint64_t Addr,
434  const MCDisassembler *Decoder) {
435  if (RegNo > 31)
436  return Fail;
437 
438  unsigned Register =
439  AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
441  return Success;
442 }
443 
444 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
445  uint64_t Addr,
446  const MCDisassembler *Decoder) {
447  if (RegNo > 31)
448  return Fail;
449 
450  unsigned Register =
451  AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
453  return Success;
454 }
455 
456 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
457  uint64_t Addr,
458  const MCDisassembler *Decoder) {
459  if (RegNo > 31)
460  return Fail;
461 
462  unsigned Register =
463  AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
465  return Success;
466 }
467 
468 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
469  uint64_t Addr,
470  const MCDisassembler *Decoder) {
471  if (RegNo > 31)
472  return Fail;
473 
474  unsigned Register =
475  AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
477  return Success;
478 }
479 
480 static DecodeStatus
482  const MCDisassembler *Decoder) {
483  if (RegNo > 30)
484  return Fail;
485 
486  unsigned Register =
487  AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
488  RegNo);
490  return Success;
491 }
492 
493 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
494  uint64_t Addr,
495  const MCDisassembler *Decoder) {
496  if (RegNo > 31)
497  return Fail;
498 
499  unsigned Register =
500  AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
502  return Success;
503 }
504 
505 static DecodeStatus
506 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
507  const MCDisassembler *Decoder) {
508  if (RegNo > 22)
509  return Fail;
510  if (RegNo & 1)
511  return Fail;
512 
513  unsigned Register =
514  AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
515  RegNo >> 1);
517  return Success;
518 }
519 
520 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
521  uint64_t Addr,
522  const MCDisassembler *Decoder) {
523  if (RegNo > 31)
524  return Fail;
525  unsigned Register =
526  AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
528  return Success;
529 }
530 
531 static DecodeStatus
533  uint64_t Addr, const void *Decoder) {
534  if (RegNo > 3)
535  return Fail;
536 
537  unsigned Register =
538  AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
539  .getRegister(RegNo);
541  return Success;
542 }
543 
544 static DecodeStatus
546  uint64_t Addr,
547  const MCDisassembler *Decoder) {
548  if (RegNo > 3)
549  return Fail;
550 
551  unsigned Register =
552  AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
553  .getRegister(RegNo);
555  return Success;
556 }
557 
558 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
559  uint64_t Addr,
560  const MCDisassembler *Decoder) {
561  if (RegNo > 31)
562  return Fail;
563 
564  unsigned Register =
565  AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
567  return Success;
568 }
569 
570 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
571  uint64_t Addr,
572  const MCDisassembler *Decoder) {
573  if (RegNo > 31)
574  return Fail;
575 
576  unsigned Register =
577  AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
579  return Success;
580 }
581 
582 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
583  uint64_t Address,
584  const MCDisassembler *Decoder) {
585  if (RegNo > 31)
586  return Fail;
587 
588  unsigned Register =
589  AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
591  return Success;
592 }
593 
594 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
595  uint64_t Address,
596  const MCDisassembler *Decoder) {
597  if (RegNo > 15)
598  return Fail;
599  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
600 }
601 
602 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
603  uint64_t Address,
604  const MCDisassembler *Decoder) {
605  if (RegNo > 7)
606  return Fail;
607  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
608 }
609 
610 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
611  uint64_t Address,
612  const MCDisassembler *Decoder) {
613  if (RegNo > 31)
614  return Fail;
615  unsigned Register =
616  AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
618  return Success;
619 }
620 
621 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
622  uint64_t Address,
623  const MCDisassembler *Decoder) {
624  if (RegNo > 31)
625  return Fail;
626  unsigned Register =
627  AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
629  return Success;
630 }
631 
632 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
633  uint64_t Address,
634  const MCDisassembler *Decoder) {
635  if (RegNo > 31)
636  return Fail;
637  unsigned Register =
638  AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
640  return Success;
641 }
642 
643 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
644  uint64_t Address,
645  const void *Decoder) {
646  if (RegNo * 2 > 30)
647  return Fail;
648  unsigned Register =
649  AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
651  return Success;
652 }
653 
654 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
655  uint64_t Address,
656  const void *Decoder) {
657  if (RegNo * 4 > 28)
658  return Fail;
659  unsigned Register =
660  AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
662  return Success;
663 }
664 
666  uint64_t Address,
667  const void *Decoder) {
668  if (RegNo > 15)
669  return Fail;
670  unsigned Register =
671  AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
672  RegNo);
674  return Success;
675 }
676 
678  uint64_t Address,
679  const void *Decoder) {
680  if (RegNo > 7)
681  return Fail;
682  unsigned Register =
683  AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
684  RegNo);
686  return Success;
687 }
688 
689 static DecodeStatus
691  uint64_t Address,
692  const MCDisassembler *Decoder) {
693  if (RegMask > 0xFF)
694  return Fail;
695  Inst.addOperand(MCOperand::createImm(RegMask));
696  return Success;
697 }
698 
701  {AArch64::ZAB0},
702  {AArch64::ZAH0, AArch64::ZAH1},
703  {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
704  {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3,
705  AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
706  {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3,
707  AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7,
708  AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11,
709  AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}};
710 
711 template <unsigned NumBitsForTile>
712 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
713  uint64_t Address,
714  const MCDisassembler *Decoder) {
715  unsigned LastReg = (1 << NumBitsForTile) - 1;
716  if (RegNo > LastReg)
717  return Fail;
718  Inst.addOperand(
719  MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
720  return Success;
721 }
722 
723 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
724  uint64_t Addr,
725  const MCDisassembler *Decoder) {
726  if (RegNo > 15)
727  return Fail;
728 
729  unsigned Register =
730  AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
732  return Success;
733 }
734 
735 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
736  uint64_t Addr,
737  const MCDisassembler *Decoder) {
738  if (RegNo > 7)
739  return Fail;
740 
741  // Just reuse the PPR decode table
742  return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
743 }
744 
745 static DecodeStatus
747  const MCDisassembler *Decoder) {
748  if (RegNo > 7)
749  return Fail;
750 
751  // Just reuse the PPR decode table
752  return DecodePPRRegisterClass(Inst, RegNo + 8, Addr, Decoder);
753 }
754 
755 static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
756  uint64_t Address,
757  const void *Decoder) {
758  if (RegNo > 15)
759  return Fail;
760 
761  unsigned Register =
762  AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
764  return Success;
765 }
766 
767 static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
768  uint64_t Address,
769  const void *Decoder) {
770  if ((RegNo * 2) > 14)
771  return Fail;
772  unsigned Register =
773  AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
775  return Success;
776 }
777 
778 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
779  uint64_t Addr,
780  const MCDisassembler *Decoder) {
781  if (RegNo > 31)
782  return Fail;
783  unsigned Register =
784  AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
786  return Success;
787 }
788 
789 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
790  uint64_t Addr,
791  const MCDisassembler *Decoder) {
792  if (RegNo > 31)
793  return Fail;
794  unsigned Register =
795  AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
797  return Success;
798 }
799 
800 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
801  uint64_t Addr,
802  const MCDisassembler *Decoder) {
803  if (RegNo > 31)
804  return Fail;
805  unsigned Register =
806  AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
808  return Success;
809 }
810 
811 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
812  uint64_t Addr,
813  const MCDisassembler *Decoder) {
814  if (RegNo > 31)
815  return Fail;
816  unsigned Register =
817  AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
819  return Success;
820 }
821 
822 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
823  uint64_t Addr,
824  const MCDisassembler *Decoder) {
825  if (RegNo > 31)
826  return Fail;
827  unsigned Register =
828  AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
830  return Success;
831 }
832 
833 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
834  uint64_t Addr,
835  const MCDisassembler *Decoder) {
836  if (RegNo > 31)
837  return Fail;
838  unsigned Register =
839  AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
841  return Success;
842 }
843 
845  uint64_t Addr,
846  const MCDisassembler *Decoder) {
847  // scale{5} is asserted as 1 in tblgen.
848  Imm |= 0x20;
849  Inst.addOperand(MCOperand::createImm(64 - Imm));
850  return Success;
851 }
852 
854  uint64_t Addr,
855  const MCDisassembler *Decoder) {
856  Inst.addOperand(MCOperand::createImm(64 - Imm));
857  return Success;
858 }
859 
860 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
861  uint64_t Addr,
862  const MCDisassembler *Decoder) {
863  int64_t ImmVal = Imm;
864 
865  // Sign-extend 19-bit immediate.
866  if (ImmVal & (1 << (19 - 1)))
867  ImmVal |= ~((1LL << 19) - 1);
868 
869  if (!Decoder->tryAddingSymbolicOperand(
870  Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
871  Inst.addOperand(MCOperand::createImm(ImmVal));
872  return Success;
873 }
874 
875 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
876  uint64_t Address,
877  const MCDisassembler *Decoder) {
878  Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
880  return Success;
881 }
882 
884  uint64_t Address,
885  const MCDisassembler *Decoder) {
887 
888  // Every system register in the encoding space is valid with the syntax
889  // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
890  return Success;
891 }
892 
894  uint64_t Address,
895  const MCDisassembler *Decoder) {
897 
898  return Success;
899 }
900 
902  uint64_t Address,
903  const MCDisassembler *Decoder) {
904  // This decoder exists to add the dummy Lane operand to the MCInst, which must
905  // be 1 in assembly but has no other real manifestation.
906  unsigned Rd = fieldFromInstruction(Insn, 0, 5);
907  unsigned Rn = fieldFromInstruction(Insn, 5, 5);
908  unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
909 
910  if (IsToVec) {
911  DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
912  DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
913  } else {
914  DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
915  DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
916  }
917 
918  // Add the lane
920 
921  return Success;
922 }
923 
924 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
925  unsigned Add) {
926  Inst.addOperand(MCOperand::createImm(Add - Imm));
927  return Success;
928 }
929 
930 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
931  unsigned Add) {
932  Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
933  return Success;
934 }
935 
937  uint64_t Addr,
938  const MCDisassembler *Decoder) {
939  return DecodeVecShiftRImm(Inst, Imm, 64);
940 }
941 
943  uint64_t Addr,
944  const MCDisassembler *Decoder) {
945  return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
946 }
947 
949  uint64_t Addr,
950  const MCDisassembler *Decoder) {
951  return DecodeVecShiftRImm(Inst, Imm, 32);
952 }
953 
955  uint64_t Addr,
956  const MCDisassembler *Decoder) {
957  return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
958 }
959 
961  uint64_t Addr,
962  const MCDisassembler *Decoder) {
963  return DecodeVecShiftRImm(Inst, Imm, 16);
964 }
965 
967  uint64_t Addr,
968  const MCDisassembler *Decoder) {
969  return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
970 }
971 
973  uint64_t Addr,
974  const MCDisassembler *Decoder) {
975  return DecodeVecShiftRImm(Inst, Imm, 8);
976 }
977 
979  uint64_t Addr,
980  const MCDisassembler *Decoder) {
981  return DecodeVecShiftLImm(Inst, Imm, 64);
982 }
983 
985  uint64_t Addr,
986  const MCDisassembler *Decoder) {
987  return DecodeVecShiftLImm(Inst, Imm, 32);
988 }
989 
991  uint64_t Addr,
992  const MCDisassembler *Decoder) {
993  return DecodeVecShiftLImm(Inst, Imm, 16);
994 }
995 
997  uint64_t Addr,
998  const MCDisassembler *Decoder) {
999  return DecodeVecShiftLImm(Inst, Imm, 8);
1000 }
1001 
1002 static DecodeStatus
1004  const MCDisassembler *Decoder) {
1005  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1006  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1007  unsigned Rm = fieldFromInstruction(insn, 16, 5);
1008  unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1009  unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1010  unsigned shift = (shiftHi << 6) | shiftLo;
1011  switch (Inst.getOpcode()) {
1012  default:
1013  return Fail;
1014  case AArch64::ADDWrs:
1015  case AArch64::ADDSWrs:
1016  case AArch64::SUBWrs:
1017  case AArch64::SUBSWrs:
1018  // if shift == '11' then ReservedValue()
1019  if (shiftHi == 0x3)
1020  return Fail;
1021  [[fallthrough]];
1022  case AArch64::ANDWrs:
1023  case AArch64::ANDSWrs:
1024  case AArch64::BICWrs:
1025  case AArch64::BICSWrs:
1026  case AArch64::ORRWrs:
1027  case AArch64::ORNWrs:
1028  case AArch64::EORWrs:
1029  case AArch64::EONWrs: {
1030  // if sf == '0' and imm6<5> == '1' then ReservedValue()
1031  if (shiftLo >> 5 == 1)
1032  return Fail;
1033  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1034  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1035  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1036  break;
1037  }
1038  case AArch64::ADDXrs:
1039  case AArch64::ADDSXrs:
1040  case AArch64::SUBXrs:
1041  case AArch64::SUBSXrs:
1042  // if shift == '11' then ReservedValue()
1043  if (shiftHi == 0x3)
1044  return Fail;
1045  [[fallthrough]];
1046  case AArch64::ANDXrs:
1047  case AArch64::ANDSXrs:
1048  case AArch64::BICXrs:
1049  case AArch64::BICSXrs:
1050  case AArch64::ORRXrs:
1051  case AArch64::ORNXrs:
1052  case AArch64::EORXrs:
1053  case AArch64::EONXrs:
1054  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1055  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1056  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1057  break;
1058  }
1059 
1061  return Success;
1062 }
1063 
1065  uint64_t Addr,
1066  const MCDisassembler *Decoder) {
1067  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1068  unsigned imm = fieldFromInstruction(insn, 5, 16);
1069  unsigned shift = fieldFromInstruction(insn, 21, 2);
1070  shift <<= 4;
1071  switch (Inst.getOpcode()) {
1072  default:
1073  return Fail;
1074  case AArch64::MOVZWi:
1075  case AArch64::MOVNWi:
1076  case AArch64::MOVKWi:
1077  if (shift & (1U << 5))
1078  return Fail;
1079  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1080  break;
1081  case AArch64::MOVZXi:
1082  case AArch64::MOVNXi:
1083  case AArch64::MOVKXi:
1084  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1085  break;
1086  }
1087 
1088  if (Inst.getOpcode() == AArch64::MOVKWi ||
1089  Inst.getOpcode() == AArch64::MOVKXi)
1090  Inst.addOperand(Inst.getOperand(0));
1091 
1092  Inst.addOperand(MCOperand::createImm(imm));
1094  return Success;
1095 }
1096 
1097 static DecodeStatus
1099  const MCDisassembler *Decoder) {
1100  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1101  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1102  unsigned offset = fieldFromInstruction(insn, 10, 12);
1103 
1104  switch (Inst.getOpcode()) {
1105  default:
1106  return Fail;
1107  case AArch64::PRFMui:
1108  // Rt is an immediate in prefetch.
1109  Inst.addOperand(MCOperand::createImm(Rt));
1110  break;
1111  case AArch64::STRBBui:
1112  case AArch64::LDRBBui:
1113  case AArch64::LDRSBWui:
1114  case AArch64::STRHHui:
1115  case AArch64::LDRHHui:
1116  case AArch64::LDRSHWui:
1117  case AArch64::STRWui:
1118  case AArch64::LDRWui:
1119  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1120  break;
1121  case AArch64::LDRSBXui:
1122  case AArch64::LDRSHXui:
1123  case AArch64::LDRSWui:
1124  case AArch64::STRXui:
1125  case AArch64::LDRXui:
1126  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1127  break;
1128  case AArch64::LDRQui:
1129  case AArch64::STRQui:
1130  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1131  break;
1132  case AArch64::LDRDui:
1133  case AArch64::STRDui:
1134  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1135  break;
1136  case AArch64::LDRSui:
1137  case AArch64::STRSui:
1138  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1139  break;
1140  case AArch64::LDRHui:
1141  case AArch64::STRHui:
1142  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1143  break;
1144  case AArch64::LDRBui:
1145  case AArch64::STRBui:
1146  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1147  break;
1148  }
1149 
1150  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1151  if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
1152  Inst.addOperand(MCOperand::createImm(offset));
1153  return Success;
1154 }
1155 
1157  uint64_t Addr,
1158  const MCDisassembler *Decoder) {
1159  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1160  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1161  int64_t offset = fieldFromInstruction(insn, 12, 9);
1162 
1163  // offset is a 9-bit signed immediate, so sign extend it to
1164  // fill the unsigned.
1165  if (offset & (1 << (9 - 1)))
1166  offset |= ~((1LL << 9) - 1);
1167 
1168  // First operand is always the writeback to the address register, if needed.
1169  switch (Inst.getOpcode()) {
1170  default:
1171  break;
1172  case AArch64::LDRSBWpre:
1173  case AArch64::LDRSHWpre:
1174  case AArch64::STRBBpre:
1175  case AArch64::LDRBBpre:
1176  case AArch64::STRHHpre:
1177  case AArch64::LDRHHpre:
1178  case AArch64::STRWpre:
1179  case AArch64::LDRWpre:
1180  case AArch64::LDRSBWpost:
1181  case AArch64::LDRSHWpost:
1182  case AArch64::STRBBpost:
1183  case AArch64::LDRBBpost:
1184  case AArch64::STRHHpost:
1185  case AArch64::LDRHHpost:
1186  case AArch64::STRWpost:
1187  case AArch64::LDRWpost:
1188  case AArch64::LDRSBXpre:
1189  case AArch64::LDRSHXpre:
1190  case AArch64::STRXpre:
1191  case AArch64::LDRSWpre:
1192  case AArch64::LDRXpre:
1193  case AArch64::LDRSBXpost:
1194  case AArch64::LDRSHXpost:
1195  case AArch64::STRXpost:
1196  case AArch64::LDRSWpost:
1197  case AArch64::LDRXpost:
1198  case AArch64::LDRQpre:
1199  case AArch64::STRQpre:
1200  case AArch64::LDRQpost:
1201  case AArch64::STRQpost:
1202  case AArch64::LDRDpre:
1203  case AArch64::STRDpre:
1204  case AArch64::LDRDpost:
1205  case AArch64::STRDpost:
1206  case AArch64::LDRSpre:
1207  case AArch64::STRSpre:
1208  case AArch64::LDRSpost:
1209  case AArch64::STRSpost:
1210  case AArch64::LDRHpre:
1211  case AArch64::STRHpre:
1212  case AArch64::LDRHpost:
1213  case AArch64::STRHpost:
1214  case AArch64::LDRBpre:
1215  case AArch64::STRBpre:
1216  case AArch64::LDRBpost:
1217  case AArch64::STRBpost:
1218  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1219  break;
1220  }
1221 
1222  switch (Inst.getOpcode()) {
1223  default:
1224  return Fail;
1225  case AArch64::PRFUMi:
1226  // Rt is an immediate in prefetch.
1227  Inst.addOperand(MCOperand::createImm(Rt));
1228  break;
1229  case AArch64::STURBBi:
1230  case AArch64::LDURBBi:
1231  case AArch64::LDURSBWi:
1232  case AArch64::STURHHi:
1233  case AArch64::LDURHHi:
1234  case AArch64::LDURSHWi:
1235  case AArch64::STURWi:
1236  case AArch64::LDURWi:
1237  case AArch64::LDTRSBWi:
1238  case AArch64::LDTRSHWi:
1239  case AArch64::STTRWi:
1240  case AArch64::LDTRWi:
1241  case AArch64::STTRHi:
1242  case AArch64::LDTRHi:
1243  case AArch64::LDTRBi:
1244  case AArch64::STTRBi:
1245  case AArch64::LDRSBWpre:
1246  case AArch64::LDRSHWpre:
1247  case AArch64::STRBBpre:
1248  case AArch64::LDRBBpre:
1249  case AArch64::STRHHpre:
1250  case AArch64::LDRHHpre:
1251  case AArch64::STRWpre:
1252  case AArch64::LDRWpre:
1253  case AArch64::LDRSBWpost:
1254  case AArch64::LDRSHWpost:
1255  case AArch64::STRBBpost:
1256  case AArch64::LDRBBpost:
1257  case AArch64::STRHHpost:
1258  case AArch64::LDRHHpost:
1259  case AArch64::STRWpost:
1260  case AArch64::LDRWpost:
1261  case AArch64::STLURBi:
1262  case AArch64::STLURHi:
1263  case AArch64::STLURWi:
1264  case AArch64::LDAPURBi:
1265  case AArch64::LDAPURSBWi:
1266  case AArch64::LDAPURHi:
1267  case AArch64::LDAPURSHWi:
1268  case AArch64::LDAPURi:
1269  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1270  break;
1271  case AArch64::LDURSBXi:
1272  case AArch64::LDURSHXi:
1273  case AArch64::LDURSWi:
1274  case AArch64::STURXi:
1275  case AArch64::LDURXi:
1276  case AArch64::LDTRSBXi:
1277  case AArch64::LDTRSHXi:
1278  case AArch64::LDTRSWi:
1279  case AArch64::STTRXi:
1280  case AArch64::LDTRXi:
1281  case AArch64::LDRSBXpre:
1282  case AArch64::LDRSHXpre:
1283  case AArch64::STRXpre:
1284  case AArch64::LDRSWpre:
1285  case AArch64::LDRXpre:
1286  case AArch64::LDRSBXpost:
1287  case AArch64::LDRSHXpost:
1288  case AArch64::STRXpost:
1289  case AArch64::LDRSWpost:
1290  case AArch64::LDRXpost:
1291  case AArch64::LDAPURSWi:
1292  case AArch64::LDAPURSHXi:
1293  case AArch64::LDAPURSBXi:
1294  case AArch64::STLURXi:
1295  case AArch64::LDAPURXi:
1296  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1297  break;
1298  case AArch64::LDURQi:
1299  case AArch64::STURQi:
1300  case AArch64::LDRQpre:
1301  case AArch64::STRQpre:
1302  case AArch64::LDRQpost:
1303  case AArch64::STRQpost:
1304  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1305  break;
1306  case AArch64::LDURDi:
1307  case AArch64::STURDi:
1308  case AArch64::LDRDpre:
1309  case AArch64::STRDpre:
1310  case AArch64::LDRDpost:
1311  case AArch64::STRDpost:
1312  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1313  break;
1314  case AArch64::LDURSi:
1315  case AArch64::STURSi:
1316  case AArch64::LDRSpre:
1317  case AArch64::STRSpre:
1318  case AArch64::LDRSpost:
1319  case AArch64::STRSpost:
1320  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1321  break;
1322  case AArch64::LDURHi:
1323  case AArch64::STURHi:
1324  case AArch64::LDRHpre:
1325  case AArch64::STRHpre:
1326  case AArch64::LDRHpost:
1327  case AArch64::STRHpost:
1328  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1329  break;
1330  case AArch64::LDURBi:
1331  case AArch64::STURBi:
1332  case AArch64::LDRBpre:
1333  case AArch64::STRBpre:
1334  case AArch64::LDRBpost:
1335  case AArch64::STRBpost:
1336  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1337  break;
1338  }
1339 
1340  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1341  Inst.addOperand(MCOperand::createImm(offset));
1342 
1343  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1344  bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1345  bool IsFP = fieldFromInstruction(insn, 26, 1);
1346 
1347  // Cannot write back to a transfer register (but xzr != sp).
1348  if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1349  return SoftFail;
1350 
1351  return Success;
1352 }
1353 
1354 static DecodeStatus
1356  const MCDisassembler *Decoder) {
1357  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1358  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1359  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1360  unsigned Rs = fieldFromInstruction(insn, 16, 5);
1361 
1362  unsigned Opcode = Inst.getOpcode();
1363  switch (Opcode) {
1364  default:
1365  return Fail;
1366  case AArch64::STLXRW:
1367  case AArch64::STLXRB:
1368  case AArch64::STLXRH:
1369  case AArch64::STXRW:
1370  case AArch64::STXRB:
1371  case AArch64::STXRH:
1372  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1373  [[fallthrough]];
1374  case AArch64::LDARW:
1375  case AArch64::LDARB:
1376  case AArch64::LDARH:
1377  case AArch64::LDAXRW:
1378  case AArch64::LDAXRB:
1379  case AArch64::LDAXRH:
1380  case AArch64::LDXRW:
1381  case AArch64::LDXRB:
1382  case AArch64::LDXRH:
1383  case AArch64::STLRW:
1384  case AArch64::STLRB:
1385  case AArch64::STLRH:
1386  case AArch64::STLLRW:
1387  case AArch64::STLLRB:
1388  case AArch64::STLLRH:
1389  case AArch64::LDLARW:
1390  case AArch64::LDLARB:
1391  case AArch64::LDLARH:
1392  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1393  break;
1394  case AArch64::STLXRX:
1395  case AArch64::STXRX:
1396  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1397  [[fallthrough]];
1398  case AArch64::LDARX:
1399  case AArch64::LDAXRX:
1400  case AArch64::LDXRX:
1401  case AArch64::STLRX:
1402  case AArch64::LDLARX:
1403  case AArch64::STLLRX:
1404  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1405  break;
1406  case AArch64::STLXPW:
1407  case AArch64::STXPW:
1408  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1409  [[fallthrough]];
1410  case AArch64::LDAXPW:
1411  case AArch64::LDXPW:
1412  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1413  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1414  break;
1415  case AArch64::STLXPX:
1416  case AArch64::STXPX:
1417  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1418  [[fallthrough]];
1419  case AArch64::LDAXPX:
1420  case AArch64::LDXPX:
1421  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1422  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1423  break;
1424  }
1425 
1426  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1427 
1428  // You shouldn't load to the same register twice in an instruction...
1429  if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1430  Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1431  Rt == Rt2)
1432  return SoftFail;
1433 
1434  return Success;
1435 }
1436 
1438  uint64_t Addr,
1439  const MCDisassembler *Decoder) {
1440  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1441  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1442  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1443  int64_t offset = fieldFromInstruction(insn, 15, 7);
1444  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1445 
1446  // offset is a 7-bit signed immediate, so sign extend it to
1447  // fill the unsigned.
1448  if (offset & (1 << (7 - 1)))
1449  offset |= ~((1LL << 7) - 1);
1450 
1451  unsigned Opcode = Inst.getOpcode();
1452  bool NeedsDisjointWritebackTransfer = false;
1453 
1454  // First operand is always writeback of base register.
1455  switch (Opcode) {
1456  default:
1457  break;
1458  case AArch64::LDPXpost:
1459  case AArch64::STPXpost:
1460  case AArch64::LDPSWpost:
1461  case AArch64::LDPXpre:
1462  case AArch64::STPXpre:
1463  case AArch64::LDPSWpre:
1464  case AArch64::LDPWpost:
1465  case AArch64::STPWpost:
1466  case AArch64::LDPWpre:
1467  case AArch64::STPWpre:
1468  case AArch64::LDPQpost:
1469  case AArch64::STPQpost:
1470  case AArch64::LDPQpre:
1471  case AArch64::STPQpre:
1472  case AArch64::LDPDpost:
1473  case AArch64::STPDpost:
1474  case AArch64::LDPDpre:
1475  case AArch64::STPDpre:
1476  case AArch64::LDPSpost:
1477  case AArch64::STPSpost:
1478  case AArch64::LDPSpre:
1479  case AArch64::STPSpre:
1480  case AArch64::STGPpre:
1481  case AArch64::STGPpost:
1482  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1483  break;
1484  }
1485 
1486  switch (Opcode) {
1487  default:
1488  return Fail;
1489  case AArch64::LDPXpost:
1490  case AArch64::STPXpost:
1491  case AArch64::LDPSWpost:
1492  case AArch64::LDPXpre:
1493  case AArch64::STPXpre:
1494  case AArch64::LDPSWpre:
1495  case AArch64::STGPpre:
1496  case AArch64::STGPpost:
1497  NeedsDisjointWritebackTransfer = true;
1498  [[fallthrough]];
1499  case AArch64::LDNPXi:
1500  case AArch64::STNPXi:
1501  case AArch64::LDPXi:
1502  case AArch64::STPXi:
1503  case AArch64::LDPSWi:
1504  case AArch64::STGPi:
1505  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1506  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1507  break;
1508  case AArch64::LDPWpost:
1509  case AArch64::STPWpost:
1510  case AArch64::LDPWpre:
1511  case AArch64::STPWpre:
1512  NeedsDisjointWritebackTransfer = true;
1513  [[fallthrough]];
1514  case AArch64::LDNPWi:
1515  case AArch64::STNPWi:
1516  case AArch64::LDPWi:
1517  case AArch64::STPWi:
1518  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1519  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1520  break;
1521  case AArch64::LDNPQi:
1522  case AArch64::STNPQi:
1523  case AArch64::LDPQpost:
1524  case AArch64::STPQpost:
1525  case AArch64::LDPQi:
1526  case AArch64::STPQi:
1527  case AArch64::LDPQpre:
1528  case AArch64::STPQpre:
1529  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1530  DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1531  break;
1532  case AArch64::LDNPDi:
1533  case AArch64::STNPDi:
1534  case AArch64::LDPDpost:
1535  case AArch64::STPDpost:
1536  case AArch64::LDPDi:
1537  case AArch64::STPDi:
1538  case AArch64::LDPDpre:
1539  case AArch64::STPDpre:
1540  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1541  DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1542  break;
1543  case AArch64::LDNPSi:
1544  case AArch64::STNPSi:
1545  case AArch64::LDPSpost:
1546  case AArch64::STPSpost:
1547  case AArch64::LDPSi:
1548  case AArch64::STPSi:
1549  case AArch64::LDPSpre:
1550  case AArch64::STPSpre:
1551  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1552  DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1553  break;
1554  }
1555 
1556  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1557  Inst.addOperand(MCOperand::createImm(offset));
1558 
1559  // You shouldn't load to the same register twice in an instruction...
1560  if (IsLoad && Rt == Rt2)
1561  return SoftFail;
1562 
1563  // ... or do any operation that writes-back to a transfer register. But note
1564  // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1565  if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1566  return SoftFail;
1567 
1568  return Success;
1569 }
1570 
1572  uint64_t Addr,
1573  const MCDisassembler *Decoder) {
1574  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1575  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1576  uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1577  fieldFromInstruction(insn, 12, 9);
1578  unsigned writeback = fieldFromInstruction(insn, 11, 1);
1579 
1580  switch (Inst.getOpcode()) {
1581  default:
1582  return Fail;
1583  case AArch64::LDRAAwriteback:
1584  case AArch64::LDRABwriteback:
1585  DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1586  Decoder);
1587  break;
1588  case AArch64::LDRAAindexed:
1589  case AArch64::LDRABindexed:
1590  break;
1591  }
1592 
1593  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1594  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1595  DecodeSImm<10>(Inst, offset, Addr, Decoder);
1596 
1597  if (writeback && Rt == Rn && Rn != 31) {
1598  return SoftFail;
1599  }
1600 
1601  return Success;
1602 }
1603 
1605  uint64_t Addr,
1606  const MCDisassembler *Decoder) {
1607  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1608  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1609  unsigned Rm = fieldFromInstruction(insn, 16, 5);
1610  unsigned extend = fieldFromInstruction(insn, 10, 6);
1611 
1612  unsigned shift = extend & 0x7;
1613  if (shift > 4)
1614  return Fail;
1615 
1616  switch (Inst.getOpcode()) {
1617  default:
1618  return Fail;
1619  case AArch64::ADDWrx:
1620  case AArch64::SUBWrx:
1621  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1622  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1623  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1624  break;
1625  case AArch64::ADDSWrx:
1626  case AArch64::SUBSWrx:
1627  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1628  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1629  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1630  break;
1631  case AArch64::ADDXrx:
1632  case AArch64::SUBXrx:
1633  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1634  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1635  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1636  break;
1637  case AArch64::ADDSXrx:
1638  case AArch64::SUBSXrx:
1639  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1640  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1641  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1642  break;
1643  case AArch64::ADDXrx64:
1644  case AArch64::SUBXrx64:
1645  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1646  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1647  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1648  break;
1649  case AArch64::SUBSXrx64:
1650  case AArch64::ADDSXrx64:
1651  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1652  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1653  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1654  break;
1655  }
1656 
1658  return Success;
1659 }
1660 
1662  uint64_t Addr,
1663  const MCDisassembler *Decoder) {
1664  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1665  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1666  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1667  unsigned imm;
1668 
1669  if (Datasize) {
1670  if (Inst.getOpcode() == AArch64::ANDSXri)
1671  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1672  else
1673  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1674  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1675  imm = fieldFromInstruction(insn, 10, 13);
1677  return Fail;
1678  } else {
1679  if (Inst.getOpcode() == AArch64::ANDSWri)
1680  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1681  else
1682  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1683  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1684  imm = fieldFromInstruction(insn, 10, 12);
1686  return Fail;
1687  }
1688  Inst.addOperand(MCOperand::createImm(imm));
1689  return Success;
1690 }
1691 
1693  uint64_t Addr,
1694  const MCDisassembler *Decoder) {
1695  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1696  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1697  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1698  imm |= fieldFromInstruction(insn, 5, 5);
1699 
1700  if (Inst.getOpcode() == AArch64::MOVID)
1701  DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1702  else
1703  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1704 
1705  Inst.addOperand(MCOperand::createImm(imm));
1706 
1707  switch (Inst.getOpcode()) {
1708  default:
1709  break;
1710  case AArch64::MOVIv4i16:
1711  case AArch64::MOVIv8i16:
1712  case AArch64::MVNIv4i16:
1713  case AArch64::MVNIv8i16:
1714  case AArch64::MOVIv2i32:
1715  case AArch64::MOVIv4i32:
1716  case AArch64::MVNIv2i32:
1717  case AArch64::MVNIv4i32:
1718  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1719  break;
1720  case AArch64::MOVIv2s_msl:
1721  case AArch64::MOVIv4s_msl:
1722  case AArch64::MVNIv2s_msl:
1723  case AArch64::MVNIv4s_msl:
1724  Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1725  break;
1726  }
1727 
1728  return Success;
1729 }
1730 
1732  uint64_t Addr,
1733  const MCDisassembler *Decoder) {
1734  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1735  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1736  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1737  imm |= fieldFromInstruction(insn, 5, 5);
1738 
1739  // Tied operands added twice.
1740  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1741  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1742 
1743  Inst.addOperand(MCOperand::createImm(imm));
1744  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1745 
1746  return Success;
1747 }
1748 
1750  uint64_t Addr,
1751  const MCDisassembler *Decoder) {
1752  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1753  int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1754  imm |= fieldFromInstruction(insn, 29, 2);
1755 
1756  // Sign-extend the 21-bit immediate.
1757  if (imm & (1 << (21 - 1)))
1758  imm |= ~((1LL << 21) - 1);
1759 
1760  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1761  if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1762  Inst.addOperand(MCOperand::createImm(imm));
1763 
1764  return Success;
1765 }
1766 
1768  uint64_t Addr,
1769  const MCDisassembler *Decoder) {
1770  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1771  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1772  unsigned Imm = fieldFromInstruction(insn, 10, 14);
1773  unsigned S = fieldFromInstruction(insn, 29, 1);
1774  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1775 
1776  unsigned ShifterVal = (Imm >> 12) & 3;
1777  unsigned ImmVal = Imm & 0xFFF;
1778 
1779  if (ShifterVal != 0 && ShifterVal != 1)
1780  return Fail;
1781 
1782  if (Datasize) {
1783  if (Rd == 31 && !S)
1784  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1785  else
1786  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1787  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1788  } else {
1789  if (Rd == 31 && !S)
1790  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1791  else
1792  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1793  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1794  }
1795 
1796  if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1797  Inst.addOperand(MCOperand::createImm(ImmVal));
1798  Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1799  return Success;
1800 }
1801 
1803  uint64_t Addr,
1804  const MCDisassembler *Decoder) {
1805  int64_t imm = fieldFromInstruction(insn, 0, 26);
1806 
1807  // Sign-extend the 26-bit immediate.
1808  if (imm & (1 << (26 - 1)))
1809  imm |= ~((1LL << 26) - 1);
1810 
1811  if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1812  Inst.addOperand(MCOperand::createImm(imm));
1813 
1814  return Success;
1815 }
1816 
1817 static DecodeStatus
1819  const MCDisassembler *Decoder) {
1820  uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1821  uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1822  uint64_t crm = fieldFromInstruction(insn, 8, 4);
1823  uint64_t pstate_field = (op1 << 3) | op2;
1824 
1825  switch (pstate_field) {
1826  case 0x01: // XAFlag
1827  case 0x02: // AXFlag
1828  return Fail;
1829  }
1830 
1831  if ((pstate_field == AArch64PState::PAN ||
1832  pstate_field == AArch64PState::UAO ||
1833  pstate_field == AArch64PState::SSBS) && crm > 1)
1834  return Fail;
1835 
1836  Inst.addOperand(MCOperand::createImm(pstate_field));
1837  Inst.addOperand(MCOperand::createImm(crm));
1838 
1839  auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1840  if (PState &&
1841  PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1842  return Success;
1843  return Fail;
1844 }
1845 
1847  uint64_t Addr,
1848  const MCDisassembler *Decoder) {
1849  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1850  uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1851  bit |= fieldFromInstruction(insn, 19, 5);
1852  int64_t dst = fieldFromInstruction(insn, 5, 14);
1853 
1854  // Sign-extend 14-bit immediate.
1855  if (dst & (1 << (14 - 1)))
1856  dst |= ~((1LL << 14) - 1);
1857 
1858  if (fieldFromInstruction(insn, 31, 1) == 0)
1859  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1860  else
1861  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1863  if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1864  Inst.addOperand(MCOperand::createImm(dst));
1865 
1866  return Success;
1867 }
1868 
1869 static DecodeStatus
1870 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1871  unsigned RegNo, uint64_t Addr,
1872  const MCDisassembler *Decoder) {
1873  // Register number must be even (see CASP instruction)
1874  if (RegNo & 0x1)
1875  return Fail;
1876 
1877  unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1879  return Success;
1880 }
1881 
1882 static DecodeStatus
1884  const MCDisassembler *Decoder) {
1886  AArch64::WSeqPairsClassRegClassID,
1887  RegNo, Addr, Decoder);
1888 }
1889 
1890 static DecodeStatus
1892  const MCDisassembler *Decoder) {
1894  AArch64::XSeqPairsClassRegClassID,
1895  RegNo, Addr, Decoder);
1896 }
1897 
1899  uint64_t Addr,
1900  const MCDisassembler *Decoder) {
1901  unsigned op1 = fieldFromInstruction(insn, 16, 3);
1902  unsigned CRn = fieldFromInstruction(insn, 12, 4);
1903  unsigned CRm = fieldFromInstruction(insn, 8, 4);
1904  unsigned op2 = fieldFromInstruction(insn, 5, 3);
1905  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1906  if (Rt != 0b11111)
1907  return Fail;
1908 
1909  Inst.addOperand(MCOperand::createImm(op1));
1910  Inst.addOperand(MCOperand::createImm(CRn));
1911  Inst.addOperand(MCOperand::createImm(CRm));
1912  Inst.addOperand(MCOperand::createImm(op2));
1913  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1914 
1915  return Success;
1916 }
1917 
1918 static DecodeStatus
1920  const MCDisassembler *Decoder) {
1921  unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1922  unsigned imm = fieldFromInstruction(insn, 5, 13);
1924  return Fail;
1925 
1926  // The same (tied) operand is added twice to the instruction.
1927  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1928  if (Inst.getOpcode() != AArch64::DUPM_ZI)
1929  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1930  Inst.addOperand(MCOperand::createImm(imm));
1931  return Success;
1932 }
1933 
1934 template <int Bits>
1936  const MCDisassembler *Decoder) {
1937  if (Imm & ~((1LL << Bits) - 1))
1938  return Fail;
1939 
1940  // Imm is a signed immediate, so sign extend it.
1941  if (Imm & (1 << (Bits - 1)))
1942  Imm |= ~((1LL << Bits) - 1);
1943 
1945  return Success;
1946 }
1947 
1948 // Decode 8-bit signed/unsigned immediate for a given element width.
1949 template <int ElementWidth>
1951  const MCDisassembler *Decoder) {
1952  unsigned Val = (uint8_t)Imm;
1953  unsigned Shift = (Imm & 0x100) ? 8 : 0;
1954  if (ElementWidth == 8 && Shift)
1955  return Fail;
1956  Inst.addOperand(MCOperand::createImm(Val));
1958  return Success;
1959 }
1960 
1961 // Decode uimm4 ranged from 1-16.
1963  uint64_t Addr,
1964  const MCDisassembler *Decoder) {
1965  Inst.addOperand(MCOperand::createImm(Imm + 1));
1966  return Success;
1967 }
1968 
1969 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1970  const MCDisassembler *Decoder) {
1971  if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1973  return Success;
1974  }
1975  return Fail;
1976 }
1977 
1979  uint64_t Addr,
1980  const MCDisassembler *Decoder) {
1981  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1982  unsigned Rs = fieldFromInstruction(insn, 16, 5);
1983  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1984 
1985  // None of the registers may alias: if they do, then the instruction is not
1986  // merely unpredictable but actually entirely unallocated.
1987  if (Rd == Rs || Rs == Rn || Rd == Rn)
1988  return MCDisassembler::Fail;
1989 
1990  // All three register operands are written back, so they all appear
1991  // twice in the operand list, once as outputs and once as inputs.
1992  if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
1993  !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
1994  !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
1995  !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
1996  !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
1997  !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder))
1998  return MCDisassembler::Fail;
1999 
2000  return MCDisassembler::Success;
2001 }
2002 
2004  uint64_t Addr,
2005  const MCDisassembler *Decoder) {
2006  unsigned Rd = fieldFromInstruction(insn, 0, 5);
2007  unsigned Rm = fieldFromInstruction(insn, 16, 5);
2008  unsigned Rn = fieldFromInstruction(insn, 5, 5);
2009 
2010  // None of the registers may alias: if they do, then the instruction is not
2011  // merely unpredictable but actually entirely unallocated.
2012  if (Rd == Rm || Rm == Rn || Rd == Rn)
2013  return MCDisassembler::Fail;
2014 
2015  // Rd and Rn (not Rm) register operands are written back, so they appear
2016  // twice in the operand list, once as outputs and once as inputs.
2017  if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2018  !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2019  !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2020  !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2021  !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder))
2022  return MCDisassembler::Fail;
2023 
2024  return MCDisassembler::Success;
2025 }
2026 
2028  uint64_t Addr,
2029  const MCDisassembler *Decoder) {
2030  // PRFM with Rt = '11xxx' should be decoded as RPRFM.
2031  // Fail to decode and defer to fallback decoder table to decode RPRFM.
2032  unsigned Mask = 0x18;
2033  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2034  if ((Rt & Mask) == Mask)
2035  return Fail;
2036 
2037  uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2038  uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2039  uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2040  uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2041 
2042  Inst.addOperand(MCOperand::createImm(Rt));
2043  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
2044 
2045  switch (Inst.getOpcode()) {
2046  default:
2047  return Fail;
2048  case AArch64::PRFMroW:
2049  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
2050  break;
2051  case AArch64::PRFMroX:
2052  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
2053  break;
2054  }
2055 
2056  DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
2057 
2058  return Success;
2059 }
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: AArch64Disassembler.cpp:371
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1870
i
i
Definition: README.txt:29
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:412
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1767
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1692
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:299
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
DecodeDDRegisterClass
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:811
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1935
DecodeQQQQRegisterClass
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:800
MCInstrDesc.h
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1919
DecodeZPR2RegisterClass
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:610
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1571
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:388
ErrorHandling.h
DecodeDDDRegisterClass
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:822
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
DecodeGPR64commonRegisterClass
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:481
DecodeSystemPStateInstruction
static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1818
AArch64BaseInfo.h
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
DecodePPR_p8to15RegisterClass
static DecodeStatus DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:746
Fail
#define Fail
Definition: AArch64Disassembler.cpp:296
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:456
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:984
DecodeMatrixIndexGPR32_8_11RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:532
Disassembler.h
Shift
bool Shift
Definition: README.txt:468
AArch64ExternalSymbolizer.h
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
DecodePPRRegisterClass
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:723
llvm::AArch64::OPERAND_IMPLICIT_IMM_0
@ OPERAND_IMPLICIT_IMM_0
Definition: AArch64MCTargetDesc.h:72
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:380
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:974
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:883
T
#define T
Definition: Mips16ISelLowering.cpp:341
AArch64Disassembler.h
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:954
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:966
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCDecoderOps.h
DecodeZPRRegisterClass
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:582
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:930
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:860
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:996
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1661
LLVMSymbolLookupCallback
const typedef char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
MatrixZATileDecoderTable
static const SmallVector< SmallVector< unsigned, 16 >, 5 > MatrixZATileDecoderTable
Definition: AArch64Disassembler.cpp:700
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1846
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1898
DecodePPR2RegisterClass
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:755
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:432
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1731
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:112
DecodeZPR4RegisterClass
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:632
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:297
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:893
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:223
MCInst.h
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2027
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:960
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:690
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1003
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:767
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1437
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:202
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:990
AArch64AddressingModes.h
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
uint64_t
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:972
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
extend
_test eax xmm0 eax xmm1 comiss xmm1 setae al movzbl ecx eax edx ecx cmove eax ret Note the cmove can be replaced with a single cmovae There are a number of issues We are introducing a setcc between the result of the intrisic call and select The intrinsic is expected to produce a i32 value so a any extend(which becomes a zero extend) is added. We probably need some kind of target DAG combine hook to fix this. We generate significantly worse code for this than GCC
Definition: README.txt:213
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:924
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:60
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:936
MCRegisterInfo.h
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:844
DecodeZPR2StridedRegisterClass
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:665
llvm::AArch64ExternalSymbolizer
Definition: AArch64ExternalSymbolizer.h:20
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:506
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
DecodeZPR_3bRegisterClass
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:602
DecodeQQQRegisterClass
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:789
DecodeFPR128_loRegisterClass
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:425
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1802
llvm::ArrayRef< uint8_t >
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:643
uint32_t
DecodeMatrixIndexGPR32_12_15RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:545
Compiler.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:110
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1749
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
DecodeZPR4StridedRegisterClass
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:677
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:853
DecodeQQRegisterClass
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:778
DecodeGPR32spRegisterClass
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:570
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:130
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1156
bit
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional ldr LCPI1_0 ldr ldr tst movne lsr ldr LCPI1_1 and r0 bx lr it saves an instruction and a register It might be profitable to cse MOVi16 if there are lots of bit immediates with the same bottom half Robert Muth started working on an alternate jump table implementation that does not put the tables in line in the text This is more like the llvm default jump table implementation This might be useful sometime Several revisions of patches are on the mailing beginning while CMP sets them like a subtract Therefore to be able to use CMN for comparisons other than the Z bit
Definition: README.txt:584
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:444
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:654
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:942
Success
#define Success
Definition: AArch64Disassembler.cpp:295
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:558
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:306
MCRelocationInfo.h
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1604
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:712
DecodeZPR3RegisterClass
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:621
AArch64MCTargetDesc.h
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1355
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:219
DecodeGPR64spRegisterClass
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:520
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:901
DecodeDDDDRegisterClass
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:833
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1891
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1950
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:322
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
shift
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra shift
Definition: README.txt:30
DecodeZPR_4bRegisterClass
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:594
llvm::AArch64Disassembler
Definition: AArch64Disassembler.h:20
DecodeFPR8RegisterClass
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:468
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1883
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1072
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1064
DecodePPR_3bRegisterClass
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:735
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:948
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:493
TargetRegistry.h
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1969
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:978
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2003
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
Debug.h
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1098
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:875
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1962
AArch64TargetInfo.h
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1978
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48