34#define DEBUG_TYPE "aarch64-disassembler"
73 uint64_t Address,
const void *Decoder);
122 const void *Decoder);
125 const void *Decoder);
128 const void *Decoder);
131 const void *Decoder);
132template <
unsigned NumBitsForTile>
154 const void *Decoder);
157 const void *Decoder);
282template <
int ElementW
idth>
300#include "AArch64GenDisassemblerTables.inc"
301#include "AArch64GenInstrInfo.inc"
303#define Success MCDisassembler::Success
304#define Fail MCDisassembler::Fail
305#define SoftFail MCDisassembler::SoftFail
322 if (Bytes.
size() < 4)
328 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
330 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
332 for (
const auto *Table : Tables) {
341 for (
unsigned i = 0; i <
Desc.getNumOperands(); i++) {
343 switch (
Desc.operands()[i].RegClass) {
346 case AArch64::MPRRegClassID:
349 case AArch64::MPR8RegClassID:
352 case AArch64::ZTRRegClassID:
356 }
else if (
Desc.operands()[i].OperandType ==
362 if (
MI.getOpcode() == AArch64::LDR_ZA ||
363 MI.getOpcode() == AArch64::STR_ZA) {
368 assert(Imm4Op.
isImm() &&
"Unexpected operand type!");
369 MI.addOperand(Imm4Op);
391 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
393 SymbolLookUp, DisInfo);
427 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
447 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
459 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
471 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
483 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
495 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
508 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
522 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
534 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
546 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
560 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
573 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
585 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
597 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
624 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
635 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
646 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
653 const void *Decoder) {
657 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
664 const void *Decoder) {
668 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
675 const void *Decoder) {
679 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
687 const void *Decoder) {
691 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
709 {AArch64::ZAH0, AArch64::ZAH1},
710 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
711 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
712 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
713 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
714 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
715 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
716 AArch64::ZAQ14, AArch64::ZAQ15}};
718template <
unsigned NumBitsForTile>
722 unsigned LastReg = (1 << NumBitsForTile) - 1;
737 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
749 AArch64MCRegisterClasses[AArch64::PNRRegClassID].getRegister(RegNo);
776 const void *Decoder) {
781 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
788 const void *Decoder) {
789 if ((RegNo * 2) > 14)
792 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
803 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
814 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
825 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
836 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
847 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
858 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
882 int64_t ImmVal = Imm;
885 if (ImmVal & (1 << (19 - 1)))
886 ImmVal |= ~((1LL << 19) - 1);
889 Inst, ImmVal * 4,
Addr, Inst.
getOpcode() != AArch64::LDRXl, 0, 0, 4))
925 unsigned Rd = fieldFromInstruction(
Insn, 0, 5);
926 unsigned Rn = fieldFromInstruction(
Insn, 5, 5);
927 unsigned IsToVec = fieldFromInstruction(
Insn, 16, 1);
1024 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1025 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1026 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1027 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1028 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1029 unsigned shift = (shiftHi << 6) | shiftLo;
1033 case AArch64::ADDWrs:
1034 case AArch64::ADDSWrs:
1035 case AArch64::SUBWrs:
1036 case AArch64::SUBSWrs:
1041 case AArch64::ANDWrs:
1042 case AArch64::ANDSWrs:
1043 case AArch64::BICWrs:
1044 case AArch64::BICSWrs:
1045 case AArch64::ORRWrs:
1046 case AArch64::ORNWrs:
1047 case AArch64::EORWrs:
1048 case AArch64::EONWrs: {
1050 if (shiftLo >> 5 == 1)
1057 case AArch64::ADDXrs:
1058 case AArch64::ADDSXrs:
1059 case AArch64::SUBXrs:
1060 case AArch64::SUBSXrs:
1065 case AArch64::ANDXrs:
1066 case AArch64::ANDSXrs:
1067 case AArch64::BICXrs:
1068 case AArch64::BICSXrs:
1069 case AArch64::ORRXrs:
1070 case AArch64::ORNXrs:
1071 case AArch64::EORXrs:
1072 case AArch64::EONXrs:
1086 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1087 unsigned imm = fieldFromInstruction(insn, 5, 16);
1088 unsigned shift = fieldFromInstruction(insn, 21, 2);
1093 case AArch64::MOVZWi:
1094 case AArch64::MOVNWi:
1095 case AArch64::MOVKWi:
1096 if (shift & (1U << 5))
1100 case AArch64::MOVZXi:
1101 case AArch64::MOVNXi:
1102 case AArch64::MOVKXi:
1107 if (Inst.
getOpcode() == AArch64::MOVKWi ||
1119 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1120 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1121 unsigned offset = fieldFromInstruction(insn, 10, 12);
1126 case AArch64::PRFMui:
1130 case AArch64::STRBBui:
1131 case AArch64::LDRBBui:
1132 case AArch64::LDRSBWui:
1133 case AArch64::STRHHui:
1134 case AArch64::LDRHHui:
1135 case AArch64::LDRSHWui:
1136 case AArch64::STRWui:
1137 case AArch64::LDRWui:
1140 case AArch64::LDRSBXui:
1141 case AArch64::LDRSHXui:
1142 case AArch64::LDRSWui:
1143 case AArch64::STRXui:
1144 case AArch64::LDRXui:
1147 case AArch64::LDRQui:
1148 case AArch64::STRQui:
1151 case AArch64::LDRDui:
1152 case AArch64::STRDui:
1155 case AArch64::LDRSui:
1156 case AArch64::STRSui:
1159 case AArch64::LDRHui:
1160 case AArch64::STRHui:
1163 case AArch64::LDRBui:
1164 case AArch64::STRBui:
1178 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1179 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1180 int64_t offset = fieldFromInstruction(insn, 12, 9);
1184 if (offset & (1 << (9 - 1)))
1185 offset |= ~((1LL << 9) - 1);
1191 case AArch64::LDRSBWpre:
1192 case AArch64::LDRSHWpre:
1193 case AArch64::STRBBpre:
1194 case AArch64::LDRBBpre:
1195 case AArch64::STRHHpre:
1196 case AArch64::LDRHHpre:
1197 case AArch64::STRWpre:
1198 case AArch64::LDRWpre:
1199 case AArch64::LDRSBWpost:
1200 case AArch64::LDRSHWpost:
1201 case AArch64::STRBBpost:
1202 case AArch64::LDRBBpost:
1203 case AArch64::STRHHpost:
1204 case AArch64::LDRHHpost:
1205 case AArch64::STRWpost:
1206 case AArch64::LDRWpost:
1207 case AArch64::LDRSBXpre:
1208 case AArch64::LDRSHXpre:
1209 case AArch64::STRXpre:
1210 case AArch64::LDRSWpre:
1211 case AArch64::LDRXpre:
1212 case AArch64::LDRSBXpost:
1213 case AArch64::LDRSHXpost:
1214 case AArch64::STRXpost:
1215 case AArch64::LDRSWpost:
1216 case AArch64::LDRXpost:
1217 case AArch64::LDRQpre:
1218 case AArch64::STRQpre:
1219 case AArch64::LDRQpost:
1220 case AArch64::STRQpost:
1221 case AArch64::LDRDpre:
1222 case AArch64::STRDpre:
1223 case AArch64::LDRDpost:
1224 case AArch64::STRDpost:
1225 case AArch64::LDRSpre:
1226 case AArch64::STRSpre:
1227 case AArch64::LDRSpost:
1228 case AArch64::STRSpost:
1229 case AArch64::LDRHpre:
1230 case AArch64::STRHpre:
1231 case AArch64::LDRHpost:
1232 case AArch64::STRHpost:
1233 case AArch64::LDRBpre:
1234 case AArch64::STRBpre:
1235 case AArch64::LDRBpost:
1236 case AArch64::STRBpost:
1244 case AArch64::PRFUMi:
1248 case AArch64::STURBBi:
1249 case AArch64::LDURBBi:
1250 case AArch64::LDURSBWi:
1251 case AArch64::STURHHi:
1252 case AArch64::LDURHHi:
1253 case AArch64::LDURSHWi:
1254 case AArch64::STURWi:
1255 case AArch64::LDURWi:
1256 case AArch64::LDTRSBWi:
1257 case AArch64::LDTRSHWi:
1258 case AArch64::STTRWi:
1259 case AArch64::LDTRWi:
1260 case AArch64::STTRHi:
1261 case AArch64::LDTRHi:
1262 case AArch64::LDTRBi:
1263 case AArch64::STTRBi:
1264 case AArch64::LDRSBWpre:
1265 case AArch64::LDRSHWpre:
1266 case AArch64::STRBBpre:
1267 case AArch64::LDRBBpre:
1268 case AArch64::STRHHpre:
1269 case AArch64::LDRHHpre:
1270 case AArch64::STRWpre:
1271 case AArch64::LDRWpre:
1272 case AArch64::LDRSBWpost:
1273 case AArch64::LDRSHWpost:
1274 case AArch64::STRBBpost:
1275 case AArch64::LDRBBpost:
1276 case AArch64::STRHHpost:
1277 case AArch64::LDRHHpost:
1278 case AArch64::STRWpost:
1279 case AArch64::LDRWpost:
1280 case AArch64::STLURBi:
1281 case AArch64::STLURHi:
1282 case AArch64::STLURWi:
1283 case AArch64::LDAPURBi:
1284 case AArch64::LDAPURSBWi:
1285 case AArch64::LDAPURHi:
1286 case AArch64::LDAPURSHWi:
1287 case AArch64::LDAPURi:
1290 case AArch64::LDURSBXi:
1291 case AArch64::LDURSHXi:
1292 case AArch64::LDURSWi:
1293 case AArch64::STURXi:
1294 case AArch64::LDURXi:
1295 case AArch64::LDTRSBXi:
1296 case AArch64::LDTRSHXi:
1297 case AArch64::LDTRSWi:
1298 case AArch64::STTRXi:
1299 case AArch64::LDTRXi:
1300 case AArch64::LDRSBXpre:
1301 case AArch64::LDRSHXpre:
1302 case AArch64::STRXpre:
1303 case AArch64::LDRSWpre:
1304 case AArch64::LDRXpre:
1305 case AArch64::LDRSBXpost:
1306 case AArch64::LDRSHXpost:
1307 case AArch64::STRXpost:
1308 case AArch64::LDRSWpost:
1309 case AArch64::LDRXpost:
1310 case AArch64::LDAPURSWi:
1311 case AArch64::LDAPURSHXi:
1312 case AArch64::LDAPURSBXi:
1313 case AArch64::STLURXi:
1314 case AArch64::LDAPURXi:
1317 case AArch64::LDURQi:
1318 case AArch64::STURQi:
1319 case AArch64::LDRQpre:
1320 case AArch64::STRQpre:
1321 case AArch64::LDRQpost:
1322 case AArch64::STRQpost:
1325 case AArch64::LDURDi:
1326 case AArch64::STURDi:
1327 case AArch64::LDRDpre:
1328 case AArch64::STRDpre:
1329 case AArch64::LDRDpost:
1330 case AArch64::STRDpost:
1333 case AArch64::LDURSi:
1334 case AArch64::STURSi:
1335 case AArch64::LDRSpre:
1336 case AArch64::STRSpre:
1337 case AArch64::LDRSpost:
1338 case AArch64::STRSpost:
1341 case AArch64::LDURHi:
1342 case AArch64::STURHi:
1343 case AArch64::LDRHpre:
1344 case AArch64::STRHpre:
1345 case AArch64::LDRHpost:
1346 case AArch64::STRHpost:
1349 case AArch64::LDURBi:
1350 case AArch64::STURBi:
1351 case AArch64::LDRBpre:
1352 case AArch64::STRBpre:
1353 case AArch64::LDRBpost:
1354 case AArch64::STRBpost:
1362 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1363 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1364 bool IsFP = fieldFromInstruction(insn, 26, 1);
1367 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1376 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1377 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1378 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1379 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1385 case AArch64::STLXRW:
1386 case AArch64::STLXRB:
1387 case AArch64::STLXRH:
1388 case AArch64::STXRW:
1389 case AArch64::STXRB:
1390 case AArch64::STXRH:
1393 case AArch64::LDARW:
1394 case AArch64::LDARB:
1395 case AArch64::LDARH:
1396 case AArch64::LDAXRW:
1397 case AArch64::LDAXRB:
1398 case AArch64::LDAXRH:
1399 case AArch64::LDXRW:
1400 case AArch64::LDXRB:
1401 case AArch64::LDXRH:
1402 case AArch64::STLRW:
1403 case AArch64::STLRB:
1404 case AArch64::STLRH:
1405 case AArch64::STLLRW:
1406 case AArch64::STLLRB:
1407 case AArch64::STLLRH:
1408 case AArch64::LDLARW:
1409 case AArch64::LDLARB:
1410 case AArch64::LDLARH:
1413 case AArch64::STLXRX:
1414 case AArch64::STXRX:
1417 case AArch64::LDARX:
1418 case AArch64::LDAXRX:
1419 case AArch64::LDXRX:
1420 case AArch64::STLRX:
1421 case AArch64::LDLARX:
1422 case AArch64::STLLRX:
1425 case AArch64::STLXPW:
1426 case AArch64::STXPW:
1429 case AArch64::LDAXPW:
1430 case AArch64::LDXPW:
1434 case AArch64::STLXPX:
1435 case AArch64::STXPX:
1438 case AArch64::LDAXPX:
1439 case AArch64::LDXPX:
1448 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1449 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1459 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1460 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1461 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1462 int64_t offset = fieldFromInstruction(insn, 15, 7);
1463 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1467 if (offset & (1 << (7 - 1)))
1468 offset |= ~((1LL << 7) - 1);
1471 bool NeedsDisjointWritebackTransfer =
false;
1477 case AArch64::LDPXpost:
1478 case AArch64::STPXpost:
1479 case AArch64::LDPSWpost:
1480 case AArch64::LDPXpre:
1481 case AArch64::STPXpre:
1482 case AArch64::LDPSWpre:
1483 case AArch64::LDPWpost:
1484 case AArch64::STPWpost:
1485 case AArch64::LDPWpre:
1486 case AArch64::STPWpre:
1487 case AArch64::LDPQpost:
1488 case AArch64::STPQpost:
1489 case AArch64::LDPQpre:
1490 case AArch64::STPQpre:
1491 case AArch64::LDPDpost:
1492 case AArch64::STPDpost:
1493 case AArch64::LDPDpre:
1494 case AArch64::STPDpre:
1495 case AArch64::LDPSpost:
1496 case AArch64::STPSpost:
1497 case AArch64::LDPSpre:
1498 case AArch64::STPSpre:
1499 case AArch64::STGPpre:
1500 case AArch64::STGPpost:
1508 case AArch64::LDPXpost:
1509 case AArch64::STPXpost:
1510 case AArch64::LDPSWpost:
1511 case AArch64::LDPXpre:
1512 case AArch64::STPXpre:
1513 case AArch64::LDPSWpre:
1514 case AArch64::STGPpre:
1515 case AArch64::STGPpost:
1516 NeedsDisjointWritebackTransfer =
true;
1518 case AArch64::LDNPXi:
1519 case AArch64::STNPXi:
1520 case AArch64::LDPXi:
1521 case AArch64::STPXi:
1522 case AArch64::LDPSWi:
1523 case AArch64::STGPi:
1527 case AArch64::LDPWpost:
1528 case AArch64::STPWpost:
1529 case AArch64::LDPWpre:
1530 case AArch64::STPWpre:
1531 NeedsDisjointWritebackTransfer =
true;
1533 case AArch64::LDNPWi:
1534 case AArch64::STNPWi:
1535 case AArch64::LDPWi:
1536 case AArch64::STPWi:
1540 case AArch64::LDNPQi:
1541 case AArch64::STNPQi:
1542 case AArch64::LDPQpost:
1543 case AArch64::STPQpost:
1544 case AArch64::LDPQi:
1545 case AArch64::STPQi:
1546 case AArch64::LDPQpre:
1547 case AArch64::STPQpre:
1551 case AArch64::LDNPDi:
1552 case AArch64::STNPDi:
1553 case AArch64::LDPDpost:
1554 case AArch64::STPDpost:
1555 case AArch64::LDPDi:
1556 case AArch64::STPDi:
1557 case AArch64::LDPDpre:
1558 case AArch64::STPDpre:
1562 case AArch64::LDNPSi:
1563 case AArch64::STNPSi:
1564 case AArch64::LDPSpost:
1565 case AArch64::STPSpost:
1566 case AArch64::LDPSi:
1567 case AArch64::STPSi:
1568 case AArch64::LDPSpre:
1569 case AArch64::STPSpre:
1579 if (IsLoad && Rt == Rt2)
1584 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1593 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1594 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1595 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1596 fieldFromInstruction(insn, 12, 9);
1597 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1602 case AArch64::LDRAAwriteback:
1603 case AArch64::LDRABwriteback:
1607 case AArch64::LDRAAindexed:
1608 case AArch64::LDRABindexed:
1614 DecodeSImm<10>(Inst, offset,
Addr, Decoder);
1616 if (writeback && Rt == Rn && Rn != 31) {
1626 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1627 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1628 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1629 unsigned extend = fieldFromInstruction(insn, 10, 6);
1631 unsigned shift = extend & 0x7;
1638 case AArch64::ADDWrx:
1639 case AArch64::SUBWrx:
1644 case AArch64::ADDSWrx:
1645 case AArch64::SUBSWrx:
1650 case AArch64::ADDXrx:
1651 case AArch64::SUBXrx:
1656 case AArch64::ADDSXrx:
1657 case AArch64::SUBSXrx:
1662 case AArch64::ADDXrx64:
1663 case AArch64::SUBXrx64:
1668 case AArch64::SUBSXrx64:
1669 case AArch64::ADDSXrx64:
1683 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1684 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1685 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1689 if (Inst.
getOpcode() == AArch64::ANDSXri)
1694 imm = fieldFromInstruction(insn, 10, 13);
1698 if (Inst.
getOpcode() == AArch64::ANDSWri)
1703 imm = fieldFromInstruction(insn, 10, 12);
1714 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1715 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1716 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1717 imm |= fieldFromInstruction(insn, 5, 5);
1729 case AArch64::MOVIv4i16:
1730 case AArch64::MOVIv8i16:
1731 case AArch64::MVNIv4i16:
1732 case AArch64::MVNIv8i16:
1733 case AArch64::MOVIv2i32:
1734 case AArch64::MOVIv4i32:
1735 case AArch64::MVNIv2i32:
1736 case AArch64::MVNIv4i32:
1739 case AArch64::MOVIv2s_msl:
1740 case AArch64::MOVIv4s_msl:
1741 case AArch64::MVNIv2s_msl:
1742 case AArch64::MVNIv4s_msl:
1753 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1754 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1755 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1756 imm |= fieldFromInstruction(insn, 5, 5);
1771 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1772 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1773 imm |= fieldFromInstruction(insn, 29, 2);
1776 if (imm & (1 << (21 - 1)))
1777 imm |= ~((1LL << 21) - 1);
1789 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1790 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1791 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1792 unsigned S = fieldFromInstruction(insn, 29, 1);
1793 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1795 unsigned ShifterVal = (Imm >> 12) & 3;
1796 unsigned ImmVal = Imm & 0xFFF;
1798 if (ShifterVal != 0 && ShifterVal != 1)
1824 int64_t imm = fieldFromInstruction(insn, 0, 26);
1827 if (imm & (1 << (26 - 1)))
1828 imm |= ~((1LL << 26) - 1);
1837 return Op1 == 0b000 && (Op2 == 0b000 ||
1845 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1846 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1847 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1848 uint64_t pstate_field = (op1 << 3) | op2;
1856 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1866 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1867 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1868 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1869 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1870 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1878 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1888 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1889 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1890 bit |= fieldFromInstruction(insn, 19, 5);
1891 int64_t dst = fieldFromInstruction(insn, 5, 14);
1894 if (dst & (1 << (14 - 1)))
1895 dst |= ~((1LL << 14) - 1);
1897 if (fieldFromInstruction(insn, 31, 1) == 0)
1916 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1925 AArch64::WSeqPairsClassRegClassID,
1926 RegNo,
Addr, Decoder);
1933 AArch64::XSeqPairsClassRegClassID,
1934 RegNo,
Addr, Decoder);
1940 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1941 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1942 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1943 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1944 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1960 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1961 unsigned imm = fieldFromInstruction(insn, 5, 13);
1967 if (Inst.
getOpcode() != AArch64::DUPM_ZI)
1976 if (Imm & ~((1LL << Bits) - 1))
1980 if (Imm & (1 << (Bits - 1)))
1981 Imm |= ~((1LL << Bits) - 1);
1988template <
int ElementW
idth>
1991 unsigned Val = (uint8_t)Imm;
1992 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1993 if (ElementWidth == 8 && Shift)
2010 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2020 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2021 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2022 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2026 if (Rd == Rs || Rs == Rn || Rd == Rn)
2045 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2046 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2047 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2051 if (Rd == Rm || Rm == Rn || Rd == Rn)
2071 unsigned Mask = 0x18;
2072 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2073 if ((Rt & Mask) == Mask)
2076 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2077 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2078 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2079 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2087 case AArch64::PRFMroW:
2090 case AArch64::PRFMroX:
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const MCPhysReg MatrixZATileDecoderTable[5][16]
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
const MCSubtargetInfo & getSubtargetInfo() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
Symbolize and annotate disassembled instructions.
Wrapper class representing virtual and physical registers.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
This class implements an extremely fast bulk output stream that can only output to a stream.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheAArch64beTarget()
Target & getTheAArch64leTarget()
Target & getTheAArch64_32Target()
Target & getTheARM64_32Target()
Target & getTheARM64Target()
Description of the encoding of one expression Op.
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.