LLVM 18.0.0git
AArch64Disassembler.cpp
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1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm-c/Disassembler.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <algorithm>
30#include <memory>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-disassembler"
35
36// Pull DecodeStatus and its enum values into the global namespace.
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39// Forward declare these because the autogenerated code will reference them.
40// Definitions are further down.
41static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
42 uint64_t Address,
43 const MCDisassembler *Decoder);
44static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
45 uint64_t Address,
46 const MCDisassembler *Decoder);
47static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
48 uint64_t Address,
49 const MCDisassembler *Decoder);
50static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
51 uint64_t Address,
52 const MCDisassembler *Decoder);
53static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
54 uint64_t Address,
55 const MCDisassembler *Decoder);
56static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
57 uint64_t Address,
58 const MCDisassembler *Decoder);
59static DecodeStatus
60DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
61 const MCDisassembler *Decoder);
62static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
63 uint64_t Address,
64 const MCDisassembler *Decoder);
65static DecodeStatus
66DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
67 const MCDisassembler *Decoder);
68static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
69 uint64_t Address,
70 const MCDisassembler *Decoder);
71static DecodeStatus
72DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
73 uint64_t Address, const void *Decoder);
74static DecodeStatus
75DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
76 uint64_t Address,
77 const MCDisassembler *Decoder);
78static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
79 uint64_t Address,
80 const MCDisassembler *Decoder);
81static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
82 uint64_t Address,
83 const MCDisassembler *Decoder);
84static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
85 uint64_t Address,
86 const MCDisassembler *Decoder);
87static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
88 uint64_t Address,
89 const MCDisassembler *Decoder);
90static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
91 uint64_t Address,
92 const MCDisassembler *Decoder);
93static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
94 uint64_t Address,
95 const MCDisassembler *Decoder);
96static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
97 uint64_t Address,
98 const MCDisassembler *Decoder);
99static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
100 uint64_t Address,
101 const MCDisassembler *Decoder);
102static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
103 uint64_t Address,
104 const MCDisassembler *Decoder);
105static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
106 uint64_t Address,
107 const MCDisassembler *Decoder);
108static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
109 uint64_t Address,
110 const MCDisassembler *Decoder);
111static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
112 uint64_t Address,
113 const MCDisassembler *Decoder);
114static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
118 uint64_t Address,
119 const MCDisassembler *Decoder);
120static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const void *Decoder);
123static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
126static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
127 uint64_t Address,
128 const void *Decoder);
129static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
130 uint64_t Address,
131 const void *Decoder);
132template <unsigned NumBitsForTile>
133static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
134 uint64_t Address,
135 const MCDisassembler *Decoder);
136static DecodeStatus
137DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
141 uint64_t Address,
142 const MCDisassembler *Decoder);
143static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
144 uint64_t Address,
145 const MCDisassembler *Decoder);
146static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address,
148 const MCDisassembler *Decoder);
149static DecodeStatus
150DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
151 const MCDisassembler *Decoder);
152static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
153 uint64_t Address,
154 const void *Decoder);
155static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address,
157 const void *Decoder);
158
159static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
160 uint64_t Address,
161 const MCDisassembler *Decoder);
162static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
163 uint64_t Address,
164 const MCDisassembler *Decoder);
165static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
166 uint64_t Address,
167 const MCDisassembler *Decoder);
168static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
169 uint64_t Address,
170 const MCDisassembler *Decoder);
171static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
172 uint64_t Address,
173 const MCDisassembler *Decoder);
174static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
175 uint64_t Address,
176 const MCDisassembler *Decoder);
177static DecodeStatus
178DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
179 const MCDisassembler *Decoder);
180static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
181 uint64_t Address,
182 const MCDisassembler *Decoder);
183static DecodeStatus
184DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
185 const MCDisassembler *Decoder);
186static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
187 uint64_t Address,
188 const MCDisassembler *Decoder);
189static DecodeStatus
190DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
191 const MCDisassembler *Decoder);
192static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
193 uint64_t Address,
194 const MCDisassembler *Decoder);
195static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
196 uint64_t Address,
197 const MCDisassembler *Decoder);
198static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
199 uint64_t Address,
200 const MCDisassembler *Decoder);
201static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
202 uint64_t Address,
203 const MCDisassembler *Decoder);
204static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
205 uint64_t Address,
206 const MCDisassembler *Decoder);
207static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
208 uint64_t Address,
209 const MCDisassembler *Decoder);
210static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
211 uint64_t Address,
212 const MCDisassembler *Decoder);
213static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
214 uint64_t Address,
215 const MCDisassembler *Decoder);
216static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
217 uint64_t Address,
218 const MCDisassembler *Decoder);
219static DecodeStatus
220DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn,
221 uint64_t Address,
222 const MCDisassembler *Decoder);
223static DecodeStatus
224DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn,
225 uint64_t Address,
226 const MCDisassembler *Decoder);
227static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
228 uint64_t Address,
229 const MCDisassembler *Decoder);
230
231static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
232 uint64_t Address,
233 const MCDisassembler *Decoder);
234static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
235 uint64_t Addr,
236 const MCDisassembler *Decoder);
237static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
238 uint64_t Addr,
239 const MCDisassembler *Decoder);
240static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
241 uint64_t Addr,
242 const MCDisassembler *Decoder);
243static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
244 uint64_t Addr,
245 const MCDisassembler *Decoder);
246static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
247 uint64_t Addr,
248 const MCDisassembler *Decoder);
249static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
250 uint64_t Addr,
251 const MCDisassembler *Decoder);
252static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
253 uint64_t Addr,
254 const MCDisassembler *Decoder);
255static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
256 uint64_t Addr,
257 const MCDisassembler *Decoder);
258static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
259 uint64_t Addr,
260 const MCDisassembler *Decoder);
261static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
262 uint64_t Addr,
263 const MCDisassembler *Decoder);
264static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
265 uint64_t Addr,
266 const MCDisassembler *Decoder);
267static DecodeStatus
268DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
269 const MCDisassembler *Decoder);
270static DecodeStatus
271DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
272 const MCDisassembler *Decoder);
273static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
274 uint64_t Addr,
275 const MCDisassembler *Decoder);
276static DecodeStatus
277DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
278 const MCDisassembler *Decoder);
279template <int Bits>
280static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
281 const MCDisassembler *Decoder);
282template <int ElementWidth>
283static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
284 const MCDisassembler *Decoder);
285static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
286 uint64_t Addr,
287 const MCDisassembler *Decoder);
288static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
289 const MCDisassembler *Decoder);
290static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
291 uint64_t Addr,
292 const MCDisassembler *Decoder);
293static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
294 uint64_t Addr,
295 const MCDisassembler *Decoder);
296static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
297 uint64_t Address,
298 const MCDisassembler *Decoder);
299
300#include "AArch64GenDisassemblerTables.inc"
301#include "AArch64GenInstrInfo.inc"
302
303#define Success MCDisassembler::Success
304#define Fail MCDisassembler::Fail
305#define SoftFail MCDisassembler::SoftFail
306
307static MCDisassembler *createAArch64Disassembler(const Target &T,
308 const MCSubtargetInfo &STI,
309 MCContext &Ctx) {
310
311 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
312}
313
314DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
315 ArrayRef<uint8_t> Bytes,
316 uint64_t Address,
317 raw_ostream &CS) const {
318 CommentStream = &CS;
319
320 Size = 0;
321 // We want to read exactly 4 bytes of data.
322 if (Bytes.size() < 4)
323 return Fail;
324 Size = 4;
325
326 // Encoded as a small-endian 32-bit word in the stream.
327 uint32_t Insn =
328 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
329
330 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
331
332 for (const auto *Table : Tables) {
333 DecodeStatus Result =
334 decodeInstruction(Table, MI, Insn, Address, this, STI);
335
336 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
337
338 // For Scalable Matrix Extension (SME) instructions that have an implicit
339 // operand for the accumulator (ZA) or implicit immediate zero which isn't
340 // encoded, manually insert operand.
341 for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
342 if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
343 switch (Desc.operands()[i].RegClass) {
344 default:
345 break;
346 case AArch64::MPRRegClassID:
347 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
348 break;
349 case AArch64::MPR8RegClassID:
350 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
351 break;
352 case AArch64::ZTRRegClassID:
353 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
354 break;
355 }
356 } else if (Desc.operands()[i].OperandType ==
357 AArch64::OPERAND_IMPLICIT_IMM_0) {
358 MI.insert(MI.begin() + i, MCOperand::createImm(0));
359 }
360 }
361
362 if (MI.getOpcode() == AArch64::LDR_ZA ||
363 MI.getOpcode() == AArch64::STR_ZA) {
364 // Spill and fill instructions have a single immediate used for both
365 // the vector select offset and optional memory offset. Replicate
366 // the decoded immediate.
367 const MCOperand &Imm4Op = MI.getOperand(2);
368 assert(Imm4Op.isImm() && "Unexpected operand type!");
369 MI.addOperand(Imm4Op);
370 }
371
372 if (Result != MCDisassembler::Fail)
373 return Result;
374 }
375
376 return MCDisassembler::Fail;
377}
378
379uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
380 uint64_t Address) const {
381 // AArch64 instructions are always 4 bytes wide, so there's no point
382 // in skipping any smaller number of bytes if an instruction can't
383 // be decoded.
384 return 4;
385}
386
387static MCSymbolizer *
388createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
389 LLVMSymbolLookupCallback SymbolLookUp,
390 void *DisInfo, MCContext *Ctx,
391 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
392 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
393 SymbolLookUp, DisInfo);
394}
395
396extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
397 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
398 createAArch64Disassembler);
399 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
400 createAArch64Disassembler);
401 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
402 createAArch64ExternalSymbolizer);
403 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
404 createAArch64ExternalSymbolizer);
405 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
406 createAArch64Disassembler);
407 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
408 createAArch64ExternalSymbolizer);
409
410 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
411 createAArch64Disassembler);
412 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
413 createAArch64ExternalSymbolizer);
414 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
415 createAArch64Disassembler);
416 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
417 createAArch64ExternalSymbolizer);
418}
419
420static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
421 uint64_t Addr,
422 const MCDisassembler *Decoder) {
423 if (RegNo > 31)
424 return Fail;
425
426 unsigned Register =
427 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
428 Inst.addOperand(MCOperand::createReg(Register));
429 return Success;
430}
431
432static DecodeStatus
433DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
434 const MCDisassembler *Decoder) {
435 if (RegNo > 15)
436 return Fail;
437 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
438}
439
440static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
441 uint64_t Addr,
442 const MCDisassembler *Decoder) {
443 if (RegNo > 31)
444 return Fail;
445
446 unsigned Register =
447 AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
448 Inst.addOperand(MCOperand::createReg(Register));
449 return Success;
450}
451
452static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
453 uint64_t Addr,
454 const MCDisassembler *Decoder) {
455 if (RegNo > 31)
456 return Fail;
457
458 unsigned Register =
459 AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
460 Inst.addOperand(MCOperand::createReg(Register));
461 return Success;
462}
463
464static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
465 uint64_t Addr,
466 const MCDisassembler *Decoder) {
467 if (RegNo > 31)
468 return Fail;
469
470 unsigned Register =
471 AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
472 Inst.addOperand(MCOperand::createReg(Register));
473 return Success;
474}
475
476static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
477 uint64_t Addr,
478 const MCDisassembler *Decoder) {
479 if (RegNo > 31)
480 return Fail;
481
482 unsigned Register =
483 AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
484 Inst.addOperand(MCOperand::createReg(Register));
485 return Success;
486}
487
488static DecodeStatus
489DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
490 const MCDisassembler *Decoder) {
491 if (RegNo > 30)
492 return Fail;
493
494 unsigned Register =
495 AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
496 RegNo);
497 Inst.addOperand(MCOperand::createReg(Register));
498 return Success;
499}
500
501static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
502 uint64_t Addr,
503 const MCDisassembler *Decoder) {
504 if (RegNo > 31)
505 return Fail;
506
507 unsigned Register =
508 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
509 Inst.addOperand(MCOperand::createReg(Register));
510 return Success;
511}
512
513static DecodeStatus
514DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
515 const MCDisassembler *Decoder) {
516 if (RegNo > 22)
517 return Fail;
518 if (RegNo & 1)
519 return Fail;
520
521 unsigned Register =
522 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
523 RegNo >> 1);
524 Inst.addOperand(MCOperand::createReg(Register));
525 return Success;
526}
527
528static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
529 uint64_t Addr,
530 const MCDisassembler *Decoder) {
531 if (RegNo > 31)
532 return Fail;
533 unsigned Register =
534 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
535 Inst.addOperand(MCOperand::createReg(Register));
536 return Success;
537}
538
539static DecodeStatus
540DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
541 uint64_t Addr, const void *Decoder) {
542 if (RegNo > 3)
543 return Fail;
544
545 unsigned Register =
546 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
547 .getRegister(RegNo);
548 Inst.addOperand(MCOperand::createReg(Register));
549 return Success;
550}
551
552static DecodeStatus
553DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
554 uint64_t Addr,
555 const MCDisassembler *Decoder) {
556 if (RegNo > 3)
557 return Fail;
558
559 unsigned Register =
560 AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
561 .getRegister(RegNo);
562 Inst.addOperand(MCOperand::createReg(Register));
563 return Success;
564}
565
566static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
567 uint64_t Addr,
568 const MCDisassembler *Decoder) {
569 if (RegNo > 31)
570 return Fail;
571
572 unsigned Register =
573 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
574 Inst.addOperand(MCOperand::createReg(Register));
575 return Success;
576}
577
578static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
579 uint64_t Addr,
580 const MCDisassembler *Decoder) {
581 if (RegNo > 31)
582 return Fail;
583
584 unsigned Register =
585 AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
586 Inst.addOperand(MCOperand::createReg(Register));
587 return Success;
588}
589
590static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
591 uint64_t Address,
592 const MCDisassembler *Decoder) {
593 if (RegNo > 31)
594 return Fail;
595
596 unsigned Register =
597 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
598 Inst.addOperand(MCOperand::createReg(Register));
599 return Success;
600}
601
602static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
603 uint64_t Address,
604 const MCDisassembler *Decoder) {
605 if (RegNo > 15)
606 return Fail;
607 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
608}
609
610static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
611 uint64_t Address,
612 const MCDisassembler *Decoder) {
613 if (RegNo > 7)
614 return Fail;
615 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
616}
617
618static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
619 uint64_t Address,
620 const MCDisassembler *Decoder) {
621 if (RegNo > 31)
622 return Fail;
623 unsigned Register =
624 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
625 Inst.addOperand(MCOperand::createReg(Register));
626 return Success;
627}
628
629static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
630 uint64_t Address,
631 const MCDisassembler *Decoder) {
632 if (RegNo > 31)
633 return Fail;
634 unsigned Register =
635 AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
636 Inst.addOperand(MCOperand::createReg(Register));
637 return Success;
638}
639
640static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
641 uint64_t Address,
642 const MCDisassembler *Decoder) {
643 if (RegNo > 31)
644 return Fail;
645 unsigned Register =
646 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
647 Inst.addOperand(MCOperand::createReg(Register));
648 return Success;
649}
650
651static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
652 uint64_t Address,
653 const void *Decoder) {
654 if (RegNo * 2 > 30)
655 return Fail;
656 unsigned Register =
657 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
658 Inst.addOperand(MCOperand::createReg(Register));
659 return Success;
660}
661
662static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
663 uint64_t Address,
664 const void *Decoder) {
665 if (RegNo * 4 > 28)
666 return Fail;
667 unsigned Register =
668 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
669 Inst.addOperand(MCOperand::createReg(Register));
670 return Success;
671}
672
673static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
674 uint64_t Address,
675 const void *Decoder) {
676 if (RegNo > 15)
677 return Fail;
678 unsigned Register =
679 AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
680 RegNo);
681 Inst.addOperand(MCOperand::createReg(Register));
682 return Success;
683}
684
685static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
686 uint64_t Address,
687 const void *Decoder) {
688 if (RegNo > 7)
689 return Fail;
690 unsigned Register =
691 AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
692 RegNo);
693 Inst.addOperand(MCOperand::createReg(Register));
694 return Success;
695}
696
697static DecodeStatus
698DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
699 uint64_t Address,
700 const MCDisassembler *Decoder) {
701 if (RegMask > 0xFF)
702 return Fail;
703 Inst.addOperand(MCOperand::createImm(RegMask));
704 return Success;
705}
706
707static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
708 {AArch64::ZAB0},
709 {AArch64::ZAH0, AArch64::ZAH1},
710 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
711 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
712 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
713 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
714 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
715 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
716 AArch64::ZAQ14, AArch64::ZAQ15}};
717
718template <unsigned NumBitsForTile>
719static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
720 uint64_t Address,
721 const MCDisassembler *Decoder) {
722 unsigned LastReg = (1 << NumBitsForTile) - 1;
723 if (RegNo > LastReg)
724 return Fail;
725 Inst.addOperand(
726 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
727 return Success;
728}
729
730static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
731 uint64_t Addr,
732 const MCDisassembler *Decoder) {
733 if (RegNo > 15)
734 return Fail;
735
736 unsigned Register =
737 AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
738 Inst.addOperand(MCOperand::createReg(Register));
739 return Success;
740}
741
742static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
743 uint64_t Addr,
744 const MCDisassembler *Decoder) {
745 if (RegNo > 15)
746 return Fail;
747
748 unsigned Register =
749 AArch64MCRegisterClasses[AArch64::PNRRegClassID].getRegister(RegNo);
750 Inst.addOperand(MCOperand::createReg(Register));
751 return Success;
752}
753
754static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
755 uint64_t Addr,
756 const MCDisassembler *Decoder) {
757 if (RegNo > 7)
758 return Fail;
759
760 // Just reuse the PPR decode table
761 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
762}
763
764static DecodeStatus
765DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
766 const MCDisassembler *Decoder) {
767 if (RegNo > 7)
768 return Fail;
769
770 // Just reuse the PPR decode table
771 return DecodePNRRegisterClass(Inst, RegNo + 8, Addr, Decoder);
772}
773
774static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
775 uint64_t Address,
776 const void *Decoder) {
777 if (RegNo > 15)
778 return Fail;
779
780 unsigned Register =
781 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
782 Inst.addOperand(MCOperand::createReg(Register));
783 return Success;
784}
785
786static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
787 uint64_t Address,
788 const void *Decoder) {
789 if ((RegNo * 2) > 14)
790 return Fail;
791 unsigned Register =
792 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
793 Inst.addOperand(MCOperand::createReg(Register));
794 return Success;
795}
796
797static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
798 uint64_t Addr,
799 const MCDisassembler *Decoder) {
800 if (RegNo > 31)
801 return Fail;
802 unsigned Register =
803 AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
804 Inst.addOperand(MCOperand::createReg(Register));
805 return Success;
806}
807
808static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
809 uint64_t Addr,
810 const MCDisassembler *Decoder) {
811 if (RegNo > 31)
812 return Fail;
813 unsigned Register =
814 AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
815 Inst.addOperand(MCOperand::createReg(Register));
816 return Success;
817}
818
819static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
820 uint64_t Addr,
821 const MCDisassembler *Decoder) {
822 if (RegNo > 31)
823 return Fail;
824 unsigned Register =
825 AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
826 Inst.addOperand(MCOperand::createReg(Register));
827 return Success;
828}
829
830static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
831 uint64_t Addr,
832 const MCDisassembler *Decoder) {
833 if (RegNo > 31)
834 return Fail;
835 unsigned Register =
836 AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
837 Inst.addOperand(MCOperand::createReg(Register));
838 return Success;
839}
840
841static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
842 uint64_t Addr,
843 const MCDisassembler *Decoder) {
844 if (RegNo > 31)
845 return Fail;
846 unsigned Register =
847 AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
848 Inst.addOperand(MCOperand::createReg(Register));
849 return Success;
850}
851
852static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
853 uint64_t Addr,
854 const MCDisassembler *Decoder) {
855 if (RegNo > 31)
856 return Fail;
857 unsigned Register =
858 AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
859 Inst.addOperand(MCOperand::createReg(Register));
860 return Success;
861}
862
863static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
864 uint64_t Addr,
865 const MCDisassembler *Decoder) {
866 // scale{5} is asserted as 1 in tblgen.
867 Imm |= 0x20;
868 Inst.addOperand(MCOperand::createImm(64 - Imm));
869 return Success;
870}
871
872static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
873 uint64_t Addr,
874 const MCDisassembler *Decoder) {
875 Inst.addOperand(MCOperand::createImm(64 - Imm));
876 return Success;
877}
878
879static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
880 uint64_t Addr,
881 const MCDisassembler *Decoder) {
882 int64_t ImmVal = Imm;
883
884 // Sign-extend 19-bit immediate.
885 if (ImmVal & (1 << (19 - 1)))
886 ImmVal |= ~((1LL << 19) - 1);
887
888 if (!Decoder->tryAddingSymbolicOperand(
889 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
890 Inst.addOperand(MCOperand::createImm(ImmVal));
891 return Success;
892}
893
894static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
895 uint64_t Address,
896 const MCDisassembler *Decoder) {
897 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
898 Inst.addOperand(MCOperand::createImm(Imm & 1));
899 return Success;
900}
901
902static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
903 uint64_t Address,
904 const MCDisassembler *Decoder) {
905 Inst.addOperand(MCOperand::createImm(Imm));
906
907 // Every system register in the encoding space is valid with the syntax
908 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
909 return Success;
910}
911
912static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
913 uint64_t Address,
914 const MCDisassembler *Decoder) {
915 Inst.addOperand(MCOperand::createImm(Imm));
916
917 return Success;
918}
919
920static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
921 uint64_t Address,
922 const MCDisassembler *Decoder) {
923 // This decoder exists to add the dummy Lane operand to the MCInst, which must
924 // be 1 in assembly but has no other real manifestation.
925 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
926 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
927 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
928
929 if (IsToVec) {
930 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
931 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
932 } else {
933 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
934 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
935 }
936
937 // Add the lane
938 Inst.addOperand(MCOperand::createImm(1));
939
940 return Success;
941}
942
943static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
944 unsigned Add) {
945 Inst.addOperand(MCOperand::createImm(Add - Imm));
946 return Success;
947}
948
949static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
950 unsigned Add) {
951 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
952 return Success;
953}
954
955static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
956 uint64_t Addr,
957 const MCDisassembler *Decoder) {
958 return DecodeVecShiftRImm(Inst, Imm, 64);
959}
960
961static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
962 uint64_t Addr,
963 const MCDisassembler *Decoder) {
964 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
965}
966
967static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
968 uint64_t Addr,
969 const MCDisassembler *Decoder) {
970 return DecodeVecShiftRImm(Inst, Imm, 32);
971}
972
973static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
974 uint64_t Addr,
975 const MCDisassembler *Decoder) {
976 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
977}
978
979static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
980 uint64_t Addr,
981 const MCDisassembler *Decoder) {
982 return DecodeVecShiftRImm(Inst, Imm, 16);
983}
984
985static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
986 uint64_t Addr,
987 const MCDisassembler *Decoder) {
988 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
989}
990
991static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
992 uint64_t Addr,
993 const MCDisassembler *Decoder) {
994 return DecodeVecShiftRImm(Inst, Imm, 8);
995}
996
997static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
998 uint64_t Addr,
999 const MCDisassembler *Decoder) {
1000 return DecodeVecShiftLImm(Inst, Imm, 64);
1001}
1002
1003static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
1004 uint64_t Addr,
1005 const MCDisassembler *Decoder) {
1006 return DecodeVecShiftLImm(Inst, Imm, 32);
1007}
1008
1009static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
1010 uint64_t Addr,
1011 const MCDisassembler *Decoder) {
1012 return DecodeVecShiftLImm(Inst, Imm, 16);
1013}
1014
1015static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
1016 uint64_t Addr,
1017 const MCDisassembler *Decoder) {
1018 return DecodeVecShiftLImm(Inst, Imm, 8);
1019}
1020
1021static DecodeStatus
1022DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1023 const MCDisassembler *Decoder) {
1024 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1025 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1026 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1027 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1028 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1029 unsigned shift = (shiftHi << 6) | shiftLo;
1030 switch (Inst.getOpcode()) {
1031 default:
1032 return Fail;
1033 case AArch64::ADDWrs:
1034 case AArch64::ADDSWrs:
1035 case AArch64::SUBWrs:
1036 case AArch64::SUBSWrs:
1037 // if shift == '11' then ReservedValue()
1038 if (shiftHi == 0x3)
1039 return Fail;
1040 [[fallthrough]];
1041 case AArch64::ANDWrs:
1042 case AArch64::ANDSWrs:
1043 case AArch64::BICWrs:
1044 case AArch64::BICSWrs:
1045 case AArch64::ORRWrs:
1046 case AArch64::ORNWrs:
1047 case AArch64::EORWrs:
1048 case AArch64::EONWrs: {
1049 // if sf == '0' and imm6<5> == '1' then ReservedValue()
1050 if (shiftLo >> 5 == 1)
1051 return Fail;
1052 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1053 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1054 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1055 break;
1056 }
1057 case AArch64::ADDXrs:
1058 case AArch64::ADDSXrs:
1059 case AArch64::SUBXrs:
1060 case AArch64::SUBSXrs:
1061 // if shift == '11' then ReservedValue()
1062 if (shiftHi == 0x3)
1063 return Fail;
1064 [[fallthrough]];
1065 case AArch64::ANDXrs:
1066 case AArch64::ANDSXrs:
1067 case AArch64::BICXrs:
1068 case AArch64::BICSXrs:
1069 case AArch64::ORRXrs:
1070 case AArch64::ORNXrs:
1071 case AArch64::EORXrs:
1072 case AArch64::EONXrs:
1073 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1074 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1075 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1076 break;
1077 }
1078
1079 Inst.addOperand(MCOperand::createImm(shift));
1080 return Success;
1081}
1082
1083static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
1084 uint64_t Addr,
1085 const MCDisassembler *Decoder) {
1086 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1087 unsigned imm = fieldFromInstruction(insn, 5, 16);
1088 unsigned shift = fieldFromInstruction(insn, 21, 2);
1089 shift <<= 4;
1090 switch (Inst.getOpcode()) {
1091 default:
1092 return Fail;
1093 case AArch64::MOVZWi:
1094 case AArch64::MOVNWi:
1095 case AArch64::MOVKWi:
1096 if (shift & (1U << 5))
1097 return Fail;
1098 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1099 break;
1100 case AArch64::MOVZXi:
1101 case AArch64::MOVNXi:
1102 case AArch64::MOVKXi:
1103 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1104 break;
1105 }
1106
1107 if (Inst.getOpcode() == AArch64::MOVKWi ||
1108 Inst.getOpcode() == AArch64::MOVKXi)
1109 Inst.addOperand(Inst.getOperand(0));
1110
1111 Inst.addOperand(MCOperand::createImm(imm));
1112 Inst.addOperand(MCOperand::createImm(shift));
1113 return Success;
1114}
1115
1116static DecodeStatus
1117DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1118 const MCDisassembler *Decoder) {
1119 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1120 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1121 unsigned offset = fieldFromInstruction(insn, 10, 12);
1122
1123 switch (Inst.getOpcode()) {
1124 default:
1125 return Fail;
1126 case AArch64::PRFMui:
1127 // Rt is an immediate in prefetch.
1128 Inst.addOperand(MCOperand::createImm(Rt));
1129 break;
1130 case AArch64::STRBBui:
1131 case AArch64::LDRBBui:
1132 case AArch64::LDRSBWui:
1133 case AArch64::STRHHui:
1134 case AArch64::LDRHHui:
1135 case AArch64::LDRSHWui:
1136 case AArch64::STRWui:
1137 case AArch64::LDRWui:
1138 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1139 break;
1140 case AArch64::LDRSBXui:
1141 case AArch64::LDRSHXui:
1142 case AArch64::LDRSWui:
1143 case AArch64::STRXui:
1144 case AArch64::LDRXui:
1145 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1146 break;
1147 case AArch64::LDRQui:
1148 case AArch64::STRQui:
1149 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1150 break;
1151 case AArch64::LDRDui:
1152 case AArch64::STRDui:
1153 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1154 break;
1155 case AArch64::LDRSui:
1156 case AArch64::STRSui:
1157 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1158 break;
1159 case AArch64::LDRHui:
1160 case AArch64::STRHui:
1161 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1162 break;
1163 case AArch64::LDRBui:
1164 case AArch64::STRBui:
1165 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1166 break;
1167 }
1168
1169 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1170 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
1171 Inst.addOperand(MCOperand::createImm(offset));
1172 return Success;
1173}
1174
1175static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1176 uint64_t Addr,
1177 const MCDisassembler *Decoder) {
1178 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1179 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1180 int64_t offset = fieldFromInstruction(insn, 12, 9);
1181
1182 // offset is a 9-bit signed immediate, so sign extend it to
1183 // fill the unsigned.
1184 if (offset & (1 << (9 - 1)))
1185 offset |= ~((1LL << 9) - 1);
1186
1187 // First operand is always the writeback to the address register, if needed.
1188 switch (Inst.getOpcode()) {
1189 default:
1190 break;
1191 case AArch64::LDRSBWpre:
1192 case AArch64::LDRSHWpre:
1193 case AArch64::STRBBpre:
1194 case AArch64::LDRBBpre:
1195 case AArch64::STRHHpre:
1196 case AArch64::LDRHHpre:
1197 case AArch64::STRWpre:
1198 case AArch64::LDRWpre:
1199 case AArch64::LDRSBWpost:
1200 case AArch64::LDRSHWpost:
1201 case AArch64::STRBBpost:
1202 case AArch64::LDRBBpost:
1203 case AArch64::STRHHpost:
1204 case AArch64::LDRHHpost:
1205 case AArch64::STRWpost:
1206 case AArch64::LDRWpost:
1207 case AArch64::LDRSBXpre:
1208 case AArch64::LDRSHXpre:
1209 case AArch64::STRXpre:
1210 case AArch64::LDRSWpre:
1211 case AArch64::LDRXpre:
1212 case AArch64::LDRSBXpost:
1213 case AArch64::LDRSHXpost:
1214 case AArch64::STRXpost:
1215 case AArch64::LDRSWpost:
1216 case AArch64::LDRXpost:
1217 case AArch64::LDRQpre:
1218 case AArch64::STRQpre:
1219 case AArch64::LDRQpost:
1220 case AArch64::STRQpost:
1221 case AArch64::LDRDpre:
1222 case AArch64::STRDpre:
1223 case AArch64::LDRDpost:
1224 case AArch64::STRDpost:
1225 case AArch64::LDRSpre:
1226 case AArch64::STRSpre:
1227 case AArch64::LDRSpost:
1228 case AArch64::STRSpost:
1229 case AArch64::LDRHpre:
1230 case AArch64::STRHpre:
1231 case AArch64::LDRHpost:
1232 case AArch64::STRHpost:
1233 case AArch64::LDRBpre:
1234 case AArch64::STRBpre:
1235 case AArch64::LDRBpost:
1236 case AArch64::STRBpost:
1237 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1238 break;
1239 }
1240
1241 switch (Inst.getOpcode()) {
1242 default:
1243 return Fail;
1244 case AArch64::PRFUMi:
1245 // Rt is an immediate in prefetch.
1246 Inst.addOperand(MCOperand::createImm(Rt));
1247 break;
1248 case AArch64::STURBBi:
1249 case AArch64::LDURBBi:
1250 case AArch64::LDURSBWi:
1251 case AArch64::STURHHi:
1252 case AArch64::LDURHHi:
1253 case AArch64::LDURSHWi:
1254 case AArch64::STURWi:
1255 case AArch64::LDURWi:
1256 case AArch64::LDTRSBWi:
1257 case AArch64::LDTRSHWi:
1258 case AArch64::STTRWi:
1259 case AArch64::LDTRWi:
1260 case AArch64::STTRHi:
1261 case AArch64::LDTRHi:
1262 case AArch64::LDTRBi:
1263 case AArch64::STTRBi:
1264 case AArch64::LDRSBWpre:
1265 case AArch64::LDRSHWpre:
1266 case AArch64::STRBBpre:
1267 case AArch64::LDRBBpre:
1268 case AArch64::STRHHpre:
1269 case AArch64::LDRHHpre:
1270 case AArch64::STRWpre:
1271 case AArch64::LDRWpre:
1272 case AArch64::LDRSBWpost:
1273 case AArch64::LDRSHWpost:
1274 case AArch64::STRBBpost:
1275 case AArch64::LDRBBpost:
1276 case AArch64::STRHHpost:
1277 case AArch64::LDRHHpost:
1278 case AArch64::STRWpost:
1279 case AArch64::LDRWpost:
1280 case AArch64::STLURBi:
1281 case AArch64::STLURHi:
1282 case AArch64::STLURWi:
1283 case AArch64::LDAPURBi:
1284 case AArch64::LDAPURSBWi:
1285 case AArch64::LDAPURHi:
1286 case AArch64::LDAPURSHWi:
1287 case AArch64::LDAPURi:
1288 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1289 break;
1290 case AArch64::LDURSBXi:
1291 case AArch64::LDURSHXi:
1292 case AArch64::LDURSWi:
1293 case AArch64::STURXi:
1294 case AArch64::LDURXi:
1295 case AArch64::LDTRSBXi:
1296 case AArch64::LDTRSHXi:
1297 case AArch64::LDTRSWi:
1298 case AArch64::STTRXi:
1299 case AArch64::LDTRXi:
1300 case AArch64::LDRSBXpre:
1301 case AArch64::LDRSHXpre:
1302 case AArch64::STRXpre:
1303 case AArch64::LDRSWpre:
1304 case AArch64::LDRXpre:
1305 case AArch64::LDRSBXpost:
1306 case AArch64::LDRSHXpost:
1307 case AArch64::STRXpost:
1308 case AArch64::LDRSWpost:
1309 case AArch64::LDRXpost:
1310 case AArch64::LDAPURSWi:
1311 case AArch64::LDAPURSHXi:
1312 case AArch64::LDAPURSBXi:
1313 case AArch64::STLURXi:
1314 case AArch64::LDAPURXi:
1315 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1316 break;
1317 case AArch64::LDURQi:
1318 case AArch64::STURQi:
1319 case AArch64::LDRQpre:
1320 case AArch64::STRQpre:
1321 case AArch64::LDRQpost:
1322 case AArch64::STRQpost:
1323 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1324 break;
1325 case AArch64::LDURDi:
1326 case AArch64::STURDi:
1327 case AArch64::LDRDpre:
1328 case AArch64::STRDpre:
1329 case AArch64::LDRDpost:
1330 case AArch64::STRDpost:
1331 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1332 break;
1333 case AArch64::LDURSi:
1334 case AArch64::STURSi:
1335 case AArch64::LDRSpre:
1336 case AArch64::STRSpre:
1337 case AArch64::LDRSpost:
1338 case AArch64::STRSpost:
1339 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1340 break;
1341 case AArch64::LDURHi:
1342 case AArch64::STURHi:
1343 case AArch64::LDRHpre:
1344 case AArch64::STRHpre:
1345 case AArch64::LDRHpost:
1346 case AArch64::STRHpost:
1347 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1348 break;
1349 case AArch64::LDURBi:
1350 case AArch64::STURBi:
1351 case AArch64::LDRBpre:
1352 case AArch64::STRBpre:
1353 case AArch64::LDRBpost:
1354 case AArch64::STRBpost:
1355 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1356 break;
1357 }
1358
1359 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1360 Inst.addOperand(MCOperand::createImm(offset));
1361
1362 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1363 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1364 bool IsFP = fieldFromInstruction(insn, 26, 1);
1365
1366 // Cannot write back to a transfer register (but xzr != sp).
1367 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1368 return SoftFail;
1369
1370 return Success;
1371}
1372
1373static DecodeStatus
1374DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1375 const MCDisassembler *Decoder) {
1376 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1377 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1378 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1379 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1380
1381 unsigned Opcode = Inst.getOpcode();
1382 switch (Opcode) {
1383 default:
1384 return Fail;
1385 case AArch64::STLXRW:
1386 case AArch64::STLXRB:
1387 case AArch64::STLXRH:
1388 case AArch64::STXRW:
1389 case AArch64::STXRB:
1390 case AArch64::STXRH:
1391 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1392 [[fallthrough]];
1393 case AArch64::LDARW:
1394 case AArch64::LDARB:
1395 case AArch64::LDARH:
1396 case AArch64::LDAXRW:
1397 case AArch64::LDAXRB:
1398 case AArch64::LDAXRH:
1399 case AArch64::LDXRW:
1400 case AArch64::LDXRB:
1401 case AArch64::LDXRH:
1402 case AArch64::STLRW:
1403 case AArch64::STLRB:
1404 case AArch64::STLRH:
1405 case AArch64::STLLRW:
1406 case AArch64::STLLRB:
1407 case AArch64::STLLRH:
1408 case AArch64::LDLARW:
1409 case AArch64::LDLARB:
1410 case AArch64::LDLARH:
1411 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1412 break;
1413 case AArch64::STLXRX:
1414 case AArch64::STXRX:
1415 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1416 [[fallthrough]];
1417 case AArch64::LDARX:
1418 case AArch64::LDAXRX:
1419 case AArch64::LDXRX:
1420 case AArch64::STLRX:
1421 case AArch64::LDLARX:
1422 case AArch64::STLLRX:
1423 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1424 break;
1425 case AArch64::STLXPW:
1426 case AArch64::STXPW:
1427 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1428 [[fallthrough]];
1429 case AArch64::LDAXPW:
1430 case AArch64::LDXPW:
1431 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1432 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1433 break;
1434 case AArch64::STLXPX:
1435 case AArch64::STXPX:
1436 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1437 [[fallthrough]];
1438 case AArch64::LDAXPX:
1439 case AArch64::LDXPX:
1440 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1441 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1442 break;
1443 }
1444
1445 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1446
1447 // You shouldn't load to the same register twice in an instruction...
1448 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1449 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1450 Rt == Rt2)
1451 return SoftFail;
1452
1453 return Success;
1454}
1455
1456static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1457 uint64_t Addr,
1458 const MCDisassembler *Decoder) {
1459 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1460 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1461 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1462 int64_t offset = fieldFromInstruction(insn, 15, 7);
1463 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1464
1465 // offset is a 7-bit signed immediate, so sign extend it to
1466 // fill the unsigned.
1467 if (offset & (1 << (7 - 1)))
1468 offset |= ~((1LL << 7) - 1);
1469
1470 unsigned Opcode = Inst.getOpcode();
1471 bool NeedsDisjointWritebackTransfer = false;
1472
1473 // First operand is always writeback of base register.
1474 switch (Opcode) {
1475 default:
1476 break;
1477 case AArch64::LDPXpost:
1478 case AArch64::STPXpost:
1479 case AArch64::LDPSWpost:
1480 case AArch64::LDPXpre:
1481 case AArch64::STPXpre:
1482 case AArch64::LDPSWpre:
1483 case AArch64::LDPWpost:
1484 case AArch64::STPWpost:
1485 case AArch64::LDPWpre:
1486 case AArch64::STPWpre:
1487 case AArch64::LDPQpost:
1488 case AArch64::STPQpost:
1489 case AArch64::LDPQpre:
1490 case AArch64::STPQpre:
1491 case AArch64::LDPDpost:
1492 case AArch64::STPDpost:
1493 case AArch64::LDPDpre:
1494 case AArch64::STPDpre:
1495 case AArch64::LDPSpost:
1496 case AArch64::STPSpost:
1497 case AArch64::LDPSpre:
1498 case AArch64::STPSpre:
1499 case AArch64::STGPpre:
1500 case AArch64::STGPpost:
1501 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1502 break;
1503 }
1504
1505 switch (Opcode) {
1506 default:
1507 return Fail;
1508 case AArch64::LDPXpost:
1509 case AArch64::STPXpost:
1510 case AArch64::LDPSWpost:
1511 case AArch64::LDPXpre:
1512 case AArch64::STPXpre:
1513 case AArch64::LDPSWpre:
1514 case AArch64::STGPpre:
1515 case AArch64::STGPpost:
1516 NeedsDisjointWritebackTransfer = true;
1517 [[fallthrough]];
1518 case AArch64::LDNPXi:
1519 case AArch64::STNPXi:
1520 case AArch64::LDPXi:
1521 case AArch64::STPXi:
1522 case AArch64::LDPSWi:
1523 case AArch64::STGPi:
1524 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1525 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1526 break;
1527 case AArch64::LDPWpost:
1528 case AArch64::STPWpost:
1529 case AArch64::LDPWpre:
1530 case AArch64::STPWpre:
1531 NeedsDisjointWritebackTransfer = true;
1532 [[fallthrough]];
1533 case AArch64::LDNPWi:
1534 case AArch64::STNPWi:
1535 case AArch64::LDPWi:
1536 case AArch64::STPWi:
1537 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1538 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1539 break;
1540 case AArch64::LDNPQi:
1541 case AArch64::STNPQi:
1542 case AArch64::LDPQpost:
1543 case AArch64::STPQpost:
1544 case AArch64::LDPQi:
1545 case AArch64::STPQi:
1546 case AArch64::LDPQpre:
1547 case AArch64::STPQpre:
1548 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1549 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1550 break;
1551 case AArch64::LDNPDi:
1552 case AArch64::STNPDi:
1553 case AArch64::LDPDpost:
1554 case AArch64::STPDpost:
1555 case AArch64::LDPDi:
1556 case AArch64::STPDi:
1557 case AArch64::LDPDpre:
1558 case AArch64::STPDpre:
1559 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1560 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1561 break;
1562 case AArch64::LDNPSi:
1563 case AArch64::STNPSi:
1564 case AArch64::LDPSpost:
1565 case AArch64::STPSpost:
1566 case AArch64::LDPSi:
1567 case AArch64::STPSi:
1568 case AArch64::LDPSpre:
1569 case AArch64::STPSpre:
1570 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1571 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1572 break;
1573 }
1574
1575 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1576 Inst.addOperand(MCOperand::createImm(offset));
1577
1578 // You shouldn't load to the same register twice in an instruction...
1579 if (IsLoad && Rt == Rt2)
1580 return SoftFail;
1581
1582 // ... or do any operation that writes-back to a transfer register. But note
1583 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1584 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1585 return SoftFail;
1586
1587 return Success;
1588}
1589
1590static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1591 uint64_t Addr,
1592 const MCDisassembler *Decoder) {
1593 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1594 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1595 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1596 fieldFromInstruction(insn, 12, 9);
1597 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1598
1599 switch (Inst.getOpcode()) {
1600 default:
1601 return Fail;
1602 case AArch64::LDRAAwriteback:
1603 case AArch64::LDRABwriteback:
1604 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1605 Decoder);
1606 break;
1607 case AArch64::LDRAAindexed:
1608 case AArch64::LDRABindexed:
1609 break;
1610 }
1611
1612 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1613 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1614 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1615
1616 if (writeback && Rt == Rn && Rn != 31) {
1617 return SoftFail;
1618 }
1619
1620 return Success;
1621}
1622
1623static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1624 uint64_t Addr,
1625 const MCDisassembler *Decoder) {
1626 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1627 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1628 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1629 unsigned extend = fieldFromInstruction(insn, 10, 6);
1630
1631 unsigned shift = extend & 0x7;
1632 if (shift > 4)
1633 return Fail;
1634
1635 switch (Inst.getOpcode()) {
1636 default:
1637 return Fail;
1638 case AArch64::ADDWrx:
1639 case AArch64::SUBWrx:
1640 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1641 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1642 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1643 break;
1644 case AArch64::ADDSWrx:
1645 case AArch64::SUBSWrx:
1646 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1647 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1648 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1649 break;
1650 case AArch64::ADDXrx:
1651 case AArch64::SUBXrx:
1652 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1653 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1654 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1655 break;
1656 case AArch64::ADDSXrx:
1657 case AArch64::SUBSXrx:
1658 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1659 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1660 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1661 break;
1662 case AArch64::ADDXrx64:
1663 case AArch64::SUBXrx64:
1664 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1665 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1666 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1667 break;
1668 case AArch64::SUBSXrx64:
1669 case AArch64::ADDSXrx64:
1670 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1671 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1672 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1673 break;
1674 }
1675
1676 Inst.addOperand(MCOperand::createImm(extend));
1677 return Success;
1678}
1679
1680static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1681 uint64_t Addr,
1682 const MCDisassembler *Decoder) {
1683 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1684 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1685 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1686 unsigned imm;
1687
1688 if (Datasize) {
1689 if (Inst.getOpcode() == AArch64::ANDSXri)
1690 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1691 else
1692 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1693 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1694 imm = fieldFromInstruction(insn, 10, 13);
1695 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1696 return Fail;
1697 } else {
1698 if (Inst.getOpcode() == AArch64::ANDSWri)
1699 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1700 else
1701 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1702 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1703 imm = fieldFromInstruction(insn, 10, 12);
1704 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1705 return Fail;
1706 }
1707 Inst.addOperand(MCOperand::createImm(imm));
1708 return Success;
1709}
1710
1711static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1712 uint64_t Addr,
1713 const MCDisassembler *Decoder) {
1714 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1715 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1716 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1717 imm |= fieldFromInstruction(insn, 5, 5);
1718
1719 if (Inst.getOpcode() == AArch64::MOVID)
1720 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1721 else
1722 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1723
1724 Inst.addOperand(MCOperand::createImm(imm));
1725
1726 switch (Inst.getOpcode()) {
1727 default:
1728 break;
1729 case AArch64::MOVIv4i16:
1730 case AArch64::MOVIv8i16:
1731 case AArch64::MVNIv4i16:
1732 case AArch64::MVNIv8i16:
1733 case AArch64::MOVIv2i32:
1734 case AArch64::MOVIv4i32:
1735 case AArch64::MVNIv2i32:
1736 case AArch64::MVNIv4i32:
1737 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1738 break;
1739 case AArch64::MOVIv2s_msl:
1740 case AArch64::MOVIv4s_msl:
1741 case AArch64::MVNIv2s_msl:
1742 case AArch64::MVNIv4s_msl:
1743 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1744 break;
1745 }
1746
1747 return Success;
1748}
1749
1750static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1751 uint64_t Addr,
1752 const MCDisassembler *Decoder) {
1753 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1754 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1755 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1756 imm |= fieldFromInstruction(insn, 5, 5);
1757
1758 // Tied operands added twice.
1759 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1760 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1761
1762 Inst.addOperand(MCOperand::createImm(imm));
1763 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1764
1765 return Success;
1766}
1767
1768static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1769 uint64_t Addr,
1770 const MCDisassembler *Decoder) {
1771 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1772 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1773 imm |= fieldFromInstruction(insn, 29, 2);
1774
1775 // Sign-extend the 21-bit immediate.
1776 if (imm & (1 << (21 - 1)))
1777 imm |= ~((1LL << 21) - 1);
1778
1779 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1780 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1781 Inst.addOperand(MCOperand::createImm(imm));
1782
1783 return Success;
1784}
1785
1786static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1787 uint64_t Addr,
1788 const MCDisassembler *Decoder) {
1789 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1790 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1791 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1792 unsigned S = fieldFromInstruction(insn, 29, 1);
1793 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1794
1795 unsigned ShifterVal = (Imm >> 12) & 3;
1796 unsigned ImmVal = Imm & 0xFFF;
1797
1798 if (ShifterVal != 0 && ShifterVal != 1)
1799 return Fail;
1800
1801 if (Datasize) {
1802 if (Rd == 31 && !S)
1803 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1804 else
1805 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1806 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1807 } else {
1808 if (Rd == 31 && !S)
1809 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1810 else
1811 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1812 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1813 }
1814
1815 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1816 Inst.addOperand(MCOperand::createImm(ImmVal));
1817 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1818 return Success;
1819}
1820
1821static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1822 uint64_t Addr,
1823 const MCDisassembler *Decoder) {
1824 int64_t imm = fieldFromInstruction(insn, 0, 26);
1825
1826 // Sign-extend the 26-bit immediate.
1827 if (imm & (1 << (26 - 1)))
1828 imm |= ~((1LL << 26) - 1);
1829
1830 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1831 Inst.addOperand(MCOperand::createImm(imm));
1832
1833 return Success;
1834}
1835
1836static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1837 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1838 Op2 == 0b001 || // XAFlag
1839 Op2 == 0b010); // AXFlag
1840}
1841
1842static DecodeStatus
1843DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1844 const MCDisassembler *Decoder) {
1845 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1846 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1847 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1848 uint64_t pstate_field = (op1 << 3) | op2;
1849
1850 if (isInvalidPState(op1, op2))
1851 return Fail;
1852
1853 Inst.addOperand(MCOperand::createImm(pstate_field));
1854 Inst.addOperand(MCOperand::createImm(imm));
1855
1856 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1857 if (PState &&
1858 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1859 return Success;
1860 return Fail;
1861}
1862
1863static DecodeStatus
1864DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1865 const MCDisassembler *Decoder) {
1866 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1867 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1868 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1869 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1870 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1871
1872 if (isInvalidPState(op1, op2))
1873 return Fail;
1874
1875 Inst.addOperand(MCOperand::createImm(pstate_field));
1876 Inst.addOperand(MCOperand::createImm(imm));
1877
1878 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1879 if (PState &&
1880 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1881 return Success;
1882 return Fail;
1883}
1884
1885static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1886 uint64_t Addr,
1887 const MCDisassembler *Decoder) {
1888 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1889 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1890 bit |= fieldFromInstruction(insn, 19, 5);
1891 int64_t dst = fieldFromInstruction(insn, 5, 14);
1892
1893 // Sign-extend 14-bit immediate.
1894 if (dst & (1 << (14 - 1)))
1895 dst |= ~((1LL << 14) - 1);
1896
1897 if (fieldFromInstruction(insn, 31, 1) == 0)
1898 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1899 else
1900 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1901 Inst.addOperand(MCOperand::createImm(bit));
1902 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1903 Inst.addOperand(MCOperand::createImm(dst));
1904
1905 return Success;
1906}
1907
1908static DecodeStatus
1909DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1910 unsigned RegNo, uint64_t Addr,
1911 const MCDisassembler *Decoder) {
1912 // Register number must be even (see CASP instruction)
1913 if (RegNo & 0x1)
1914 return Fail;
1915
1916 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1917 Inst.addOperand(MCOperand::createReg(Reg));
1918 return Success;
1919}
1920
1921static DecodeStatus
1922DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1923 const MCDisassembler *Decoder) {
1924 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1925 AArch64::WSeqPairsClassRegClassID,
1926 RegNo, Addr, Decoder);
1927}
1928
1929static DecodeStatus
1930DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1931 const MCDisassembler *Decoder) {
1932 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1933 AArch64::XSeqPairsClassRegClassID,
1934 RegNo, Addr, Decoder);
1935}
1936
1937static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1938 uint64_t Addr,
1939 const MCDisassembler *Decoder) {
1940 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1941 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1942 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1943 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1944 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1945 if (Rt != 0b11111)
1946 return Fail;
1947
1948 Inst.addOperand(MCOperand::createImm(op1));
1949 Inst.addOperand(MCOperand::createImm(CRn));
1950 Inst.addOperand(MCOperand::createImm(CRm));
1951 Inst.addOperand(MCOperand::createImm(op2));
1952 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1953
1954 return Success;
1955}
1956
1957static DecodeStatus
1958DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1959 const MCDisassembler *Decoder) {
1960 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1961 unsigned imm = fieldFromInstruction(insn, 5, 13);
1962 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1963 return Fail;
1964
1965 // The same (tied) operand is added twice to the instruction.
1966 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1967 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1968 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1969 Inst.addOperand(MCOperand::createImm(imm));
1970 return Success;
1971}
1972
1973template <int Bits>
1974static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1975 const MCDisassembler *Decoder) {
1976 if (Imm & ~((1LL << Bits) - 1))
1977 return Fail;
1978
1979 // Imm is a signed immediate, so sign extend it.
1980 if (Imm & (1 << (Bits - 1)))
1981 Imm |= ~((1LL << Bits) - 1);
1982
1983 Inst.addOperand(MCOperand::createImm(Imm));
1984 return Success;
1985}
1986
1987// Decode 8-bit signed/unsigned immediate for a given element width.
1988template <int ElementWidth>
1989static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
1990 const MCDisassembler *Decoder) {
1991 unsigned Val = (uint8_t)Imm;
1992 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1993 if (ElementWidth == 8 && Shift)
1994 return Fail;
1995 Inst.addOperand(MCOperand::createImm(Val));
1996 Inst.addOperand(MCOperand::createImm(Shift));
1997 return Success;
1998}
1999
2000// Decode uimm4 ranged from 1-16.
2001static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
2002 uint64_t Addr,
2003 const MCDisassembler *Decoder) {
2004 Inst.addOperand(MCOperand::createImm(Imm + 1));
2005 return Success;
2006}
2007
2008static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
2009 const MCDisassembler *Decoder) {
2010 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2011 Inst.addOperand(MCOperand::createImm(Imm));
2012 return Success;
2013 }
2014 return Fail;
2015}
2016
2017static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
2018 uint64_t Addr,
2019 const MCDisassembler *Decoder) {
2020 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2021 unsigned Rs = fieldFromInstruction(insn, 16, 5);
2022 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2023
2024 // None of the registers may alias: if they do, then the instruction is not
2025 // merely unpredictable but actually entirely unallocated.
2026 if (Rd == Rs || Rs == Rn || Rd == Rn)
2027 return MCDisassembler::Fail;
2028
2029 // All three register operands are written back, so they all appear
2030 // twice in the operand list, once as outputs and once as inputs.
2031 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2032 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2033 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2034 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2035 !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2036 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder))
2037 return MCDisassembler::Fail;
2038
2039 return MCDisassembler::Success;
2040}
2041
2042static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
2043 uint64_t Addr,
2044 const MCDisassembler *Decoder) {
2045 unsigned Rd = fieldFromInstruction(insn, 0, 5);
2046 unsigned Rm = fieldFromInstruction(insn, 16, 5);
2047 unsigned Rn = fieldFromInstruction(insn, 5, 5);
2048
2049 // None of the registers may alias: if they do, then the instruction is not
2050 // merely unpredictable but actually entirely unallocated.
2051 if (Rd == Rm || Rm == Rn || Rd == Rn)
2052 return MCDisassembler::Fail;
2053
2054 // Rd and Rn (not Rm) register operands are written back, so they appear
2055 // twice in the operand list, once as outputs and once as inputs.
2056 if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2057 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2058 !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2059 !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2060 !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder))
2061 return MCDisassembler::Fail;
2062
2063 return MCDisassembler::Success;
2064}
2065
2066static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
2067 uint64_t Addr,
2068 const MCDisassembler *Decoder) {
2069 // PRFM with Rt = '11xxx' should be decoded as RPRFM.
2070 // Fail to decode and defer to fallback decoder table to decode RPRFM.
2071 unsigned Mask = 0x18;
2072 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2073 if ((Rt & Mask) == Mask)
2074 return Fail;
2075
2076 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2077 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2078 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2079 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2080
2081 Inst.addOperand(MCOperand::createImm(Rt));
2082 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
2083
2084 switch (Inst.getOpcode()) {
2085 default:
2086 return Fail;
2087 case AArch64::PRFMroW:
2088 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
2089 break;
2090 case AArch64::PRFMroX:
2091 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
2092 break;
2093 }
2094
2095 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
2096
2097 return Success;
2098}
DecodePPRRegisterClass
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:730
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1821
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:997
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1003
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:388
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2017
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:991
DecodeQQQQRegisterClass
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:819
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:872
DecodeGPR32spRegisterClass
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:578
DecodePNRRegisterClass
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:742
DecodeFPR8RegisterClass
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:476
DecodeZPR4RegisterClass
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:640
DecodeFPR128_loRegisterClass
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:433
DecodeQQRegisterClass
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:797
DecodeZPR3RegisterClass
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:629
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1623
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1711
DecodeDDDRegisterClass
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:841
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1680
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1083
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1864
DecodeDDRegisterClass
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:830
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:307
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:514
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1117
DecodePPR2RegisterClass
static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:774
MatrixZATileDecoderTable
static const MCPhysReg MatrixZATileDecoderTable[5][16]
Definition: AArch64Disassembler.cpp:707
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1930
DecodeGPR64commonRegisterClass
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:489
DecodeMatrixIndexGPR32_12_15RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:553
DecodeQQQRegisterClass
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:808
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:651
DecodeZPRRegisterClass
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:590
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1590
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1009
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1456
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:464
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:305
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:719
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1974
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:973
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:786
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1843
DecodeDDDDRegisterClass
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:852
DecodeGPR64spRegisterClass
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:528
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1015
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2001
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:863
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1885
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1958
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:943
DecodePNR_p8to15RegisterClass
static DecodeStatus DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:765
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:396
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:955
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:949
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:985
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:566
DecodePPR_3bRegisterClass
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:754
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2008
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1922
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:961
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:662
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1786
Fail
#define Fail
Definition: AArch64Disassembler.cpp:304
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:912
DecodeZPR2StridedRegisterClass
static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:673
Success
#define Success
Definition: AArch64Disassembler.cpp:303
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2042
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:879
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1022
DecodeZPR4StridedRegisterClass
static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:685
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:894
DecodeZPR_3bRegisterClass
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:610
DecodeMatrixIndexGPR32_8_11RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:540
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1175
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1374
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1937
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:920
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:501
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition: AArch64Disassembler.cpp:1836
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:698
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1768
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:2066
DecodeZPR_4bRegisterClass
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:602
DecodeZPR2RegisterClass
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:618
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:979
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:967
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:452
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1989
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:420
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1909
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:902
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:440
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1750
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:157
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:314
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: AArch64Disassembler.cpp:379
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:83
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:218
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:201
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:222
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:107
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint32_t
uint64_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:321
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:61
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1070
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:972
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