LLVM  10.0.0svn
AArch64Disassembler.cpp
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1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64Disassembler.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm-c/Disassembler.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
28 #include <algorithm>
29 #include <memory>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "aarch64-disassembler"
34 
35 // Pull DecodeStatus and its enum values into the global namespace.
37 
38 // Forward declare these because the autogenerated code will reference them.
39 // Definitions are further down.
41  unsigned RegNo, uint64_t Address,
42  const void *Decoder);
44  unsigned RegNo,
45  uint64_t Address,
46  const void *Decoder);
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
48  uint64_t Address,
49  const void *Decoder);
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
51  uint64_t Address,
52  const void *Decoder);
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
54  uint64_t Address,
55  const void *Decoder);
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
57  uint64_t Address,
58  const void *Decoder);
59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
60  uint64_t Address,
61  const void *Decoder);
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
63  uint64_t Address,
64  const void *Decoder);
66  unsigned RegNo, uint64_t Address,
67  const void *Decoder);
68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
69  uint64_t Address,
70  const void *Decoder);
72  unsigned RegNo, uint64_t Address,
73  const void *Decoder);
74 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
75  uint64_t Address,
76  const void *Decoder);
77 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
78  uint64_t Address,
79  const void *Decoder);
80 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
81  uint64_t Address,
82  const void *Decoder);
83 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
84  uint64_t Address,
85  const void *Decoder);
86 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
87  uint64_t Address,
88  const void *Decoder);
89 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
90  uint64_t Address,
91  const void *Decoder);
92 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
93  uint64_t Address,
94  const void *Decoder);
95 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
96  uint64_t Address,
97  const void *Decoder);
98 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
99  uint64_t Address,
100  const void *Decoder);
101 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
102  uint64_t Address,
103  const void *Decoder);
104 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
105  uint64_t Address,
106  const void *Decoder);
107 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
108  uint64_t Address,
109  const void *Decoder);
110 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
111  uint64_t Address,
112  const void *Decoder);
113 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
114  uint64_t Address,
115  const void *Decoder);
116 
117 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
118  uint64_t Address,
119  const void *Decoder);
120 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
121  uint64_t Address,
122  const void *Decoder);
123 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
124  uint64_t Address, const void *Decoder);
125 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
126  uint64_t Address, const void *Decoder);
127 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
128  uint64_t Address, const void *Decoder);
129 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
130  uint64_t Address, const void *Decoder);
132  uint64_t Address,
133  const void *Decoder);
135  uint64_t Address,
136  const void *Decoder);
138  uint64_t Address,
139  const void *Decoder);
141  uint64_t Address,
142  const void *Decoder);
144  uint64_t Address,
145  const void *Decoder);
147  uint64_t Address,
148  const void *Decoder);
150  uint64_t Address,
151  const void *Decoder);
153  uint64_t Address,
154  const void *Decoder);
156  uint64_t Address,
157  const void *Decoder);
159  uint64_t Address,
160  const void *Decoder);
162  uint64_t Address, const void *Decoder);
164  uint64_t Address, const void *Decoder);
166  uint64_t Address,
167  const void *Decoder);
169  uint64_t Address,
170  const void *Decoder);
172  uint64_t Address, const void *Decoder);
173 
174 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
175  uint64_t Address,
176  const void *Decoder);
177 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
178  uint64_t Addr, const void *Decoder);
179 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
180  uint64_t Addr,
181  const void *Decoder);
182 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
183  uint64_t Addr, const void *Decoder);
184 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
185  uint64_t Addr,
186  const void *Decoder);
187 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
188  uint64_t Addr, const void *Decoder);
189 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
190  uint64_t Addr,
191  const void *Decoder);
192 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
193  uint64_t Addr, const void *Decoder);
194 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
195  uint64_t Addr, const void *Decoder);
196 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
197  uint64_t Addr, const void *Decoder);
198 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
199  uint64_t Addr, const void *Decoder);
200 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
201  uint64_t Addr, const void *Decoder);
203  unsigned RegNo,
204  uint64_t Addr,
205  const void *Decoder);
207  unsigned RegNo,
208  uint64_t Addr,
209  const void *Decoder);
211  uint32_t insn,
212  uint64_t Address,
213  const void *Decoder);
214 template<int Bits>
215 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
216  uint64_t Address, const void *Decoder);
217 template <int ElementWidth>
218 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
219  uint64_t Addr, const void *Decoder);
220 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
221  uint64_t Addr, const void *Decoder);
222 
223 static bool Check(DecodeStatus &Out, DecodeStatus In) {
224  switch (In) {
226  // Out stays the same.
227  return true;
229  Out = In;
230  return true;
232  Out = In;
233  return false;
234  }
235  llvm_unreachable("Invalid DecodeStatus!");
236 }
237 
238 #include "AArch64GenDisassemblerTables.inc"
239 #include "AArch64GenInstrInfo.inc"
240 
241 #define Success MCDisassembler::Success
242 #define Fail MCDisassembler::Fail
243 #define SoftFail MCDisassembler::SoftFail
244 
246  const MCSubtargetInfo &STI,
247  MCContext &Ctx) {
248  return new AArch64Disassembler(STI, Ctx);
249 }
250 
252  ArrayRef<uint8_t> Bytes,
253  uint64_t Address,
254  raw_ostream &OS,
255  raw_ostream &CS) const {
256  CommentStream = &CS;
257 
258  Size = 0;
259  // We want to read exactly 4 bytes of data.
260  if (Bytes.size() < 4)
261  return Fail;
262  Size = 4;
263 
264  // Encoded as a small-endian 32-bit word in the stream.
265  uint32_t Insn =
266  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
267 
268  // Calling the auto-generated decoder function.
269  return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
270 }
271 
272 static MCSymbolizer *
274  LLVMSymbolLookupCallback SymbolLookUp,
275  void *DisInfo, MCContext *Ctx,
276  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
277  return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
278  SymbolLookUp, DisInfo);
279 }
280 
294 
303 }
304 
305 static const unsigned FPR128DecoderTable[] = {
306  AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
307  AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
308  AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
309  AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
310  AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
311  AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
312  AArch64::Q30, AArch64::Q31
313 };
314 
315 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
316  uint64_t Addr,
317  const void *Decoder) {
318  if (RegNo > 31)
319  return Fail;
320 
321  unsigned Register = FPR128DecoderTable[RegNo];
322  Inst.addOperand(MCOperand::createReg(Register));
323  return Success;
324 }
325 
326 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
327  uint64_t Addr,
328  const void *Decoder) {
329  if (RegNo > 15)
330  return Fail;
331  return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
332 }
333 
334 static const unsigned FPR64DecoderTable[] = {
335  AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
336  AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
337  AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
338  AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
339  AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
340  AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
341  AArch64::D30, AArch64::D31
342 };
343 
344 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
345  uint64_t Addr,
346  const void *Decoder) {
347  if (RegNo > 31)
348  return Fail;
349 
350  unsigned Register = FPR64DecoderTable[RegNo];
351  Inst.addOperand(MCOperand::createReg(Register));
352  return Success;
353 }
354 
355 static const unsigned FPR32DecoderTable[] = {
356  AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
357  AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
358  AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
359  AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
360  AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
361  AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
362  AArch64::S30, AArch64::S31
363 };
364 
365 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
366  uint64_t Addr,
367  const void *Decoder) {
368  if (RegNo > 31)
369  return Fail;
370 
371  unsigned Register = FPR32DecoderTable[RegNo];
372  Inst.addOperand(MCOperand::createReg(Register));
373  return Success;
374 }
375 
376 static const unsigned FPR16DecoderTable[] = {
377  AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
378  AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
379  AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
380  AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
381  AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
382  AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
383  AArch64::H30, AArch64::H31
384 };
385 
386 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
387  uint64_t Addr,
388  const void *Decoder) {
389  if (RegNo > 31)
390  return Fail;
391 
392  unsigned Register = FPR16DecoderTable[RegNo];
393  Inst.addOperand(MCOperand::createReg(Register));
394  return Success;
395 }
396 
397 static const unsigned FPR8DecoderTable[] = {
398  AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
399  AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
400  AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
401  AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
402  AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
403  AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
404  AArch64::B30, AArch64::B31
405 };
406 
407 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
408  uint64_t Addr,
409  const void *Decoder) {
410  if (RegNo > 31)
411  return Fail;
412 
413  unsigned Register = FPR8DecoderTable[RegNo];
414  Inst.addOperand(MCOperand::createReg(Register));
415  return Success;
416 }
417 
418 static const unsigned GPR64DecoderTable[] = {
419  AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
420  AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
421  AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
422  AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
423  AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
424  AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
425  AArch64::LR, AArch64::XZR
426 };
427 
429  uint64_t Addr,
430  const void *Decoder) {
431  if (RegNo > 30)
432  return Fail;
433 
434  unsigned Register = GPR64DecoderTable[RegNo];
435  Inst.addOperand(MCOperand::createReg(Register));
436  return Success;
437 }
438 
439 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
440  uint64_t Addr,
441  const void *Decoder) {
442  if (RegNo > 31)
443  return Fail;
444 
445  unsigned Register = GPR64DecoderTable[RegNo];
446  Inst.addOperand(MCOperand::createReg(Register));
447  return Success;
448 }
449 
450 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
451  uint64_t Addr,
452  const void *Decoder) {
453  if (RegNo > 31)
454  return Fail;
455  unsigned Register = GPR64DecoderTable[RegNo];
456  if (Register == AArch64::XZR)
457  Register = AArch64::SP;
458  Inst.addOperand(MCOperand::createReg(Register));
459  return Success;
460 }
461 
462 static const unsigned GPR32DecoderTable[] = {
463  AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
464  AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
465  AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
466  AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
467  AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
468  AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
469  AArch64::W30, AArch64::WZR
470 };
471 
472 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
473  uint64_t Addr,
474  const void *Decoder) {
475  if (RegNo > 31)
476  return Fail;
477 
478  unsigned Register = GPR32DecoderTable[RegNo];
479  Inst.addOperand(MCOperand::createReg(Register));
480  return Success;
481 }
482 
483 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
484  uint64_t Addr,
485  const void *Decoder) {
486  if (RegNo > 31)
487  return Fail;
488 
489  unsigned Register = GPR32DecoderTable[RegNo];
490  if (Register == AArch64::WZR)
491  Register = AArch64::WSP;
492  Inst.addOperand(MCOperand::createReg(Register));
493  return Success;
494 }
495 static const unsigned ZPRDecoderTable[] = {
496  AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
497  AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
498  AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
499  AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
500  AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
501  AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
502  AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
503  AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
504 };
505 
506 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
507  uint64_t Address,
508  const void* Decoder) {
509  if (RegNo > 31)
510  return Fail;
511 
512  unsigned Register = ZPRDecoderTable[RegNo];
513  Inst.addOperand(MCOperand::createReg(Register));
514  return Success;
515 }
516 
517 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
518  uint64_t Address,
519  const void *Decoder) {
520  if (RegNo > 15)
521  return Fail;
522  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
523 }
524 
525 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
526  uint64_t Address,
527  const void *Decoder) {
528  if (RegNo > 7)
529  return Fail;
530  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
531 }
532 
533 static const unsigned ZZDecoderTable[] = {
534  AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
535  AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
536  AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
537  AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
538  AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
539  AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
540  AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
541  AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
542 };
543 
544 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
545  uint64_t Address,
546  const void* Decoder) {
547  if (RegNo > 31)
548  return Fail;
549  unsigned Register = ZZDecoderTable[RegNo];
550  Inst.addOperand(MCOperand::createReg(Register));
551  return Success;
552 }
553 
554 static const unsigned ZZZDecoderTable[] = {
555  AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
556  AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
557  AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
558  AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
559  AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
560  AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
561  AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
562  AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
563  AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
564  AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
565  AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
566 };
567 
568 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
569  uint64_t Address,
570  const void* Decoder) {
571  if (RegNo > 31)
572  return Fail;
573  unsigned Register = ZZZDecoderTable[RegNo];
574  Inst.addOperand(MCOperand::createReg(Register));
575  return Success;
576 }
577 
578 static const unsigned ZZZZDecoderTable[] = {
579  AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
580  AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
581  AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
582  AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
583  AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
584  AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
585  AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
586  AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
587  AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
588  AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
589  AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
590 };
591 
592 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
593  uint64_t Address,
594  const void* Decoder) {
595  if (RegNo > 31)
596  return Fail;
597  unsigned Register = ZZZZDecoderTable[RegNo];
598  Inst.addOperand(MCOperand::createReg(Register));
599  return Success;
600 }
601 
602 static const unsigned PPRDecoderTable[] = {
603  AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
604  AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
605  AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
606  AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
607 };
608 
609 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
610  uint64_t Addr, const void *Decoder) {
611  if (RegNo > 15)
612  return Fail;
613 
614  unsigned Register = PPRDecoderTable[RegNo];
615  Inst.addOperand(MCOperand::createReg(Register));
616  return Success;
617 }
618 
619 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
620  uint64_t Addr,
621  const void* Decoder) {
622  if (RegNo > 7)
623  return Fail;
624 
625  // Just reuse the PPR decode table
626  return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
627 }
628 
629 static const unsigned VectorDecoderTable[] = {
630  AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
631  AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
632  AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
633  AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
634  AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
635  AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
636  AArch64::Q30, AArch64::Q31
637 };
638 
639 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
640  uint64_t Addr,
641  const void *Decoder) {
642  if (RegNo > 31)
643  return Fail;
644 
645  unsigned Register = VectorDecoderTable[RegNo];
646  Inst.addOperand(MCOperand::createReg(Register));
647  return Success;
648 }
649 
650 static const unsigned QQDecoderTable[] = {
651  AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
652  AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
653  AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
654  AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
655  AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
656  AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
657  AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
658  AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
659 };
660 
661 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
662  uint64_t Addr, const void *Decoder) {
663  if (RegNo > 31)
664  return Fail;
665  unsigned Register = QQDecoderTable[RegNo];
666  Inst.addOperand(MCOperand::createReg(Register));
667  return Success;
668 }
669 
670 static const unsigned QQQDecoderTable[] = {
671  AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
672  AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
673  AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
674  AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
675  AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
676  AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
677  AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
678  AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
679  AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
680  AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
681  AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
682 };
683 
684 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
685  uint64_t Addr, const void *Decoder) {
686  if (RegNo > 31)
687  return Fail;
688  unsigned Register = QQQDecoderTable[RegNo];
689  Inst.addOperand(MCOperand::createReg(Register));
690  return Success;
691 }
692 
693 static const unsigned QQQQDecoderTable[] = {
694  AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
695  AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
696  AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
697  AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
698  AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
699  AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
700  AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
701  AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
702  AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
703  AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
704  AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
705 };
706 
707 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
708  uint64_t Addr,
709  const void *Decoder) {
710  if (RegNo > 31)
711  return Fail;
712  unsigned Register = QQQQDecoderTable[RegNo];
713  Inst.addOperand(MCOperand::createReg(Register));
714  return Success;
715 }
716 
717 static const unsigned DDDecoderTable[] = {
718  AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
719  AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
720  AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
721  AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
722  AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
723  AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
724  AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
725  AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
726 };
727 
728 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
729  uint64_t Addr, const void *Decoder) {
730  if (RegNo > 31)
731  return Fail;
732  unsigned Register = DDDecoderTable[RegNo];
733  Inst.addOperand(MCOperand::createReg(Register));
734  return Success;
735 }
736 
737 static const unsigned DDDDecoderTable[] = {
738  AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
739  AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
740  AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
741  AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
742  AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
743  AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
744  AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
745  AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
746  AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
747  AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
748  AArch64::D30_D31_D0, AArch64::D31_D0_D1
749 };
750 
751 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
752  uint64_t Addr, const void *Decoder) {
753  if (RegNo > 31)
754  return Fail;
755  unsigned Register = DDDDecoderTable[RegNo];
756  Inst.addOperand(MCOperand::createReg(Register));
757  return Success;
758 }
759 
760 static const unsigned DDDDDecoderTable[] = {
761  AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
762  AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
763  AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
764  AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
765  AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
766  AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
767  AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
768  AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
769  AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
770  AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
771  AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
772 };
773 
774 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
775  uint64_t Addr,
776  const void *Decoder) {
777  if (RegNo > 31)
778  return Fail;
779  unsigned Register = DDDDDecoderTable[RegNo];
780  Inst.addOperand(MCOperand::createReg(Register));
781  return Success;
782 }
783 
784 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
785  uint64_t Addr,
786  const void *Decoder) {
787  // scale{5} is asserted as 1 in tblgen.
788  Imm |= 0x20;
789  Inst.addOperand(MCOperand::createImm(64 - Imm));
790  return Success;
791 }
792 
793 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
794  uint64_t Addr,
795  const void *Decoder) {
796  Inst.addOperand(MCOperand::createImm(64 - Imm));
797  return Success;
798 }
799 
800 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
801  uint64_t Addr, const void *Decoder) {
802  int64_t ImmVal = Imm;
803  const AArch64Disassembler *Dis =
804  static_cast<const AArch64Disassembler *>(Decoder);
805 
806  // Sign-extend 19-bit immediate.
807  if (ImmVal & (1 << (19 - 1)))
808  ImmVal |= ~((1LL << 19) - 1);
809 
810  if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
811  Inst.getOpcode() != AArch64::LDRXl, 0, 4))
812  Inst.addOperand(MCOperand::createImm(ImmVal));
813  return Success;
814 }
815 
816 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
817  uint64_t Address, const void *Decoder) {
818  Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
819  Inst.addOperand(MCOperand::createImm(Imm & 1));
820  return Success;
821 }
822 
823 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
824  uint64_t Address,
825  const void *Decoder) {
826  Inst.addOperand(MCOperand::createImm(Imm));
827 
828  // Every system register in the encoding space is valid with the syntax
829  // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
830  return Success;
831 }
832 
833 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
834  uint64_t Address,
835  const void *Decoder) {
836  Inst.addOperand(MCOperand::createImm(Imm));
837 
838  return Success;
839 }
840 
841 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
842  uint64_t Address,
843  const void *Decoder) {
844  // This decoder exists to add the dummy Lane operand to the MCInst, which must
845  // be 1 in assembly but has no other real manifestation.
846  unsigned Rd = fieldFromInstruction(Insn, 0, 5);
847  unsigned Rn = fieldFromInstruction(Insn, 5, 5);
848  unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
849 
850  if (IsToVec) {
851  DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
852  DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
853  } else {
854  DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
855  DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
856  }
857 
858  // Add the lane
860 
861  return Success;
862 }
863 
864 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
865  unsigned Add) {
866  Inst.addOperand(MCOperand::createImm(Add - Imm));
867  return Success;
868 }
869 
870 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
871  unsigned Add) {
872  Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
873  return Success;
874 }
875 
876 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
877  uint64_t Addr, const void *Decoder) {
878  return DecodeVecShiftRImm(Inst, Imm, 64);
879 }
880 
881 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
882  uint64_t Addr,
883  const void *Decoder) {
884  return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
885 }
886 
887 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
888  uint64_t Addr, const void *Decoder) {
889  return DecodeVecShiftRImm(Inst, Imm, 32);
890 }
891 
892 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
893  uint64_t Addr,
894  const void *Decoder) {
895  return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
896 }
897 
898 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
899  uint64_t Addr, const void *Decoder) {
900  return DecodeVecShiftRImm(Inst, Imm, 16);
901 }
902 
903 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
904  uint64_t Addr,
905  const void *Decoder) {
906  return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
907 }
908 
909 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
910  uint64_t Addr, const void *Decoder) {
911  return DecodeVecShiftRImm(Inst, Imm, 8);
912 }
913 
914 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
915  uint64_t Addr, const void *Decoder) {
916  return DecodeVecShiftLImm(Inst, Imm, 64);
917 }
918 
919 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
920  uint64_t Addr, const void *Decoder) {
921  return DecodeVecShiftLImm(Inst, Imm, 32);
922 }
923 
924 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
925  uint64_t Addr, const void *Decoder) {
926  return DecodeVecShiftLImm(Inst, Imm, 16);
927 }
928 
929 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
930  uint64_t Addr, const void *Decoder) {
931  return DecodeVecShiftLImm(Inst, Imm, 8);
932 }
933 
935  uint64_t Addr,
936  const void *Decoder) {
937  unsigned Rd = fieldFromInstruction(insn, 0, 5);
938  unsigned Rn = fieldFromInstruction(insn, 5, 5);
939  unsigned Rm = fieldFromInstruction(insn, 16, 5);
940  unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
941  unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
942  unsigned shift = (shiftHi << 6) | shiftLo;
943  switch (Inst.getOpcode()) {
944  default:
945  return Fail;
946  case AArch64::ADDWrs:
947  case AArch64::ADDSWrs:
948  case AArch64::SUBWrs:
949  case AArch64::SUBSWrs:
950  // if shift == '11' then ReservedValue()
951  if (shiftHi == 0x3)
952  return Fail;
954  case AArch64::ANDWrs:
955  case AArch64::ANDSWrs:
956  case AArch64::BICWrs:
957  case AArch64::BICSWrs:
958  case AArch64::ORRWrs:
959  case AArch64::ORNWrs:
960  case AArch64::EORWrs:
961  case AArch64::EONWrs: {
962  // if sf == '0' and imm6<5> == '1' then ReservedValue()
963  if (shiftLo >> 5 == 1)
964  return Fail;
965  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
966  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
967  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
968  break;
969  }
970  case AArch64::ADDXrs:
971  case AArch64::ADDSXrs:
972  case AArch64::SUBXrs:
973  case AArch64::SUBSXrs:
974  // if shift == '11' then ReservedValue()
975  if (shiftHi == 0x3)
976  return Fail;
978  case AArch64::ANDXrs:
979  case AArch64::ANDSXrs:
980  case AArch64::BICXrs:
981  case AArch64::BICSXrs:
982  case AArch64::ORRXrs:
983  case AArch64::ORNXrs:
984  case AArch64::EORXrs:
985  case AArch64::EONXrs:
986  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
987  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
988  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
989  break;
990  }
991 
992  Inst.addOperand(MCOperand::createImm(shift));
993  return Success;
994 }
995 
997  uint64_t Addr,
998  const void *Decoder) {
999  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1000  unsigned imm = fieldFromInstruction(insn, 5, 16);
1001  unsigned shift = fieldFromInstruction(insn, 21, 2);
1002  shift <<= 4;
1003  switch (Inst.getOpcode()) {
1004  default:
1005  return Fail;
1006  case AArch64::MOVZWi:
1007  case AArch64::MOVNWi:
1008  case AArch64::MOVKWi:
1009  if (shift & (1U << 5))
1010  return Fail;
1011  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1012  break;
1013  case AArch64::MOVZXi:
1014  case AArch64::MOVNXi:
1015  case AArch64::MOVKXi:
1016  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1017  break;
1018  }
1019 
1020  if (Inst.getOpcode() == AArch64::MOVKWi ||
1021  Inst.getOpcode() == AArch64::MOVKXi)
1022  Inst.addOperand(Inst.getOperand(0));
1023 
1024  Inst.addOperand(MCOperand::createImm(imm));
1025  Inst.addOperand(MCOperand::createImm(shift));
1026  return Success;
1027 }
1028 
1030  uint64_t Addr,
1031  const void *Decoder) {
1032  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1033  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1034  unsigned offset = fieldFromInstruction(insn, 10, 12);
1035  const AArch64Disassembler *Dis =
1036  static_cast<const AArch64Disassembler *>(Decoder);
1037 
1038  switch (Inst.getOpcode()) {
1039  default:
1040  return Fail;
1041  case AArch64::PRFMui:
1042  // Rt is an immediate in prefetch.
1043  Inst.addOperand(MCOperand::createImm(Rt));
1044  break;
1045  case AArch64::STRBBui:
1046  case AArch64::LDRBBui:
1047  case AArch64::LDRSBWui:
1048  case AArch64::STRHHui:
1049  case AArch64::LDRHHui:
1050  case AArch64::LDRSHWui:
1051  case AArch64::STRWui:
1052  case AArch64::LDRWui:
1053  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1054  break;
1055  case AArch64::LDRSBXui:
1056  case AArch64::LDRSHXui:
1057  case AArch64::LDRSWui:
1058  case AArch64::STRXui:
1059  case AArch64::LDRXui:
1060  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1061  break;
1062  case AArch64::LDRQui:
1063  case AArch64::STRQui:
1064  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1065  break;
1066  case AArch64::LDRDui:
1067  case AArch64::STRDui:
1068  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1069  break;
1070  case AArch64::LDRSui:
1071  case AArch64::STRSui:
1072  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1073  break;
1074  case AArch64::LDRHui:
1075  case AArch64::STRHui:
1076  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1077  break;
1078  case AArch64::LDRBui:
1079  case AArch64::STRBui:
1080  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1081  break;
1082  }
1083 
1084  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1085  if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
1086  Inst.addOperand(MCOperand::createImm(offset));
1087  return Success;
1088 }
1089 
1091  uint64_t Addr,
1092  const void *Decoder) {
1093  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1094  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1095  int64_t offset = fieldFromInstruction(insn, 12, 9);
1096 
1097  // offset is a 9-bit signed immediate, so sign extend it to
1098  // fill the unsigned.
1099  if (offset & (1 << (9 - 1)))
1100  offset |= ~((1LL << 9) - 1);
1101 
1102  // First operand is always the writeback to the address register, if needed.
1103  switch (Inst.getOpcode()) {
1104  default:
1105  break;
1106  case AArch64::LDRSBWpre:
1107  case AArch64::LDRSHWpre:
1108  case AArch64::STRBBpre:
1109  case AArch64::LDRBBpre:
1110  case AArch64::STRHHpre:
1111  case AArch64::LDRHHpre:
1112  case AArch64::STRWpre:
1113  case AArch64::LDRWpre:
1114  case AArch64::LDRSBWpost:
1115  case AArch64::LDRSHWpost:
1116  case AArch64::STRBBpost:
1117  case AArch64::LDRBBpost:
1118  case AArch64::STRHHpost:
1119  case AArch64::LDRHHpost:
1120  case AArch64::STRWpost:
1121  case AArch64::LDRWpost:
1122  case AArch64::LDRSBXpre:
1123  case AArch64::LDRSHXpre:
1124  case AArch64::STRXpre:
1125  case AArch64::LDRSWpre:
1126  case AArch64::LDRXpre:
1127  case AArch64::LDRSBXpost:
1128  case AArch64::LDRSHXpost:
1129  case AArch64::STRXpost:
1130  case AArch64::LDRSWpost:
1131  case AArch64::LDRXpost:
1132  case AArch64::LDRQpre:
1133  case AArch64::STRQpre:
1134  case AArch64::LDRQpost:
1135  case AArch64::STRQpost:
1136  case AArch64::LDRDpre:
1137  case AArch64::STRDpre:
1138  case AArch64::LDRDpost:
1139  case AArch64::STRDpost:
1140  case AArch64::LDRSpre:
1141  case AArch64::STRSpre:
1142  case AArch64::LDRSpost:
1143  case AArch64::STRSpost:
1144  case AArch64::LDRHpre:
1145  case AArch64::STRHpre:
1146  case AArch64::LDRHpost:
1147  case AArch64::STRHpost:
1148  case AArch64::LDRBpre:
1149  case AArch64::STRBpre:
1150  case AArch64::LDRBpost:
1151  case AArch64::STRBpost:
1152  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1153  break;
1154  }
1155 
1156  switch (Inst.getOpcode()) {
1157  default:
1158  return Fail;
1159  case AArch64::PRFUMi:
1160  // Rt is an immediate in prefetch.
1161  Inst.addOperand(MCOperand::createImm(Rt));
1162  break;
1163  case AArch64::STURBBi:
1164  case AArch64::LDURBBi:
1165  case AArch64::LDURSBWi:
1166  case AArch64::STURHHi:
1167  case AArch64::LDURHHi:
1168  case AArch64::LDURSHWi:
1169  case AArch64::STURWi:
1170  case AArch64::LDURWi:
1171  case AArch64::LDTRSBWi:
1172  case AArch64::LDTRSHWi:
1173  case AArch64::STTRWi:
1174  case AArch64::LDTRWi:
1175  case AArch64::STTRHi:
1176  case AArch64::LDTRHi:
1177  case AArch64::LDTRBi:
1178  case AArch64::STTRBi:
1179  case AArch64::LDRSBWpre:
1180  case AArch64::LDRSHWpre:
1181  case AArch64::STRBBpre:
1182  case AArch64::LDRBBpre:
1183  case AArch64::STRHHpre:
1184  case AArch64::LDRHHpre:
1185  case AArch64::STRWpre:
1186  case AArch64::LDRWpre:
1187  case AArch64::LDRSBWpost:
1188  case AArch64::LDRSHWpost:
1189  case AArch64::STRBBpost:
1190  case AArch64::LDRBBpost:
1191  case AArch64::STRHHpost:
1192  case AArch64::LDRHHpost:
1193  case AArch64::STRWpost:
1194  case AArch64::LDRWpost:
1195  case AArch64::STLURBi:
1196  case AArch64::STLURHi:
1197  case AArch64::STLURWi:
1198  case AArch64::LDAPURBi:
1199  case AArch64::LDAPURSBWi:
1200  case AArch64::LDAPURHi:
1201  case AArch64::LDAPURSHWi:
1202  case AArch64::LDAPURi:
1203  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1204  break;
1205  case AArch64::LDURSBXi:
1206  case AArch64::LDURSHXi:
1207  case AArch64::LDURSWi:
1208  case AArch64::STURXi:
1209  case AArch64::LDURXi:
1210  case AArch64::LDTRSBXi:
1211  case AArch64::LDTRSHXi:
1212  case AArch64::LDTRSWi:
1213  case AArch64::STTRXi:
1214  case AArch64::LDTRXi:
1215  case AArch64::LDRSBXpre:
1216  case AArch64::LDRSHXpre:
1217  case AArch64::STRXpre:
1218  case AArch64::LDRSWpre:
1219  case AArch64::LDRXpre:
1220  case AArch64::LDRSBXpost:
1221  case AArch64::LDRSHXpost:
1222  case AArch64::STRXpost:
1223  case AArch64::LDRSWpost:
1224  case AArch64::LDRXpost:
1225  case AArch64::LDAPURSWi:
1226  case AArch64::LDAPURSHXi:
1227  case AArch64::LDAPURSBXi:
1228  case AArch64::STLURXi:
1229  case AArch64::LDAPURXi:
1230  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1231  break;
1232  case AArch64::LDURQi:
1233  case AArch64::STURQi:
1234  case AArch64::LDRQpre:
1235  case AArch64::STRQpre:
1236  case AArch64::LDRQpost:
1237  case AArch64::STRQpost:
1238  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1239  break;
1240  case AArch64::LDURDi:
1241  case AArch64::STURDi:
1242  case AArch64::LDRDpre:
1243  case AArch64::STRDpre:
1244  case AArch64::LDRDpost:
1245  case AArch64::STRDpost:
1246  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1247  break;
1248  case AArch64::LDURSi:
1249  case AArch64::STURSi:
1250  case AArch64::LDRSpre:
1251  case AArch64::STRSpre:
1252  case AArch64::LDRSpost:
1253  case AArch64::STRSpost:
1254  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1255  break;
1256  case AArch64::LDURHi:
1257  case AArch64::STURHi:
1258  case AArch64::LDRHpre:
1259  case AArch64::STRHpre:
1260  case AArch64::LDRHpost:
1261  case AArch64::STRHpost:
1262  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1263  break;
1264  case AArch64::LDURBi:
1265  case AArch64::STURBi:
1266  case AArch64::LDRBpre:
1267  case AArch64::STRBpre:
1268  case AArch64::LDRBpost:
1269  case AArch64::STRBpost:
1270  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1271  break;
1272  }
1273 
1274  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1275  Inst.addOperand(MCOperand::createImm(offset));
1276 
1277  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1278  bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1279  bool IsFP = fieldFromInstruction(insn, 26, 1);
1280 
1281  // Cannot write back to a transfer register (but xzr != sp).
1282  if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1283  return SoftFail;
1284 
1285  return Success;
1286 }
1287 
1289  uint64_t Addr,
1290  const void *Decoder) {
1291  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1292  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1293  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1294  unsigned Rs = fieldFromInstruction(insn, 16, 5);
1295 
1296  unsigned Opcode = Inst.getOpcode();
1297  switch (Opcode) {
1298  default:
1299  return Fail;
1300  case AArch64::STLXRW:
1301  case AArch64::STLXRB:
1302  case AArch64::STLXRH:
1303  case AArch64::STXRW:
1304  case AArch64::STXRB:
1305  case AArch64::STXRH:
1306  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1308  case AArch64::LDARW:
1309  case AArch64::LDARB:
1310  case AArch64::LDARH:
1311  case AArch64::LDAXRW:
1312  case AArch64::LDAXRB:
1313  case AArch64::LDAXRH:
1314  case AArch64::LDXRW:
1315  case AArch64::LDXRB:
1316  case AArch64::LDXRH:
1317  case AArch64::STLRW:
1318  case AArch64::STLRB:
1319  case AArch64::STLRH:
1320  case AArch64::STLLRW:
1321  case AArch64::STLLRB:
1322  case AArch64::STLLRH:
1323  case AArch64::LDLARW:
1324  case AArch64::LDLARB:
1325  case AArch64::LDLARH:
1326  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1327  break;
1328  case AArch64::STLXRX:
1329  case AArch64::STXRX:
1330  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1332  case AArch64::LDARX:
1333  case AArch64::LDAXRX:
1334  case AArch64::LDXRX:
1335  case AArch64::STLRX:
1336  case AArch64::LDLARX:
1337  case AArch64::STLLRX:
1338  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1339  break;
1340  case AArch64::STLXPW:
1341  case AArch64::STXPW:
1342  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1344  case AArch64::LDAXPW:
1345  case AArch64::LDXPW:
1346  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1347  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1348  break;
1349  case AArch64::STLXPX:
1350  case AArch64::STXPX:
1351  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1353  case AArch64::LDAXPX:
1354  case AArch64::LDXPX:
1355  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1356  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1357  break;
1358  }
1359 
1360  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1361 
1362  // You shouldn't load to the same register twice in an instruction...
1363  if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1364  Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1365  Rt == Rt2)
1366  return SoftFail;
1367 
1368  return Success;
1369 }
1370 
1372  uint64_t Addr,
1373  const void *Decoder) {
1374  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1375  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1376  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1377  int64_t offset = fieldFromInstruction(insn, 15, 7);
1378  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1379 
1380  // offset is a 7-bit signed immediate, so sign extend it to
1381  // fill the unsigned.
1382  if (offset & (1 << (7 - 1)))
1383  offset |= ~((1LL << 7) - 1);
1384 
1385  unsigned Opcode = Inst.getOpcode();
1386  bool NeedsDisjointWritebackTransfer = false;
1387 
1388  // First operand is always writeback of base register.
1389  switch (Opcode) {
1390  default:
1391  break;
1392  case AArch64::LDPXpost:
1393  case AArch64::STPXpost:
1394  case AArch64::LDPSWpost:
1395  case AArch64::LDPXpre:
1396  case AArch64::STPXpre:
1397  case AArch64::LDPSWpre:
1398  case AArch64::LDPWpost:
1399  case AArch64::STPWpost:
1400  case AArch64::LDPWpre:
1401  case AArch64::STPWpre:
1402  case AArch64::LDPQpost:
1403  case AArch64::STPQpost:
1404  case AArch64::LDPQpre:
1405  case AArch64::STPQpre:
1406  case AArch64::LDPDpost:
1407  case AArch64::STPDpost:
1408  case AArch64::LDPDpre:
1409  case AArch64::STPDpre:
1410  case AArch64::LDPSpost:
1411  case AArch64::STPSpost:
1412  case AArch64::LDPSpre:
1413  case AArch64::STPSpre:
1414  case AArch64::STGPpre:
1415  case AArch64::STGPpost:
1416  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1417  break;
1418  }
1419 
1420  switch (Opcode) {
1421  default:
1422  return Fail;
1423  case AArch64::LDPXpost:
1424  case AArch64::STPXpost:
1425  case AArch64::LDPSWpost:
1426  case AArch64::LDPXpre:
1427  case AArch64::STPXpre:
1428  case AArch64::LDPSWpre:
1429  case AArch64::STGPpre:
1430  case AArch64::STGPpost:
1431  NeedsDisjointWritebackTransfer = true;
1433  case AArch64::LDNPXi:
1434  case AArch64::STNPXi:
1435  case AArch64::LDPXi:
1436  case AArch64::STPXi:
1437  case AArch64::LDPSWi:
1438  case AArch64::STGPi:
1439  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1440  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1441  break;
1442  case AArch64::LDPWpost:
1443  case AArch64::STPWpost:
1444  case AArch64::LDPWpre:
1445  case AArch64::STPWpre:
1446  NeedsDisjointWritebackTransfer = true;
1448  case AArch64::LDNPWi:
1449  case AArch64::STNPWi:
1450  case AArch64::LDPWi:
1451  case AArch64::STPWi:
1452  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1453  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1454  break;
1455  case AArch64::LDNPQi:
1456  case AArch64::STNPQi:
1457  case AArch64::LDPQpost:
1458  case AArch64::STPQpost:
1459  case AArch64::LDPQi:
1460  case AArch64::STPQi:
1461  case AArch64::LDPQpre:
1462  case AArch64::STPQpre:
1463  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1464  DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1465  break;
1466  case AArch64::LDNPDi:
1467  case AArch64::STNPDi:
1468  case AArch64::LDPDpost:
1469  case AArch64::STPDpost:
1470  case AArch64::LDPDi:
1471  case AArch64::STPDi:
1472  case AArch64::LDPDpre:
1473  case AArch64::STPDpre:
1474  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1475  DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1476  break;
1477  case AArch64::LDNPSi:
1478  case AArch64::STNPSi:
1479  case AArch64::LDPSpost:
1480  case AArch64::STPSpost:
1481  case AArch64::LDPSi:
1482  case AArch64::STPSi:
1483  case AArch64::LDPSpre:
1484  case AArch64::STPSpre:
1485  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1486  DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1487  break;
1488  }
1489 
1490  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1491  Inst.addOperand(MCOperand::createImm(offset));
1492 
1493  // You shouldn't load to the same register twice in an instruction...
1494  if (IsLoad && Rt == Rt2)
1495  return SoftFail;
1496 
1497  // ... or do any operation that writes-back to a transfer register. But note
1498  // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1499  if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1500  return SoftFail;
1501 
1502  return Success;
1503 }
1504 
1506  uint64_t Addr,
1507  const void *Decoder) {
1508  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1509  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1510  unsigned Rm = fieldFromInstruction(insn, 16, 5);
1511  unsigned extend = fieldFromInstruction(insn, 10, 6);
1512 
1513  unsigned shift = extend & 0x7;
1514  if (shift > 4)
1515  return Fail;
1516 
1517  switch (Inst.getOpcode()) {
1518  default:
1519  return Fail;
1520  case AArch64::ADDWrx:
1521  case AArch64::SUBWrx:
1522  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1523  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1524  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1525  break;
1526  case AArch64::ADDSWrx:
1527  case AArch64::SUBSWrx:
1528  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1529  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1530  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1531  break;
1532  case AArch64::ADDXrx:
1533  case AArch64::SUBXrx:
1534  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1535  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1536  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1537  break;
1538  case AArch64::ADDSXrx:
1539  case AArch64::SUBSXrx:
1540  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1541  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1542  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1543  break;
1544  case AArch64::ADDXrx64:
1545  case AArch64::SUBXrx64:
1546  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1547  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1548  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1549  break;
1550  case AArch64::SUBSXrx64:
1551  case AArch64::ADDSXrx64:
1552  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1553  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1554  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1555  break;
1556  }
1557 
1558  Inst.addOperand(MCOperand::createImm(extend));
1559  return Success;
1560 }
1561 
1563  uint64_t Addr,
1564  const void *Decoder) {
1565  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1566  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1567  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1568  unsigned imm;
1569 
1570  if (Datasize) {
1571  if (Inst.getOpcode() == AArch64::ANDSXri)
1572  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1573  else
1574  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1575  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1576  imm = fieldFromInstruction(insn, 10, 13);
1578  return Fail;
1579  } else {
1580  if (Inst.getOpcode() == AArch64::ANDSWri)
1581  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1582  else
1583  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1584  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1585  imm = fieldFromInstruction(insn, 10, 12);
1587  return Fail;
1588  }
1589  Inst.addOperand(MCOperand::createImm(imm));
1590  return Success;
1591 }
1592 
1594  uint64_t Addr,
1595  const void *Decoder) {
1596  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1597  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1598  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1599  imm |= fieldFromInstruction(insn, 5, 5);
1600 
1601  if (Inst.getOpcode() == AArch64::MOVID)
1602  DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1603  else
1604  DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1605 
1606  Inst.addOperand(MCOperand::createImm(imm));
1607 
1608  switch (Inst.getOpcode()) {
1609  default:
1610  break;
1611  case AArch64::MOVIv4i16:
1612  case AArch64::MOVIv8i16:
1613  case AArch64::MVNIv4i16:
1614  case AArch64::MVNIv8i16:
1615  case AArch64::MOVIv2i32:
1616  case AArch64::MOVIv4i32:
1617  case AArch64::MVNIv2i32:
1618  case AArch64::MVNIv4i32:
1619  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1620  break;
1621  case AArch64::MOVIv2s_msl:
1622  case AArch64::MOVIv4s_msl:
1623  case AArch64::MVNIv2s_msl:
1624  case AArch64::MVNIv4s_msl:
1625  Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1626  break;
1627  }
1628 
1629  return Success;
1630 }
1631 
1633  uint64_t Addr,
1634  const void *Decoder) {
1635  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1636  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1637  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1638  imm |= fieldFromInstruction(insn, 5, 5);
1639 
1640  // Tied operands added twice.
1641  DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1642  DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1643 
1644  Inst.addOperand(MCOperand::createImm(imm));
1645  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1646 
1647  return Success;
1648 }
1649 
1651  uint64_t Addr, const void *Decoder) {
1652  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1653  int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1654  imm |= fieldFromInstruction(insn, 29, 2);
1655  const AArch64Disassembler *Dis =
1656  static_cast<const AArch64Disassembler *>(Decoder);
1657 
1658  // Sign-extend the 21-bit immediate.
1659  if (imm & (1 << (21 - 1)))
1660  imm |= ~((1LL << 21) - 1);
1661 
1662  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1663  if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1664  Inst.addOperand(MCOperand::createImm(imm));
1665 
1666  return Success;
1667 }
1668 
1670  uint64_t Addr, const void *Decoder) {
1671  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1672  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1673  unsigned Imm = fieldFromInstruction(insn, 10, 14);
1674  unsigned S = fieldFromInstruction(insn, 29, 1);
1675  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1676 
1677  unsigned ShifterVal = (Imm >> 12) & 3;
1678  unsigned ImmVal = Imm & 0xFFF;
1679  const AArch64Disassembler *Dis =
1680  static_cast<const AArch64Disassembler *>(Decoder);
1681 
1682  if (ShifterVal != 0 && ShifterVal != 1)
1683  return Fail;
1684 
1685  if (Datasize) {
1686  if (Rd == 31 && !S)
1687  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1688  else
1689  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1690  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1691  } else {
1692  if (Rd == 31 && !S)
1693  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1694  else
1695  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1696  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1697  }
1698 
1699  if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1700  Inst.addOperand(MCOperand::createImm(ImmVal));
1701  Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1702  return Success;
1703 }
1704 
1706  uint64_t Addr,
1707  const void *Decoder) {
1708  int64_t imm = fieldFromInstruction(insn, 0, 26);
1709  const AArch64Disassembler *Dis =
1710  static_cast<const AArch64Disassembler *>(Decoder);
1711 
1712  // Sign-extend the 26-bit immediate.
1713  if (imm & (1 << (26 - 1)))
1714  imm |= ~((1LL << 26) - 1);
1715 
1716  if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1717  Inst.addOperand(MCOperand::createImm(imm));
1718 
1719  return Success;
1720 }
1721 
1723  uint64_t Addr,
1724  const void *Decoder) {
1725  uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1726  uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1727  uint64_t crm = fieldFromInstruction(insn, 8, 4);
1728  uint64_t pstate_field = (op1 << 3) | op2;
1729 
1730  switch (pstate_field) {
1731  case 0x01: // XAFlag
1732  case 0x02: // AXFlag
1733  return Fail;
1734  }
1735 
1736  if ((pstate_field == AArch64PState::PAN ||
1737  pstate_field == AArch64PState::UAO ||
1738  pstate_field == AArch64PState::SSBS) && crm > 1)
1739  return Fail;
1740 
1741  Inst.addOperand(MCOperand::createImm(pstate_field));
1742  Inst.addOperand(MCOperand::createImm(crm));
1743 
1744  const AArch64Disassembler *Dis =
1745  static_cast<const AArch64Disassembler *>(Decoder);
1746  auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1747  if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1748  return Success;
1749  return Fail;
1750 }
1751 
1753  uint64_t Addr, const void *Decoder) {
1754  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1755  uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1756  bit |= fieldFromInstruction(insn, 19, 5);
1757  int64_t dst = fieldFromInstruction(insn, 5, 14);
1758  const AArch64Disassembler *Dis =
1759  static_cast<const AArch64Disassembler *>(Decoder);
1760 
1761  // Sign-extend 14-bit immediate.
1762  if (dst & (1 << (14 - 1)))
1763  dst |= ~((1LL << 14) - 1);
1764 
1765  if (fieldFromInstruction(insn, 31, 1) == 0)
1766  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1767  else
1768  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1769  Inst.addOperand(MCOperand::createImm(bit));
1770  if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1771  Inst.addOperand(MCOperand::createImm(dst));
1772 
1773  return Success;
1774 }
1775 
1777  unsigned RegClassID,
1778  unsigned RegNo,
1779  uint64_t Addr,
1780  const void *Decoder) {
1781  // Register number must be even (see CASP instruction)
1782  if (RegNo & 0x1)
1783  return Fail;
1784 
1785  unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1786  Inst.addOperand(MCOperand::createReg(Reg));
1787  return Success;
1788 }
1789 
1791  unsigned RegNo,
1792  uint64_t Addr,
1793  const void *Decoder) {
1795  AArch64::WSeqPairsClassRegClassID,
1796  RegNo, Addr, Decoder);
1797 }
1798 
1800  unsigned RegNo,
1801  uint64_t Addr,
1802  const void *Decoder) {
1804  AArch64::XSeqPairsClassRegClassID,
1805  RegNo, Addr, Decoder);
1806 }
1807 
1809  uint32_t insn,
1810  uint64_t Addr,
1811  const void *Decoder) {
1812  unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1813  unsigned imm = fieldFromInstruction(insn, 5, 13);
1815  return Fail;
1816 
1817  // The same (tied) operand is added twice to the instruction.
1818  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1819  if (Inst.getOpcode() != AArch64::DUPM_ZI)
1820  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1821  Inst.addOperand(MCOperand::createImm(imm));
1822  return Success;
1823 }
1824 
1825 template<int Bits>
1826 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1827  uint64_t Address, const void *Decoder) {
1828  if (Imm & ~((1LL << Bits) - 1))
1829  return Fail;
1830 
1831  // Imm is a signed immediate, so sign extend it.
1832  if (Imm & (1 << (Bits - 1)))
1833  Imm |= ~((1LL << Bits) - 1);
1834 
1835  Inst.addOperand(MCOperand::createImm(Imm));
1836  return Success;
1837 }
1838 
1839 // Decode 8-bit signed/unsigned immediate for a given element width.
1840 template <int ElementWidth>
1841 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1842  uint64_t Addr, const void *Decoder) {
1843  unsigned Val = (uint8_t)Imm;
1844  unsigned Shift = (Imm & 0x100) ? 8 : 0;
1845  if (ElementWidth == 8 && Shift)
1846  return Fail;
1847  Inst.addOperand(MCOperand::createImm(Val));
1848  Inst.addOperand(MCOperand::createImm(Shift));
1849  return Success;
1850 }
1851 
1852 // Decode uimm4 ranged from 1-16.
1853 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1854  uint64_t Addr, const void *Decoder) {
1855  Inst.addOperand(MCOperand::createImm(Imm + 1));
1856  return Success;
1857 }
static const unsigned FPR32DecoderTable[]
static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static bool Check(DecodeStatus &Out, DecodeStatus In)
static const unsigned ZZZDecoderTable[]
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheAArch64beTarget()
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheARM64_32Target()
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheAArch64leTarget()
Superclass for all disassemblers.
raw_ostream * CommentStream
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
unsigned Reg
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static const unsigned QQQDecoderTable[]
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static const unsigned VectorDecoderTable[]
static const unsigned GPR64DecoderTable[]
static const unsigned ZZDecoderTable[]
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
const FeatureBitset & getFeatureBits() const
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
Target & getTheARM64Target()
static const unsigned FPR128DecoderTable[]
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Context object for machine code objects.
Definition: MCContext.h:65
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
const MCSubtargetInfo & STI
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder)
void LLVMInitializeAArch64Disassembler()
static const unsigned FPR8DecoderTable[]
static const unsigned PPRDecoderTable[]
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static const unsigned QQQQDecoderTable[]
static const unsigned FPR16DecoderTable[]
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:38
Target & getTheAArch64_32Target()
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static const unsigned GPR32DecoderTable[]
static const unsigned FPR64DecoderTable[]
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
static const unsigned ZPRDecoderTable[]
static const unsigned DDDDecoderTable[]
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static const unsigned DDDDDecoderTable[]
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
static const unsigned QQDecoderTable[]
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target - Wrapper for Target specific information.
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static const unsigned DDDecoderTable[]
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
static const unsigned ZZZZDecoderTable[]
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
const MCSubtargetInfo & getSubtargetInfo() const
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
unsigned getOpcode() const
Definition: MCInst.h:171
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)