LLVM  14.0.0git
AArch64Disassembler.cpp
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1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64Disassembler.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm-c/Disassembler.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/TargetRegistry.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/Support/Debug.h"
28 #include <algorithm>
29 #include <memory>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "aarch64-disassembler"
34 
35 // Pull DecodeStatus and its enum values into the global namespace.
37 
38 // Forward declare these because the autogenerated code will reference them.
39 // Definitions are further down.
41  unsigned RegNo, uint64_t Address,
42  const void *Decoder);
44  unsigned RegNo,
45  uint64_t Address,
46  const void *Decoder);
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
48  uint64_t Address,
49  const void *Decoder);
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
51  uint64_t Address,
52  const void *Decoder);
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
54  uint64_t Address,
55  const void *Decoder);
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
57  uint64_t Address,
58  const void *Decoder);
59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
60  uint64_t Address,
61  const void *Decoder);
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
63  uint64_t Address,
64  const void *Decoder);
66  unsigned RegNo,
67  uint64_t Address,
68  const void *Decoder);
70  unsigned RegNo, uint64_t Address,
71  const void *Decoder);
73  unsigned RegNo,
74  uint64_t Address,
75  const void *Decoder);
76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
77  uint64_t Address,
78  const void *Decoder);
80  unsigned RegNo, uint64_t Address,
81  const void *Decoder);
82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
83  uint64_t Address,
84  const void *Decoder);
85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
86  uint64_t Address,
87  const void *Decoder);
88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
89  uint64_t Address,
90  const void *Decoder);
91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
92  uint64_t Address,
93  const void *Decoder);
94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
95  uint64_t Address,
96  const void *Decoder);
97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
98  uint64_t Address,
99  const void *Decoder);
100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
101  uint64_t Address,
102  const void *Decoder);
103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
104  uint64_t Address,
105  const void *Decoder);
106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
107  uint64_t Address,
108  const void *Decoder);
109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
110  uint64_t Address,
111  const void *Decoder);
112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
113  uint64_t Address,
114  const void *Decoder);
115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
116  uint64_t Address,
117  const void *Decoder);
118 template <unsigned NumBitsForTile>
119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
120  uint64_t Address, const void *Decoder);
122  unsigned RegMask,
123  uint64_t Address,
124  const void *Decoder);
125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
126  uint64_t Address,
127  const void *Decoder);
128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
129  uint64_t Address,
130  const void *Decoder);
131 
132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
133  uint64_t Address,
134  const void *Decoder);
135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
136  uint64_t Address,
137  const void *Decoder);
138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
139  uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
141  uint64_t Address, const void *Decoder);
142 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
143  uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
145  uint64_t Address, const void *Decoder);
147  uint64_t Address,
148  const void *Decoder);
150  uint64_t Address,
151  const void *Decoder);
153  uint64_t Address,
154  const void *Decoder);
156  uint64_t Address,
157  const void *Decoder);
159  uint64_t Address,
160  const void *Decoder);
162  uint64_t Address,
163  const void *Decoder);
165  uint64_t Address,
166  const void *Decoder);
168  uint64_t Address,
169  const void *Decoder);
171  uint64_t Address,
172  const void *Decoder);
174  uint64_t Address,
175  const void *Decoder);
177  uint64_t Address,
178  const void *Decoder);
180  uint64_t Address, const void *Decoder);
182  uint64_t Address, const void *Decoder);
184  uint64_t Address,
185  const void *Decoder);
187  uint64_t Address,
188  const void *Decoder);
190  uint64_t Address, const void *Decoder);
191 
192 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
193  uint64_t Address,
194  const void *Decoder);
195 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
196  uint64_t Addr, const void *Decoder);
197 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
198  uint64_t Addr,
199  const void *Decoder);
200 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
201  uint64_t Addr, const void *Decoder);
202 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
203  uint64_t Addr,
204  const void *Decoder);
205 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
206  uint64_t Addr, const void *Decoder);
207 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
208  uint64_t Addr,
209  const void *Decoder);
210 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
211  uint64_t Addr, const void *Decoder);
212 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
213  uint64_t Addr, const void *Decoder);
214 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
215  uint64_t Addr, const void *Decoder);
216 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
217  uint64_t Addr, const void *Decoder);
218 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
219  uint64_t Addr, const void *Decoder);
221  unsigned RegNo,
222  uint64_t Addr,
223  const void *Decoder);
225  unsigned RegNo,
226  uint64_t Addr,
227  const void *Decoder);
229  uint64_t Address,
230  const void *Decoder);
231 template <int Bits>
232 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
233  const void *Decoder);
234 template <int ElementWidth>
235 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
236  uint64_t Addr, const void *Decoder);
237 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
238  uint64_t Addr, const void *Decoder);
239 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
240  const void *Decoder);
242  uint64_t Addr,
243  const void *Decoder);
245  uint64_t Addr,
246  const void *Decoder);
247 
248 static bool Check(DecodeStatus &Out, DecodeStatus In) {
249  switch (In) {
251  // Out stays the same.
252  return true;
254  Out = In;
255  return true;
257  Out = In;
258  return false;
259  }
260  llvm_unreachable("Invalid DecodeStatus!");
261 }
262 
263 #include "AArch64GenDisassemblerTables.inc"
264 #include "AArch64GenInstrInfo.inc"
265 
266 #define Success MCDisassembler::Success
267 #define Fail MCDisassembler::Fail
268 #define SoftFail MCDisassembler::SoftFail
269 
271  const MCSubtargetInfo &STI,
272  MCContext &Ctx) {
273  return new AArch64Disassembler(STI, Ctx);
274 }
275 
277  ArrayRef<uint8_t> Bytes,
278  uint64_t Address,
279  raw_ostream &CS) const {
280  CommentStream = &CS;
281 
282  Size = 0;
283  // We want to read exactly 4 bytes of data.
284  if (Bytes.size() < 4)
285  return Fail;
286  Size = 4;
287 
288  // Encoded as a small-endian 32-bit word in the stream.
289  uint32_t Insn =
290  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
291 
292  const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
293 
294  for (auto Table : Tables) {
295  DecodeStatus Result =
296  decodeInstruction(Table, MI, Insn, Address, this, STI);
297 
298  switch (MI.getOpcode()) {
299  default:
300  break;
301  // For Scalable Matrix Extension (SME) instructions that have an implicit
302  // operand for the accumulator (ZA) which isn't encoded, manually insert
303  // operand.
304  case AArch64::LDR_ZA:
305  case AArch64::STR_ZA: {
306  MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA));
307  // Spill and fill instructions have a single immediate used for both the
308  // vector select offset and optional memory offset. Replicate the decoded
309  // immediate.
310  const MCOperand &Imm4Op = MI.getOperand(2);
311  assert(Imm4Op.isImm() && "Unexpected operand type!");
312  MI.addOperand(Imm4Op);
313  break;
314  }
315  case AArch64::LD1_MXIPXX_H_B:
316  case AArch64::LD1_MXIPXX_V_B:
317  case AArch64::ST1_MXIPXX_H_B:
318  case AArch64::ST1_MXIPXX_V_B:
319  case AArch64::INSERT_MXIPZ_H_B:
320  case AArch64::INSERT_MXIPZ_V_B:
321  // e.g.
322  // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B
323  // ^ insert implicit 8-bit element tile
324  MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0));
325  break;
326  case AArch64::EXTRACT_ZPMXI_H_B:
327  case AArch64::EXTRACT_ZPMXI_V_B:
328  // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>]
329  // ^ insert implicit 8-bit element tile
330  MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0));
331  break;
332  case AArch64::LD1_MXIPXX_H_Q:
333  case AArch64::LD1_MXIPXX_V_Q:
334  case AArch64::ST1_MXIPXX_H_Q:
335  case AArch64::ST1_MXIPXX_V_Q:
336  // 128-bit load/store have implicit zero vector index.
337  MI.insert(MI.begin()+2, MCOperand::createImm(0));
338  break;
339  // 128-bit mova have implicit zero vector index.
340  case AArch64::INSERT_MXIPZ_H_Q:
341  case AArch64::INSERT_MXIPZ_V_Q:
342  MI.insert(MI.begin()+2, MCOperand::createImm(0));
343  break;
344  case AArch64::EXTRACT_ZPMXI_H_Q:
345  case AArch64::EXTRACT_ZPMXI_V_Q:
346  MI.addOperand(MCOperand::createImm(0));
347  break;
348  case AArch64::SMOVvi8to32_idx0:
349  case AArch64::SMOVvi8to64_idx0:
350  case AArch64::SMOVvi16to32_idx0:
351  case AArch64::SMOVvi16to64_idx0:
352  case AArch64::SMOVvi32to64_idx0:
353  case AArch64::UMOVvi8_idx0:
354  case AArch64::UMOVvi16_idx0:
355  case AArch64::UMOVvi32_idx0:
356  case AArch64::UMOVvi64_idx0:
357  MI.addOperand(MCOperand::createImm(0));
358  break;
359  }
360 
361  if (Result != MCDisassembler::Fail)
362  return Result;
363  }
364 
365  return MCDisassembler::Fail;
366 }
367 
368 static MCSymbolizer *
370  LLVMSymbolLookupCallback SymbolLookUp,
371  void *DisInfo, MCContext *Ctx,
372  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
373  return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
374  SymbolLookUp, DisInfo);
375 }
376 
390 
399 }
400 
401 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
402  uint64_t Addr,
403  const void *Decoder) {
404  if (RegNo > 31)
405  return Fail;
406 
407  unsigned Register =
408  AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
410  return Success;
411 }
412 
413 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
414  uint64_t Addr,
415  const void *Decoder) {
416  if (RegNo > 15)
417  return Fail;
418  return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
419 }
420 
421 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
422  uint64_t Addr,
423  const void *Decoder) {
424  if (RegNo > 31)
425  return Fail;
426 
427  unsigned Register =
428  AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
430  return Success;
431 }
432 
433 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
434  uint64_t Addr,
435  const void *Decoder) {
436  if (RegNo > 31)
437  return Fail;
438 
439  unsigned Register =
440  AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
442  return Success;
443 }
444 
445 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
446  uint64_t Addr,
447  const void *Decoder) {
448  if (RegNo > 31)
449  return Fail;
450 
451  unsigned Register =
452  AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
454  return Success;
455 }
456 
457 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
458  uint64_t Addr,
459  const void *Decoder) {
460  if (RegNo > 31)
461  return Fail;
462 
463  unsigned Register =
464  AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
466  return Success;
467 }
468 
470  uint64_t Addr,
471  const void *Decoder) {
472  if (RegNo > 30)
473  return Fail;
474 
475  unsigned Register =
476  AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
477  RegNo);
479  return Success;
480 }
481 
482 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
483  uint64_t Addr,
484  const void *Decoder) {
485  if (RegNo > 31)
486  return Fail;
487 
488  unsigned Register =
489  AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
491  return Success;
492 }
493 
495  unsigned RegNo,
496  uint64_t Address,
497  const void *Decoder) {
498  if (RegNo > 22)
499  return Fail;
500  if (RegNo & 1)
501  return Fail;
502 
503  unsigned Register =
504  AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
505  RegNo >> 1);
507  return Success;
508 }
509 
510 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
511  uint64_t Addr,
512  const void *Decoder) {
513  if (RegNo > 31)
514  return Fail;
515  unsigned Register =
516  AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
518  return Success;
519 }
520 
522  unsigned RegNo,
523  uint64_t Addr,
524  const void *Decoder) {
525  if (RegNo > 3)
526  return Fail;
527 
528  unsigned Register =
529  AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
530  .getRegister(RegNo);
532  return Success;
533 }
534 
535 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
536  uint64_t Addr,
537  const void *Decoder) {
538  if (RegNo > 31)
539  return Fail;
540 
541  unsigned Register =
542  AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
544  return Success;
545 }
546 
547 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
548  uint64_t Addr,
549  const void *Decoder) {
550  if (RegNo > 31)
551  return Fail;
552 
553  unsigned Register =
554  AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
556  return Success;
557 }
558 
559 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
560  uint64_t Address,
561  const void* Decoder) {
562  if (RegNo > 31)
563  return Fail;
564 
565  unsigned Register =
566  AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
568  return Success;
569 }
570 
571 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
572  uint64_t Address,
573  const void *Decoder) {
574  if (RegNo > 15)
575  return Fail;
576  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
577 }
578 
579 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
580  uint64_t Address,
581  const void *Decoder) {
582  if (RegNo > 7)
583  return Fail;
584  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
585 }
586 
587 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
588  uint64_t Address,
589  const void* Decoder) {
590  if (RegNo > 31)
591  return Fail;
592  unsigned Register =
593  AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
595  return Success;
596 }
597 
598 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
599  uint64_t Address,
600  const void* Decoder) {
601  if (RegNo > 31)
602  return Fail;
603  unsigned Register =
604  AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
606  return Success;
607 }
608 
609 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
610  uint64_t Address,
611  const void* Decoder) {
612  if (RegNo > 31)
613  return Fail;
614  unsigned Register =
615  AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
617  return Success;
618 }
619 
621  unsigned RegMask,
622  uint64_t Address,
623  const void *Decoder) {
624  if (RegMask > 0xFF)
625  return Fail;
626  Inst.addOperand(MCOperand::createImm(RegMask));
627  return Success;
628 }
629 
632  {AArch64::ZAB0},
633  {AArch64::ZAH0, AArch64::ZAH1},
634  {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
635  {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3,
636  AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
637  {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3,
638  AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7,
639  AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11,
640  AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}};
641 
642 template <unsigned NumBitsForTile>
643 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
644  uint64_t Address, const void *Decoder) {
645  unsigned LastReg = (1 << NumBitsForTile) - 1;
646  if (RegNo > LastReg)
647  return Fail;
648  Inst.addOperand(
649  MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
650  return Success;
651 }
652 
653 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
654  uint64_t Addr, const void *Decoder) {
655  if (RegNo > 15)
656  return Fail;
657 
658  unsigned Register =
659  AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
661  return Success;
662 }
663 
664 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
665  uint64_t Addr,
666  const void* Decoder) {
667  if (RegNo > 7)
668  return Fail;
669 
670  // Just reuse the PPR decode table
671  return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
672 }
673 
674 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
675  uint64_t Addr, const void *Decoder) {
676  if (RegNo > 31)
677  return Fail;
678  unsigned Register =
679  AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
681  return Success;
682 }
683 
684 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
685  uint64_t Addr, const void *Decoder) {
686  if (RegNo > 31)
687  return Fail;
688  unsigned Register =
689  AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
691  return Success;
692 }
693 
694 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
695  uint64_t Addr,
696  const void *Decoder) {
697  if (RegNo > 31)
698  return Fail;
699  unsigned Register =
700  AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
702  return Success;
703 }
704 
705 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
706  uint64_t Addr, const void *Decoder) {
707  if (RegNo > 31)
708  return Fail;
709  unsigned Register =
710  AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
712  return Success;
713 }
714 
715 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
716  uint64_t Addr, const void *Decoder) {
717  if (RegNo > 31)
718  return Fail;
719  unsigned Register =
720  AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
722  return Success;
723 }
724 
725 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
726  uint64_t Addr,
727  const void *Decoder) {
728  if (RegNo > 31)
729  return Fail;
730  unsigned Register =
731  AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
733  return Success;
734 }
735 
736 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
737  uint64_t Addr,
738  const void *Decoder) {
739  // scale{5} is asserted as 1 in tblgen.
740  Imm |= 0x20;
741  Inst.addOperand(MCOperand::createImm(64 - Imm));
742  return Success;
743 }
744 
745 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
746  uint64_t Addr,
747  const void *Decoder) {
748  Inst.addOperand(MCOperand::createImm(64 - Imm));
749  return Success;
750 }
751 
752 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
753  uint64_t Addr, const void *Decoder) {
754  int64_t ImmVal = Imm;
755  const AArch64Disassembler *Dis =
756  static_cast<const AArch64Disassembler *>(Decoder);
757 
758  // Sign-extend 19-bit immediate.
759  if (ImmVal & (1 << (19 - 1)))
760  ImmVal |= ~((1LL << 19) - 1);
761 
762  if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
763  Inst.getOpcode() != AArch64::LDRXl, 0, 4))
764  Inst.addOperand(MCOperand::createImm(ImmVal));
765  return Success;
766 }
767 
768 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
769  uint64_t Address, const void *Decoder) {
770  Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
771  Inst.addOperand(MCOperand::createImm(Imm & 1));
772  return Success;
773 }
774 
775 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
776  uint64_t Address,
777  const void *Decoder) {
778  Inst.addOperand(MCOperand::createImm(Imm));
779 
780  // Every system register in the encoding space is valid with the syntax
781  // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
782  return Success;
783 }
784 
785 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
786  uint64_t Address,
787  const void *Decoder) {
788  Inst.addOperand(MCOperand::createImm(Imm));
789 
790  return Success;
791 }
792 
794  uint64_t Address,
795  const void *Decoder) {
796  // This decoder exists to add the dummy Lane operand to the MCInst, which must
797  // be 1 in assembly but has no other real manifestation.
798  unsigned Rd = fieldFromInstruction(Insn, 0, 5);
799  unsigned Rn = fieldFromInstruction(Insn, 5, 5);
800  unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
801 
802  if (IsToVec) {
803  DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
804  DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
805  } else {
806  DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
807  DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
808  }
809 
810  // Add the lane
812 
813  return Success;
814 }
815 
816 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
817  unsigned Add) {
818  Inst.addOperand(MCOperand::createImm(Add - Imm));
819  return Success;
820 }
821 
822 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
823  unsigned Add) {
824  Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
825  return Success;
826 }
827 
828 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
829  uint64_t Addr, const void *Decoder) {
830  return DecodeVecShiftRImm(Inst, Imm, 64);
831 }
832 
833 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
834  uint64_t Addr,
835  const void *Decoder) {
836  return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
837 }
838 
839 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
840  uint64_t Addr, const void *Decoder) {
841  return DecodeVecShiftRImm(Inst, Imm, 32);
842 }
843 
844 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
845  uint64_t Addr,
846  const void *Decoder) {
847  return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
848 }
849 
850 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
851  uint64_t Addr, const void *Decoder) {
852  return DecodeVecShiftRImm(Inst, Imm, 16);
853 }
854 
855 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
856  uint64_t Addr,
857  const void *Decoder) {
858  return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
859 }
860 
861 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
862  uint64_t Addr, const void *Decoder) {
863  return DecodeVecShiftRImm(Inst, Imm, 8);
864 }
865 
866 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
867  uint64_t Addr, const void *Decoder) {
868  return DecodeVecShiftLImm(Inst, Imm, 64);
869 }
870 
871 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
872  uint64_t Addr, const void *Decoder) {
873  return DecodeVecShiftLImm(Inst, Imm, 32);
874 }
875 
876 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
877  uint64_t Addr, const void *Decoder) {
878  return DecodeVecShiftLImm(Inst, Imm, 16);
879 }
880 
881 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
882  uint64_t Addr, const void *Decoder) {
883  return DecodeVecShiftLImm(Inst, Imm, 8);
884 }
885 
887  uint64_t Addr,
888  const void *Decoder) {
889  unsigned Rd = fieldFromInstruction(insn, 0, 5);
890  unsigned Rn = fieldFromInstruction(insn, 5, 5);
891  unsigned Rm = fieldFromInstruction(insn, 16, 5);
892  unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
893  unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
894  unsigned shift = (shiftHi << 6) | shiftLo;
895  switch (Inst.getOpcode()) {
896  default:
897  return Fail;
898  case AArch64::ADDWrs:
899  case AArch64::ADDSWrs:
900  case AArch64::SUBWrs:
901  case AArch64::SUBSWrs:
902  // if shift == '11' then ReservedValue()
903  if (shiftHi == 0x3)
904  return Fail;
906  case AArch64::ANDWrs:
907  case AArch64::ANDSWrs:
908  case AArch64::BICWrs:
909  case AArch64::BICSWrs:
910  case AArch64::ORRWrs:
911  case AArch64::ORNWrs:
912  case AArch64::EORWrs:
913  case AArch64::EONWrs: {
914  // if sf == '0' and imm6<5> == '1' then ReservedValue()
915  if (shiftLo >> 5 == 1)
916  return Fail;
917  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
918  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
919  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
920  break;
921  }
922  case AArch64::ADDXrs:
923  case AArch64::ADDSXrs:
924  case AArch64::SUBXrs:
925  case AArch64::SUBSXrs:
926  // if shift == '11' then ReservedValue()
927  if (shiftHi == 0x3)
928  return Fail;
930  case AArch64::ANDXrs:
931  case AArch64::ANDSXrs:
932  case AArch64::BICXrs:
933  case AArch64::BICSXrs:
934  case AArch64::ORRXrs:
935  case AArch64::ORNXrs:
936  case AArch64::EORXrs:
937  case AArch64::EONXrs:
938  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
939  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
940  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
941  break;
942  }
943 
945  return Success;
946 }
947 
949  uint64_t Addr,
950  const void *Decoder) {
951  unsigned Rd = fieldFromInstruction(insn, 0, 5);
952  unsigned imm = fieldFromInstruction(insn, 5, 16);
953  unsigned shift = fieldFromInstruction(insn, 21, 2);
954  shift <<= 4;
955  switch (Inst.getOpcode()) {
956  default:
957  return Fail;
958  case AArch64::MOVZWi:
959  case AArch64::MOVNWi:
960  case AArch64::MOVKWi:
961  if (shift & (1U << 5))
962  return Fail;
963  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
964  break;
965  case AArch64::MOVZXi:
966  case AArch64::MOVNXi:
967  case AArch64::MOVKXi:
968  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
969  break;
970  }
971 
972  if (Inst.getOpcode() == AArch64::MOVKWi ||
973  Inst.getOpcode() == AArch64::MOVKXi)
974  Inst.addOperand(Inst.getOperand(0));
975 
976  Inst.addOperand(MCOperand::createImm(imm));
978  return Success;
979 }
980 
982  uint64_t Addr,
983  const void *Decoder) {
984  unsigned Rt = fieldFromInstruction(insn, 0, 5);
985  unsigned Rn = fieldFromInstruction(insn, 5, 5);
986  unsigned offset = fieldFromInstruction(insn, 10, 12);
987  const AArch64Disassembler *Dis =
988  static_cast<const AArch64Disassembler *>(Decoder);
989 
990  switch (Inst.getOpcode()) {
991  default:
992  return Fail;
993  case AArch64::PRFMui:
994  // Rt is an immediate in prefetch.
996  break;
997  case AArch64::STRBBui:
998  case AArch64::LDRBBui:
999  case AArch64::LDRSBWui:
1000  case AArch64::STRHHui:
1001  case AArch64::LDRHHui:
1002  case AArch64::LDRSHWui:
1003  case AArch64::STRWui:
1004  case AArch64::LDRWui:
1005  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1006  break;
1007  case AArch64::LDRSBXui:
1008  case AArch64::LDRSHXui:
1009  case AArch64::LDRSWui:
1010  case AArch64::STRXui:
1011  case AArch64::LDRXui:
1012  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1013  break;
1014  case AArch64::LDRQui:
1015  case AArch64::STRQui:
1016  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1017  break;
1018  case AArch64::LDRDui:
1019  case AArch64::STRDui:
1020  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1021  break;
1022  case AArch64::LDRSui:
1023  case AArch64::STRSui:
1024  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1025  break;
1026  case AArch64::LDRHui:
1027  case AArch64::STRHui:
1028  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1029  break;
1030  case AArch64::LDRBui:
1031  case AArch64::STRBui:
1032  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1033  break;
1034  }
1035 
1036  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1037  if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
1038  Inst.addOperand(MCOperand::createImm(offset));
1039  return Success;
1040 }
1041 
1043  uint64_t Addr,
1044  const void *Decoder) {
1045  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1046  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1047  int64_t offset = fieldFromInstruction(insn, 12, 9);
1048 
1049  // offset is a 9-bit signed immediate, so sign extend it to
1050  // fill the unsigned.
1051  if (offset & (1 << (9 - 1)))
1052  offset |= ~((1LL << 9) - 1);
1053 
1054  // First operand is always the writeback to the address register, if needed.
1055  switch (Inst.getOpcode()) {
1056  default:
1057  break;
1058  case AArch64::LDRSBWpre:
1059  case AArch64::LDRSHWpre:
1060  case AArch64::STRBBpre:
1061  case AArch64::LDRBBpre:
1062  case AArch64::STRHHpre:
1063  case AArch64::LDRHHpre:
1064  case AArch64::STRWpre:
1065  case AArch64::LDRWpre:
1066  case AArch64::LDRSBWpost:
1067  case AArch64::LDRSHWpost:
1068  case AArch64::STRBBpost:
1069  case AArch64::LDRBBpost:
1070  case AArch64::STRHHpost:
1071  case AArch64::LDRHHpost:
1072  case AArch64::STRWpost:
1073  case AArch64::LDRWpost:
1074  case AArch64::LDRSBXpre:
1075  case AArch64::LDRSHXpre:
1076  case AArch64::STRXpre:
1077  case AArch64::LDRSWpre:
1078  case AArch64::LDRXpre:
1079  case AArch64::LDRSBXpost:
1080  case AArch64::LDRSHXpost:
1081  case AArch64::STRXpost:
1082  case AArch64::LDRSWpost:
1083  case AArch64::LDRXpost:
1084  case AArch64::LDRQpre:
1085  case AArch64::STRQpre:
1086  case AArch64::LDRQpost:
1087  case AArch64::STRQpost:
1088  case AArch64::LDRDpre:
1089  case AArch64::STRDpre:
1090  case AArch64::LDRDpost:
1091  case AArch64::STRDpost:
1092  case AArch64::LDRSpre:
1093  case AArch64::STRSpre:
1094  case AArch64::LDRSpost:
1095  case AArch64::STRSpost:
1096  case AArch64::LDRHpre:
1097  case AArch64::STRHpre:
1098  case AArch64::LDRHpost:
1099  case AArch64::STRHpost:
1100  case AArch64::LDRBpre:
1101  case AArch64::STRBpre:
1102  case AArch64::LDRBpost:
1103  case AArch64::STRBpost:
1104  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1105  break;
1106  }
1107 
1108  switch (Inst.getOpcode()) {
1109  default:
1110  return Fail;
1111  case AArch64::PRFUMi:
1112  // Rt is an immediate in prefetch.
1113  Inst.addOperand(MCOperand::createImm(Rt));
1114  break;
1115  case AArch64::STURBBi:
1116  case AArch64::LDURBBi:
1117  case AArch64::LDURSBWi:
1118  case AArch64::STURHHi:
1119  case AArch64::LDURHHi:
1120  case AArch64::LDURSHWi:
1121  case AArch64::STURWi:
1122  case AArch64::LDURWi:
1123  case AArch64::LDTRSBWi:
1124  case AArch64::LDTRSHWi:
1125  case AArch64::STTRWi:
1126  case AArch64::LDTRWi:
1127  case AArch64::STTRHi:
1128  case AArch64::LDTRHi:
1129  case AArch64::LDTRBi:
1130  case AArch64::STTRBi:
1131  case AArch64::LDRSBWpre:
1132  case AArch64::LDRSHWpre:
1133  case AArch64::STRBBpre:
1134  case AArch64::LDRBBpre:
1135  case AArch64::STRHHpre:
1136  case AArch64::LDRHHpre:
1137  case AArch64::STRWpre:
1138  case AArch64::LDRWpre:
1139  case AArch64::LDRSBWpost:
1140  case AArch64::LDRSHWpost:
1141  case AArch64::STRBBpost:
1142  case AArch64::LDRBBpost:
1143  case AArch64::STRHHpost:
1144  case AArch64::LDRHHpost:
1145  case AArch64::STRWpost:
1146  case AArch64::LDRWpost:
1147  case AArch64::STLURBi:
1148  case AArch64::STLURHi:
1149  case AArch64::STLURWi:
1150  case AArch64::LDAPURBi:
1151  case AArch64::LDAPURSBWi:
1152  case AArch64::LDAPURHi:
1153  case AArch64::LDAPURSHWi:
1154  case AArch64::LDAPURi:
1155  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1156  break;
1157  case AArch64::LDURSBXi:
1158  case AArch64::LDURSHXi:
1159  case AArch64::LDURSWi:
1160  case AArch64::STURXi:
1161  case AArch64::LDURXi:
1162  case AArch64::LDTRSBXi:
1163  case AArch64::LDTRSHXi:
1164  case AArch64::LDTRSWi:
1165  case AArch64::STTRXi:
1166  case AArch64::LDTRXi:
1167  case AArch64::LDRSBXpre:
1168  case AArch64::LDRSHXpre:
1169  case AArch64::STRXpre:
1170  case AArch64::LDRSWpre:
1171  case AArch64::LDRXpre:
1172  case AArch64::LDRSBXpost:
1173  case AArch64::LDRSHXpost:
1174  case AArch64::STRXpost:
1175  case AArch64::LDRSWpost:
1176  case AArch64::LDRXpost:
1177  case AArch64::LDAPURSWi:
1178  case AArch64::LDAPURSHXi:
1179  case AArch64::LDAPURSBXi:
1180  case AArch64::STLURXi:
1181  case AArch64::LDAPURXi:
1182  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1183  break;
1184  case AArch64::LDURQi:
1185  case AArch64::STURQi:
1186  case AArch64::LDRQpre:
1187  case AArch64::STRQpre:
1188  case AArch64::LDRQpost:
1189  case AArch64::STRQpost:
1190  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1191  break;
1192  case AArch64::LDURDi:
1193  case AArch64::STURDi:
1194  case AArch64::LDRDpre:
1195  case AArch64::STRDpre:
1196  case AArch64::LDRDpost:
1197  case AArch64::STRDpost:
1198  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1199  break;
1200  case AArch64::LDURSi:
1201  case AArch64::STURSi:
1202  case AArch64::LDRSpre:
1203  case AArch64::STRSpre:
1204  case AArch64::LDRSpost:
1205  case AArch64::STRSpost:
1206  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1207  break;
1208  case AArch64::LDURHi:
1209  case AArch64::STURHi:
1210  case AArch64::LDRHpre:
1211  case AArch64::STRHpre:
1212  case AArch64::LDRHpost:
1213  case AArch64::STRHpost:
1214  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1215  break;
1216  case AArch64::LDURBi:
1217  case AArch64::STURBi:
1218  case AArch64::LDRBpre:
1219  case AArch64::STRBpre:
1220  case AArch64::LDRBpost:
1221  case AArch64::STRBpost:
1222  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1223  break;
1224  }
1225 
1226  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1227  Inst.addOperand(MCOperand::createImm(offset));
1228 
1229  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1230  bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1231  bool IsFP = fieldFromInstruction(insn, 26, 1);
1232 
1233  // Cannot write back to a transfer register (but xzr != sp).
1234  if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1235  return SoftFail;
1236 
1237  return Success;
1238 }
1239 
1241  uint64_t Addr,
1242  const void *Decoder) {
1243  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1244  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1245  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1246  unsigned Rs = fieldFromInstruction(insn, 16, 5);
1247 
1248  unsigned Opcode = Inst.getOpcode();
1249  switch (Opcode) {
1250  default:
1251  return Fail;
1252  case AArch64::STLXRW:
1253  case AArch64::STLXRB:
1254  case AArch64::STLXRH:
1255  case AArch64::STXRW:
1256  case AArch64::STXRB:
1257  case AArch64::STXRH:
1258  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1260  case AArch64::LDARW:
1261  case AArch64::LDARB:
1262  case AArch64::LDARH:
1263  case AArch64::LDAXRW:
1264  case AArch64::LDAXRB:
1265  case AArch64::LDAXRH:
1266  case AArch64::LDXRW:
1267  case AArch64::LDXRB:
1268  case AArch64::LDXRH:
1269  case AArch64::STLRW:
1270  case AArch64::STLRB:
1271  case AArch64::STLRH:
1272  case AArch64::STLLRW:
1273  case AArch64::STLLRB:
1274  case AArch64::STLLRH:
1275  case AArch64::LDLARW:
1276  case AArch64::LDLARB:
1277  case AArch64::LDLARH:
1278  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1279  break;
1280  case AArch64::STLXRX:
1281  case AArch64::STXRX:
1282  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1284  case AArch64::LDARX:
1285  case AArch64::LDAXRX:
1286  case AArch64::LDXRX:
1287  case AArch64::STLRX:
1288  case AArch64::LDLARX:
1289  case AArch64::STLLRX:
1290  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1291  break;
1292  case AArch64::STLXPW:
1293  case AArch64::STXPW:
1294  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1296  case AArch64::LDAXPW:
1297  case AArch64::LDXPW:
1298  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1299  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1300  break;
1301  case AArch64::STLXPX:
1302  case AArch64::STXPX:
1303  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1305  case AArch64::LDAXPX:
1306  case AArch64::LDXPX:
1307  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1308  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1309  break;
1310  }
1311 
1312  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1313 
1314  // You shouldn't load to the same register twice in an instruction...
1315  if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1316  Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1317  Rt == Rt2)
1318  return SoftFail;
1319 
1320  return Success;
1321 }
1322 
1324  uint64_t Addr,
1325  const void *Decoder) {
1326  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1327  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1328  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1329  int64_t offset = fieldFromInstruction(insn, 15, 7);
1330  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1331 
1332  // offset is a 7-bit signed immediate, so sign extend it to
1333  // fill the unsigned.
1334  if (offset & (1 << (7 - 1)))
1335  offset |= ~((1LL << 7) - 1);
1336 
1337  unsigned Opcode = Inst.getOpcode();
1338  bool NeedsDisjointWritebackTransfer = false;
1339 
1340  // First operand is always writeback of base register.
1341  switch (Opcode) {
1342  default:
1343  break;
1344  case AArch64::LDPXpost:
1345  case AArch64::STPXpost:
1346  case AArch64::LDPSWpost:
1347  case AArch64::LDPXpre:
1348  case AArch64::STPXpre:
1349  case AArch64::LDPSWpre:
1350  case AArch64::LDPWpost:
1351  case AArch64::STPWpost:
1352  case AArch64::LDPWpre:
1353  case AArch64::STPWpre:
1354  case AArch64::LDPQpost:
1355  case AArch64::STPQpost:
1356  case AArch64::LDPQpre:
1357  case AArch64::STPQpre:
1358  case AArch64::LDPDpost:
1359  case AArch64::STPDpost:
1360  case AArch64::LDPDpre:
1361  case AArch64::STPDpre:
1362  case AArch64::LDPSpost:
1363  case AArch64::STPSpost:
1364  case AArch64::LDPSpre:
1365  case AArch64::STPSpre:
1366  case AArch64::STGPpre:
1367  case AArch64::STGPpost:
1368  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1369  break;
1370  }
1371 
1372  switch (Opcode) {
1373  default:
1374  return Fail;
1375  case AArch64::LDPXpost:
1376  case AArch64::STPXpost:
1377  case AArch64::LDPSWpost:
1378  case AArch64::LDPXpre:
1379  case AArch64::STPXpre:
1380  case AArch64::LDPSWpre:
1381  case AArch64::STGPpre:
1382  case AArch64::STGPpost:
1383  NeedsDisjointWritebackTransfer = true;
1385  case AArch64::LDNPXi:
1386  case AArch64::STNPXi:
1387  case AArch64::LDPXi:
1388  case AArch64::STPXi:
1389  case AArch64::LDPSWi:
1390  case AArch64::STGPi:
1391  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1392  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1393  break;
1394  case AArch64::LDPWpost:
1395  case AArch64::STPWpost:
1396  case AArch64::LDPWpre:
1397  case AArch64::STPWpre:
1398  NeedsDisjointWritebackTransfer = true;
1400  case AArch64::LDNPWi:
1401  case AArch64::STNPWi:
1402  case AArch64::LDPWi:
1403  case AArch64::STPWi:
1404  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1405  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1406  break;
1407  case AArch64::LDNPQi:
1408  case AArch64::STNPQi:
1409  case AArch64::LDPQpost:
1410  case AArch64::STPQpost:
1411  case AArch64::LDPQi:
1412  case AArch64::STPQi:
1413  case AArch64::LDPQpre:
1414  case AArch64::STPQpre:
1415  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1416  DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1417  break;
1418  case AArch64::LDNPDi:
1419  case AArch64::STNPDi:
1420  case AArch64::LDPDpost:
1421  case AArch64::STPDpost:
1422  case AArch64::LDPDi:
1423  case AArch64::STPDi:
1424  case AArch64::LDPDpre:
1425  case AArch64::STPDpre:
1426  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1427  DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1428  break;
1429  case AArch64::LDNPSi:
1430  case AArch64::STNPSi:
1431  case AArch64::LDPSpost:
1432  case AArch64::STPSpost:
1433  case AArch64::LDPSi:
1434  case AArch64::STPSi:
1435  case AArch64::LDPSpre:
1436  case AArch64::STPSpre:
1437  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1438  DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1439  break;
1440  }
1441 
1442  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1443  Inst.addOperand(MCOperand::createImm(offset));
1444 
1445  // You shouldn't load to the same register twice in an instruction...
1446  if (IsLoad && Rt == Rt2)
1447  return SoftFail;
1448 
1449  // ... or do any operation that writes-back to a transfer register. But note
1450  // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1451  if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1452  return SoftFail;
1453 
1454  return Success;
1455 }
1456 
1458  uint64_t Addr,
1459  const void *Decoder) {
1460  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1461  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1462  uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1463  fieldFromInstruction(insn, 12, 9);
1464  unsigned writeback = fieldFromInstruction(insn, 11, 1);
1465 
1466  switch (Inst.getOpcode()) {
1467  default:
1468  return Fail;
1469  case AArch64::LDRAAwriteback:
1470  case AArch64::LDRABwriteback:
1471  DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1472  Decoder);
1473  break;
1474  case AArch64::LDRAAindexed:
1475  case AArch64::LDRABindexed:
1476  break;
1477  }
1478 
1479  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1480  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1481  DecodeSImm<10>(Inst, offset, Addr, Decoder);
1482 
1483  if (writeback && Rt == Rn && Rn != 31) {
1484  return SoftFail;
1485  }
1486 
1487  return Success;
1488 }
1489 
1491  uint64_t Addr,
1492  const void *Decoder) {
1493  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1494  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1495  unsigned Rm = fieldFromInstruction(insn, 16, 5);
1496  unsigned extend = fieldFromInstruction(insn, 10, 6);
1497 
1498  unsigned shift = extend & 0x7;
1499  if (shift > 4)
1500  return Fail;
1501 
1502  switch (Inst.getOpcode()) {
1503  default:
1504  return Fail;
1505  case AArch64::ADDWrx:
1506  case AArch64::SUBWrx:
1507  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1508  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1509  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1510  break;
1511  case AArch64::ADDSWrx:
1512  case AArch64::SUBSWrx:
1513  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1514  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1515  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1516  break;
1517  case AArch64::ADDXrx:
1518  case AArch64::SUBXrx:
1519  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1520  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1521  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1522  break;
1523  case AArch64::ADDSXrx:
1524  case AArch64::SUBSXrx:
1525  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1526  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1527  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1528  break;
1529  case AArch64::ADDXrx64:
1530  case AArch64::SUBXrx64:
1531  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1532  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1533  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1534  break;
1535  case AArch64::SUBSXrx64:
1536  case AArch64::ADDSXrx64:
1537  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1538  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1539  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1540  break;
1541  }
1542 
1544  return Success;
1545 }
1546 
1548  uint64_t Addr,
1549  const void *Decoder) {
1550  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1551  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1552  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1553  unsigned imm;
1554 
1555  if (Datasize) {
1556  if (Inst.getOpcode() == AArch64::ANDSXri)
1557  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1558  else
1559  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1560  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1561  imm = fieldFromInstruction(insn, 10, 13);
1563  return Fail;
1564  } else {
1565  if (Inst.getOpcode() == AArch64::ANDSWri)
1566  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1567  else
1568  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1569  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1570  imm = fieldFromInstruction(insn, 10, 12);
1572  return Fail;
1573  }
1574  Inst.addOperand(MCOperand::createImm(imm));
1575  return Success;
1576 }
1577 
1579  uint64_t Addr,
1580  const void *Decoder) {
1581  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1582  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1583  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1584  imm |= fieldFromInstruction(insn, 5, 5);
1585 
1586  if (Inst.getOpcode() == AArch64::MOVID)
1587  DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1588  else
1589  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1590 
1591  Inst.addOperand(MCOperand::createImm(imm));
1592 
1593  switch (Inst.getOpcode()) {
1594  default:
1595  break;
1596  case AArch64::MOVIv4i16:
1597  case AArch64::MOVIv8i16:
1598  case AArch64::MVNIv4i16:
1599  case AArch64::MVNIv8i16:
1600  case AArch64::MOVIv2i32:
1601  case AArch64::MOVIv4i32:
1602  case AArch64::MVNIv2i32:
1603  case AArch64::MVNIv4i32:
1604  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1605  break;
1606  case AArch64::MOVIv2s_msl:
1607  case AArch64::MOVIv4s_msl:
1608  case AArch64::MVNIv2s_msl:
1609  case AArch64::MVNIv4s_msl:
1610  Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1611  break;
1612  }
1613 
1614  return Success;
1615 }
1616 
1618  uint64_t Addr,
1619  const void *Decoder) {
1620  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1621  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1622  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1623  imm |= fieldFromInstruction(insn, 5, 5);
1624 
1625  // Tied operands added twice.
1626  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1627  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1628 
1629  Inst.addOperand(MCOperand::createImm(imm));
1630  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1631 
1632  return Success;
1633 }
1634 
1636  uint64_t Addr, const void *Decoder) {
1637  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1638  int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1639  imm |= fieldFromInstruction(insn, 29, 2);
1640  const AArch64Disassembler *Dis =
1641  static_cast<const AArch64Disassembler *>(Decoder);
1642 
1643  // Sign-extend the 21-bit immediate.
1644  if (imm & (1 << (21 - 1)))
1645  imm |= ~((1LL << 21) - 1);
1646 
1647  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1648  if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1649  Inst.addOperand(MCOperand::createImm(imm));
1650 
1651  return Success;
1652 }
1653 
1655  uint64_t Addr, const void *Decoder) {
1656  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1657  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1658  unsigned Imm = fieldFromInstruction(insn, 10, 14);
1659  unsigned S = fieldFromInstruction(insn, 29, 1);
1660  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1661 
1662  unsigned ShifterVal = (Imm >> 12) & 3;
1663  unsigned ImmVal = Imm & 0xFFF;
1664  const AArch64Disassembler *Dis =
1665  static_cast<const AArch64Disassembler *>(Decoder);
1666 
1667  if (ShifterVal != 0 && ShifterVal != 1)
1668  return Fail;
1669 
1670  if (Datasize) {
1671  if (Rd == 31 && !S)
1672  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1673  else
1674  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1675  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1676  } else {
1677  if (Rd == 31 && !S)
1678  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1679  else
1680  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1681  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1682  }
1683 
1684  if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1685  Inst.addOperand(MCOperand::createImm(ImmVal));
1686  Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1687  return Success;
1688 }
1689 
1691  uint64_t Addr,
1692  const void *Decoder) {
1693  int64_t imm = fieldFromInstruction(insn, 0, 26);
1694  const AArch64Disassembler *Dis =
1695  static_cast<const AArch64Disassembler *>(Decoder);
1696 
1697  // Sign-extend the 26-bit immediate.
1698  if (imm & (1 << (26 - 1)))
1699  imm |= ~((1LL << 26) - 1);
1700 
1701  if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1702  Inst.addOperand(MCOperand::createImm(imm));
1703 
1704  return Success;
1705 }
1706 
1708  uint64_t Addr,
1709  const void *Decoder) {
1710  uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1711  uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1712  uint64_t crm = fieldFromInstruction(insn, 8, 4);
1713  uint64_t pstate_field = (op1 << 3) | op2;
1714 
1715  switch (pstate_field) {
1716  case 0x01: // XAFlag
1717  case 0x02: // AXFlag
1718  return Fail;
1719  }
1720 
1721  if ((pstate_field == AArch64PState::PAN ||
1722  pstate_field == AArch64PState::UAO ||
1723  pstate_field == AArch64PState::SSBS) && crm > 1)
1724  return Fail;
1725 
1726  Inst.addOperand(MCOperand::createImm(pstate_field));
1727  Inst.addOperand(MCOperand::createImm(crm));
1728 
1729  const AArch64Disassembler *Dis =
1730  static_cast<const AArch64Disassembler *>(Decoder);
1731  auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1732  if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1733  return Success;
1734  return Fail;
1735 }
1736 
1738  uint64_t Addr, const void *Decoder) {
1739  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1740  uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1741  bit |= fieldFromInstruction(insn, 19, 5);
1742  int64_t dst = fieldFromInstruction(insn, 5, 14);
1743  const AArch64Disassembler *Dis =
1744  static_cast<const AArch64Disassembler *>(Decoder);
1745 
1746  // Sign-extend 14-bit immediate.
1747  if (dst & (1 << (14 - 1)))
1748  dst |= ~((1LL << 14) - 1);
1749 
1750  if (fieldFromInstruction(insn, 31, 1) == 0)
1751  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1752  else
1753  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1755  if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1756  Inst.addOperand(MCOperand::createImm(dst));
1757 
1758  return Success;
1759 }
1760 
1762  unsigned RegClassID,
1763  unsigned RegNo,
1764  uint64_t Addr,
1765  const void *Decoder) {
1766  // Register number must be even (see CASP instruction)
1767  if (RegNo & 0x1)
1768  return Fail;
1769 
1770  unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1772  return Success;
1773 }
1774 
1776  unsigned RegNo,
1777  uint64_t Addr,
1778  const void *Decoder) {
1780  AArch64::WSeqPairsClassRegClassID,
1781  RegNo, Addr, Decoder);
1782 }
1783 
1785  unsigned RegNo,
1786  uint64_t Addr,
1787  const void *Decoder) {
1789  AArch64::XSeqPairsClassRegClassID,
1790  RegNo, Addr, Decoder);
1791 }
1792 
1794  uint64_t Addr,
1795  const void *Decoder) {
1796  unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1797  unsigned imm = fieldFromInstruction(insn, 5, 13);
1799  return Fail;
1800 
1801  // The same (tied) operand is added twice to the instruction.
1802  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1803  if (Inst.getOpcode() != AArch64::DUPM_ZI)
1804  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1805  Inst.addOperand(MCOperand::createImm(imm));
1806  return Success;
1807 }
1808 
1809 template <int Bits>
1810 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1811  const void *Decoder) {
1812  if (Imm & ~((1LL << Bits) - 1))
1813  return Fail;
1814 
1815  // Imm is a signed immediate, so sign extend it.
1816  if (Imm & (1 << (Bits - 1)))
1817  Imm |= ~((1LL << Bits) - 1);
1818 
1819  Inst.addOperand(MCOperand::createImm(Imm));
1820  return Success;
1821 }
1822 
1823 // Decode 8-bit signed/unsigned immediate for a given element width.
1824 template <int ElementWidth>
1825 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1826  uint64_t Addr, const void *Decoder) {
1827  unsigned Val = (uint8_t)Imm;
1828  unsigned Shift = (Imm & 0x100) ? 8 : 0;
1829  if (ElementWidth == 8 && Shift)
1830  return Fail;
1831  Inst.addOperand(MCOperand::createImm(Val));
1833  return Success;
1834 }
1835 
1836 // Decode uimm4 ranged from 1-16.
1837 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1838  uint64_t Addr, const void *Decoder) {
1839  Inst.addOperand(MCOperand::createImm(Imm + 1));
1840  return Success;
1841 }
1842 
1843 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1844  const void *Decoder) {
1845  if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1846  Inst.addOperand(MCOperand::createImm(Imm));
1847  return Success;
1848  }
1849  return Fail;
1850 }
1851 
1853  uint64_t Addr,
1854  const void *Decoder) {
1855  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1856  unsigned Rs = fieldFromInstruction(insn, 16, 5);
1857  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1858 
1859  // None of the registers may alias: if they do, then the instruction is not
1860  // merely unpredictable but actually entirely unallocated.
1861  if (Rd == Rs || Rs == Rn || Rd == Rn)
1862  return MCDisassembler::Fail;
1863 
1864  // All three register operands are written back, so they all appear
1865  // twice in the operand list, once as outputs and once as inputs.
1866  if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
1867  !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
1868  !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
1869  !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
1870  !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
1871  !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder))
1872  return MCDisassembler::Fail;
1873 
1874  return MCDisassembler::Success;
1875 }
1876 
1878  uint64_t Addr,
1879  const void *Decoder) {
1880  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1881  unsigned Rm = fieldFromInstruction(insn, 16, 5);
1882  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1883 
1884  // None of the registers may alias: if they do, then the instruction is not
1885  // merely unpredictable but actually entirely unallocated.
1886  if (Rd == Rm || Rm == Rn || Rd == Rn)
1887  return MCDisassembler::Fail;
1888 
1889  // Rd and Rn (not Rm) register operands are written back, so they appear
1890  // twice in the operand list, once as outputs and once as inputs.
1891  if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
1892  !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
1893  !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
1894  !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
1895  !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder))
1896  return MCDisassembler::Fail;
1897 
1898  return MCDisassembler::Success;
1899 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1837
MCFixedLenDisassembler.h
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:752
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1457
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:270
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
DecodeFPR128_loRegisterClass
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:413
DecodeZPR3RegisterClass
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:598
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1042
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:981
DecodeZPR_3bRegisterClass
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:579
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
DecodeQQQRegisterClass
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:684
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:494
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:377
ErrorHandling.h
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1654
AArch64BaseInfo.h
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
Fail
#define Fail
Definition: AArch64Disassembler.cpp:267
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:793
Disassembler.h
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:828
Shift
bool Shift
Definition: README.txt:468
llvm::MCDisassembler::SoftFail
@ SoftFail
Definition: MCDisassembler.h:102
AArch64ExternalSymbolizer.h
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:775
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:535
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:369
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:866
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:421
DecodeDDRegisterClass
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:705
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:948
AArch64Disassembler.h
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:876
DecodeGPR64commonRegisterClass
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:469
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:833
DecodeGPR64spRegisterClass
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:510
DecodeGPR32spRegisterClass
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:547
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:822
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1690
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:445
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
LLVMSymbolLookupCallback
const typedef char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
MatrixZATileDecoderTable
static const SmallVector< SmallVector< unsigned, 16 >, 5 > MatrixZATileDecoderTable
Definition: AArch64Disassembler.cpp:631
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:736
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:268
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:881
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:192
MCInst.h
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:844
DecodeZPR_4bRegisterClass
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:571
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:482
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:850
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:170
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
AArch64AddressingModes.h
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1635
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:861
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:248
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1240
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
DecodeQQQQRegisterClass
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:694
uint64_t
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:136
DecodeQQRegisterClass
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:674
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
extend
_test eax xmm0 eax xmm1 comiss xmm1 setae al movzbl ecx eax edx ecx cmove eax ret Note the cmove can be replaced with a single cmovae There are a number of issues We are introducing a setcc between the result of the intrisic call and select The intrinsic is expected to produce a i32 value so a any extend(which becomes a zero extend) is added. We probably need some kind of target DAG combine hook to fix this. We generate significantly worse code for this than GCC
Definition: README.txt:213
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:816
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:745
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1852
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:643
DecodeZPR2RegisterClass
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:587
MCRegisterInfo.h
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1490
llvm::HighlightColor::Address
@ Address
DecodeDDDRegisterClass
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:715
llvm::AArch64ExternalSymbolizer
Definition: AArch64ExternalSymbolizer.h:20
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:871
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1617
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
Definition: MCDisassembler.cpp:26
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
DecodeMatrixIndexGPR32_12_15RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:521
llvm::ArrayRef< uint8_t >
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
DecodePPRRegisterClass
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:653
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1793
uint32_t
Compiler.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:433
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:886
DecodeDDDDRegisterClass
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:725
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1578
DecodeSystemPStateInstruction
static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1707
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:86
bit
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional ldr LCPI1_0 ldr ldr tst movne lsr ldr LCPI1_1 and r0 bx lr it saves an instruction and a register It might be profitable to cse MOVi16 if there are lots of bit immediates with the same bottom half Robert Muth started working on an alternate jump table implementation that does not put the tables in line in the text This is more like the llvm default jump table implementation This might be useful sometime Several revisions of patches are on the mailing beginning while CMP sets them like a subtract Therefore to be able to use CMN for comparisons other than the Z bit
Definition: README.txt:584
Success
#define Success
Definition: AArch64Disassembler.cpp:266
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1825
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:276
MCRelocationInfo.h
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1761
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1737
AArch64MCTargetDesc.h
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1843
DecodePPR_3bRegisterClass
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:664
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:188
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:839
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1784
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:401
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:855
DecodeZPR4RegisterClass
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:609
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:768
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:322
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
shift
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra shift
Definition: README.txt:30
DecodeZPRRegisterClass
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:559
llvm::AArch64Disassembler
Definition: AArch64Disassembler.h:19
DecodeFPR8RegisterClass
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:457
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:785
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1006
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1547
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1877
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1323
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1810
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:620
Debug.h
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1775
AArch64TargetInfo.h