LLVM  14.0.0git
AArch64Disassembler.cpp
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1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64Disassembler.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm-c/Disassembler.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
28 #include <algorithm>
29 #include <memory>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "aarch64-disassembler"
34 
35 // Pull DecodeStatus and its enum values into the global namespace.
37 
38 // Forward declare these because the autogenerated code will reference them.
39 // Definitions are further down.
41  unsigned RegNo, uint64_t Address,
42  const void *Decoder);
44  unsigned RegNo,
45  uint64_t Address,
46  const void *Decoder);
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
48  uint64_t Address,
49  const void *Decoder);
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
51  uint64_t Address,
52  const void *Decoder);
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
54  uint64_t Address,
55  const void *Decoder);
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
57  uint64_t Address,
58  const void *Decoder);
59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
60  uint64_t Address,
61  const void *Decoder);
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
63  uint64_t Address,
64  const void *Decoder);
66  unsigned RegNo,
67  uint64_t Address,
68  const void *Decoder);
70  unsigned RegNo, uint64_t Address,
71  const void *Decoder);
73  unsigned RegNo,
74  uint64_t Address,
75  const void *Decoder);
76 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
77  uint64_t Address,
78  const void *Decoder);
80  unsigned RegNo, uint64_t Address,
81  const void *Decoder);
82 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
83  uint64_t Address,
84  const void *Decoder);
85 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
86  uint64_t Address,
87  const void *Decoder);
88 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
89  uint64_t Address,
90  const void *Decoder);
91 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
92  uint64_t Address,
93  const void *Decoder);
94 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
95  uint64_t Address,
96  const void *Decoder);
97 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
98  uint64_t Address,
99  const void *Decoder);
100 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
101  uint64_t Address,
102  const void *Decoder);
103 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
104  uint64_t Address,
105  const void *Decoder);
106 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
107  uint64_t Address,
108  const void *Decoder);
109 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
110  uint64_t Address,
111  const void *Decoder);
112 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
113  uint64_t Address,
114  const void *Decoder);
115 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
116  uint64_t Address,
117  const void *Decoder);
118 template <unsigned NumBitsForTile>
119 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
120  uint64_t Address, const void *Decoder);
122  unsigned RegMask,
123  uint64_t Address,
124  const void *Decoder);
125 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
126  uint64_t Address,
127  const void *Decoder);
128 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
129  uint64_t Address,
130  const void *Decoder);
131 
132 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
133  uint64_t Address,
134  const void *Decoder);
135 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
136  uint64_t Address,
137  const void *Decoder);
138 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
139  uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
141  uint64_t Address, const void *Decoder);
142 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
143  uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
145  uint64_t Address, const void *Decoder);
147  uint64_t Address,
148  const void *Decoder);
150  uint64_t Address,
151  const void *Decoder);
153  uint64_t Address,
154  const void *Decoder);
156  uint64_t Address,
157  const void *Decoder);
159  uint64_t Address,
160  const void *Decoder);
162  uint64_t Address,
163  const void *Decoder);
165  uint64_t Address,
166  const void *Decoder);
168  uint64_t Address,
169  const void *Decoder);
171  uint64_t Address,
172  const void *Decoder);
174  uint64_t Address,
175  const void *Decoder);
177  uint64_t Address,
178  const void *Decoder);
180  uint64_t Address, const void *Decoder);
182  uint64_t Address, const void *Decoder);
184  uint64_t Address,
185  const void *Decoder);
187  uint64_t Address,
188  const void *Decoder);
190  uint64_t Address, const void *Decoder);
191 
192 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
193  uint64_t Address,
194  const void *Decoder);
195 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
196  uint64_t Addr, const void *Decoder);
197 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
198  uint64_t Addr,
199  const void *Decoder);
200 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
201  uint64_t Addr, const void *Decoder);
202 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
203  uint64_t Addr,
204  const void *Decoder);
205 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
206  uint64_t Addr, const void *Decoder);
207 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
208  uint64_t Addr,
209  const void *Decoder);
210 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
211  uint64_t Addr, const void *Decoder);
212 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
213  uint64_t Addr, const void *Decoder);
214 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
215  uint64_t Addr, const void *Decoder);
216 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
217  uint64_t Addr, const void *Decoder);
218 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
219  uint64_t Addr, const void *Decoder);
221  unsigned RegNo,
222  uint64_t Addr,
223  const void *Decoder);
225  unsigned RegNo,
226  uint64_t Addr,
227  const void *Decoder);
229  uint64_t Address,
230  const void *Decoder);
231 template <int Bits>
232 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
233  const void *Decoder);
234 template <int ElementWidth>
235 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
236  uint64_t Addr, const void *Decoder);
237 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
238  uint64_t Addr, const void *Decoder);
239 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
240  const void *Decoder);
241 
242 static bool Check(DecodeStatus &Out, DecodeStatus In) {
243  switch (In) {
245  // Out stays the same.
246  return true;
248  Out = In;
249  return true;
251  Out = In;
252  return false;
253  }
254  llvm_unreachable("Invalid DecodeStatus!");
255 }
256 
257 #include "AArch64GenDisassemblerTables.inc"
258 #include "AArch64GenInstrInfo.inc"
259 
260 #define Success MCDisassembler::Success
261 #define Fail MCDisassembler::Fail
262 #define SoftFail MCDisassembler::SoftFail
263 
265  const MCSubtargetInfo &STI,
266  MCContext &Ctx) {
267  return new AArch64Disassembler(STI, Ctx);
268 }
269 
271  ArrayRef<uint8_t> Bytes,
272  uint64_t Address,
273  raw_ostream &CS) const {
274  CommentStream = &CS;
275 
276  Size = 0;
277  // We want to read exactly 4 bytes of data.
278  if (Bytes.size() < 4)
279  return Fail;
280  Size = 4;
281 
282  // Encoded as a small-endian 32-bit word in the stream.
283  uint32_t Insn =
284  (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
285 
286  const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
287 
288  for (auto Table : Tables) {
289  DecodeStatus Result =
290  decodeInstruction(Table, MI, Insn, Address, this, STI);
291 
292  switch (MI.getOpcode()) {
293  default:
294  break;
295  // For Scalable Matrix Extension (SME) instructions that have an implicit
296  // operand for the accumulator (ZA) which isn't encoded, manually insert
297  // operand.
298  case AArch64::LDR_ZA:
299  case AArch64::STR_ZA: {
300  MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA));
301  // Spill and fill instructions have a single immediate used for both the
302  // vector select offset and optional memory offset. Replicate the decoded
303  // immediate.
304  const MCOperand &Imm4Op = MI.getOperand(2);
305  assert(Imm4Op.isImm() && "Unexpected operand type!");
306  MI.addOperand(Imm4Op);
307  break;
308  }
309  case AArch64::LD1_MXIPXX_H_B:
310  case AArch64::LD1_MXIPXX_V_B:
311  case AArch64::ST1_MXIPXX_H_B:
312  case AArch64::ST1_MXIPXX_V_B:
313  case AArch64::INSERT_MXIPZ_H_B:
314  case AArch64::INSERT_MXIPZ_V_B:
315  // e.g.
316  // MOVA ZA0<HV>.B[<Ws>, <imm>], <Pg>/M, <Zn>.B
317  // ^ insert implicit 8-bit element tile
318  MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0));
319  break;
320  case AArch64::EXTRACT_ZPMXI_H_B:
321  case AArch64::EXTRACT_ZPMXI_V_B:
322  // MOVA <Zd>.B, <Pg>/M, ZA0<HV>.B[<Ws>, <imm>]
323  // ^ insert implicit 8-bit element tile
324  MI.insert(MI.begin()+2, MCOperand::createReg(AArch64::ZAB0));
325  break;
326  case AArch64::SMOVvi8to32_idx0:
327  case AArch64::SMOVvi8to64_idx0:
328  case AArch64::SMOVvi16to32_idx0:
329  case AArch64::SMOVvi16to64_idx0:
330  case AArch64::SMOVvi32to64_idx0:
331  case AArch64::UMOVvi8_idx0:
332  case AArch64::UMOVvi16_idx0:
333  case AArch64::UMOVvi32_idx0:
334  case AArch64::UMOVvi64_idx0:
335  MI.addOperand(MCOperand::createImm(0));
336  break;
337  }
338 
339  if (Result != MCDisassembler::Fail)
340  return Result;
341  }
342 
343  return MCDisassembler::Fail;
344 }
345 
346 static MCSymbolizer *
348  LLVMSymbolLookupCallback SymbolLookUp,
349  void *DisInfo, MCContext *Ctx,
350  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
351  return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
352  SymbolLookUp, DisInfo);
353 }
354 
368 
377 }
378 
379 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
380  uint64_t Addr,
381  const void *Decoder) {
382  if (RegNo > 31)
383  return Fail;
384 
385  unsigned Register =
386  AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
388  return Success;
389 }
390 
391 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
392  uint64_t Addr,
393  const void *Decoder) {
394  if (RegNo > 15)
395  return Fail;
396  return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
397 }
398 
399 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
400  uint64_t Addr,
401  const void *Decoder) {
402  if (RegNo > 31)
403  return Fail;
404 
405  unsigned Register =
406  AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
408  return Success;
409 }
410 
411 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
412  uint64_t Addr,
413  const void *Decoder) {
414  if (RegNo > 31)
415  return Fail;
416 
417  unsigned Register =
418  AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
420  return Success;
421 }
422 
423 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
424  uint64_t Addr,
425  const void *Decoder) {
426  if (RegNo > 31)
427  return Fail;
428 
429  unsigned Register =
430  AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
432  return Success;
433 }
434 
435 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
436  uint64_t Addr,
437  const void *Decoder) {
438  if (RegNo > 31)
439  return Fail;
440 
441  unsigned Register =
442  AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
444  return Success;
445 }
446 
448  uint64_t Addr,
449  const void *Decoder) {
450  if (RegNo > 30)
451  return Fail;
452 
453  unsigned Register =
454  AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
455  RegNo);
457  return Success;
458 }
459 
460 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
461  uint64_t Addr,
462  const void *Decoder) {
463  if (RegNo > 31)
464  return Fail;
465 
466  unsigned Register =
467  AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
469  return Success;
470 }
471 
473  unsigned RegNo,
474  uint64_t Address,
475  const void *Decoder) {
476  if (RegNo > 22)
477  return Fail;
478  if (RegNo & 1)
479  return Fail;
480 
481  unsigned Register =
482  AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
483  RegNo >> 1);
485  return Success;
486 }
487 
488 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
489  uint64_t Addr,
490  const void *Decoder) {
491  if (RegNo > 31)
492  return Fail;
493  unsigned Register =
494  AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
496  return Success;
497 }
498 
500  unsigned RegNo,
501  uint64_t Addr,
502  const void *Decoder) {
503  if (RegNo > 3)
504  return Fail;
505 
506  unsigned Register =
507  AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
508  .getRegister(RegNo);
510  return Success;
511 }
512 
513 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
514  uint64_t Addr,
515  const void *Decoder) {
516  if (RegNo > 31)
517  return Fail;
518 
519  unsigned Register =
520  AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
522  return Success;
523 }
524 
525 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
526  uint64_t Addr,
527  const void *Decoder) {
528  if (RegNo > 31)
529  return Fail;
530 
531  unsigned Register =
532  AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
534  return Success;
535 }
536 
537 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
538  uint64_t Address,
539  const void* Decoder) {
540  if (RegNo > 31)
541  return Fail;
542 
543  unsigned Register =
544  AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
546  return Success;
547 }
548 
549 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
550  uint64_t Address,
551  const void *Decoder) {
552  if (RegNo > 15)
553  return Fail;
554  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
555 }
556 
557 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
558  uint64_t Address,
559  const void *Decoder) {
560  if (RegNo > 7)
561  return Fail;
562  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
563 }
564 
565 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
566  uint64_t Address,
567  const void* Decoder) {
568  if (RegNo > 31)
569  return Fail;
570  unsigned Register =
571  AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
573  return Success;
574 }
575 
576 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
577  uint64_t Address,
578  const void* Decoder) {
579  if (RegNo > 31)
580  return Fail;
581  unsigned Register =
582  AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
584  return Success;
585 }
586 
587 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
588  uint64_t Address,
589  const void* Decoder) {
590  if (RegNo > 31)
591  return Fail;
592  unsigned Register =
593  AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
595  return Success;
596 }
597 
599  unsigned RegMask,
600  uint64_t Address,
601  const void *Decoder) {
602  if (RegMask > 0xFF)
603  return Fail;
604  Inst.addOperand(MCOperand::createImm(RegMask));
605  return Success;
606 }
607 
610  {AArch64::ZAB0},
611  {AArch64::ZAH0, AArch64::ZAH1},
612  {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
613  {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3,
614  AArch64::ZAD4, AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
615  {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3,
616  AArch64::ZAQ4, AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7,
617  AArch64::ZAQ8, AArch64::ZAQ9, AArch64::ZAQ10, AArch64::ZAQ11,
618  AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}};
619 
620 template <unsigned NumBitsForTile>
621 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
622  uint64_t Address, const void *Decoder) {
623  unsigned LastReg = (1 << NumBitsForTile) - 1;
624  if (RegNo > LastReg)
625  return Fail;
626  Inst.addOperand(
627  MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
628  return Success;
629 }
630 
631 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
632  uint64_t Addr, const void *Decoder) {
633  if (RegNo > 15)
634  return Fail;
635 
636  unsigned Register =
637  AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
639  return Success;
640 }
641 
642 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
643  uint64_t Addr,
644  const void* Decoder) {
645  if (RegNo > 7)
646  return Fail;
647 
648  // Just reuse the PPR decode table
649  return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
650 }
651 
652 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
653  uint64_t Addr, const void *Decoder) {
654  if (RegNo > 31)
655  return Fail;
656  unsigned Register =
657  AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
659  return Success;
660 }
661 
662 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
663  uint64_t Addr, const void *Decoder) {
664  if (RegNo > 31)
665  return Fail;
666  unsigned Register =
667  AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
669  return Success;
670 }
671 
672 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
673  uint64_t Addr,
674  const void *Decoder) {
675  if (RegNo > 31)
676  return Fail;
677  unsigned Register =
678  AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
680  return Success;
681 }
682 
683 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
684  uint64_t Addr, const void *Decoder) {
685  if (RegNo > 31)
686  return Fail;
687  unsigned Register =
688  AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
690  return Success;
691 }
692 
693 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
694  uint64_t Addr, const void *Decoder) {
695  if (RegNo > 31)
696  return Fail;
697  unsigned Register =
698  AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
700  return Success;
701 }
702 
703 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
704  uint64_t Addr,
705  const void *Decoder) {
706  if (RegNo > 31)
707  return Fail;
708  unsigned Register =
709  AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
711  return Success;
712 }
713 
714 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
715  uint64_t Addr,
716  const void *Decoder) {
717  // scale{5} is asserted as 1 in tblgen.
718  Imm |= 0x20;
719  Inst.addOperand(MCOperand::createImm(64 - Imm));
720  return Success;
721 }
722 
723 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
724  uint64_t Addr,
725  const void *Decoder) {
726  Inst.addOperand(MCOperand::createImm(64 - Imm));
727  return Success;
728 }
729 
730 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
731  uint64_t Addr, const void *Decoder) {
732  int64_t ImmVal = Imm;
733  const AArch64Disassembler *Dis =
734  static_cast<const AArch64Disassembler *>(Decoder);
735 
736  // Sign-extend 19-bit immediate.
737  if (ImmVal & (1 << (19 - 1)))
738  ImmVal |= ~((1LL << 19) - 1);
739 
740  if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
741  Inst.getOpcode() != AArch64::LDRXl, 0, 4))
742  Inst.addOperand(MCOperand::createImm(ImmVal));
743  return Success;
744 }
745 
746 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
747  uint64_t Address, const void *Decoder) {
748  Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
749  Inst.addOperand(MCOperand::createImm(Imm & 1));
750  return Success;
751 }
752 
753 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
754  uint64_t Address,
755  const void *Decoder) {
756  Inst.addOperand(MCOperand::createImm(Imm));
757 
758  // Every system register in the encoding space is valid with the syntax
759  // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
760  return Success;
761 }
762 
763 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
764  uint64_t Address,
765  const void *Decoder) {
766  Inst.addOperand(MCOperand::createImm(Imm));
767 
768  return Success;
769 }
770 
771 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
772  uint64_t Address,
773  const void *Decoder) {
774  // This decoder exists to add the dummy Lane operand to the MCInst, which must
775  // be 1 in assembly but has no other real manifestation.
776  unsigned Rd = fieldFromInstruction(Insn, 0, 5);
777  unsigned Rn = fieldFromInstruction(Insn, 5, 5);
778  unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
779 
780  if (IsToVec) {
781  DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
782  DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
783  } else {
784  DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
785  DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
786  }
787 
788  // Add the lane
790 
791  return Success;
792 }
793 
794 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
795  unsigned Add) {
796  Inst.addOperand(MCOperand::createImm(Add - Imm));
797  return Success;
798 }
799 
800 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
801  unsigned Add) {
802  Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
803  return Success;
804 }
805 
806 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
807  uint64_t Addr, const void *Decoder) {
808  return DecodeVecShiftRImm(Inst, Imm, 64);
809 }
810 
811 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
812  uint64_t Addr,
813  const void *Decoder) {
814  return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
815 }
816 
817 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
818  uint64_t Addr, const void *Decoder) {
819  return DecodeVecShiftRImm(Inst, Imm, 32);
820 }
821 
822 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
823  uint64_t Addr,
824  const void *Decoder) {
825  return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
826 }
827 
828 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
829  uint64_t Addr, const void *Decoder) {
830  return DecodeVecShiftRImm(Inst, Imm, 16);
831 }
832 
833 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
834  uint64_t Addr,
835  const void *Decoder) {
836  return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
837 }
838 
839 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
840  uint64_t Addr, const void *Decoder) {
841  return DecodeVecShiftRImm(Inst, Imm, 8);
842 }
843 
844 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
845  uint64_t Addr, const void *Decoder) {
846  return DecodeVecShiftLImm(Inst, Imm, 64);
847 }
848 
849 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
850  uint64_t Addr, const void *Decoder) {
851  return DecodeVecShiftLImm(Inst, Imm, 32);
852 }
853 
854 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
855  uint64_t Addr, const void *Decoder) {
856  return DecodeVecShiftLImm(Inst, Imm, 16);
857 }
858 
859 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
860  uint64_t Addr, const void *Decoder) {
861  return DecodeVecShiftLImm(Inst, Imm, 8);
862 }
863 
865  uint64_t Addr,
866  const void *Decoder) {
867  unsigned Rd = fieldFromInstruction(insn, 0, 5);
868  unsigned Rn = fieldFromInstruction(insn, 5, 5);
869  unsigned Rm = fieldFromInstruction(insn, 16, 5);
870  unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
871  unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
872  unsigned shift = (shiftHi << 6) | shiftLo;
873  switch (Inst.getOpcode()) {
874  default:
875  return Fail;
876  case AArch64::ADDWrs:
877  case AArch64::ADDSWrs:
878  case AArch64::SUBWrs:
879  case AArch64::SUBSWrs:
880  // if shift == '11' then ReservedValue()
881  if (shiftHi == 0x3)
882  return Fail;
884  case AArch64::ANDWrs:
885  case AArch64::ANDSWrs:
886  case AArch64::BICWrs:
887  case AArch64::BICSWrs:
888  case AArch64::ORRWrs:
889  case AArch64::ORNWrs:
890  case AArch64::EORWrs:
891  case AArch64::EONWrs: {
892  // if sf == '0' and imm6<5> == '1' then ReservedValue()
893  if (shiftLo >> 5 == 1)
894  return Fail;
895  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
896  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
897  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
898  break;
899  }
900  case AArch64::ADDXrs:
901  case AArch64::ADDSXrs:
902  case AArch64::SUBXrs:
903  case AArch64::SUBSXrs:
904  // if shift == '11' then ReservedValue()
905  if (shiftHi == 0x3)
906  return Fail;
908  case AArch64::ANDXrs:
909  case AArch64::ANDSXrs:
910  case AArch64::BICXrs:
911  case AArch64::BICSXrs:
912  case AArch64::ORRXrs:
913  case AArch64::ORNXrs:
914  case AArch64::EORXrs:
915  case AArch64::EONXrs:
916  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
917  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
918  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
919  break;
920  }
921 
923  return Success;
924 }
925 
927  uint64_t Addr,
928  const void *Decoder) {
929  unsigned Rd = fieldFromInstruction(insn, 0, 5);
930  unsigned imm = fieldFromInstruction(insn, 5, 16);
931  unsigned shift = fieldFromInstruction(insn, 21, 2);
932  shift <<= 4;
933  switch (Inst.getOpcode()) {
934  default:
935  return Fail;
936  case AArch64::MOVZWi:
937  case AArch64::MOVNWi:
938  case AArch64::MOVKWi:
939  if (shift & (1U << 5))
940  return Fail;
941  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
942  break;
943  case AArch64::MOVZXi:
944  case AArch64::MOVNXi:
945  case AArch64::MOVKXi:
946  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
947  break;
948  }
949 
950  if (Inst.getOpcode() == AArch64::MOVKWi ||
951  Inst.getOpcode() == AArch64::MOVKXi)
952  Inst.addOperand(Inst.getOperand(0));
953 
954  Inst.addOperand(MCOperand::createImm(imm));
956  return Success;
957 }
958 
960  uint64_t Addr,
961  const void *Decoder) {
962  unsigned Rt = fieldFromInstruction(insn, 0, 5);
963  unsigned Rn = fieldFromInstruction(insn, 5, 5);
964  unsigned offset = fieldFromInstruction(insn, 10, 12);
965  const AArch64Disassembler *Dis =
966  static_cast<const AArch64Disassembler *>(Decoder);
967 
968  switch (Inst.getOpcode()) {
969  default:
970  return Fail;
971  case AArch64::PRFMui:
972  // Rt is an immediate in prefetch.
974  break;
975  case AArch64::STRBBui:
976  case AArch64::LDRBBui:
977  case AArch64::LDRSBWui:
978  case AArch64::STRHHui:
979  case AArch64::LDRHHui:
980  case AArch64::LDRSHWui:
981  case AArch64::STRWui:
982  case AArch64::LDRWui:
983  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
984  break;
985  case AArch64::LDRSBXui:
986  case AArch64::LDRSHXui:
987  case AArch64::LDRSWui:
988  case AArch64::STRXui:
989  case AArch64::LDRXui:
990  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
991  break;
992  case AArch64::LDRQui:
993  case AArch64::STRQui:
994  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
995  break;
996  case AArch64::LDRDui:
997  case AArch64::STRDui:
998  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
999  break;
1000  case AArch64::LDRSui:
1001  case AArch64::STRSui:
1002  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1003  break;
1004  case AArch64::LDRHui:
1005  case AArch64::STRHui:
1006  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1007  break;
1008  case AArch64::LDRBui:
1009  case AArch64::STRBui:
1010  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1011  break;
1012  }
1013 
1014  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1015  if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
1016  Inst.addOperand(MCOperand::createImm(offset));
1017  return Success;
1018 }
1019 
1021  uint64_t Addr,
1022  const void *Decoder) {
1023  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1024  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1025  int64_t offset = fieldFromInstruction(insn, 12, 9);
1026 
1027  // offset is a 9-bit signed immediate, so sign extend it to
1028  // fill the unsigned.
1029  if (offset & (1 << (9 - 1)))
1030  offset |= ~((1LL << 9) - 1);
1031 
1032  // First operand is always the writeback to the address register, if needed.
1033  switch (Inst.getOpcode()) {
1034  default:
1035  break;
1036  case AArch64::LDRSBWpre:
1037  case AArch64::LDRSHWpre:
1038  case AArch64::STRBBpre:
1039  case AArch64::LDRBBpre:
1040  case AArch64::STRHHpre:
1041  case AArch64::LDRHHpre:
1042  case AArch64::STRWpre:
1043  case AArch64::LDRWpre:
1044  case AArch64::LDRSBWpost:
1045  case AArch64::LDRSHWpost:
1046  case AArch64::STRBBpost:
1047  case AArch64::LDRBBpost:
1048  case AArch64::STRHHpost:
1049  case AArch64::LDRHHpost:
1050  case AArch64::STRWpost:
1051  case AArch64::LDRWpost:
1052  case AArch64::LDRSBXpre:
1053  case AArch64::LDRSHXpre:
1054  case AArch64::STRXpre:
1055  case AArch64::LDRSWpre:
1056  case AArch64::LDRXpre:
1057  case AArch64::LDRSBXpost:
1058  case AArch64::LDRSHXpost:
1059  case AArch64::STRXpost:
1060  case AArch64::LDRSWpost:
1061  case AArch64::LDRXpost:
1062  case AArch64::LDRQpre:
1063  case AArch64::STRQpre:
1064  case AArch64::LDRQpost:
1065  case AArch64::STRQpost:
1066  case AArch64::LDRDpre:
1067  case AArch64::STRDpre:
1068  case AArch64::LDRDpost:
1069  case AArch64::STRDpost:
1070  case AArch64::LDRSpre:
1071  case AArch64::STRSpre:
1072  case AArch64::LDRSpost:
1073  case AArch64::STRSpost:
1074  case AArch64::LDRHpre:
1075  case AArch64::STRHpre:
1076  case AArch64::LDRHpost:
1077  case AArch64::STRHpost:
1078  case AArch64::LDRBpre:
1079  case AArch64::STRBpre:
1080  case AArch64::LDRBpost:
1081  case AArch64::STRBpost:
1082  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1083  break;
1084  }
1085 
1086  switch (Inst.getOpcode()) {
1087  default:
1088  return Fail;
1089  case AArch64::PRFUMi:
1090  // Rt is an immediate in prefetch.
1091  Inst.addOperand(MCOperand::createImm(Rt));
1092  break;
1093  case AArch64::STURBBi:
1094  case AArch64::LDURBBi:
1095  case AArch64::LDURSBWi:
1096  case AArch64::STURHHi:
1097  case AArch64::LDURHHi:
1098  case AArch64::LDURSHWi:
1099  case AArch64::STURWi:
1100  case AArch64::LDURWi:
1101  case AArch64::LDTRSBWi:
1102  case AArch64::LDTRSHWi:
1103  case AArch64::STTRWi:
1104  case AArch64::LDTRWi:
1105  case AArch64::STTRHi:
1106  case AArch64::LDTRHi:
1107  case AArch64::LDTRBi:
1108  case AArch64::STTRBi:
1109  case AArch64::LDRSBWpre:
1110  case AArch64::LDRSHWpre:
1111  case AArch64::STRBBpre:
1112  case AArch64::LDRBBpre:
1113  case AArch64::STRHHpre:
1114  case AArch64::LDRHHpre:
1115  case AArch64::STRWpre:
1116  case AArch64::LDRWpre:
1117  case AArch64::LDRSBWpost:
1118  case AArch64::LDRSHWpost:
1119  case AArch64::STRBBpost:
1120  case AArch64::LDRBBpost:
1121  case AArch64::STRHHpost:
1122  case AArch64::LDRHHpost:
1123  case AArch64::STRWpost:
1124  case AArch64::LDRWpost:
1125  case AArch64::STLURBi:
1126  case AArch64::STLURHi:
1127  case AArch64::STLURWi:
1128  case AArch64::LDAPURBi:
1129  case AArch64::LDAPURSBWi:
1130  case AArch64::LDAPURHi:
1131  case AArch64::LDAPURSHWi:
1132  case AArch64::LDAPURi:
1133  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1134  break;
1135  case AArch64::LDURSBXi:
1136  case AArch64::LDURSHXi:
1137  case AArch64::LDURSWi:
1138  case AArch64::STURXi:
1139  case AArch64::LDURXi:
1140  case AArch64::LDTRSBXi:
1141  case AArch64::LDTRSHXi:
1142  case AArch64::LDTRSWi:
1143  case AArch64::STTRXi:
1144  case AArch64::LDTRXi:
1145  case AArch64::LDRSBXpre:
1146  case AArch64::LDRSHXpre:
1147  case AArch64::STRXpre:
1148  case AArch64::LDRSWpre:
1149  case AArch64::LDRXpre:
1150  case AArch64::LDRSBXpost:
1151  case AArch64::LDRSHXpost:
1152  case AArch64::STRXpost:
1153  case AArch64::LDRSWpost:
1154  case AArch64::LDRXpost:
1155  case AArch64::LDAPURSWi:
1156  case AArch64::LDAPURSHXi:
1157  case AArch64::LDAPURSBXi:
1158  case AArch64::STLURXi:
1159  case AArch64::LDAPURXi:
1160  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1161  break;
1162  case AArch64::LDURQi:
1163  case AArch64::STURQi:
1164  case AArch64::LDRQpre:
1165  case AArch64::STRQpre:
1166  case AArch64::LDRQpost:
1167  case AArch64::STRQpost:
1168  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1169  break;
1170  case AArch64::LDURDi:
1171  case AArch64::STURDi:
1172  case AArch64::LDRDpre:
1173  case AArch64::STRDpre:
1174  case AArch64::LDRDpost:
1175  case AArch64::STRDpost:
1176  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1177  break;
1178  case AArch64::LDURSi:
1179  case AArch64::STURSi:
1180  case AArch64::LDRSpre:
1181  case AArch64::STRSpre:
1182  case AArch64::LDRSpost:
1183  case AArch64::STRSpost:
1184  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1185  break;
1186  case AArch64::LDURHi:
1187  case AArch64::STURHi:
1188  case AArch64::LDRHpre:
1189  case AArch64::STRHpre:
1190  case AArch64::LDRHpost:
1191  case AArch64::STRHpost:
1192  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1193  break;
1194  case AArch64::LDURBi:
1195  case AArch64::STURBi:
1196  case AArch64::LDRBpre:
1197  case AArch64::STRBpre:
1198  case AArch64::LDRBpost:
1199  case AArch64::STRBpost:
1200  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1201  break;
1202  }
1203 
1204  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1205  Inst.addOperand(MCOperand::createImm(offset));
1206 
1207  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1208  bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1209  bool IsFP = fieldFromInstruction(insn, 26, 1);
1210 
1211  // Cannot write back to a transfer register (but xzr != sp).
1212  if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1213  return SoftFail;
1214 
1215  return Success;
1216 }
1217 
1219  uint64_t Addr,
1220  const void *Decoder) {
1221  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1222  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1223  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1224  unsigned Rs = fieldFromInstruction(insn, 16, 5);
1225 
1226  unsigned Opcode = Inst.getOpcode();
1227  switch (Opcode) {
1228  default:
1229  return Fail;
1230  case AArch64::STLXRW:
1231  case AArch64::STLXRB:
1232  case AArch64::STLXRH:
1233  case AArch64::STXRW:
1234  case AArch64::STXRB:
1235  case AArch64::STXRH:
1236  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1238  case AArch64::LDARW:
1239  case AArch64::LDARB:
1240  case AArch64::LDARH:
1241  case AArch64::LDAXRW:
1242  case AArch64::LDAXRB:
1243  case AArch64::LDAXRH:
1244  case AArch64::LDXRW:
1245  case AArch64::LDXRB:
1246  case AArch64::LDXRH:
1247  case AArch64::STLRW:
1248  case AArch64::STLRB:
1249  case AArch64::STLRH:
1250  case AArch64::STLLRW:
1251  case AArch64::STLLRB:
1252  case AArch64::STLLRH:
1253  case AArch64::LDLARW:
1254  case AArch64::LDLARB:
1255  case AArch64::LDLARH:
1256  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1257  break;
1258  case AArch64::STLXRX:
1259  case AArch64::STXRX:
1260  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1262  case AArch64::LDARX:
1263  case AArch64::LDAXRX:
1264  case AArch64::LDXRX:
1265  case AArch64::STLRX:
1266  case AArch64::LDLARX:
1267  case AArch64::STLLRX:
1268  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1269  break;
1270  case AArch64::STLXPW:
1271  case AArch64::STXPW:
1272  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1274  case AArch64::LDAXPW:
1275  case AArch64::LDXPW:
1276  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1277  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1278  break;
1279  case AArch64::STLXPX:
1280  case AArch64::STXPX:
1281  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1283  case AArch64::LDAXPX:
1284  case AArch64::LDXPX:
1285  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1286  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1287  break;
1288  }
1289 
1290  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1291 
1292  // You shouldn't load to the same register twice in an instruction...
1293  if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1294  Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1295  Rt == Rt2)
1296  return SoftFail;
1297 
1298  return Success;
1299 }
1300 
1302  uint64_t Addr,
1303  const void *Decoder) {
1304  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1305  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1306  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1307  int64_t offset = fieldFromInstruction(insn, 15, 7);
1308  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1309 
1310  // offset is a 7-bit signed immediate, so sign extend it to
1311  // fill the unsigned.
1312  if (offset & (1 << (7 - 1)))
1313  offset |= ~((1LL << 7) - 1);
1314 
1315  unsigned Opcode = Inst.getOpcode();
1316  bool NeedsDisjointWritebackTransfer = false;
1317 
1318  // First operand is always writeback of base register.
1319  switch (Opcode) {
1320  default:
1321  break;
1322  case AArch64::LDPXpost:
1323  case AArch64::STPXpost:
1324  case AArch64::LDPSWpost:
1325  case AArch64::LDPXpre:
1326  case AArch64::STPXpre:
1327  case AArch64::LDPSWpre:
1328  case AArch64::LDPWpost:
1329  case AArch64::STPWpost:
1330  case AArch64::LDPWpre:
1331  case AArch64::STPWpre:
1332  case AArch64::LDPQpost:
1333  case AArch64::STPQpost:
1334  case AArch64::LDPQpre:
1335  case AArch64::STPQpre:
1336  case AArch64::LDPDpost:
1337  case AArch64::STPDpost:
1338  case AArch64::LDPDpre:
1339  case AArch64::STPDpre:
1340  case AArch64::LDPSpost:
1341  case AArch64::STPSpost:
1342  case AArch64::LDPSpre:
1343  case AArch64::STPSpre:
1344  case AArch64::STGPpre:
1345  case AArch64::STGPpost:
1346  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1347  break;
1348  }
1349 
1350  switch (Opcode) {
1351  default:
1352  return Fail;
1353  case AArch64::LDPXpost:
1354  case AArch64::STPXpost:
1355  case AArch64::LDPSWpost:
1356  case AArch64::LDPXpre:
1357  case AArch64::STPXpre:
1358  case AArch64::LDPSWpre:
1359  case AArch64::STGPpre:
1360  case AArch64::STGPpost:
1361  NeedsDisjointWritebackTransfer = true;
1363  case AArch64::LDNPXi:
1364  case AArch64::STNPXi:
1365  case AArch64::LDPXi:
1366  case AArch64::STPXi:
1367  case AArch64::LDPSWi:
1368  case AArch64::STGPi:
1369  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1370  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1371  break;
1372  case AArch64::LDPWpost:
1373  case AArch64::STPWpost:
1374  case AArch64::LDPWpre:
1375  case AArch64::STPWpre:
1376  NeedsDisjointWritebackTransfer = true;
1378  case AArch64::LDNPWi:
1379  case AArch64::STNPWi:
1380  case AArch64::LDPWi:
1381  case AArch64::STPWi:
1382  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1383  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1384  break;
1385  case AArch64::LDNPQi:
1386  case AArch64::STNPQi:
1387  case AArch64::LDPQpost:
1388  case AArch64::STPQpost:
1389  case AArch64::LDPQi:
1390  case AArch64::STPQi:
1391  case AArch64::LDPQpre:
1392  case AArch64::STPQpre:
1393  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1394  DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1395  break;
1396  case AArch64::LDNPDi:
1397  case AArch64::STNPDi:
1398  case AArch64::LDPDpost:
1399  case AArch64::STPDpost:
1400  case AArch64::LDPDi:
1401  case AArch64::STPDi:
1402  case AArch64::LDPDpre:
1403  case AArch64::STPDpre:
1404  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1405  DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1406  break;
1407  case AArch64::LDNPSi:
1408  case AArch64::STNPSi:
1409  case AArch64::LDPSpost:
1410  case AArch64::STPSpost:
1411  case AArch64::LDPSi:
1412  case AArch64::STPSi:
1413  case AArch64::LDPSpre:
1414  case AArch64::STPSpre:
1415  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1416  DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1417  break;
1418  }
1419 
1420  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1421  Inst.addOperand(MCOperand::createImm(offset));
1422 
1423  // You shouldn't load to the same register twice in an instruction...
1424  if (IsLoad && Rt == Rt2)
1425  return SoftFail;
1426 
1427  // ... or do any operation that writes-back to a transfer register. But note
1428  // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1429  if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1430  return SoftFail;
1431 
1432  return Success;
1433 }
1434 
1436  uint64_t Addr,
1437  const void *Decoder) {
1438  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1439  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1440  uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1441  fieldFromInstruction(insn, 12, 9);
1442  unsigned writeback = fieldFromInstruction(insn, 11, 1);
1443 
1444  switch (Inst.getOpcode()) {
1445  default:
1446  return Fail;
1447  case AArch64::LDRAAwriteback:
1448  case AArch64::LDRABwriteback:
1449  DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1450  Decoder);
1451  break;
1452  case AArch64::LDRAAindexed:
1453  case AArch64::LDRABindexed:
1454  break;
1455  }
1456 
1457  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1458  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1459  DecodeSImm<10>(Inst, offset, Addr, Decoder);
1460 
1461  if (writeback && Rt == Rn && Rn != 31) {
1462  return SoftFail;
1463  }
1464 
1465  return Success;
1466 }
1467 
1469  uint64_t Addr,
1470  const void *Decoder) {
1471  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1472  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1473  unsigned Rm = fieldFromInstruction(insn, 16, 5);
1474  unsigned extend = fieldFromInstruction(insn, 10, 6);
1475 
1476  unsigned shift = extend & 0x7;
1477  if (shift > 4)
1478  return Fail;
1479 
1480  switch (Inst.getOpcode()) {
1481  default:
1482  return Fail;
1483  case AArch64::ADDWrx:
1484  case AArch64::SUBWrx:
1485  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1486  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1487  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1488  break;
1489  case AArch64::ADDSWrx:
1490  case AArch64::SUBSWrx:
1491  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1492  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1493  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1494  break;
1495  case AArch64::ADDXrx:
1496  case AArch64::SUBXrx:
1497  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1498  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1499  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1500  break;
1501  case AArch64::ADDSXrx:
1502  case AArch64::SUBSXrx:
1503  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1504  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1505  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1506  break;
1507  case AArch64::ADDXrx64:
1508  case AArch64::SUBXrx64:
1509  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1510  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1511  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1512  break;
1513  case AArch64::SUBSXrx64:
1514  case AArch64::ADDSXrx64:
1515  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1516  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1517  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1518  break;
1519  }
1520 
1522  return Success;
1523 }
1524 
1526  uint64_t Addr,
1527  const void *Decoder) {
1528  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1529  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1530  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1531  unsigned imm;
1532 
1533  if (Datasize) {
1534  if (Inst.getOpcode() == AArch64::ANDSXri)
1535  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1536  else
1537  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1538  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1539  imm = fieldFromInstruction(insn, 10, 13);
1541  return Fail;
1542  } else {
1543  if (Inst.getOpcode() == AArch64::ANDSWri)
1544  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1545  else
1546  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1547  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1548  imm = fieldFromInstruction(insn, 10, 12);
1550  return Fail;
1551  }
1552  Inst.addOperand(MCOperand::createImm(imm));
1553  return Success;
1554 }
1555 
1557  uint64_t Addr,
1558  const void *Decoder) {
1559  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1560  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1561  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1562  imm |= fieldFromInstruction(insn, 5, 5);
1563 
1564  if (Inst.getOpcode() == AArch64::MOVID)
1565  DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1566  else
1567  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1568 
1569  Inst.addOperand(MCOperand::createImm(imm));
1570 
1571  switch (Inst.getOpcode()) {
1572  default:
1573  break;
1574  case AArch64::MOVIv4i16:
1575  case AArch64::MOVIv8i16:
1576  case AArch64::MVNIv4i16:
1577  case AArch64::MVNIv8i16:
1578  case AArch64::MOVIv2i32:
1579  case AArch64::MOVIv4i32:
1580  case AArch64::MVNIv2i32:
1581  case AArch64::MVNIv4i32:
1582  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1583  break;
1584  case AArch64::MOVIv2s_msl:
1585  case AArch64::MOVIv4s_msl:
1586  case AArch64::MVNIv2s_msl:
1587  case AArch64::MVNIv4s_msl:
1588  Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1589  break;
1590  }
1591 
1592  return Success;
1593 }
1594 
1596  uint64_t Addr,
1597  const void *Decoder) {
1598  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1599  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1600  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1601  imm |= fieldFromInstruction(insn, 5, 5);
1602 
1603  // Tied operands added twice.
1604  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1605  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1606 
1607  Inst.addOperand(MCOperand::createImm(imm));
1608  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1609 
1610  return Success;
1611 }
1612 
1614  uint64_t Addr, const void *Decoder) {
1615  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1616  int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1617  imm |= fieldFromInstruction(insn, 29, 2);
1618  const AArch64Disassembler *Dis =
1619  static_cast<const AArch64Disassembler *>(Decoder);
1620 
1621  // Sign-extend the 21-bit immediate.
1622  if (imm & (1 << (21 - 1)))
1623  imm |= ~((1LL << 21) - 1);
1624 
1625  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1626  if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1627  Inst.addOperand(MCOperand::createImm(imm));
1628 
1629  return Success;
1630 }
1631 
1633  uint64_t Addr, const void *Decoder) {
1634  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1635  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1636  unsigned Imm = fieldFromInstruction(insn, 10, 14);
1637  unsigned S = fieldFromInstruction(insn, 29, 1);
1638  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1639 
1640  unsigned ShifterVal = (Imm >> 12) & 3;
1641  unsigned ImmVal = Imm & 0xFFF;
1642  const AArch64Disassembler *Dis =
1643  static_cast<const AArch64Disassembler *>(Decoder);
1644 
1645  if (ShifterVal != 0 && ShifterVal != 1)
1646  return Fail;
1647 
1648  if (Datasize) {
1649  if (Rd == 31 && !S)
1650  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1651  else
1652  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1653  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1654  } else {
1655  if (Rd == 31 && !S)
1656  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1657  else
1658  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1659  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1660  }
1661 
1662  if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1663  Inst.addOperand(MCOperand::createImm(ImmVal));
1664  Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1665  return Success;
1666 }
1667 
1669  uint64_t Addr,
1670  const void *Decoder) {
1671  int64_t imm = fieldFromInstruction(insn, 0, 26);
1672  const AArch64Disassembler *Dis =
1673  static_cast<const AArch64Disassembler *>(Decoder);
1674 
1675  // Sign-extend the 26-bit immediate.
1676  if (imm & (1 << (26 - 1)))
1677  imm |= ~((1LL << 26) - 1);
1678 
1679  if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1680  Inst.addOperand(MCOperand::createImm(imm));
1681 
1682  return Success;
1683 }
1684 
1686  uint64_t Addr,
1687  const void *Decoder) {
1688  uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1689  uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1690  uint64_t crm = fieldFromInstruction(insn, 8, 4);
1691  uint64_t pstate_field = (op1 << 3) | op2;
1692 
1693  switch (pstate_field) {
1694  case 0x01: // XAFlag
1695  case 0x02: // AXFlag
1696  return Fail;
1697  }
1698 
1699  if ((pstate_field == AArch64PState::PAN ||
1700  pstate_field == AArch64PState::UAO ||
1701  pstate_field == AArch64PState::SSBS) && crm > 1)
1702  return Fail;
1703 
1704  Inst.addOperand(MCOperand::createImm(pstate_field));
1705  Inst.addOperand(MCOperand::createImm(crm));
1706 
1707  const AArch64Disassembler *Dis =
1708  static_cast<const AArch64Disassembler *>(Decoder);
1709  auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1710  if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1711  return Success;
1712  return Fail;
1713 }
1714 
1716  uint64_t Addr, const void *Decoder) {
1717  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1718  uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1719  bit |= fieldFromInstruction(insn, 19, 5);
1720  int64_t dst = fieldFromInstruction(insn, 5, 14);
1721  const AArch64Disassembler *Dis =
1722  static_cast<const AArch64Disassembler *>(Decoder);
1723 
1724  // Sign-extend 14-bit immediate.
1725  if (dst & (1 << (14 - 1)))
1726  dst |= ~((1LL << 14) - 1);
1727 
1728  if (fieldFromInstruction(insn, 31, 1) == 0)
1729  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1730  else
1731  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1733  if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1734  Inst.addOperand(MCOperand::createImm(dst));
1735 
1736  return Success;
1737 }
1738 
1740  unsigned RegClassID,
1741  unsigned RegNo,
1742  uint64_t Addr,
1743  const void *Decoder) {
1744  // Register number must be even (see CASP instruction)
1745  if (RegNo & 0x1)
1746  return Fail;
1747 
1748  unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1750  return Success;
1751 }
1752 
1754  unsigned RegNo,
1755  uint64_t Addr,
1756  const void *Decoder) {
1758  AArch64::WSeqPairsClassRegClassID,
1759  RegNo, Addr, Decoder);
1760 }
1761 
1763  unsigned RegNo,
1764  uint64_t Addr,
1765  const void *Decoder) {
1767  AArch64::XSeqPairsClassRegClassID,
1768  RegNo, Addr, Decoder);
1769 }
1770 
1772  uint64_t Addr,
1773  const void *Decoder) {
1774  unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1775  unsigned imm = fieldFromInstruction(insn, 5, 13);
1777  return Fail;
1778 
1779  // The same (tied) operand is added twice to the instruction.
1780  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1781  if (Inst.getOpcode() != AArch64::DUPM_ZI)
1782  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1783  Inst.addOperand(MCOperand::createImm(imm));
1784  return Success;
1785 }
1786 
1787 template <int Bits>
1788 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1789  const void *Decoder) {
1790  if (Imm & ~((1LL << Bits) - 1))
1791  return Fail;
1792 
1793  // Imm is a signed immediate, so sign extend it.
1794  if (Imm & (1 << (Bits - 1)))
1795  Imm |= ~((1LL << Bits) - 1);
1796 
1797  Inst.addOperand(MCOperand::createImm(Imm));
1798  return Success;
1799 }
1800 
1801 // Decode 8-bit signed/unsigned immediate for a given element width.
1802 template <int ElementWidth>
1803 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1804  uint64_t Addr, const void *Decoder) {
1805  unsigned Val = (uint8_t)Imm;
1806  unsigned Shift = (Imm & 0x100) ? 8 : 0;
1807  if (ElementWidth == 8 && Shift)
1808  return Fail;
1809  Inst.addOperand(MCOperand::createImm(Val));
1811  return Success;
1812 }
1813 
1814 // Decode uimm4 ranged from 1-16.
1815 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1816  uint64_t Addr, const void *Decoder) {
1817  Inst.addOperand(MCOperand::createImm(Imm + 1));
1818  return Success;
1819 }
1820 
1821 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1822  const void *Decoder) {
1823  if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1824  Inst.addOperand(MCOperand::createImm(Imm));
1825  return Success;
1826  }
1827  return Fail;
1828 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1815
MCFixedLenDisassembler.h
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:730
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1435
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:264
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
DecodeFPR128_loRegisterClass
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:391
DecodeZPR3RegisterClass
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:576
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1020
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:959
DecodeZPR_3bRegisterClass
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:557
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
DecodeQQQRegisterClass
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:662
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:472
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:355
ErrorHandling.h
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1632
AArch64BaseInfo.h
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
Fail
#define Fail
Definition: AArch64Disassembler.cpp:261
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:771
Disassembler.h
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:806
Shift
bool Shift
Definition: README.txt:468
llvm::MCDisassembler::SoftFail
@ SoftFail
Definition: MCDisassembler.h:102
AArch64ExternalSymbolizer.h
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:753
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:513
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:347
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:844
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:399
DecodeDDRegisterClass
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:683
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:926
AArch64Disassembler.h
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:854
DecodeGPR64commonRegisterClass
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:447
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:811
DecodeGPR64spRegisterClass
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:488
DecodeGPR32spRegisterClass
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:525
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:800
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1668
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:423
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
MatrixZATileDecoderTable
static const SmallVector< SmallVector< unsigned, 16 >, 5 > MatrixZATileDecoderTable
Definition: AArch64Disassembler.cpp:609
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:42
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:714
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:262
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:859
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:192
MCInst.h
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:822
DecodeZPR_4bRegisterClass
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:549
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:460
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:828
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:170
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
AArch64AddressingModes.h
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1613
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:839
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:242
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1218
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
LLVMSymbolLookupCallback
const typedef char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:112
DecodeQQQQRegisterClass
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:672
uint64_t
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
DecodeQQRegisterClass
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:652
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
extend
_test eax xmm0 eax xmm1 comiss xmm1 setae al movzbl ecx eax edx ecx cmove eax ret Note the cmove can be replaced with a single cmovae There are a number of issues We are introducing a setcc between the result of the intrisic call and select The intrinsic is expected to produce a i32 value so a any extend(which becomes a zero extend) is added. We probably need some kind of target DAG combine hook to fix this. We generate significantly worse code for this than GCC
Definition: README.txt:213
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:794
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:723
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:621
DecodeZPR2RegisterClass
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:565
MCRegisterInfo.h
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1468
llvm::HighlightColor::Address
@ Address
DecodeDDDRegisterClass
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:693
llvm::AArch64ExternalSymbolizer
Definition: AArch64ExternalSymbolizer.h:20
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:849
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1595
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
Definition: MCDisassembler.cpp:26
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
DecodeMatrixIndexGPR32_12_15RegisterClass
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:499
llvm::ArrayRef< uint8_t >
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
DecodePPRRegisterClass
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:631
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1771
uint32_t
Compiler.h
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:411
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:864
DecodeDDDDRegisterClass
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:703
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1556
DecodeSystemPStateInstruction
static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1685
bit
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional ldr LCPI1_0 ldr ldr tst movne lsr ldr LCPI1_1 and r0 bx lr it saves an instruction and a register It might be profitable to cse MOVi16 if there are lots of bit immediates with the same bottom half Robert Muth started working on an alternate jump table implementation that does not put the tables in line in the text This is more like the llvm default jump table implementation This might be useful sometime Several revisions of patches are on the mailing beginning while CMP sets them like a subtract Therefore to be able to use CMN for comparisons other than the Z bit
Definition: README.txt:584
Success
#define Success
Definition: AArch64Disassembler.cpp:260
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1803
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:270
MCRelocationInfo.h
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1739
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1715
AArch64MCTargetDesc.h
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1821
DecodePPR_3bRegisterClass
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:642
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:188
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:817
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1762
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:379
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:833
DecodeZPR4RegisterClass
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:587
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:746
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:321
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
shift
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra shift
Definition: README.txt:30
DecodeZPRRegisterClass
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:537
llvm::AArch64Disassembler
Definition: AArch64Disassembler.h:19
DecodeFPR8RegisterClass
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:435
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:763
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1006
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1525
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1301
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:1788
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:598
Debug.h
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder)
Definition: AArch64Disassembler.cpp:1753
AArch64TargetInfo.h