LLVM 20.0.0git
AArch64Disassembler.cpp
Go to the documentation of this file.
1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Debug.h"
27#include <memory>
28
29using namespace llvm;
30
31#define DEBUG_TYPE "aarch64-disassembler"
32
33// Pull DecodeStatus and its enum values into the global namespace.
34using DecodeStatus = MCDisassembler::DecodeStatus;
35
36// Forward declare these because the autogenerated code will reference them.
37// Definitions are further down.
38template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
39static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
40 uint64_t Address,
41 const MCDisassembler *Decoder);
42static DecodeStatus
43DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
44 const MCDisassembler *Decoder);
45template <unsigned Min, unsigned Max>
46static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
47 uint64_t Address,
48 const MCDisassembler *Decoder);
49static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
50 const MCDisassembler *Decoder);
51template <unsigned Min, unsigned Max>
52static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
53 uint64_t Address,
54 const void *Decoder);
55static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
56 uint64_t Address,
57 const void *Decoder);
58template <unsigned NumBitsForTile>
59static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
60 uint64_t Address,
61 const MCDisassembler *Decoder);
62static DecodeStatus
63DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
64 uint64_t Address,
65 const MCDisassembler *Decoder);
66static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
67 uint64_t Address,
68 const void *Decoder);
69
70static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
71 uint64_t Address,
72 const MCDisassembler *Decoder);
73static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
74 uint64_t Address,
75 const MCDisassembler *Decoder);
76static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
77 uint64_t Address,
78 const MCDisassembler *Decoder);
79static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
80 uint64_t Address,
81 const MCDisassembler *Decoder);
82static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm,
83 uint64_t Address,
84 const MCDisassembler *Decoder);
85static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
86 uint64_t Address,
87 const MCDisassembler *Decoder);
88static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
89 uint64_t Address,
90 const MCDisassembler *Decoder);
91static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
92 uint64_t Address,
93 const MCDisassembler *Decoder);
94static DecodeStatus
95DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
96 const MCDisassembler *Decoder);
97static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
98 uint64_t Address,
99 const MCDisassembler *Decoder);
100static DecodeStatus
101DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
102 const MCDisassembler *Decoder);
103static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
104 uint64_t Address,
105 const MCDisassembler *Decoder);
106static DecodeStatus
107DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
108 const MCDisassembler *Decoder);
109static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
110 uint64_t Address,
111 const MCDisassembler *Decoder);
112static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
113 uint64_t Address,
114 const MCDisassembler *Decoder);
115static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
116 uint64_t Address,
117 const MCDisassembler *Decoder);
118static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
119 uint64_t Address,
120 const MCDisassembler *Decoder);
121static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
122 uint64_t Address,
123 const MCDisassembler *Decoder);
124static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
125 uint64_t Address,
126 const MCDisassembler *Decoder);
127static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
128 uint64_t Address,
129 const MCDisassembler *Decoder);
130static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
131 uint64_t Address,
132 const MCDisassembler *Decoder);
133static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
134 uint64_t Address,
135 const MCDisassembler *Decoder);
136static DecodeStatus
137DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn,
138 uint64_t Address,
139 const MCDisassembler *Decoder);
140static DecodeStatus
141DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn,
142 uint64_t Address,
143 const MCDisassembler *Decoder);
144static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
145 uint64_t Address,
146 const MCDisassembler *Decoder);
147
148static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
149 uint64_t Address,
150 const MCDisassembler *Decoder);
151static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
152 uint64_t Addr,
153 const MCDisassembler *Decoder);
154static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
155 uint64_t Addr,
156 const MCDisassembler *Decoder);
157static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
158 uint64_t Addr,
159 const MCDisassembler *Decoder);
160static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
161 uint64_t Addr,
162 const MCDisassembler *Decoder);
163static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
164 uint64_t Addr,
165 const MCDisassembler *Decoder);
166static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
167 uint64_t Addr,
168 const MCDisassembler *Decoder);
169static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
170 uint64_t Addr,
171 const MCDisassembler *Decoder);
172static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
173 uint64_t Addr,
174 const MCDisassembler *Decoder);
175static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
176 uint64_t Addr,
177 const MCDisassembler *Decoder);
178static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
179 uint64_t Addr,
180 const MCDisassembler *Decoder);
181static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
182 uint64_t Addr,
183 const MCDisassembler *Decoder);
184static DecodeStatus
185DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
186 const MCDisassembler *Decoder);
187static DecodeStatus
188DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
189 const MCDisassembler *Decoder);
190static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
191 uint64_t Addr,
192 const MCDisassembler *Decoder);
193static DecodeStatus
194DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
195 const MCDisassembler *Decoder);
196template <int Bits>
197static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
198 const MCDisassembler *Decoder);
199template <int ElementWidth>
200static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
201 const MCDisassembler *Decoder);
202static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
203 uint64_t Addr,
204 const MCDisassembler *Decoder);
205static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
206 const MCDisassembler *Decoder);
207static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
208 uint64_t Addr,
209 const MCDisassembler *Decoder);
210static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
211 uint64_t Addr,
212 const MCDisassembler *Decoder);
213static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
214 uint64_t Address,
215 const MCDisassembler *Decoder);
216
217#include "AArch64GenDisassemblerTables.inc"
218#include "AArch64GenInstrInfo.inc"
219
220#define Success MCDisassembler::Success
221#define Fail MCDisassembler::Fail
222#define SoftFail MCDisassembler::SoftFail
223
224static MCDisassembler *createAArch64Disassembler(const Target &T,
225 const MCSubtargetInfo &STI,
226 MCContext &Ctx) {
227
228 return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
229}
230
231DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
232 ArrayRef<uint8_t> Bytes,
233 uint64_t Address,
234 raw_ostream &CS) const {
235 CommentStream = &CS;
236
237 Size = 0;
238 // We want to read exactly 4 bytes of data.
239 if (Bytes.size() < 4)
240 return Fail;
241 Size = 4;
242
243 // Encoded as a small-endian 32-bit word in the stream.
244 uint32_t Insn =
245 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
246
247 const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
248
249 for (const auto *Table : Tables) {
250 DecodeStatus Result =
251 decodeInstruction(Table, MI, Insn, Address, this, STI);
252
253 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
254
255 // For Scalable Matrix Extension (SME) instructions that have an implicit
256 // operand for the accumulator (ZA) or implicit immediate zero which isn't
257 // encoded, manually insert operand.
258 for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
259 if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
260 switch (Desc.operands()[i].RegClass) {
261 default:
262 break;
263 case AArch64::MPRRegClassID:
264 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
265 break;
266 case AArch64::MPR8RegClassID:
267 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
268 break;
269 case AArch64::ZTRRegClassID:
270 MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
271 break;
272 }
273 } else if (Desc.operands()[i].OperandType ==
274 AArch64::OPERAND_IMPLICIT_IMM_0) {
275 MI.insert(MI.begin() + i, MCOperand::createImm(0));
276 }
277 }
278
279 if (MI.getOpcode() == AArch64::LDR_ZA ||
280 MI.getOpcode() == AArch64::STR_ZA) {
281 // Spill and fill instructions have a single immediate used for both
282 // the vector select offset and optional memory offset. Replicate
283 // the decoded immediate.
284 const MCOperand &Imm4Op = MI.getOperand(2);
285 assert(Imm4Op.isImm() && "Unexpected operand type!");
286 MI.addOperand(Imm4Op);
287 }
288
289 if (Result != MCDisassembler::Fail)
290 return Result;
291 }
292
293 return MCDisassembler::Fail;
294}
295
296uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
297 uint64_t Address) const {
298 // AArch64 instructions are always 4 bytes wide, so there's no point
299 // in skipping any smaller number of bytes if an instruction can't
300 // be decoded.
301 return 4;
302}
303
304static MCSymbolizer *
305createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
306 LLVMSymbolLookupCallback SymbolLookUp,
307 void *DisInfo, MCContext *Ctx,
308 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
309 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
310 SymbolLookUp, DisInfo);
311}
312
313extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
314 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
315 createAArch64Disassembler);
316 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
317 createAArch64Disassembler);
318 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
319 createAArch64ExternalSymbolizer);
320 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
321 createAArch64ExternalSymbolizer);
322 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
323 createAArch64Disassembler);
324 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
325 createAArch64ExternalSymbolizer);
326
327 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
328 createAArch64Disassembler);
329 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
330 createAArch64ExternalSymbolizer);
331 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
332 createAArch64Disassembler);
333 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
334 createAArch64ExternalSymbolizer);
335}
336
337template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
338static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
339 uint64_t Address,
340 const MCDisassembler *Decoder) {
341 if (RegNo > NumRegsInClass - 1)
342 return Fail;
343
344 unsigned Register =
345 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);
346 Inst.addOperand(MCOperand::createReg(Register));
347 return Success;
348}
349
350static DecodeStatus
351DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
352 const MCDisassembler *Decoder) {
353 if (RegNo > 22)
354 return Fail;
355 if (RegNo & 1)
356 return Fail;
357
358 unsigned Register =
359 AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
360 RegNo >> 1);
361 Inst.addOperand(MCOperand::createReg(Register));
362 return Success;
363}
364
365template <unsigned Min, unsigned Max>
366static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
367 uint64_t Address,
368 const MCDisassembler *Decoder) {
369 unsigned Reg = (RegNo * 2) + Min;
370 if (Reg < Min || Reg > Max || (Reg & 1))
371 return Fail;
372 unsigned Register =
373 AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
374 Inst.addOperand(MCOperand::createReg(Register));
375 return Success;
376}
377
378template <unsigned Min, unsigned Max>
379static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
380 uint64_t Address,
381 const void *Decoder) {
382 unsigned Reg = (RegNo * 2) + Min;
383 if (Reg < Min || Reg > Max || (Reg & 1))
384 return Fail;
385
386 unsigned Register =
387 AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(Reg);
388 Inst.addOperand(MCOperand::createReg(Register));
389 return Success;
390}
391
392static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
393 const MCDisassembler *Decoder) {
394 if (RegNo > 7)
395 return Fail;
396
397 unsigned Register =
398 AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
399 Inst.addOperand(MCOperand::createReg(Register));
400 return Success;
401}
402
403static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
404 uint64_t Address,
405 const void *Decoder) {
406 if (RegNo * 4 > 28)
407 return Fail;
408 unsigned Register =
409 AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
410 Inst.addOperand(MCOperand::createReg(Register));
411 return Success;
412}
413
414static DecodeStatus
415DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
416 uint64_t Address,
417 const MCDisassembler *Decoder) {
418 if (RegMask > 0xFF)
419 return Fail;
420 Inst.addOperand(MCOperand::createImm(RegMask));
421 return Success;
422}
423
424static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
425 {AArch64::ZAB0},
426 {AArch64::ZAH0, AArch64::ZAH1},
427 {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
428 {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
429 AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
430 {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
431 AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
432 AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
433 AArch64::ZAQ14, AArch64::ZAQ15}};
434
435template <unsigned NumBitsForTile>
436static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
437 uint64_t Address,
438 const MCDisassembler *Decoder) {
439 unsigned LastReg = (1 << NumBitsForTile) - 1;
440 if (RegNo > LastReg)
441 return Fail;
442 Inst.addOperand(
443 MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
444 return Success;
445}
446
447static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
448 uint64_t Address,
449 const void *Decoder) {
450 if ((RegNo * 2) > 14)
451 return Fail;
452 unsigned Register =
453 AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
454 Inst.addOperand(MCOperand::createReg(Register));
455 return Success;
456}
457
458static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
459 uint64_t Addr,
460 const MCDisassembler *Decoder) {
461 // scale{5} is asserted as 1 in tblgen.
462 Imm |= 0x20;
463 Inst.addOperand(MCOperand::createImm(64 - Imm));
464 return Success;
465}
466
467static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
468 uint64_t Addr,
469 const MCDisassembler *Decoder) {
470 Inst.addOperand(MCOperand::createImm(64 - Imm));
471 return Success;
472}
473
474static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
475 uint64_t Addr,
476 const MCDisassembler *Decoder) {
477 // Immediate is encoded as the top 16-bits of an unsigned 18-bit negative
478 // PC-relative offset.
479 uint64_t ImmVal = Imm;
480 if (ImmVal > (1 << 16))
481 return Fail;
482 ImmVal = -ImmVal;
483 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal << 2), Addr,
484 /*IsBranch=*/false, 0, 0, 4))
485 Inst.addOperand(MCOperand::createImm(ImmVal));
486 return Success;
487}
488
489static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
490 uint64_t Addr,
491 const MCDisassembler *Decoder) {
492 int64_t ImmVal = Imm;
493
494 // Sign-extend 19-bit immediate.
495 if (ImmVal & (1 << (19 - 1)))
496 ImmVal |= ~((1LL << 19) - 1);
497
498 if (!Decoder->tryAddingSymbolicOperand(
499 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
500 Inst.addOperand(MCOperand::createImm(ImmVal));
501 return Success;
502}
503
504static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr,
505 const MCDisassembler *Decoder) {
506 int64_t ImmVal = Imm;
507
508 // Sign-extend 9-bit immediate.
509 if (ImmVal & (1 << (9 - 1)))
510 ImmVal |= ~((1LL << 9) - 1);
511
512 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal * 4), Addr,
513 /*IsBranch=*/true, 0, 0, 4))
514 Inst.addOperand(MCOperand::createImm(ImmVal));
515 return Success;
516}
517
518static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
519 uint64_t Address,
520 const MCDisassembler *Decoder) {
521 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
522 Inst.addOperand(MCOperand::createImm(Imm & 1));
523 return Success;
524}
525
526static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
527 uint64_t Address,
528 const MCDisassembler *Decoder) {
529 Inst.addOperand(MCOperand::createImm(Imm));
530
531 // Every system register in the encoding space is valid with the syntax
532 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
533 return Success;
534}
535
536static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
537 uint64_t Address,
538 const MCDisassembler *Decoder) {
539 Inst.addOperand(MCOperand::createImm(Imm));
540
541 return Success;
542}
543
544static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
545 uint64_t Address,
546 const MCDisassembler *Decoder) {
547 // This decoder exists to add the dummy Lane operand to the MCInst, which must
548 // be 1 in assembly but has no other real manifestation.
549 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
550 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
551 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
552
553 if (IsToVec) {
554 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
555 Inst, Rd, Address, Decoder);
556 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
557 Inst, Rn, Address, Decoder);
558 } else {
559 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
560 Inst, Rd, Address, Decoder);
561 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(
562 Inst, Rn, Address, Decoder);
563 }
564
565 // Add the lane
566 Inst.addOperand(MCOperand::createImm(1));
567
568 return Success;
569}
570
571static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
572 unsigned Add) {
573 Inst.addOperand(MCOperand::createImm(Add - Imm));
574 return Success;
575}
576
577static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
578 unsigned Add) {
579 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
580 return Success;
581}
582
583static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
584 uint64_t Addr,
585 const MCDisassembler *Decoder) {
586 return DecodeVecShiftRImm(Inst, Imm, 64);
587}
588
589static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
590 uint64_t Addr,
591 const MCDisassembler *Decoder) {
592 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
593}
594
595static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
596 uint64_t Addr,
597 const MCDisassembler *Decoder) {
598 return DecodeVecShiftRImm(Inst, Imm, 32);
599}
600
601static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
602 uint64_t Addr,
603 const MCDisassembler *Decoder) {
604 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
605}
606
607static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
608 uint64_t Addr,
609 const MCDisassembler *Decoder) {
610 return DecodeVecShiftRImm(Inst, Imm, 16);
611}
612
613static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
614 uint64_t Addr,
615 const MCDisassembler *Decoder) {
616 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
617}
618
619static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
620 uint64_t Addr,
621 const MCDisassembler *Decoder) {
622 return DecodeVecShiftRImm(Inst, Imm, 8);
623}
624
625static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
626 uint64_t Addr,
627 const MCDisassembler *Decoder) {
628 return DecodeVecShiftLImm(Inst, Imm, 64);
629}
630
631static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
632 uint64_t Addr,
633 const MCDisassembler *Decoder) {
634 return DecodeVecShiftLImm(Inst, Imm, 32);
635}
636
637static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
638 uint64_t Addr,
639 const MCDisassembler *Decoder) {
640 return DecodeVecShiftLImm(Inst, Imm, 16);
641}
642
643static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
644 uint64_t Addr,
645 const MCDisassembler *Decoder) {
646 return DecodeVecShiftLImm(Inst, Imm, 8);
647}
648
649static DecodeStatus
650DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
651 const MCDisassembler *Decoder) {
652 unsigned Rd = fieldFromInstruction(insn, 0, 5);
653 unsigned Rn = fieldFromInstruction(insn, 5, 5);
654 unsigned Rm = fieldFromInstruction(insn, 16, 5);
655 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
656 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
657 unsigned shift = (shiftHi << 6) | shiftLo;
658 switch (Inst.getOpcode()) {
659 default:
660 return Fail;
661 case AArch64::ADDWrs:
662 case AArch64::ADDSWrs:
663 case AArch64::SUBWrs:
664 case AArch64::SUBSWrs:
665 // if shift == '11' then ReservedValue()
666 if (shiftHi == 0x3)
667 return Fail;
668 [[fallthrough]];
669 case AArch64::ANDWrs:
670 case AArch64::ANDSWrs:
671 case AArch64::BICWrs:
672 case AArch64::BICSWrs:
673 case AArch64::ORRWrs:
674 case AArch64::ORNWrs:
675 case AArch64::EORWrs:
676 case AArch64::EONWrs: {
677 // if sf == '0' and imm6<5> == '1' then ReservedValue()
678 if (shiftLo >> 5 == 1)
679 return Fail;
680 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
681 Decoder);
682 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
683 Decoder);
684 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
685 Decoder);
686 break;
687 }
688 case AArch64::ADDXrs:
689 case AArch64::ADDSXrs:
690 case AArch64::SUBXrs:
691 case AArch64::SUBSXrs:
692 // if shift == '11' then ReservedValue()
693 if (shiftHi == 0x3)
694 return Fail;
695 [[fallthrough]];
696 case AArch64::ANDXrs:
697 case AArch64::ANDSXrs:
698 case AArch64::BICXrs:
699 case AArch64::BICSXrs:
700 case AArch64::ORRXrs:
701 case AArch64::ORNXrs:
702 case AArch64::EORXrs:
703 case AArch64::EONXrs:
704 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
705 Decoder);
706 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
707 Decoder);
708 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
709 Decoder);
710 break;
711 }
712
713 Inst.addOperand(MCOperand::createImm(shift));
714 return Success;
715}
716
717static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
718 uint64_t Addr,
719 const MCDisassembler *Decoder) {
720 unsigned Rd = fieldFromInstruction(insn, 0, 5);
721 unsigned imm = fieldFromInstruction(insn, 5, 16);
722 unsigned shift = fieldFromInstruction(insn, 21, 2);
723 shift <<= 4;
724 switch (Inst.getOpcode()) {
725 default:
726 return Fail;
727 case AArch64::MOVZWi:
728 case AArch64::MOVNWi:
729 case AArch64::MOVKWi:
730 if (shift & (1U << 5))
731 return Fail;
732 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
733 Decoder);
734 break;
735 case AArch64::MOVZXi:
736 case AArch64::MOVNXi:
737 case AArch64::MOVKXi:
738 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
739 Decoder);
740 break;
741 }
742
743 if (Inst.getOpcode() == AArch64::MOVKWi ||
744 Inst.getOpcode() == AArch64::MOVKXi)
745 Inst.addOperand(Inst.getOperand(0));
746
747 Inst.addOperand(MCOperand::createImm(imm));
748 Inst.addOperand(MCOperand::createImm(shift));
749 return Success;
750}
751
752static DecodeStatus
753DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
754 const MCDisassembler *Decoder) {
755 unsigned Rt = fieldFromInstruction(insn, 0, 5);
756 unsigned Rn = fieldFromInstruction(insn, 5, 5);
757 unsigned offset = fieldFromInstruction(insn, 10, 12);
758
759 switch (Inst.getOpcode()) {
760 default:
761 return Fail;
762 case AArch64::PRFMui:
763 // Rt is an immediate in prefetch.
764 Inst.addOperand(MCOperand::createImm(Rt));
765 break;
766 case AArch64::STRBBui:
767 case AArch64::LDRBBui:
768 case AArch64::LDRSBWui:
769 case AArch64::STRHHui:
770 case AArch64::LDRHHui:
771 case AArch64::LDRSHWui:
772 case AArch64::STRWui:
773 case AArch64::LDRWui:
774 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
775 Decoder);
776 break;
777 case AArch64::LDRSBXui:
778 case AArch64::LDRSHXui:
779 case AArch64::LDRSWui:
780 case AArch64::STRXui:
781 case AArch64::LDRXui:
782 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
783 Decoder);
784 break;
785 case AArch64::LDRQui:
786 case AArch64::STRQui:
787 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
788 Decoder);
789 break;
790 case AArch64::LDRDui:
791 case AArch64::STRDui:
792 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
793 Decoder);
794 break;
795 case AArch64::LDRSui:
796 case AArch64::STRSui:
797 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
798 Decoder);
799 break;
800 case AArch64::LDRHui:
801 case AArch64::STRHui:
802 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
803 Decoder);
804 break;
805 case AArch64::LDRBui:
806 case AArch64::STRBui:
807 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
808 Decoder);
809 break;
810 }
811
812 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
813 Decoder);
814 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
815 Inst.addOperand(MCOperand::createImm(offset));
816 return Success;
817}
818
819static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
820 uint64_t Addr,
821 const MCDisassembler *Decoder) {
822 unsigned Rt = fieldFromInstruction(insn, 0, 5);
823 unsigned Rn = fieldFromInstruction(insn, 5, 5);
824 int64_t offset = fieldFromInstruction(insn, 12, 9);
825
826 // offset is a 9-bit signed immediate, so sign extend it to
827 // fill the unsigned.
828 if (offset & (1 << (9 - 1)))
829 offset |= ~((1LL << 9) - 1);
830
831 // First operand is always the writeback to the address register, if needed.
832 switch (Inst.getOpcode()) {
833 default:
834 break;
835 case AArch64::LDRSBWpre:
836 case AArch64::LDRSHWpre:
837 case AArch64::STRBBpre:
838 case AArch64::LDRBBpre:
839 case AArch64::STRHHpre:
840 case AArch64::LDRHHpre:
841 case AArch64::STRWpre:
842 case AArch64::LDRWpre:
843 case AArch64::LDRSBWpost:
844 case AArch64::LDRSHWpost:
845 case AArch64::STRBBpost:
846 case AArch64::LDRBBpost:
847 case AArch64::STRHHpost:
848 case AArch64::LDRHHpost:
849 case AArch64::STRWpost:
850 case AArch64::LDRWpost:
851 case AArch64::LDRSBXpre:
852 case AArch64::LDRSHXpre:
853 case AArch64::STRXpre:
854 case AArch64::LDRSWpre:
855 case AArch64::LDRXpre:
856 case AArch64::LDRSBXpost:
857 case AArch64::LDRSHXpost:
858 case AArch64::STRXpost:
859 case AArch64::LDRSWpost:
860 case AArch64::LDRXpost:
861 case AArch64::LDRQpre:
862 case AArch64::STRQpre:
863 case AArch64::LDRQpost:
864 case AArch64::STRQpost:
865 case AArch64::LDRDpre:
866 case AArch64::STRDpre:
867 case AArch64::LDRDpost:
868 case AArch64::STRDpost:
869 case AArch64::LDRSpre:
870 case AArch64::STRSpre:
871 case AArch64::LDRSpost:
872 case AArch64::STRSpost:
873 case AArch64::LDRHpre:
874 case AArch64::STRHpre:
875 case AArch64::LDRHpost:
876 case AArch64::STRHpost:
877 case AArch64::LDRBpre:
878 case AArch64::STRBpre:
879 case AArch64::LDRBpost:
880 case AArch64::STRBpost:
881 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
882 Decoder);
883 break;
884 }
885
886 switch (Inst.getOpcode()) {
887 default:
888 return Fail;
889 case AArch64::PRFUMi:
890 // Rt is an immediate in prefetch.
891 Inst.addOperand(MCOperand::createImm(Rt));
892 break;
893 case AArch64::STURBBi:
894 case AArch64::LDURBBi:
895 case AArch64::LDURSBWi:
896 case AArch64::STURHHi:
897 case AArch64::LDURHHi:
898 case AArch64::LDURSHWi:
899 case AArch64::STURWi:
900 case AArch64::LDURWi:
901 case AArch64::LDTRSBWi:
902 case AArch64::LDTRSHWi:
903 case AArch64::STTRWi:
904 case AArch64::LDTRWi:
905 case AArch64::STTRHi:
906 case AArch64::LDTRHi:
907 case AArch64::LDTRBi:
908 case AArch64::STTRBi:
909 case AArch64::LDRSBWpre:
910 case AArch64::LDRSHWpre:
911 case AArch64::STRBBpre:
912 case AArch64::LDRBBpre:
913 case AArch64::STRHHpre:
914 case AArch64::LDRHHpre:
915 case AArch64::STRWpre:
916 case AArch64::LDRWpre:
917 case AArch64::LDRSBWpost:
918 case AArch64::LDRSHWpost:
919 case AArch64::STRBBpost:
920 case AArch64::LDRBBpost:
921 case AArch64::STRHHpost:
922 case AArch64::LDRHHpost:
923 case AArch64::STRWpost:
924 case AArch64::LDRWpost:
925 case AArch64::STLURBi:
926 case AArch64::STLURHi:
927 case AArch64::STLURWi:
928 case AArch64::LDAPURBi:
929 case AArch64::LDAPURSBWi:
930 case AArch64::LDAPURHi:
931 case AArch64::LDAPURSHWi:
932 case AArch64::LDAPURi:
933 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
934 Decoder);
935 break;
936 case AArch64::LDURSBXi:
937 case AArch64::LDURSHXi:
938 case AArch64::LDURSWi:
939 case AArch64::STURXi:
940 case AArch64::LDURXi:
941 case AArch64::LDTRSBXi:
942 case AArch64::LDTRSHXi:
943 case AArch64::LDTRSWi:
944 case AArch64::STTRXi:
945 case AArch64::LDTRXi:
946 case AArch64::LDRSBXpre:
947 case AArch64::LDRSHXpre:
948 case AArch64::STRXpre:
949 case AArch64::LDRSWpre:
950 case AArch64::LDRXpre:
951 case AArch64::LDRSBXpost:
952 case AArch64::LDRSHXpost:
953 case AArch64::STRXpost:
954 case AArch64::LDRSWpost:
955 case AArch64::LDRXpost:
956 case AArch64::LDAPURSWi:
957 case AArch64::LDAPURSHXi:
958 case AArch64::LDAPURSBXi:
959 case AArch64::STLURXi:
960 case AArch64::LDAPURXi:
961 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
962 Decoder);
963 break;
964 case AArch64::LDURQi:
965 case AArch64::STURQi:
966 case AArch64::LDRQpre:
967 case AArch64::STRQpre:
968 case AArch64::LDRQpost:
969 case AArch64::STRQpost:
970 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
971 Decoder);
972 break;
973 case AArch64::LDURDi:
974 case AArch64::STURDi:
975 case AArch64::LDRDpre:
976 case AArch64::STRDpre:
977 case AArch64::LDRDpost:
978 case AArch64::STRDpost:
979 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
980 Decoder);
981 break;
982 case AArch64::LDURSi:
983 case AArch64::STURSi:
984 case AArch64::LDRSpre:
985 case AArch64::STRSpre:
986 case AArch64::LDRSpost:
987 case AArch64::STRSpost:
988 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
989 Decoder);
990 break;
991 case AArch64::LDURHi:
992 case AArch64::STURHi:
993 case AArch64::LDRHpre:
994 case AArch64::STRHpre:
995 case AArch64::LDRHpost:
996 case AArch64::STRHpost:
997 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
998 Decoder);
999 break;
1000 case AArch64::LDURBi:
1001 case AArch64::STURBi:
1002 case AArch64::LDRBpre:
1003 case AArch64::STRBpre:
1004 case AArch64::LDRBpost:
1005 case AArch64::STRBpost:
1006 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
1007 Decoder);
1008 break;
1009 }
1010
1011 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1012 Decoder);
1013 Inst.addOperand(MCOperand::createImm(offset));
1014
1015 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1016 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1017 bool IsFP = fieldFromInstruction(insn, 26, 1);
1018
1019 // Cannot write back to a transfer register (but xzr != sp).
1020 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1021 return SoftFail;
1022
1023 return Success;
1024}
1025
1026static DecodeStatus
1027DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1028 const MCDisassembler *Decoder) {
1029 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1030 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1031 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1032 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1033
1034 unsigned Opcode = Inst.getOpcode();
1035 switch (Opcode) {
1036 default:
1037 return Fail;
1038 case AArch64::STLXRW:
1039 case AArch64::STLXRB:
1040 case AArch64::STLXRH:
1041 case AArch64::STXRW:
1042 case AArch64::STXRB:
1043 case AArch64::STXRH:
1044 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1045 Decoder);
1046 [[fallthrough]];
1047 case AArch64::LDARW:
1048 case AArch64::LDARB:
1049 case AArch64::LDARH:
1050 case AArch64::LDAXRW:
1051 case AArch64::LDAXRB:
1052 case AArch64::LDAXRH:
1053 case AArch64::LDXRW:
1054 case AArch64::LDXRB:
1055 case AArch64::LDXRH:
1056 case AArch64::STLRW:
1057 case AArch64::STLRB:
1058 case AArch64::STLRH:
1059 case AArch64::STLLRW:
1060 case AArch64::STLLRB:
1061 case AArch64::STLLRH:
1062 case AArch64::LDLARW:
1063 case AArch64::LDLARB:
1064 case AArch64::LDLARH:
1065 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1066 Decoder);
1067 break;
1068 case AArch64::STLXRX:
1069 case AArch64::STXRX:
1070 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1071 Decoder);
1072 [[fallthrough]];
1073 case AArch64::LDARX:
1074 case AArch64::LDAXRX:
1075 case AArch64::LDXRX:
1076 case AArch64::STLRX:
1077 case AArch64::LDLARX:
1078 case AArch64::STLLRX:
1079 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1080 Decoder);
1081 break;
1082 case AArch64::STLXPW:
1083 case AArch64::STXPW:
1084 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1085 Decoder);
1086 [[fallthrough]];
1087 case AArch64::LDAXPW:
1088 case AArch64::LDXPW:
1089 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1090 Decoder);
1091 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1092 Decoder);
1093 break;
1094 case AArch64::STLXPX:
1095 case AArch64::STXPX:
1096 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1097 Decoder);
1098 [[fallthrough]];
1099 case AArch64::LDAXPX:
1100 case AArch64::LDXPX:
1101 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1102 Decoder);
1103 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1104 Decoder);
1105 break;
1106 }
1107
1108 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1109 Decoder);
1110
1111 // You shouldn't load to the same register twice in an instruction...
1112 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1113 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1114 Rt == Rt2)
1115 return SoftFail;
1116
1117 return Success;
1118}
1119
1120static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1121 uint64_t Addr,
1122 const MCDisassembler *Decoder) {
1123 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1124 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1125 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1126 int64_t offset = fieldFromInstruction(insn, 15, 7);
1127 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1128
1129 // offset is a 7-bit signed immediate, so sign extend it to
1130 // fill the unsigned.
1131 if (offset & (1 << (7 - 1)))
1132 offset |= ~((1LL << 7) - 1);
1133
1134 unsigned Opcode = Inst.getOpcode();
1135 bool NeedsDisjointWritebackTransfer = false;
1136
1137 // First operand is always writeback of base register.
1138 switch (Opcode) {
1139 default:
1140 break;
1141 case AArch64::LDPXpost:
1142 case AArch64::STPXpost:
1143 case AArch64::LDPSWpost:
1144 case AArch64::LDPXpre:
1145 case AArch64::STPXpre:
1146 case AArch64::LDPSWpre:
1147 case AArch64::LDPWpost:
1148 case AArch64::STPWpost:
1149 case AArch64::LDPWpre:
1150 case AArch64::STPWpre:
1151 case AArch64::LDPQpost:
1152 case AArch64::STPQpost:
1153 case AArch64::LDPQpre:
1154 case AArch64::STPQpre:
1155 case AArch64::LDPDpost:
1156 case AArch64::STPDpost:
1157 case AArch64::LDPDpre:
1158 case AArch64::STPDpre:
1159 case AArch64::LDPSpost:
1160 case AArch64::STPSpost:
1161 case AArch64::LDPSpre:
1162 case AArch64::STPSpre:
1163 case AArch64::STGPpre:
1164 case AArch64::STGPpost:
1165 case AArch64::LDTPpre:
1166 case AArch64::LDTPpost:
1167 case AArch64::LDTPQpost:
1168 case AArch64::LDTPQpre:
1169 case AArch64::STTPpost:
1170 case AArch64::STTPpre:
1171 case AArch64::STTPQpost:
1172 case AArch64::STTPQpre:
1173 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1174 Decoder);
1175 break;
1176 }
1177
1178 switch (Opcode) {
1179 default:
1180 return Fail;
1181 case AArch64::LDPXpost:
1182 case AArch64::STPXpost:
1183 case AArch64::LDPSWpost:
1184 case AArch64::LDPXpre:
1185 case AArch64::STPXpre:
1186 case AArch64::LDPSWpre:
1187 case AArch64::STGPpre:
1188 case AArch64::STGPpost:
1189 case AArch64::LDTPpost:
1190 case AArch64::LDTPpre:
1191 case AArch64::STTPpost:
1192 case AArch64::STTPpre:
1193 NeedsDisjointWritebackTransfer = true;
1194 [[fallthrough]];
1195 case AArch64::LDNPXi:
1196 case AArch64::STNPXi:
1197 case AArch64::LDPXi:
1198 case AArch64::STPXi:
1199 case AArch64::LDPSWi:
1200 case AArch64::STGPi:
1201 case AArch64::LDTPi:
1202 case AArch64::STTPi:
1203 case AArch64::STTNPXi:
1204 case AArch64::LDTNPXi:
1205 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1206 Decoder);
1207 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1208 Decoder);
1209 break;
1210 case AArch64::LDPWpost:
1211 case AArch64::STPWpost:
1212 case AArch64::LDPWpre:
1213 case AArch64::STPWpre:
1214 NeedsDisjointWritebackTransfer = true;
1215 [[fallthrough]];
1216 case AArch64::LDNPWi:
1217 case AArch64::STNPWi:
1218 case AArch64::LDPWi:
1219 case AArch64::STPWi:
1220 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1221 Decoder);
1222 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1223 Decoder);
1224 break;
1225 case AArch64::LDNPQi:
1226 case AArch64::STNPQi:
1227 case AArch64::LDPQpost:
1228 case AArch64::STPQpost:
1229 case AArch64::LDPQi:
1230 case AArch64::STPQi:
1231 case AArch64::LDPQpre:
1232 case AArch64::STPQpre:
1233 case AArch64::LDTPQi:
1234 case AArch64::LDTPQpost:
1235 case AArch64::LDTPQpre:
1236 case AArch64::LDTNPQi:
1237 case AArch64::STTPQi:
1238 case AArch64::STTPQpost:
1239 case AArch64::STTPQpre:
1240 case AArch64::STTNPQi:
1241 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
1242 Decoder);
1243 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt2, Addr,
1244 Decoder);
1245 break;
1246 case AArch64::LDNPDi:
1247 case AArch64::STNPDi:
1248 case AArch64::LDPDpost:
1249 case AArch64::STPDpost:
1250 case AArch64::LDPDi:
1251 case AArch64::STPDi:
1252 case AArch64::LDPDpre:
1253 case AArch64::STPDpre:
1254 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1255 Decoder);
1256 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1257 Decoder);
1258 break;
1259 case AArch64::LDNPSi:
1260 case AArch64::STNPSi:
1261 case AArch64::LDPSpost:
1262 case AArch64::STPSpost:
1263 case AArch64::LDPSi:
1264 case AArch64::STPSi:
1265 case AArch64::LDPSpre:
1266 case AArch64::STPSpre:
1267 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1268 Decoder);
1269 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1270 Decoder);
1271 break;
1272 }
1273
1274 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1275 Decoder);
1276 Inst.addOperand(MCOperand::createImm(offset));
1277
1278 // You shouldn't load to the same register twice in an instruction...
1279 if (IsLoad && Rt == Rt2)
1280 return SoftFail;
1281
1282 // ... or do any operation that writes-back to a transfer register. But note
1283 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1284 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1285 return SoftFail;
1286
1287 return Success;
1288}
1289
1290static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1291 uint64_t Addr,
1292 const MCDisassembler *Decoder) {
1293 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1294 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1295 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1296 fieldFromInstruction(insn, 12, 9);
1297 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1298
1299 switch (Inst.getOpcode()) {
1300 default:
1301 return Fail;
1302 case AArch64::LDRAAwriteback:
1303 case AArch64::LDRABwriteback:
1304 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1305 Inst, Rn /* writeback register */, Addr, Decoder);
1306 break;
1307 case AArch64::LDRAAindexed:
1308 case AArch64::LDRABindexed:
1309 break;
1310 }
1311
1312 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1313 Decoder);
1314 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1315 Decoder);
1316 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1317
1318 if (writeback && Rt == Rn && Rn != 31) {
1319 return SoftFail;
1320 }
1321
1322 return Success;
1323}
1324
1325static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1326 uint64_t Addr,
1327 const MCDisassembler *Decoder) {
1328 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1329 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1330 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1331 unsigned extend = fieldFromInstruction(insn, 10, 6);
1332
1333 unsigned shift = extend & 0x7;
1334 if (shift > 4)
1335 return Fail;
1336
1337 switch (Inst.getOpcode()) {
1338 default:
1339 return Fail;
1340 case AArch64::ADDWrx:
1341 case AArch64::SUBWrx:
1342 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rd, Addr,
1343 Decoder);
1344 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1345 Decoder);
1346 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1347 Decoder);
1348 break;
1349 case AArch64::ADDSWrx:
1350 case AArch64::SUBSWrx:
1351 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1352 Decoder);
1353 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1354 Decoder);
1355 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1356 Decoder);
1357 break;
1358 case AArch64::ADDXrx:
1359 case AArch64::SUBXrx:
1360 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1361 Decoder);
1362 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1363 Decoder);
1364 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1365 Decoder);
1366 break;
1367 case AArch64::ADDSXrx:
1368 case AArch64::SUBSXrx:
1369 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1370 Decoder);
1371 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1372 Decoder);
1373 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1374 Decoder);
1375 break;
1376 case AArch64::ADDXrx64:
1377 case AArch64::SUBXrx64:
1378 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1379 Decoder);
1380 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1381 Decoder);
1382 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1383 Decoder);
1384 break;
1385 case AArch64::SUBSXrx64:
1386 case AArch64::ADDSXrx64:
1387 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1388 Decoder);
1389 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1390 Decoder);
1391 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1392 Decoder);
1393 break;
1394 }
1395
1396 Inst.addOperand(MCOperand::createImm(extend));
1397 return Success;
1398}
1399
1400static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1401 uint64_t Addr,
1402 const MCDisassembler *Decoder) {
1403 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1404 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1405 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1406 unsigned imm;
1407
1408 if (Datasize) {
1409 if (Inst.getOpcode() == AArch64::ANDSXri)
1410 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1411 Decoder);
1412 else
1413 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1414 Inst, Rd, Addr, Decoder);
1415 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
1416 Decoder);
1417 imm = fieldFromInstruction(insn, 10, 13);
1418 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1419 return Fail;
1420 } else {
1421 if (Inst.getOpcode() == AArch64::ANDSWri)
1422 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1423 Decoder);
1424 else
1425 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1426 Inst, Rd, Addr, Decoder);
1427 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
1428 Decoder);
1429 imm = fieldFromInstruction(insn, 10, 12);
1430 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1431 return Fail;
1432 }
1433 Inst.addOperand(MCOperand::createImm(imm));
1434 return Success;
1435}
1436
1437static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1438 uint64_t Addr,
1439 const MCDisassembler *Decoder) {
1440 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1441 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1442 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1443 imm |= fieldFromInstruction(insn, 5, 5);
1444
1445 if (Inst.getOpcode() == AArch64::MOVID)
1446 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1447 Decoder);
1448 else
1449 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1450 Decoder);
1451
1452 Inst.addOperand(MCOperand::createImm(imm));
1453
1454 switch (Inst.getOpcode()) {
1455 default:
1456 break;
1457 case AArch64::MOVIv4i16:
1458 case AArch64::MOVIv8i16:
1459 case AArch64::MVNIv4i16:
1460 case AArch64::MVNIv8i16:
1461 case AArch64::MOVIv2i32:
1462 case AArch64::MOVIv4i32:
1463 case AArch64::MVNIv2i32:
1464 case AArch64::MVNIv4i32:
1465 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1466 break;
1467 case AArch64::MOVIv2s_msl:
1468 case AArch64::MOVIv4s_msl:
1469 case AArch64::MVNIv2s_msl:
1470 case AArch64::MVNIv4s_msl:
1471 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1472 break;
1473 }
1474
1475 return Success;
1476}
1477
1478static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1479 uint64_t Addr,
1480 const MCDisassembler *Decoder) {
1481 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1482 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1483 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1484 imm |= fieldFromInstruction(insn, 5, 5);
1485
1486 // Tied operands added twice.
1487 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1488 Decoder);
1489 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1490 Decoder);
1491
1492 Inst.addOperand(MCOperand::createImm(imm));
1493 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1494
1495 return Success;
1496}
1497
1498static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1499 uint64_t Addr,
1500 const MCDisassembler *Decoder) {
1501 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1502 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1503 imm |= fieldFromInstruction(insn, 29, 2);
1504
1505 // Sign-extend the 21-bit immediate.
1506 if (imm & (1 << (21 - 1)))
1507 imm |= ~((1LL << 21) - 1);
1508
1509 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1510 Decoder);
1511 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1512 Inst.addOperand(MCOperand::createImm(imm));
1513
1514 return Success;
1515}
1516
1517static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1518 uint64_t Addr,
1519 const MCDisassembler *Decoder) {
1520 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1521 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1522 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1523 unsigned S = fieldFromInstruction(insn, 29, 1);
1524 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1525
1526 unsigned ShifterVal = (Imm >> 12) & 3;
1527 unsigned ImmVal = Imm & 0xFFF;
1528
1529 if (ShifterVal != 0 && ShifterVal != 1)
1530 return Fail;
1531
1532 if (Datasize) {
1533 if (Rd == 31 && !S)
1534 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(
1535 Inst, Rd, Addr, Decoder);
1536 else
1537 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1538 Decoder);
1539 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1540 Decoder);
1541 } else {
1542 if (Rd == 31 && !S)
1543 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(
1544 Inst, Rd, Addr, Decoder);
1545 else
1546 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1547 Decoder);
1548 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1549 Decoder);
1550 }
1551
1552 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1553 Inst.addOperand(MCOperand::createImm(ImmVal));
1554 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1555 return Success;
1556}
1557
1558static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1559 uint64_t Addr,
1560 const MCDisassembler *Decoder) {
1561 int64_t imm = fieldFromInstruction(insn, 0, 26);
1562
1563 // Sign-extend the 26-bit immediate.
1564 if (imm & (1 << (26 - 1)))
1565 imm |= ~((1LL << 26) - 1);
1566
1567 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1568 Inst.addOperand(MCOperand::createImm(imm));
1569
1570 return Success;
1571}
1572
1573static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1574 return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1575 Op2 == 0b001 || // XAFlag
1576 Op2 == 0b010); // AXFlag
1577}
1578
1579static DecodeStatus
1580DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1581 const MCDisassembler *Decoder) {
1582 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1583 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1584 uint64_t imm = fieldFromInstruction(insn, 8, 4);
1585 uint64_t pstate_field = (op1 << 3) | op2;
1586
1587 if (isInvalidPState(op1, op2))
1588 return Fail;
1589
1590 Inst.addOperand(MCOperand::createImm(pstate_field));
1591 Inst.addOperand(MCOperand::createImm(imm));
1592
1593 auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1594 if (PState &&
1595 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1596 return Success;
1597 return Fail;
1598}
1599
1600static DecodeStatus
1601DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1602 const MCDisassembler *Decoder) {
1603 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1604 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1605 uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1606 uint64_t imm = fieldFromInstruction(insn, 8, 1);
1607 uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1608
1609 if (isInvalidPState(op1, op2))
1610 return Fail;
1611
1612 Inst.addOperand(MCOperand::createImm(pstate_field));
1613 Inst.addOperand(MCOperand::createImm(imm));
1614
1615 auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1616 if (PState &&
1617 PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1618 return Success;
1619 return Fail;
1620}
1621
1622static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1623 uint64_t Addr,
1624 const MCDisassembler *Decoder) {
1625 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1626 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1627 bit |= fieldFromInstruction(insn, 19, 5);
1628 int64_t dst = fieldFromInstruction(insn, 5, 14);
1629
1630 // Sign-extend 14-bit immediate.
1631 if (dst & (1 << (14 - 1)))
1632 dst |= ~((1LL << 14) - 1);
1633
1634 if (fieldFromInstruction(insn, 31, 1) == 0)
1635 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1636 Decoder);
1637 else
1638 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1639 Decoder);
1640 Inst.addOperand(MCOperand::createImm(bit));
1641 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1642 Inst.addOperand(MCOperand::createImm(dst));
1643
1644 return Success;
1645}
1646
1647static DecodeStatus
1648DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1649 unsigned RegNo, uint64_t Addr,
1650 const MCDisassembler *Decoder) {
1651 // Register number must be even (see CASP instruction)
1652 if (RegNo & 0x1)
1653 return Fail;
1654
1655 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1656 Inst.addOperand(MCOperand::createReg(Reg));
1657 return Success;
1658}
1659
1660static DecodeStatus
1661DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1662 const MCDisassembler *Decoder) {
1663 return DecodeGPRSeqPairsClassRegisterClass(
1664 Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1665}
1666
1667static DecodeStatus
1668DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1669 const MCDisassembler *Decoder) {
1670 return DecodeGPRSeqPairsClassRegisterClass(
1671 Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1672}
1673
1674static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1675 uint64_t Addr,
1676 const MCDisassembler *Decoder) {
1677 unsigned op1 = fieldFromInstruction(insn, 16, 3);
1678 unsigned CRn = fieldFromInstruction(insn, 12, 4);
1679 unsigned CRm = fieldFromInstruction(insn, 8, 4);
1680 unsigned op2 = fieldFromInstruction(insn, 5, 3);
1681 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1682 if (Rt != 0b11111)
1683 return Fail;
1684
1685 Inst.addOperand(MCOperand::createImm(op1));
1686 Inst.addOperand(MCOperand::createImm(CRn));
1687 Inst.addOperand(MCOperand::createImm(CRm));
1688 Inst.addOperand(MCOperand::createImm(op2));
1689 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1690 Decoder);
1691
1692 return Success;
1693}
1694
1695static DecodeStatus
1696DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1697 const MCDisassembler *Decoder) {
1698 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1699 unsigned imm = fieldFromInstruction(insn, 5, 13);
1700 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1701 return Fail;
1702
1703 // The same (tied) operand is added twice to the instruction.
1704 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1705 Decoder);
1706 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1707 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1708 Decoder);
1709 Inst.addOperand(MCOperand::createImm(imm));
1710 return Success;
1711}
1712
1713template <int Bits>
1714static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1715 const MCDisassembler *Decoder) {
1716 if (Imm & ~((1LL << Bits) - 1))
1717 return Fail;
1718
1719 // Imm is a signed immediate, so sign extend it.
1720 if (Imm & (1 << (Bits - 1)))
1721 Imm |= ~((1LL << Bits) - 1);
1722
1723 Inst.addOperand(MCOperand::createImm(Imm));
1724 return Success;
1725}
1726
1727// Decode 8-bit signed/unsigned immediate for a given element width.
1728template <int ElementWidth>
1729static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
1730 const MCDisassembler *Decoder) {
1731 unsigned Val = (uint8_t)Imm;
1732 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1733 if (ElementWidth == 8 && Shift)
1734 return Fail;
1735 Inst.addOperand(MCOperand::createImm(Val));
1736 Inst.addOperand(MCOperand::createImm(Shift));
1737 return Success;
1738}
1739
1740// Decode uimm4 ranged from 1-16.
1741static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1742 uint64_t Addr,
1743 const MCDisassembler *Decoder) {
1744 Inst.addOperand(MCOperand::createImm(Imm + 1));
1745 return Success;
1746}
1747
1748static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1749 const MCDisassembler *Decoder) {
1750 if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
1751 Inst.addOperand(MCOperand::createImm(Imm));
1752 return Success;
1753 }
1754 return Fail;
1755}
1756
1757static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
1758 uint64_t Addr,
1759 const MCDisassembler *Decoder) {
1760 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1761 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1762 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1763
1764 // None of the registers may alias: if they do, then the instruction is not
1765 // merely unpredictable but actually entirely unallocated.
1766 if (Rd == Rs || Rs == Rn || Rd == Rn)
1767 return MCDisassembler::Fail;
1768
1769 // All three register operands are written back, so they all appear
1770 // twice in the operand list, once as outputs and once as inputs.
1771 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1772 Inst, Rd, Addr, Decoder) ||
1773 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1774 Inst, Rs, Addr, Decoder) ||
1775 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1776 Inst, Rn, Addr, Decoder) ||
1777 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1778 Inst, Rd, Addr, Decoder) ||
1779 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1780 Inst, Rs, Addr, Decoder) ||
1781 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1782 Inst, Rn, Addr, Decoder))
1783 return MCDisassembler::Fail;
1784
1785 return MCDisassembler::Success;
1786}
1787
1788static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
1789 uint64_t Addr,
1790 const MCDisassembler *Decoder) {
1791 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1792 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1793 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1794
1795 // None of the registers may alias: if they do, then the instruction is not
1796 // merely unpredictable but actually entirely unallocated.
1797 if (Rd == Rm || Rm == Rn || Rd == Rn)
1798 return MCDisassembler::Fail;
1799
1800 // Rd and Rn (not Rm) register operands are written back, so they appear
1801 // twice in the operand list, once as outputs and once as inputs.
1802 if (!DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1803 Inst, Rd, Addr, Decoder) ||
1804 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1805 Inst, Rn, Addr, Decoder) ||
1806 !DecodeSimpleRegisterClass<AArch64::GPR64commonRegClassID, 0, 31>(
1807 Inst, Rd, Addr, Decoder) ||
1808 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1809 Inst, Rn, Addr, Decoder) ||
1810 !DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(
1811 Inst, Rm, Addr, Decoder))
1812 return MCDisassembler::Fail;
1813
1814 return MCDisassembler::Success;
1815}
1816
1817static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
1818 uint64_t Addr,
1819 const MCDisassembler *Decoder) {
1820 // PRFM with Rt = '11xxx' should be decoded as RPRFM.
1821 // Fail to decode and defer to fallback decoder table to decode RPRFM.
1822 unsigned Mask = 0x18;
1823 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1824 if ((Rt & Mask) == Mask)
1825 return Fail;
1826
1827 uint64_t Rn = fieldFromInstruction(insn, 5, 5);
1828 uint64_t Shift = fieldFromInstruction(insn, 12, 1);
1829 uint64_t Extend = fieldFromInstruction(insn, 15, 1);
1830 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
1831
1832 Inst.addOperand(MCOperand::createImm(Rt));
1833 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1834 Decoder);
1835
1836 switch (Inst.getOpcode()) {
1837 default:
1838 return Fail;
1839 case AArch64::PRFMroW:
1840 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1841 Decoder);
1842 break;
1843 case AArch64::PRFMroX:
1844 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1845 Decoder);
1846 break;
1847 }
1848
1849 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
1850
1851 return Success;
1852}
DecodeUnconditionalBranch
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1558
DecodeZPRMul2_MinMax
static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:366
DecodeVecShiftL64Imm
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:625
DecodeVecShiftL32Imm
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:631
createAArch64ExternalSymbolizer
static MCSymbolizer * createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AArch64Disassembler.cpp:305
DecodeCPYMemOpInstruction
static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1757
DecodeVecShiftR8Imm
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:619
DecodeFixedPointScaleImm64
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:467
DecodeAddSubERegInstruction
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1325
DecodeModImmInstruction
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1437
DecodeLogicalImmInstruction
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1400
DecodeMoveImmInstruction
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:717
DecodeSystemPStateImm0_1Instruction
static DecodeStatus DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1601
createAArch64Disassembler
static MCDisassembler * createAArch64Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AArch64Disassembler.cpp:224
DecodeGPR64x8ClassRegisterClass
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:351
DecodeUnsignedLdStInstruction
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:753
MatrixZATileDecoderTable
static const MCPhysReg MatrixZATileDecoderTable[5][16]
Definition: AArch64Disassembler.cpp:424
DecodeXSeqPairsClassRegisterClass
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1668
DecodeAuthLoadInstruction
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1290
DecodeVecShiftL16Imm
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:637
DecodePairLdStInstruction
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1120
SoftFail
#define SoftFail
Definition: AArch64Disassembler.cpp:222
DecodeMatrixTile
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:436
DecodeSImm
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1714
DecodeVecShiftR32ImmNarrow
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:601
DecodeZK
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:392
DecodePPR2Mul2RegisterClass
static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:447
DecodeSystemPStateImm0_15Instruction
static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1580
DecodeVecShiftL8Imm
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:643
DecodePCRelLabel16
static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:474
DecodeSVEIncDecImm
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1741
DecodeFixedPointScaleImm32
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:458
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1622
DecodeSVELogicalImmInstruction
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1696
DecodeVecShiftRImm
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:571
LLVMInitializeAArch64Disassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler()
Definition: AArch64Disassembler.cpp:313
DecodeVecShiftR64Imm
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:583
DecodeVecShiftLImm
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, unsigned Add)
Definition: AArch64Disassembler.cpp:577
DecodeVecShiftR16ImmNarrow
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:613
DecodePCRelLabel9
static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:504
DecodeSVCROp
static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1748
DecodeWSeqPairsClassRegisterClass
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1661
DecodeVecShiftR64ImmNarrow
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:589
DecodeZPR4Mul4RegisterClass
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:403
DecodeAddSubImmShift
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1517
Fail
#define Fail
Definition: AArch64Disassembler.cpp:221
DecodeMSRSystemRegister
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:536
DecodeZPR2Mul2RegisterClass
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: AArch64Disassembler.cpp:379
Success
#define Success
Definition: AArch64Disassembler.cpp:220
DecodeSETMemOpInstruction
static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1788
DecodePCRelLabel19
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:489
DecodeThreeAddrSRegInstruction
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:650
DecodeMemExtend
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:518
DecodeSignedLdStInstruction
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:819
DecodeExclusiveLdStInstruction
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1027
DecodeSyspXzrInstruction
static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1674
DecodeFMOVLaneInstruction
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:544
isInvalidPState
static bool isInvalidPState(uint64_t Op1, uint64_t Op2)
Definition: AArch64Disassembler.cpp:1573
DecodeSimpleRegisterClass
static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:338
DecodeMatrixTileListRegisterClass
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:415
DecodeAdrInstruction
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1498
DecodePRFMRegInstruction
static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1817
DecodeVecShiftR16Imm
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:607
DecodeVecShiftR32Imm
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:595
DecodeImm8OptLsl
static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1729
DecodeGPRSeqPairsClassRegisterClass
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1648
DecodeMRSSystemRegister
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:526
DecodeModImmTiedInstruction
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: AArch64Disassembler.cpp:1478
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:167
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:128
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64Disassembler::getInstruction
MCDisassembler::DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Returns the disassembly of a single instruction.
Definition: AArch64Disassembler.cpp:231
llvm::AArch64Disassembler::suggestBytesToSkip
uint64_t suggestBytesToSkip(ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Suggest a distance to skip in a buffer of data to find the next place to look for the start of an ins...
Definition: AArch64Disassembler.cpp:296
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:168
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:84
llvm::MCDisassembler::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
Definition: MCDisassembler.cpp:28
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:217
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:200
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:224
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:108
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:199
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:211
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:207
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:37
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:135
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:142
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:63
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:114
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:144
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint16_t
uint32_t
uint64_t
uint8_t
LLVMSymbolLookupCallback
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
llvm::AArch64_AM::isValidDecodeLogicalImmediate
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
Definition: AArch64AddressingModes.h:321
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:61
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:964
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:878
Generated on Mon Jan 20 2025 00:13:35 for LLVM by doxygen 1.9.6