LLVM 17.0.0git
AArch64MCTargetDesc.h
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1//===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AArch64 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
14#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15
16#include "llvm/MC/MCInstrDesc.h"
18
19#include <memory>
20
21namespace llvm {
22class formatted_raw_ostream;
23class MCAsmBackend;
24class MCCodeEmitter;
25class MCContext;
26class MCInst;
27class MCInstrInfo;
28class MCInstPrinter;
29class MCRegisterInfo;
30class MCObjectTargetWriter;
31class MCStreamer;
32class MCSubtargetInfo;
33class MCTargetOptions;
34class MCTargetStreamer;
35class Target;
36class Triple;
37
38MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
39 MCContext &Ctx);
40MCAsmBackend *createAArch64leAsmBackend(const Target &T,
41 const MCSubtargetInfo &STI,
42 const MCRegisterInfo &MRI,
43 const MCTargetOptions &Options);
44MCAsmBackend *createAArch64beAsmBackend(const Target &T,
45 const MCSubtargetInfo &STI,
46 const MCRegisterInfo &MRI,
47 const MCTargetOptions &Options);
48
49std::unique_ptr<MCObjectTargetWriter>
50createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
51
52std::unique_ptr<MCObjectTargetWriter>
54 bool IsILP32);
55
56std::unique_ptr<MCObjectTargetWriter>
57createAArch64WinCOFFObjectWriter(const Triple &TheTriple);
58
59MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
60 formatted_raw_ostream &OS,
61 MCInstPrinter *InstPrint,
62 bool isVerboseAsm);
63
64namespace AArch64_MC {
66bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
67bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
68}
69
70namespace AArch64 {
73};
74} // namespace AArch64
75
76} // End llvm namespace
77
78// Defines symbolic names for AArch64 registers. This defines a mapping from
79// register name to register number.
80//
81#define GET_REGINFO_ENUM
82#include "AArch64GenRegisterInfo.inc"
83
84// Defines symbolic names for the AArch64 instructions.
85//
86#define GET_INSTRINFO_ENUM
87#define GET_INSTRINFO_MC_HELPER_DECLS
88#include "AArch64GenInstrInfo.inc"
89
90#define GET_SUBTARGETINFO_ENUM
91#include "AArch64GenSubtargetInfo.inc"
92
93#endif
unsigned const MachineRegisterInfo * MRI
IRTranslator LLVM IR MI
static LVOptions Options
Definition: LVOptions.cpp:25
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
bool isQForm(const MCInst &MI, const MCInstrInfo *MCII)
bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII)
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter(const Triple &TheTriple)
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)