LLVM 24.0.0git
AArch64MCTargetDesc.cpp
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1//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AArch64 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64MCTargetDesc.h"
14#include "AArch64ELFStreamer.h"
15#include "AArch64MCAsmInfo.h"
16#include "AArch64MCLFIRewriter.h"
17#include "AArch64MCOptions.h"
18#include "AArch64WinCOFFStreamer.h"
19#include "MCTargetDesc/AArch64InstPrinter.h"
20#include "TargetInfo/AArch64TargetInfo.h"
21#include "llvm/DebugInfo/CodeView/CodeView.h"
22#include "llvm/MC/MCAsmBackend.h"
23#include "llvm/MC/MCCodeEmitter.h"
24#include "llvm/MC/MCInstrAnalysis.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCObjectWriter.h"
27#include "llvm/MC/MCRegisterInfo.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/MC/TargetRegistry.h"
31#include "llvm/Option/LibraryOptions.h"
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/Endian.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/TargetParser/AArch64TargetParser.h"
36
37using namespace llvm;
38
39#define GET_INSTRINFO_MC_DESC
40#define GET_INSTRINFO_MC_HELPERS
41#define ENABLE_INSTR_PREDICATE_VERIFIER
42#include "AArch64GenInstrInfo.inc"
43
44#define GET_SUBTARGETINFO_MC_DESC
45#include "AArch64GenSubtargetInfo.inc"
46
47#define OPTIONS_STRUCT_DEFS
48#include "AArch64MCOptions.inc"
49
50#define GET_REGINFO_MC_DESC
51#include "AArch64GenRegisterInfo.inc"
52
53static MCInstrInfo *createAArch64MCInstrInfo() {
54 MCInstrInfo *X = new MCInstrInfo();
55 InitAArch64MCInstrInfo(X);
56 return X;
57}
58
59static MCSubtargetInfo *
60createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
61 CPU = AArch64::resolveCPUAlias(CPU);
62
63 if (CPU.empty()) {
64 CPU = "generic";
65 if (FS.empty())
66 FS = "+v8a";
67
68 if (TT.isArm64e())
69 CPU = "apple-a12";
70 }
71
72 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
73}
74
75void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
76 // Mapping from CodeView to MC register id.
77 static const struct {
78 codeview::RegisterId CVReg;
79 MCPhysReg Reg;
80 } RegMap[] = {
81 {codeview::RegisterId::ARM64_W0, AArch64::W0},
82 {codeview::RegisterId::ARM64_W1, AArch64::W1},
83 {codeview::RegisterId::ARM64_W2, AArch64::W2},
84 {codeview::RegisterId::ARM64_W3, AArch64::W3},
85 {codeview::RegisterId::ARM64_W4, AArch64::W4},
86 {codeview::RegisterId::ARM64_W5, AArch64::W5},
87 {codeview::RegisterId::ARM64_W6, AArch64::W6},
88 {codeview::RegisterId::ARM64_W7, AArch64::W7},
89 {codeview::RegisterId::ARM64_W8, AArch64::W8},
90 {codeview::RegisterId::ARM64_W9, AArch64::W9},
91 {codeview::RegisterId::ARM64_W10, AArch64::W10},
92 {codeview::RegisterId::ARM64_W11, AArch64::W11},
93 {codeview::RegisterId::ARM64_W12, AArch64::W12},
94 {codeview::RegisterId::ARM64_W13, AArch64::W13},
95 {codeview::RegisterId::ARM64_W14, AArch64::W14},
96 {codeview::RegisterId::ARM64_W15, AArch64::W15},
97 {codeview::RegisterId::ARM64_W16, AArch64::W16},
98 {codeview::RegisterId::ARM64_W17, AArch64::W17},
99 {codeview::RegisterId::ARM64_W18, AArch64::W18},
100 {codeview::RegisterId::ARM64_W19, AArch64::W19},
101 {codeview::RegisterId::ARM64_W20, AArch64::W20},
102 {codeview::RegisterId::ARM64_W21, AArch64::W21},
103 {codeview::RegisterId::ARM64_W22, AArch64::W22},
104 {codeview::RegisterId::ARM64_W23, AArch64::W23},
105 {codeview::RegisterId::ARM64_W24, AArch64::W24},
106 {codeview::RegisterId::ARM64_W25, AArch64::W25},
107 {codeview::RegisterId::ARM64_W26, AArch64::W26},
108 {codeview::RegisterId::ARM64_W27, AArch64::W27},
109 {codeview::RegisterId::ARM64_W28, AArch64::W28},
110 {codeview::RegisterId::ARM64_W29, AArch64::W29},
111 {codeview::RegisterId::ARM64_W30, AArch64::W30},
112 {codeview::RegisterId::ARM64_WZR, AArch64::WZR},
113 {codeview::RegisterId::ARM64_X0, AArch64::X0},
114 {codeview::RegisterId::ARM64_X1, AArch64::X1},
115 {codeview::RegisterId::ARM64_X2, AArch64::X2},
116 {codeview::RegisterId::ARM64_X3, AArch64::X3},
117 {codeview::RegisterId::ARM64_X4, AArch64::X4},
118 {codeview::RegisterId::ARM64_X5, AArch64::X5},
119 {codeview::RegisterId::ARM64_X6, AArch64::X6},
120 {codeview::RegisterId::ARM64_X7, AArch64::X7},
121 {codeview::RegisterId::ARM64_X8, AArch64::X8},
122 {codeview::RegisterId::ARM64_X9, AArch64::X9},
123 {codeview::RegisterId::ARM64_X10, AArch64::X10},
124 {codeview::RegisterId::ARM64_X11, AArch64::X11},
125 {codeview::RegisterId::ARM64_X12, AArch64::X12},
126 {codeview::RegisterId::ARM64_X13, AArch64::X13},
127 {codeview::RegisterId::ARM64_X14, AArch64::X14},
128 {codeview::RegisterId::ARM64_X15, AArch64::X15},
129 {codeview::RegisterId::ARM64_X16, AArch64::X16},
130 {codeview::RegisterId::ARM64_X17, AArch64::X17},
131 {codeview::RegisterId::ARM64_X18, AArch64::X18},
132 {codeview::RegisterId::ARM64_X19, AArch64::X19},
133 {codeview::RegisterId::ARM64_X20, AArch64::X20},
134 {codeview::RegisterId::ARM64_X21, AArch64::X21},
135 {codeview::RegisterId::ARM64_X22, AArch64::X22},
136 {codeview::RegisterId::ARM64_X23, AArch64::X23},
137 {codeview::RegisterId::ARM64_X24, AArch64::X24},
138 {codeview::RegisterId::ARM64_X25, AArch64::X25},
139 {codeview::RegisterId::ARM64_X26, AArch64::X26},
140 {codeview::RegisterId::ARM64_X27, AArch64::X27},
141 {codeview::RegisterId::ARM64_X28, AArch64::X28},
142 {codeview::RegisterId::ARM64_FP, AArch64::FP},
143 {codeview::RegisterId::ARM64_LR, AArch64::LR},
144 {codeview::RegisterId::ARM64_SP, AArch64::SP},
145 {codeview::RegisterId::ARM64_ZR, AArch64::XZR},
146 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},
147 {codeview::RegisterId::ARM64_S0, AArch64::S0},
148 {codeview::RegisterId::ARM64_S1, AArch64::S1},
149 {codeview::RegisterId::ARM64_S2, AArch64::S2},
150 {codeview::RegisterId::ARM64_S3, AArch64::S3},
151 {codeview::RegisterId::ARM64_S4, AArch64::S4},
152 {codeview::RegisterId::ARM64_S5, AArch64::S5},
153 {codeview::RegisterId::ARM64_S6, AArch64::S6},
154 {codeview::RegisterId::ARM64_S7, AArch64::S7},
155 {codeview::RegisterId::ARM64_S8, AArch64::S8},
156 {codeview::RegisterId::ARM64_S9, AArch64::S9},
157 {codeview::RegisterId::ARM64_S10, AArch64::S10},
158 {codeview::RegisterId::ARM64_S11, AArch64::S11},
159 {codeview::RegisterId::ARM64_S12, AArch64::S12},
160 {codeview::RegisterId::ARM64_S13, AArch64::S13},
161 {codeview::RegisterId::ARM64_S14, AArch64::S14},
162 {codeview::RegisterId::ARM64_S15, AArch64::S15},
163 {codeview::RegisterId::ARM64_S16, AArch64::S16},
164 {codeview::RegisterId::ARM64_S17, AArch64::S17},
165 {codeview::RegisterId::ARM64_S18, AArch64::S18},
166 {codeview::RegisterId::ARM64_S19, AArch64::S19},
167 {codeview::RegisterId::ARM64_S20, AArch64::S20},
168 {codeview::RegisterId::ARM64_S21, AArch64::S21},
169 {codeview::RegisterId::ARM64_S22, AArch64::S22},
170 {codeview::RegisterId::ARM64_S23, AArch64::S23},
171 {codeview::RegisterId::ARM64_S24, AArch64::S24},
172 {codeview::RegisterId::ARM64_S25, AArch64::S25},
173 {codeview::RegisterId::ARM64_S26, AArch64::S26},
174 {codeview::RegisterId::ARM64_S27, AArch64::S27},
175 {codeview::RegisterId::ARM64_S28, AArch64::S28},
176 {codeview::RegisterId::ARM64_S29, AArch64::S29},
177 {codeview::RegisterId::ARM64_S30, AArch64::S30},
178 {codeview::RegisterId::ARM64_S31, AArch64::S31},
179 {codeview::RegisterId::ARM64_D0, AArch64::D0},
180 {codeview::RegisterId::ARM64_D1, AArch64::D1},
181 {codeview::RegisterId::ARM64_D2, AArch64::D2},
182 {codeview::RegisterId::ARM64_D3, AArch64::D3},
183 {codeview::RegisterId::ARM64_D4, AArch64::D4},
184 {codeview::RegisterId::ARM64_D5, AArch64::D5},
185 {codeview::RegisterId::ARM64_D6, AArch64::D6},
186 {codeview::RegisterId::ARM64_D7, AArch64::D7},
187 {codeview::RegisterId::ARM64_D8, AArch64::D8},
188 {codeview::RegisterId::ARM64_D9, AArch64::D9},
189 {codeview::RegisterId::ARM64_D10, AArch64::D10},
190 {codeview::RegisterId::ARM64_D11, AArch64::D11},
191 {codeview::RegisterId::ARM64_D12, AArch64::D12},
192 {codeview::RegisterId::ARM64_D13, AArch64::D13},
193 {codeview::RegisterId::ARM64_D14, AArch64::D14},
194 {codeview::RegisterId::ARM64_D15, AArch64::D15},
195 {codeview::RegisterId::ARM64_D16, AArch64::D16},
196 {codeview::RegisterId::ARM64_D17, AArch64::D17},
197 {codeview::RegisterId::ARM64_D18, AArch64::D18},
198 {codeview::RegisterId::ARM64_D19, AArch64::D19},
199 {codeview::RegisterId::ARM64_D20, AArch64::D20},
200 {codeview::RegisterId::ARM64_D21, AArch64::D21},
201 {codeview::RegisterId::ARM64_D22, AArch64::D22},
202 {codeview::RegisterId::ARM64_D23, AArch64::D23},
203 {codeview::RegisterId::ARM64_D24, AArch64::D24},
204 {codeview::RegisterId::ARM64_D25, AArch64::D25},
205 {codeview::RegisterId::ARM64_D26, AArch64::D26},
206 {codeview::RegisterId::ARM64_D27, AArch64::D27},
207 {codeview::RegisterId::ARM64_D28, AArch64::D28},
208 {codeview::RegisterId::ARM64_D29, AArch64::D29},
209 {codeview::RegisterId::ARM64_D30, AArch64::D30},
210 {codeview::RegisterId::ARM64_D31, AArch64::D31},
211 {codeview::RegisterId::ARM64_Q0, AArch64::Q0},
212 {codeview::RegisterId::ARM64_Q1, AArch64::Q1},
213 {codeview::RegisterId::ARM64_Q2, AArch64::Q2},
214 {codeview::RegisterId::ARM64_Q3, AArch64::Q3},
215 {codeview::RegisterId::ARM64_Q4, AArch64::Q4},
216 {codeview::RegisterId::ARM64_Q5, AArch64::Q5},
217 {codeview::RegisterId::ARM64_Q6, AArch64::Q6},
218 {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
219 {codeview::RegisterId::ARM64_Q8, AArch64::Q8},
220 {codeview::RegisterId::ARM64_Q9, AArch64::Q9},
221 {codeview::RegisterId::ARM64_Q10, AArch64::Q10},
222 {codeview::RegisterId::ARM64_Q11, AArch64::Q11},
223 {codeview::RegisterId::ARM64_Q12, AArch64::Q12},
224 {codeview::RegisterId::ARM64_Q13, AArch64::Q13},
225 {codeview::RegisterId::ARM64_Q14, AArch64::Q14},
226 {codeview::RegisterId::ARM64_Q15, AArch64::Q15},
227 {codeview::RegisterId::ARM64_Q16, AArch64::Q16},
228 {codeview::RegisterId::ARM64_Q17, AArch64::Q17},
229 {codeview::RegisterId::ARM64_Q18, AArch64::Q18},
230 {codeview::RegisterId::ARM64_Q19, AArch64::Q19},
231 {codeview::RegisterId::ARM64_Q20, AArch64::Q20},
232 {codeview::RegisterId::ARM64_Q21, AArch64::Q21},
233 {codeview::RegisterId::ARM64_Q22, AArch64::Q22},
234 {codeview::RegisterId::ARM64_Q23, AArch64::Q23},
235 {codeview::RegisterId::ARM64_Q24, AArch64::Q24},
236 {codeview::RegisterId::ARM64_Q25, AArch64::Q25},
237 {codeview::RegisterId::ARM64_Q26, AArch64::Q26},
238 {codeview::RegisterId::ARM64_Q27, AArch64::Q27},
239 {codeview::RegisterId::ARM64_Q28, AArch64::Q28},
240 {codeview::RegisterId::ARM64_Q29, AArch64::Q29},
241 {codeview::RegisterId::ARM64_Q30, AArch64::Q30},
242 {codeview::RegisterId::ARM64_Q31, AArch64::Q31},
243 {codeview::RegisterId::ARM64_B0, AArch64::B0},
244 {codeview::RegisterId::ARM64_B1, AArch64::B1},
245 {codeview::RegisterId::ARM64_B2, AArch64::B2},
246 {codeview::RegisterId::ARM64_B3, AArch64::B3},
247 {codeview::RegisterId::ARM64_B4, AArch64::B4},
248 {codeview::RegisterId::ARM64_B5, AArch64::B5},
249 {codeview::RegisterId::ARM64_B6, AArch64::B6},
250 {codeview::RegisterId::ARM64_B7, AArch64::B7},
251 {codeview::RegisterId::ARM64_B8, AArch64::B8},
252 {codeview::RegisterId::ARM64_B9, AArch64::B9},
253 {codeview::RegisterId::ARM64_B10, AArch64::B10},
254 {codeview::RegisterId::ARM64_B11, AArch64::B11},
255 {codeview::RegisterId::ARM64_B12, AArch64::B12},
256 {codeview::RegisterId::ARM64_B13, AArch64::B13},
257 {codeview::RegisterId::ARM64_B14, AArch64::B14},
258 {codeview::RegisterId::ARM64_B15, AArch64::B15},
259 {codeview::RegisterId::ARM64_B16, AArch64::B16},
260 {codeview::RegisterId::ARM64_B17, AArch64::B17},
261 {codeview::RegisterId::ARM64_B18, AArch64::B18},
262 {codeview::RegisterId::ARM64_B19, AArch64::B19},
263 {codeview::RegisterId::ARM64_B20, AArch64::B20},
264 {codeview::RegisterId::ARM64_B21, AArch64::B21},
265 {codeview::RegisterId::ARM64_B22, AArch64::B22},
266 {codeview::RegisterId::ARM64_B23, AArch64::B23},
267 {codeview::RegisterId::ARM64_B24, AArch64::B24},
268 {codeview::RegisterId::ARM64_B25, AArch64::B25},
269 {codeview::RegisterId::ARM64_B26, AArch64::B26},
270 {codeview::RegisterId::ARM64_B27, AArch64::B27},
271 {codeview::RegisterId::ARM64_B28, AArch64::B28},
272 {codeview::RegisterId::ARM64_B29, AArch64::B29},
273 {codeview::RegisterId::ARM64_B30, AArch64::B30},
274 {codeview::RegisterId::ARM64_B31, AArch64::B31},
275 {codeview::RegisterId::ARM64_H0, AArch64::H0},
276 {codeview::RegisterId::ARM64_H1, AArch64::H1},
277 {codeview::RegisterId::ARM64_H2, AArch64::H2},
278 {codeview::RegisterId::ARM64_H3, AArch64::H3},
279 {codeview::RegisterId::ARM64_H4, AArch64::H4},
280 {codeview::RegisterId::ARM64_H5, AArch64::H5},
281 {codeview::RegisterId::ARM64_H6, AArch64::H6},
282 {codeview::RegisterId::ARM64_H7, AArch64::H7},
283 {codeview::RegisterId::ARM64_H8, AArch64::H8},
284 {codeview::RegisterId::ARM64_H9, AArch64::H9},
285 {codeview::RegisterId::ARM64_H10, AArch64::H10},
286 {codeview::RegisterId::ARM64_H11, AArch64::H11},
287 {codeview::RegisterId::ARM64_H12, AArch64::H12},
288 {codeview::RegisterId::ARM64_H13, AArch64::H13},
289 {codeview::RegisterId::ARM64_H14, AArch64::H14},
290 {codeview::RegisterId::ARM64_H15, AArch64::H15},
291 {codeview::RegisterId::ARM64_H16, AArch64::H16},
292 {codeview::RegisterId::ARM64_H17, AArch64::H17},
293 {codeview::RegisterId::ARM64_H18, AArch64::H18},
294 {codeview::RegisterId::ARM64_H19, AArch64::H19},
295 {codeview::RegisterId::ARM64_H20, AArch64::H20},
296 {codeview::RegisterId::ARM64_H21, AArch64::H21},
297 {codeview::RegisterId::ARM64_H22, AArch64::H22},
298 {codeview::RegisterId::ARM64_H23, AArch64::H23},
299 {codeview::RegisterId::ARM64_H24, AArch64::H24},
300 {codeview::RegisterId::ARM64_H25, AArch64::H25},
301 {codeview::RegisterId::ARM64_H26, AArch64::H26},
302 {codeview::RegisterId::ARM64_H27, AArch64::H27},
303 {codeview::RegisterId::ARM64_H28, AArch64::H28},
304 {codeview::RegisterId::ARM64_H29, AArch64::H29},
305 {codeview::RegisterId::ARM64_H30, AArch64::H30},
306 {codeview::RegisterId::ARM64_H31, AArch64::H31},
307 };
308 for (const auto &I : RegMap)
309 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
310}
311
312bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) {
313 const auto &FPR16 = getAArch64MCRegisterClass(AArch64::FPR16RegClassID);
314 return llvm::any_of(MI, [&](const MCOperand &Op) {
315 return Op.isReg() && FPR16.contains(Op.getReg());
316 });
317}
318
319bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) {
320 const auto &FPR128 = getAArch64MCRegisterClass(AArch64::FPR128RegClassID);
321 return llvm::any_of(MI, [&](const MCOperand &Op) {
322 return Op.isReg() && FPR128.contains(Op.getReg());
323 });
324}
325
326bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) {
327 const auto &FPR128 = getAArch64MCRegisterClass(AArch64::FPR128RegClassID);
328 const auto &FPR64 = getAArch64MCRegisterClass(AArch64::FPR64RegClassID);
329 const auto &FPR32 = getAArch64MCRegisterClass(AArch64::FPR32RegClassID);
330 const auto &FPR16 = getAArch64MCRegisterClass(AArch64::FPR16RegClassID);
331 const auto &FPR8 = getAArch64MCRegisterClass(AArch64::FPR8RegClassID);
332
333 auto IsFPR = [&](const MCOperand &Op) {
334 if (!Op.isReg())
335 return false;
336 auto Reg = Op.getReg();
337 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) ||
338 FPR16.contains(Reg) || FPR8.contains(Reg);
339 };
340
341 return llvm::any_of(MI, IsFPR);
342}
343
344static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
345 MCRegisterInfo *X = new MCRegisterInfo();
346 InitAArch64MCRegisterInfo(X, AArch64::LR);
347 AArch64_MC::initLLVMToCVRegMapping(X);
348 return X;
349}
350
351static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
352 const Triple &TheTriple,
353 const MCTargetOptions &Options) {
354 MCAsmInfo *MAI;
355 if (TheTriple.isOSBinFormatMachO())
356 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32,
357 Options);
358 else if (TheTriple.isOSBinFormatELF())
359 MAI = new AArch64MCAsmInfoELF(TheTriple, Options);
360 else if (TheTriple.isWindowsMSVCEnvironment())
361 MAI = new AArch64MCAsmInfoMicrosoftCOFF(Options);
362 else if (TheTriple.isOSBinFormatCOFF())
363 MAI = new AArch64MCAsmInfoGNUCOFF(Options);
364 else
365 reportFatalUsageError("unsupported object format");
366
367 // Initial state of the frame pointer is SP.
368 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
369 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
370 MAI->addInitialFrameState(Inst);
371
372 return MAI;
373}
374
375static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
376 unsigned SyntaxVariant,
377 const MCAsmInfo &MAI,
378 const MCInstrInfo &MII,
379 const MCRegisterInfo &MRI) {
380 if (SyntaxVariant == 0)
381 return new AArch64InstPrinter(MAI, MII, MRI);
382 if (SyntaxVariant == 1)
383 return new AArch64AppleInstPrinter(MAI, MII, MRI);
384
385 return nullptr;
386}
387
388static MCStreamer *
389createMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
390 std::unique_ptr<MCObjectWriter> &&OW,
391 std::unique_ptr<MCCodeEmitter> &&Emitter) {
392 return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
393 std::move(Emitter), /*ignore=*/false,
394 /*LabelSections*/ true);
395}
396
397namespace {
398
399class AArch64MCInstrAnalysis : public MCInstrAnalysis {
400public:
401 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
402
403 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
404 uint64_t &Target) const override {
405 // Search for a PC-relative argument.
406 // This will handle instructions like bcc (where the first argument is the
407 // condition code) and cbz (where it is a register).
408 const auto &Desc = Info->get(Inst.getOpcode());
409 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
410 if (Desc.operands()[i].OperandType == MCOI::OPERAND_PCREL) {
411 int64_t Imm = Inst.getOperand(i).getImm();
412 if (Inst.getOpcode() == AArch64::ADR)
413 Target = Addr + Imm;
414 else if (Inst.getOpcode() == AArch64::ADRP)
415 Target = (Addr & -4096) + Imm * 4096;
416 else
417 Target = Addr + Imm * 4;
418 return true;
419 }
420 }
421 return false;
422 }
423
424 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
425 APInt &Mask) const override {
426 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
427 unsigned NumDefs = Desc.getNumDefs();
428 unsigned NumImplicitDefs = Desc.implicit_defs().size();
429 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
430 "Unexpected number of bits in the mask!");
431 // 32-bit General Purpose Register class.
432 const MCRegisterClass &GPR32RC = MRI.getRegClass(AArch64::GPR32RegClassID);
433 // Floating Point Register classes.
434 const MCRegisterClass &FPR8RC = MRI.getRegClass(AArch64::FPR8RegClassID);
435 const MCRegisterClass &FPR16RC = MRI.getRegClass(AArch64::FPR16RegClassID);
436 const MCRegisterClass &FPR32RC = MRI.getRegClass(AArch64::FPR32RegClassID);
437 const MCRegisterClass &FPR64RC = MRI.getRegClass(AArch64::FPR64RegClassID);
438 const MCRegisterClass &FPR128RC =
439 MRI.getRegClass(AArch64::FPR128RegClassID);
440
441 auto ClearsSuperReg = [&](MCRegister Reg) {
442 // An update to the lower 32 bits of a 64 bit integer register is
443 // architecturally defined to zero extend the upper 32 bits on a write.
444 if (GPR32RC.contains(Reg))
445 return true;
446 // SIMD&FP instructions operating on scalar data only access the lower
447 // bits of a register, the upper bits are zero extended on a write. For
448 // SIMD vector registers smaller than 128-bits, the upper 64-bits of the
449 // register are zero extended on a write.
450 // When VL is higher than 128 bits, any write to a SIMD&FP register sets
451 // bits higher than 128 to zero.
452 return FPR8RC.contains(Reg) || FPR16RC.contains(Reg) ||
453 FPR32RC.contains(Reg) || FPR64RC.contains(Reg) ||
454 FPR128RC.contains(Reg);
455 };
456
457 Mask.clearAllBits();
458 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
459 const MCOperand &Op = Inst.getOperand(I);
460 if (ClearsSuperReg(Op.getReg()))
461 Mask.setBit(I);
462 }
463
464 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
465 const MCPhysReg Reg = Desc.implicit_defs()[I];
466 if (ClearsSuperReg(Reg))
467 Mask.setBit(NumDefs + I);
468 }
469
470 return Mask.getBoolValue();
471 }
472
473 std::vector<std::pair<uint64_t, uint64_t>>
474 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
475 const MCSubtargetInfo &STI) const override {
476 // Do a lightweight parsing of PLT entries.
477 std::vector<std::pair<uint64_t, uint64_t>> Result;
478 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
479 Byte += 4) {
480 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
481 uint64_t Off = 0;
482 // Check for optional bti c that prefixes adrp in BTI enabled entries
483 if (Insn == 0xd503245f) {
484 Off = 4;
485 Insn = support::endian::read32le(PltContents.data() + Byte + Off);
486 }
487 // Check for adrp.
488 if ((Insn & 0x9f000000) != 0x90000000)
489 continue;
490 Off += 4;
491 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
492 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
493 uint32_t Insn2 =
494 support::endian::read32le(PltContents.data() + Byte + Off);
495 // Check for: ldr Xt, [Xn, #pimm].
496 if (Insn2 >> 22 == 0x3e5) {
497 Imm += ((Insn2 >> 10) & 0xfff) << 3;
498 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
499 Byte += 4;
500 }
501 }
502 return Result;
503 }
504};
505
506} // end anonymous namespace
507
508static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
509 return new AArch64MCInstrAnalysis(Info);
510}
511
512static MCLFIRewriter *
513createAArch64MCLFIRewriter(MCContext &Ctx,
514 std::unique_ptr<MCRegisterInfo> &&RegInfo,
515 std::unique_ptr<MCInstrInfo> &&InstInfo) {
516 return new AArch64MCLFIRewriter(Ctx, std::move(RegInfo), std::move(InstInfo));
517}
518
519// Force static initialization.
520extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
521LLVMInitializeAArch64TargetMC() {
522 static opt::RegisterLibraryOptions<AArch64MCOptions> O;
523 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
524 &getTheAArch64_32Target(), &getTheARM64Target(),
525 &getTheARM64_32Target()}) {
526 // Register the MC asm info.
527 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
528
529 // Register the MC instruction info.
530 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
531
532 // Register the MC register info.
533 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
534
535 // Register the MC subtarget info.
536 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
537
538 // Register the MC instruction analyzer.
539 TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);
540
541 // Register the MC Code Emitter
542 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
543
544 // Register the obj streamers.
545 TargetRegistry::RegisterELFStreamer(*T, createAArch64ELFStreamer);
546 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
547 TargetRegistry::RegisterCOFFStreamer(*T, createAArch64WinCOFFStreamer);
548
549 // Register the LFI rewriter.
550 TargetRegistry::RegisterMCLFIRewriter(*T, createAArch64MCLFIRewriter);
551
552 // Register the obj target streamer.
553 TargetRegistry::RegisterObjectTargetStreamer(
554 *T, createAArch64ObjectTargetStreamer);
555
556 // Register the asm streamer.
557 TargetRegistry::RegisterAsmTargetStreamer(*T,
558 createAArch64AsmTargetStreamer);
559 // Register the null streamer.
560 TargetRegistry::RegisterNullTargetStreamer(*T,
561 createAArch64NullTargetStreamer);
562
563 // Register the MCInstPrinter.
564 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
565 }
566
567 // Register the asm backend.
568 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),
569 &getTheARM64Target(), &getTheARM64_32Target()})
570 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
571 TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
572 createAArch64beAsmBackend);
573}
createAArch64MCInstPrinter
static MCInstPrinter * createAArch64MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition AArch64MCTargetDesc.cpp:375
createAArch64MCLFIRewriter
static MCLFIRewriter * createAArch64MCLFIRewriter(MCContext &Ctx, std::unique_ptr< MCRegisterInfo > &&RegInfo, std::unique_ptr< MCInstrInfo > &&InstInfo)
Definition AArch64MCTargetDesc.cpp:513
createAArch64MCSubtargetInfo
static MCSubtargetInfo * createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Definition AArch64MCTargetDesc.cpp:60
createAArch64MCRegisterInfo
static MCRegisterInfo * createAArch64MCRegisterInfo(const Triple &Triple)
Definition AArch64MCTargetDesc.cpp:344
LLVMInitializeAArch64TargetMC
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC()
Definition AArch64MCTargetDesc.cpp:521
createAArch64MCInstrInfo
static MCInstrInfo * createAArch64MCInstrInfo()
Definition AArch64MCTargetDesc.cpp:53
createAArch64InstrAnalysis
static MCInstrAnalysis * createAArch64InstrAnalysis(const MCInstrInfo *Info)
Definition AArch64MCTargetDesc.cpp:508
createAArch64MCAsmInfo
static MCAsmInfo * createAArch64MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition AArch64MCTargetDesc.cpp:351
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:539
uint64_t
unsigned uint64_t
Definition AMDGPUDisassembler.cpp:540
X
#define X(NUM, ENUM, NAME)
Definition ELF.h:857
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:215
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
Emitter
dxil DXContainer Global Emitter
Definition DXContainerGlobals.cpp:429
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:863
Options
static LVOptions Options
Definition LVOptions.cpp:25
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2127
T
#define T
Definition Mips16ISelLowering.cpp:282
llvm::AArch64MCLFIRewriter
Rewrites AArch64 instructions for LFI sandboxing.
Definition AArch64MCLFIRewriter.h:47
llvm::ArrayRef::size
size_t size() const
Get the array size.
Definition ArrayRef.h:141
llvm::ArrayRef::data
const T * data() const
Definition ArrayRef.h:138
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition MCAsmInfo.h:67
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition MCAsmInfo.cpp:39
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition MCDwarf.h:628
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition MCInstPrinter.h:46
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition MCInst.h:212
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition MCInst.h:202
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::getImm
int64_t getImm() const
Definition MCInst.h:84
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition MCRegisterInfo.h:106
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:272
llvm::MCRegisterInfo::mapLLVMRegToCVReg
void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg)
Definition MCRegisterInfo.h:480
llvm::MCRegisterInfo::getRegClass
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition MCRegisterInfo.h:595
llvm::MCRegisterInfo::getDwarfRegNum
virtual int64_t getDwarfRegNum(MCRegister Reg, bool isEH) const
Map a target register to an equivalent dwarf register number.
Definition MCRegisterInfo.cpp:144
llvm::MCStreamer
Streaming machine code generation interface.
Definition MCStreamer.h:222
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:141
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:138
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:48
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition Triple.h:876
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition Triple.h:515
llvm::Triple::isOSBinFormatCOFF
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition Triple.h:870
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition Triple.h:867
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition Triple.h:792
llvm::opt::RegisterLibraryOptions
Registers T::Global with cl::ParseCommandLineOptions.
Definition LibraryOptions.h:144
llvm::AArch64_MC::isHForm
bool isHForm(const MCInst &MI, const MCInstrInfo *MCII)
Definition AArch64MCTargetDesc.cpp:312
llvm::AArch64_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition AArch64MCTargetDesc.cpp:75
llvm::AArch64_MC::isQForm
bool isQForm(const MCInst &MI, const MCInstrInfo *MCII)
Definition AArch64MCTargetDesc.cpp:319
llvm::AArch64_MC::isFpOrNEON
bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII)
Definition AArch64MCTargetDesc.cpp:326
llvm::AArch64::resolveCPUAlias
LLVM_ABI StringRef resolveCPUAlias(StringRef CPU)
Definition AArch64TargetParser.cpp:118
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition BitmaskEnum.h:126
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition Endian.h:412
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::createAArch64ELFStreamer
MCStreamer * createAArch64ELFStreamer(const Triple &, MCContext &Context, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)
Definition AArch64ELFStreamer.cpp:573
llvm::createAArch64AsmTargetStreamer
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)
Definition AArch64ELFStreamer.cpp:567
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition AArch64TargetInfo.cpp:18
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:25
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition AArch64TargetInfo.cpp:14
llvm::createMachOStreamer
LLVM_ABI MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
Definition MCMachOStreamer.cpp:500
llvm::createAArch64NullTargetStreamer
MCTargetStreamer * createAArch64NullTargetStreamer(MCStreamer &S)
Definition AArch64TargetStreamer.cpp:147
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1762
llvm::createAArch64leAsmBackend
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition AArch64AsmBackend.cpp:782
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition AArch64TargetInfo.cpp:22
llvm::createAArch64WinCOFFStreamer
MCStreamer * createAArch64WinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)
Definition AArch64WinCOFFStreamer.cpp:302
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition AArch64TargetInfo.cpp:30
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition AArch64TargetInfo.cpp:26
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:24
llvm::createAArch64beAsmBackend
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition AArch64AsmBackend.cpp:802
llvm::createAArch64ObjectTargetStreamer
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition AArch64TargetStreamer.cpp:137
llvm::createAArch64MCCodeEmitter
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition AArch64MCCodeEmitter.cpp:790
llvm::reportFatalUsageError
LLVM_ABI void reportFatalUsageError(Error Err)
Report a fatal error that does not indicate a bug in LLVM.
Definition Error.cpp:177
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition TargetRegistry.h:1100
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition TargetRegistry.h:821
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition TargetRegistry.h:861
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition TargetRegistry.h:927
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition TargetRegistry.h:834
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition TargetRegistry.h:962
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition TargetRegistry.h:807
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition TargetRegistry.h:939
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition TargetRegistry.h:947
llvm::TargetRegistry::RegisterMCLFIRewriter
static void RegisterMCLFIRewriter(Target &T, Target::MCLFIRewriterCtorTy Fn)
Definition TargetRegistry.h:1037
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition TargetRegistry.h:914
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition TargetRegistry.h:931
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition TargetRegistry.h:801
llvm::TargetRegistry::RegisterMachOStreamer
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
Definition TargetRegistry.h:935
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition TargetRegistry.h:956
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