LLVM 20.0.0git
AArch64ELFObjectWriter.cpp
Go to the documentation of this file.
1//===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file handles ELF-specific object emission, converting LLVM's internal
10// fixups into the appropriate relocations.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/AArch64FixupKinds.h"
15#include "MCTargetDesc/AArch64MCExpr.h"
16#include "MCTargetDesc/AArch64MCTargetDesc.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCELFObjectWriter.h"
20#include "llvm/MC/MCFixup.h"
21#include "llvm/MC/MCObjectWriter.h"
22#include "llvm/MC/MCValue.h"
23#include "llvm/Support/ErrorHandling.h"
24#include <cassert>
25#include <cstdint>
26
27using namespace llvm;
28
29namespace {
30
31class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
32public:
33 AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
34
35 ~AArch64ELFObjectWriter() override = default;
36
37 MCSectionELF *getMemtagRelocsSection(MCContext &Ctx) const override;
38
39protected:
40 unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
41 const MCFixup &Fixup, bool IsPCRel) const override;
42 bool needsRelocateWithSymbol(const MCValue &Val, const MCSymbol &Sym,
43 unsigned Type) const override;
44 bool IsILP32;
45};
46
47} // end anonymous namespace
48
49AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
50 : MCELFObjectTargetWriter(/*Is64Bit*/ !IsILP32, OSABI, ELF::EM_AARCH64,
51 /*HasRelocationAddend*/ true),
52 IsILP32(IsILP32) {}
53
54#define R_CLS(rtype) \
55 IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
56#define BAD_ILP32_MOV(lp64rtype) \
57 "ILP32 absolute MOV relocation not " \
58 "supported (LP64 eqv: " #lp64rtype ")"
59
60// assumes IsILP32 is true
61static bool isNonILP32reloc(const MCFixup &Fixup,
62 AArch64MCExpr::VariantKind RefKind,
63 MCContext &Ctx) {
64 if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
65 return false;
66 switch (RefKind) {
67 case AArch64MCExpr::VK_ABS_G3:
68 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
69 return true;
70 case AArch64MCExpr::VK_ABS_G2:
71 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
72 return true;
73 case AArch64MCExpr::VK_ABS_G2_S:
74 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
75 return true;
76 case AArch64MCExpr::VK_ABS_G2_NC:
77 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
78 return true;
79 case AArch64MCExpr::VK_ABS_G1_S:
80 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
81 return true;
82 case AArch64MCExpr::VK_ABS_G1_NC:
83 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
84 return true;
85 case AArch64MCExpr::VK_DTPREL_G2:
86 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
87 return true;
88 case AArch64MCExpr::VK_DTPREL_G1_NC:
89 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
90 return true;
91 case AArch64MCExpr::VK_TPREL_G2:
92 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
93 return true;
94 case AArch64MCExpr::VK_TPREL_G1_NC:
95 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
96 return true;
97 case AArch64MCExpr::VK_GOTTPREL_G1:
98 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
99 return true;
100 case AArch64MCExpr::VK_GOTTPREL_G0_NC:
101 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
102 return true;
103 default:
104 return false;
105 }
106 return false;
107}
108
109unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
110 const MCValue &Target,
111 const MCFixup &Fixup,
112 bool IsPCRel) const {
113 unsigned Kind = Fixup.getTargetKind();
114 if (Kind >= FirstLiteralRelocationKind)
115 return Kind - FirstLiteralRelocationKind;
116 AArch64MCExpr::VariantKind RefKind =
117 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
118 AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
119 bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
120
121 assert((!Target.getSymA() ||
122 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None ||
123 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_PLT ||
124 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_GOTPCREL) &&
125 "Should only be expression-level modifiers here");
126
127 assert((!Target.getSymB() ||
128 Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
129 "Should only be expression-level modifiers here");
130
131 if (IsPCRel) {
132 switch (Kind) {
133 case FK_Data_1:
134 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
135 return ELF::R_AARCH64_NONE;
136 case FK_Data_2:
137 return R_CLS(PREL16);
138 case FK_Data_4: {
139 return Target.getAccessVariant() == MCSymbolRefExpr::VK_PLT
140 ? R_CLS(PLT32)
141 : R_CLS(PREL32);
142 }
143 case FK_Data_8:
144 if (IsILP32) {
145 Ctx.reportError(Fixup.getLoc(),
146 "ILP32 8 byte PC relative data "
147 "relocation not supported (LP64 eqv: PREL64)");
148 return ELF::R_AARCH64_NONE;
149 }
150 return ELF::R_AARCH64_PREL64;
151 case AArch64::fixup_aarch64_pcrel_adr_imm21:
152 if (SymLoc != AArch64MCExpr::VK_ABS)
153 Ctx.reportError(Fixup.getLoc(),
154 "invalid symbol kind for ADR relocation");
155 return R_CLS(ADR_PREL_LO21);
156 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
157 if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
158 return R_CLS(ADR_PREL_PG_HI21);
159 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
160 if (IsILP32) {
161 Ctx.reportError(Fixup.getLoc(),
162 "invalid fixup for 32-bit pcrel ADRP instruction "
163 "VK_ABS VK_NC");
164 return ELF::R_AARCH64_NONE;
165 }
166 return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
167 }
168 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
169 return R_CLS(ADR_GOT_PAGE);
170 if (SymLoc == AArch64MCExpr::VK_GOT_AUTH && !IsNC) {
171 if (IsILP32) {
172 Ctx.reportError(Fixup.getLoc(),
173 "ILP32 ADRP AUTH relocation not supported "
174 "(LP64 eqv: AUTH_ADR_GOT_PAGE)");
175 return ELF::R_AARCH64_NONE;
176 }
177 return ELF::R_AARCH64_AUTH_ADR_GOT_PAGE;
178 }
179 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
180 return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
181 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
182 return R_CLS(TLSDESC_ADR_PAGE21);
183 Ctx.reportError(Fixup.getLoc(),
184 "invalid symbol kind for ADRP relocation");
185 return ELF::R_AARCH64_NONE;
186 case AArch64::fixup_aarch64_pcrel_branch26:
187 return R_CLS(JUMP26);
188 case AArch64::fixup_aarch64_pcrel_call26:
189 return R_CLS(CALL26);
190 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
191 if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
192 return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
193 if (SymLoc == AArch64MCExpr::VK_GOT)
194 return R_CLS(GOT_LD_PREL19);
195 return R_CLS(LD_PREL_LO19);
196 case AArch64::fixup_aarch64_pcrel_branch14:
197 return R_CLS(TSTBR14);
198 case AArch64::fixup_aarch64_pcrel_branch16:
199 Ctx.reportError(Fixup.getLoc(),
200 "relocation of PAC/AUT instructions is not supported");
201 return ELF::R_AARCH64_NONE;
202 case AArch64::fixup_aarch64_pcrel_branch19:
203 return R_CLS(CONDBR19);
204 default:
205 Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
206 return ELF::R_AARCH64_NONE;
207 }
208 } else {
209 if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
210 return ELF::R_AARCH64_NONE;
211 switch (Fixup.getTargetKind()) {
212 case FK_Data_1:
213 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
214 return ELF::R_AARCH64_NONE;
215 case FK_Data_2:
216 return R_CLS(ABS16);
217 case FK_Data_4:
218 return (!IsILP32 &&
219 Target.getAccessVariant() == MCSymbolRefExpr::VK_GOTPCREL)
220 ? ELF::R_AARCH64_GOTPCREL32
221 : R_CLS(ABS32);
222 case FK_Data_8: {
223 bool IsAuth = (RefKind == AArch64MCExpr::VK_AUTH ||
224 RefKind == AArch64MCExpr::VK_AUTHADDR);
225 if (IsILP32) {
226 Ctx.reportError(Fixup.getLoc(),
227 Twine("ILP32 8 byte absolute data "
228 "relocation not supported (LP64 eqv: ") +
229 (IsAuth ? "AUTH_ABS64" : "ABS64") + Twine(')'));
230 return ELF::R_AARCH64_NONE;
231 }
232 return (IsAuth ? ELF::R_AARCH64_AUTH_ABS64 : ELF::R_AARCH64_ABS64);
233 }
234 case AArch64::fixup_aarch64_add_imm12:
235 if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
236 return R_CLS(TLSLD_ADD_DTPREL_HI12);
237 if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
238 return R_CLS(TLSLE_ADD_TPREL_HI12);
239 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
240 return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
241 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
242 return R_CLS(TLSLD_ADD_DTPREL_LO12);
243 if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
244 return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
245 if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
246 return R_CLS(TLSLE_ADD_TPREL_LO12);
247 if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
248 return R_CLS(TLSDESC_ADD_LO12);
249 if (RefKind == AArch64MCExpr::VK_GOT_AUTH_LO12 && IsNC) {
250 if (IsILP32) {
251 Ctx.reportError(Fixup.getLoc(),
252 "ILP32 ADD AUTH relocation not supported "
253 "(LP64 eqv: AUTH_GOT_ADD_LO12_NC)");
254 return ELF::R_AARCH64_NONE;
255 }
256 return ELF::R_AARCH64_AUTH_GOT_ADD_LO12_NC;
257 }
258 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
259 return R_CLS(ADD_ABS_LO12_NC);
260
261 Ctx.reportError(Fixup.getLoc(),
262 "invalid fixup for add (uimm12) instruction");
263 return ELF::R_AARCH64_NONE;
264 case AArch64::fixup_aarch64_ldst_imm12_scale1:
265 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
266 return R_CLS(LDST8_ABS_LO12_NC);
267 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
268 return R_CLS(TLSLD_LDST8_DTPREL_LO12);
269 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
270 return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
271 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
272 return R_CLS(TLSLE_LDST8_TPREL_LO12);
273 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
274 return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
275
276 Ctx.reportError(Fixup.getLoc(),
277 "invalid fixup for 8-bit load/store instruction");
278 return ELF::R_AARCH64_NONE;
279 case AArch64::fixup_aarch64_ldst_imm12_scale2:
280 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
281 return R_CLS(LDST16_ABS_LO12_NC);
282 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
283 return R_CLS(TLSLD_LDST16_DTPREL_LO12);
284 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
285 return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
286 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
287 return R_CLS(TLSLE_LDST16_TPREL_LO12);
288 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
289 return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
290
291 Ctx.reportError(Fixup.getLoc(),
292 "invalid fixup for 16-bit load/store instruction");
293 return ELF::R_AARCH64_NONE;
294 case AArch64::fixup_aarch64_ldst_imm12_scale4:
295 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
296 return R_CLS(LDST32_ABS_LO12_NC);
297 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
298 return R_CLS(TLSLD_LDST32_DTPREL_LO12);
299 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
300 return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
301 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
302 return R_CLS(TLSLE_LDST32_TPREL_LO12);
303 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
304 return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
305 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
306 if (IsILP32)
307 return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
308 Ctx.reportError(Fixup.getLoc(),
309 "LP64 4 byte unchecked GOT load/store relocation "
310 "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
311 return ELF::R_AARCH64_NONE;
312 }
313 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
314 if (IsILP32) {
315 Ctx.reportError(Fixup.getLoc(),
316 "ILP32 4 byte checked GOT load/store relocation "
317 "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
318 } else {
319 Ctx.reportError(Fixup.getLoc(),
320 "LP64 4 byte checked GOT load/store relocation "
321 "not supported (unchecked/ILP32 eqv: "
322 "LD32_GOT_LO12_NC)");
323 }
324 return ELF::R_AARCH64_NONE;
325 }
326 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
327 if (IsILP32)
328 return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
329 Ctx.reportError(Fixup.getLoc(), "LP64 32-bit load/store "
330 "relocation not supported (ILP32 eqv: "
331 "TLSIE_LD32_GOTTPREL_LO12_NC)");
332 return ELF::R_AARCH64_NONE;
333 }
334 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
335 if (IsILP32)
336 return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
337 Ctx.reportError(Fixup.getLoc(),
338 "LP64 4 byte TLSDESC load/store relocation "
339 "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
340 return ELF::R_AARCH64_NONE;
341 }
342
343 Ctx.reportError(Fixup.getLoc(),
344 "invalid fixup for 32-bit load/store instruction "
345 "fixup_aarch64_ldst_imm12_scale4");
346 return ELF::R_AARCH64_NONE;
347 case AArch64::fixup_aarch64_ldst_imm12_scale8:
348 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
349 return R_CLS(LDST64_ABS_LO12_NC);
350 if ((SymLoc == AArch64MCExpr::VK_GOT ||
351 SymLoc == AArch64MCExpr::VK_GOT_AUTH) &&
352 IsNC) {
353 AArch64MCExpr::VariantKind AddressLoc =
354 AArch64MCExpr::getAddressFrag(RefKind);
355 bool IsAuth = (SymLoc == AArch64MCExpr::VK_GOT_AUTH);
356 if (!IsILP32) {
357 if (AddressLoc == AArch64MCExpr::VK_LO15)
358 return ELF::R_AARCH64_LD64_GOTPAGE_LO15;
359 return (IsAuth ? ELF::R_AARCH64_AUTH_LD64_GOT_LO12_NC
360 : ELF::R_AARCH64_LD64_GOT_LO12_NC);
361 }
362 Ctx.reportError(Fixup.getLoc(),
363 Twine("ILP32 64-bit load/store "
364 "relocation not supported (LP64 eqv: ") +
365 (IsAuth ? "AUTH_GOT_LO12_NC" : "LD64_GOT_LO12_NC") +
366 Twine(')'));
367 return ELF::R_AARCH64_NONE;
368 }
369 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
370 return R_CLS(TLSLD_LDST64_DTPREL_LO12);
371 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
372 return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
373 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
374 return R_CLS(TLSLE_LDST64_TPREL_LO12);
375 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
376 return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
377 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
378 if (!IsILP32)
379 return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
380 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
381 "relocation not supported (LP64 eqv: "
382 "TLSIE_LD64_GOTTPREL_LO12_NC)");
383 return ELF::R_AARCH64_NONE;
384 }
385 if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
386 if (!IsILP32)
387 return ELF::R_AARCH64_TLSDESC_LD64_LO12;
388 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
389 "relocation not supported (LP64 eqv: "
390 "TLSDESC_LD64_LO12)");
391 return ELF::R_AARCH64_NONE;
392 }
393 Ctx.reportError(Fixup.getLoc(),
394 "invalid fixup for 64-bit load/store instruction");
395 return ELF::R_AARCH64_NONE;
396 case AArch64::fixup_aarch64_ldst_imm12_scale16:
397 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
398 return R_CLS(LDST128_ABS_LO12_NC);
399 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
400 return R_CLS(TLSLD_LDST128_DTPREL_LO12);
401 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
402 return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
403 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
404 return R_CLS(TLSLE_LDST128_TPREL_LO12);
405 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
406 return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
407
408 Ctx.reportError(Fixup.getLoc(),
409 "invalid fixup for 128-bit load/store instruction");
410 return ELF::R_AARCH64_NONE;
411 // ILP32 case not reached here, tested with isNonILP32reloc
412 case AArch64::fixup_aarch64_movw:
413 if (RefKind == AArch64MCExpr::VK_ABS_G3)
414 return ELF::R_AARCH64_MOVW_UABS_G3;
415 if (RefKind == AArch64MCExpr::VK_ABS_G2)
416 return ELF::R_AARCH64_MOVW_UABS_G2;
417 if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
418 return ELF::R_AARCH64_MOVW_SABS_G2;
419 if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
420 return ELF::R_AARCH64_MOVW_UABS_G2_NC;
421 if (RefKind == AArch64MCExpr::VK_ABS_G1)
422 return R_CLS(MOVW_UABS_G1);
423 if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
424 return ELF::R_AARCH64_MOVW_SABS_G1;
425 if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
426 return ELF::R_AARCH64_MOVW_UABS_G1_NC;
427 if (RefKind == AArch64MCExpr::VK_ABS_G0)
428 return R_CLS(MOVW_UABS_G0);
429 if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
430 return R_CLS(MOVW_SABS_G0);
431 if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
432 return R_CLS(MOVW_UABS_G0_NC);
433 if (RefKind == AArch64MCExpr::VK_PREL_G3)
434 return ELF::R_AARCH64_MOVW_PREL_G3;
435 if (RefKind == AArch64MCExpr::VK_PREL_G2)
436 return ELF::R_AARCH64_MOVW_PREL_G2;
437 if (RefKind == AArch64MCExpr::VK_PREL_G2_NC)
438 return ELF::R_AARCH64_MOVW_PREL_G2_NC;
439 if (RefKind == AArch64MCExpr::VK_PREL_G1)
440 return R_CLS(MOVW_PREL_G1);
441 if (RefKind == AArch64MCExpr::VK_PREL_G1_NC)
442 return ELF::R_AARCH64_MOVW_PREL_G1_NC;
443 if (RefKind == AArch64MCExpr::VK_PREL_G0)
444 return R_CLS(MOVW_PREL_G0);
445 if (RefKind == AArch64MCExpr::VK_PREL_G0_NC)
446 return R_CLS(MOVW_PREL_G0_NC);
447 if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
448 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
449 if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
450 return R_CLS(TLSLD_MOVW_DTPREL_G1);
451 if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
452 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
453 if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
454 return R_CLS(TLSLD_MOVW_DTPREL_G0);
455 if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
456 return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
457 if (RefKind == AArch64MCExpr::VK_TPREL_G2)
458 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
459 if (RefKind == AArch64MCExpr::VK_TPREL_G1)
460 return R_CLS(TLSLE_MOVW_TPREL_G1);
461 if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
462 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
463 if (RefKind == AArch64MCExpr::VK_TPREL_G0)
464 return R_CLS(TLSLE_MOVW_TPREL_G0);
465 if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
466 return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
467 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
468 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
469 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
470 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
471 Ctx.reportError(Fixup.getLoc(),
472 "invalid fixup for movz/movk instruction");
473 return ELF::R_AARCH64_NONE;
474 default:
475 Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
476 return ELF::R_AARCH64_NONE;
477 }
478 }
479
480 llvm_unreachable("Unimplemented fixup -> relocation");
481}
482
483bool AArch64ELFObjectWriter::needsRelocateWithSymbol(const MCValue &Val,
484 const MCSymbol &,
485 unsigned) const {
486 return (Val.getRefKind() & AArch64MCExpr::VK_GOT) == AArch64MCExpr::VK_GOT;
487}
488
489MCSectionELF *
490AArch64ELFObjectWriter::getMemtagRelocsSection(MCContext &Ctx) const {
491 return Ctx.getELFSection(".memtag.globals.static",
492 ELF::SHT_AARCH64_MEMTAG_GLOBALS_STATIC, 0);
493}
494
495std::unique_ptr<MCObjectTargetWriter>
496llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
497 return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
498}
BAD_ILP32_MOV
#define BAD_ILP32_MOV(lp64rtype)
Definition: AArch64ELFObjectWriter.cpp:56
R_CLS
#define R_CLS(rtype)
Definition: AArch64ELFObjectWriter.cpp:54
isNonILP32reloc
static bool isNonILP32reloc(const MCFixup &Fixup, AArch64MCExpr::VariantKind RefKind, MCContext &Ctx)
Definition: AArch64ELFObjectWriter.cpp:61
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1965
Sym
Symbol * Sym
Definition: ELF_riscv.cpp:479
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:340
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64MCExpr::getSymbolLoc
static VariantKind getSymbolLoc(VariantKind Kind)
Definition: AArch64MCExpr.h:153
llvm::AArch64MCExpr::isNotChecked
static bool isNotChecked(VariantKind Kind)
Definition: AArch64MCExpr.h:161
llvm::AArch64MCExpr::getAddressFrag
static VariantKind getAddressFrag(VariantKind Kind)
Definition: AArch64MCExpr.h:157
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCContext::getELFSection
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:551
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1068
llvm::MCELFObjectTargetWriter::needsRelocateWithSymbol
virtual bool needsRelocateWithSymbol(const MCValue &Val, const MCSymbol &Sym, unsigned Type) const
Definition: MCELFObjectTargetWriter.cpp:20
llvm::MCELFObjectTargetWriter::getMemtagRelocsSection
virtual MCSectionELF * getMemtagRelocsSection(MCContext &Ctx) const
Definition: MCELFObjectWriter.h:150
llvm::MCELFObjectTargetWriter::getRelocType
virtual unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const =0
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::MCSectionELF
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:27
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::MCValue::getRefKind
uint32_t getRefKind() const
Definition: MCValue.h:46
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:144
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AArch64::fixup_aarch64_ldst_imm12_scale16
@ fixup_aarch64_ldst_imm12_scale16
Definition: AArch64FixupKinds.h:33
llvm::ELF::EM_AARCH64
@ EM_AARCH64
Definition: ELF.h:281
llvm::ELF::SHT_AARCH64_MEMTAG_GLOBALS_STATIC
@ SHT_AARCH64_MEMTAG_GLOBALS_STATIC
Definition: ELF.h:1148
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::FirstLiteralRelocationKind
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
llvm::createAArch64ELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
Definition: AArch64ELFObjectWriter.cpp:496
Generated on Thu Aug 15 2024 18:49:45 for LLVM by doxygen 1.9.6