50#define DEBUG_TYPE "regalloc"
54STATISTIC(NumCoalesced,
"Number of copies coalesced");
70 bool ClearVirtRegs_ =
true) :
72 ShouldAllocateClass(
F),
73 StackSlotForVirtReg(-1),
74 ClearVirtRegs(ClearVirtRegs_) {
99 bool Reloaded =
false;
102 explicit LiveReg(
Register VirtReg) : VirtReg(VirtReg) {}
104 unsigned getSparseSetIndex()
const {
112 LiveRegMap LiveVirtRegs;
146 std::vector<unsigned> RegUnitStates;
153 RegUnitSet UsedInInstr;
154 RegUnitSet PhysRegUses;
159 void setPhysRegState(
MCPhysReg PhysReg,
unsigned NewState);
160 bool isPhysRegFree(
MCPhysReg PhysReg)
const;
163 void markRegUsedInInstr(
MCPhysReg PhysReg) {
165 UsedInInstr.insert(*Units);
169 bool isClobberedByRegMasks(
MCPhysReg PhysReg)
const {
176 bool isRegUsedInInstr(
MCPhysReg PhysReg,
bool LookAtPhysRegUses)
const {
177 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
180 if (UsedInInstr.count(*Units))
182 if (LookAtPhysRegUses && PhysRegUses.count(*Units))
190 void markPhysRegUsedInInstr(
MCPhysReg PhysReg) {
192 PhysRegUses.insert(*Units);
196 void unmarkRegUsedInInstr(
MCPhysReg PhysReg) {
198 UsedInInstr.erase(*Units);
205 spillImpossible = ~0
u
218 MachineFunctionProperties::Property::NoPHIs);
224 MachineFunctionProperties::Property::NoVRegs);
232 MachineFunctionProperties::Property::IsSSA);
240 void addRegClassDefCounts(std::vector<unsigned> &RegClassDefCounts,
254 unsigned calcSpillCost(
MCPhysReg PhysReg)
const;
266 bool LookAtPhysRegUses =
false);
273 bool LookAtPhysRegUses =
false);
286 bool shouldAllocateRegister(
const Register Reg)
const;
287 int getStackSpaceFor(
Register VirtReg);
289 MCPhysReg AssignedReg,
bool Kill,
bool LiveOut);
296 void dumpState()
const;
301char RegAllocFast::ID = 0;
309 return ShouldAllocateClass(*
TRI, RC);
312void RegAllocFast::setPhysRegState(
MCPhysReg PhysReg,
unsigned NewState) {
314 RegUnitStates[*UI] = NewState;
317bool RegAllocFast::isPhysRegFree(
MCPhysReg PhysReg)
const {
319 if (RegUnitStates[*UI] != regFree)
327int RegAllocFast::getStackSpaceFor(
Register VirtReg) {
329 int SS = StackSlotForVirtReg[VirtReg];
336 unsigned Size =
TRI->getSpillSize(RC);
337 Align Alignment =
TRI->getSpillAlign(RC);
341 StackSlotForVirtReg[VirtReg] = FrameIdx;
353 for (; &*
I !=
A && &*
I !=
B; ++
I)
360bool RegAllocFast::mayLiveOut(
Register VirtReg) {
373 if (DefInst.getParent() !=
MBB) {
378 SelfLoopDef = &DefInst;
389 static const unsigned Limit = 8;
391 for (
const MachineInstr &UseInst :
MRI->use_nodbg_instructions(VirtReg)) {
392 if (UseInst.getParent() !=
MBB || ++
C >= Limit) {
401 if (SelfLoopDef == &UseInst ||
413bool RegAllocFast::mayLiveIn(
Register VirtReg) {
418 static const unsigned Limit = 8;
421 if (DefInst.getParent() !=
MBB || ++
C >= Limit) {
433 MCPhysReg AssignedReg,
bool Kill,
bool LiveOut) {
436 int FI = getStackSpaceFor(VirtReg);
453 SpilledOperandsMap[MO->getParent()].push_back(MO);
454 for (
auto MISpilledOperands : SpilledOperandsMap) {
460 *
MBB, Before, *MISpilledOperands.first, FI, MISpilledOperands.second);
463 LLVM_DEBUG(
dbgs() <<
"Inserting debug info due to spill:\n" << *NewDV);
472 LLVM_DEBUG(
dbgs() <<
"Cloning debug info due to live out spill\n");
488 LRIDbgOperands.clear();
496 int FI = getStackSpaceFor(VirtReg);
507RegAllocFast::getMBBBeginInsertionPoint(
517 if (!
TII->isBasicBlockPrologue(*
I))
535 if (LiveVirtRegs.empty())
542 setPhysRegState(Reg, regLiveIn);
551 = getMBBBeginInsertionPoint(
MBB, PrologLiveIns);
552 for (
const LiveReg &LR : LiveVirtRegs) {
558 if (RegUnitStates[FirstUnit] == regLiveIn)
562 "no reload in start block. Missing vreg def?");
564 if (PrologLiveIns.
count(PhysReg)) {
568 reload(
MBB.
begin(), LR.VirtReg, PhysReg);
570 reload(InsertBefore, LR.VirtReg, PhysReg);
572 LiveVirtRegs.clear();
580 bool displacedAny = displacePhysReg(
MI, Reg);
581 setPhysRegState(Reg, regPreAssigned);
582 markRegUsedInInstr(Reg);
587 bool displacedAny = displacePhysReg(
MI, Reg);
588 setPhysRegState(Reg, regPreAssigned);
596 bool displacedAny =
false;
600 switch (
unsigned VirtReg = RegUnitStates[Unit]) {
602 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
603 assert(LRI != LiveVirtRegs.end() &&
"datastructures in sync");
606 reload(ReloadBefore, VirtReg, LRI->PhysReg);
608 setPhysRegState(LRI->PhysReg, regFree);
610 LRI->Reloaded =
true;
615 RegUnitStates[Unit] = regFree;
625void RegAllocFast::freePhysReg(
MCPhysReg PhysReg) {
629 switch (
unsigned VirtReg = RegUnitStates[FirstUnit]) {
635 setPhysRegState(PhysReg, regFree);
638 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
639 assert(LRI != LiveVirtRegs.end());
641 setPhysRegState(LRI->PhysReg, regFree);
652unsigned RegAllocFast::calcSpillCost(
MCPhysReg PhysReg)
const {
654 switch (
unsigned VirtReg = RegUnitStates[*UI]) {
660 return spillImpossible;
662 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 ||
663 findLiveVirtReg(VirtReg)->LiveOut;
664 return SureSpill ? spillClean : spillDirty;
671void RegAllocFast::assignDanglingDebugValues(
MachineInstr &Definition,
673 auto UDBGValIter = DanglingDbgValues.
find(VirtReg);
674 if (UDBGValIter == DanglingDbgValues.
end())
680 if (!
DbgValue->hasDebugOperandForReg(VirtReg))
688 if (
I->modifiesRegister(Reg,
TRI) || --Limit == 0) {
707void RegAllocFast::assignVirtToPhysReg(
MachineInstr &AtMI, LiveReg &LR,
712 assert(LR.PhysReg == 0 &&
"Already assigned a physreg");
713 assert(PhysReg != 0 &&
"Trying to assign no register");
714 LR.PhysReg = PhysReg;
715 setPhysRegState(PhysReg, VirtReg);
717 assignDanglingDebugValues(AtMI, VirtReg, PhysReg);
721 return MI.isFullCopy();
725 static const unsigned ChainLengthLimit = 3;
728 if (
Reg.isPhysical())
736 }
while (++
C <= ChainLengthLimit);
744 static const unsigned DefLimit = 3;
749 Reg = traceCopyChain(Reg);
762 Register Hint0,
bool LookAtPhysRegUses) {
763 const Register VirtReg = LR.VirtReg;
768 <<
" in class " <<
TRI->getRegClassName(&RC)
773 !isRegUsedInInstr(Hint0, LookAtPhysRegUses)) {
775 if (isPhysRegFree(Hint0)) {
778 assignVirtToPhysReg(
MI, LR, Hint0);
790 Register Hint1 = traceCopies(VirtReg);
792 !isRegUsedInInstr(Hint1, LookAtPhysRegUses)) {
794 if (isPhysRegFree(Hint1)) {
797 assignVirtToPhysReg(
MI, LR, Hint1);
808 unsigned BestCost = spillImpossible;
812 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) {
817 unsigned Cost = calcSpillCost(PhysReg);
821 assignVirtToPhysReg(
MI, LR, PhysReg);
825 if (PhysReg == Hint0 || PhysReg == Hint1)
826 Cost -= spillPrefBonus;
828 if (
Cost < BestCost) {
837 if (
MI.isInlineAsm())
838 MI.emitError(
"inline assembly requires more registers than available");
840 MI.emitError(
"ran out of registers during register allocation");
847 displacePhysReg(
MI, BestReg);
848 assignVirtToPhysReg(
MI, LR, BestReg);
855 if (!shouldAllocateRegister(VirtReg))
858 LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
860 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
861 PhysReg = LRI->PhysReg;
870 if (SubRegIdx != 0) {
871 PhysReg =
TRI->getSubReg(PhysReg, SubRegIdx);
881bool RegAllocFast::defineLiveThroughVirtReg(
MachineInstr &
MI,
unsigned OpNum,
883 if (!shouldAllocateRegister(VirtReg))
885 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
886 if (LRI != LiveVirtRegs.end()) {
888 if (PrevReg != 0 && isRegUsedInInstr(PrevReg,
true)) {
890 <<
" (tied/earlyclobber resolution)\n");
891 freePhysReg(PrevReg);
893 allocVirtReg(
MI, *LRI, 0,
true);
899 TII->get(TargetOpcode::COPY), PrevReg)
907 return defineVirtReg(
MI, OpNum, VirtReg,
true);
918 Register VirtReg,
bool LookAtPhysRegUses) {
920 if (!shouldAllocateRegister(VirtReg))
923 LiveRegMap::iterator LRI;
925 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
928 if (mayLiveOut(VirtReg)) {
936 if (LRI->PhysReg == 0)
937 allocVirtReg(
MI, *LRI, 0, LookAtPhysRegUses);
939 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) &&
940 "TODO: preassign mismatch");
942 <<
" use existing assignment to "
947 assert(PhysReg != 0 &&
"Register not assigned");
948 if (LRI->Reloaded || LRI->LiveOut) {
949 if (!
MI.isImplicitDef()) {
952 LLVM_DEBUG(
dbgs() <<
"Spill Reason: LO: " << LRI->LiveOut <<
" RL: "
953 << LRI->Reloaded <<
'\n');
954 bool Kill = LRI->LastUse ==
nullptr;
955 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
959 if (
MI.getOpcode() == TargetOpcode::INLINEASM_BR) {
960 int FI = StackSlotForVirtReg[VirtReg];
966 FI, &RC,
TRI, VirtReg);
973 LRI->LastUse =
nullptr;
975 LRI->LiveOut =
false;
976 LRI->Reloaded =
false;
978 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
979 BundleVirtRegsMap[VirtReg] = PhysReg;
981 markRegUsedInInstr(PhysReg);
982 return setPhysReg(
MI, MO, PhysReg);
990 if (!shouldAllocateRegister(VirtReg))
993 LiveRegMap::iterator LRI;
995 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
999 if (mayLiveOut(VirtReg)) {
1000 LRI->LiveOut =
true;
1007 assert((!MO.
isKill() || LRI->LastUse == &
MI) &&
"Invalid kill flag");
1011 if (LRI->PhysReg == 0) {
1014 if (
MI.isCopy() &&
MI.getOperand(1).getSubReg() == 0) {
1015 Hint =
MI.getOperand(0).getReg();
1017 assert(!shouldAllocateRegister(Hint));
1021 "Copy destination should already be assigned");
1024 allocVirtReg(
MI, *LRI, Hint,
false);
1034 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
1035 BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1037 markRegUsedInInstr(LRI->PhysReg);
1038 return setPhysReg(
MI, MO, LRI->PhysReg);
1063 MI.addRegisterKilled(PhysReg,
TRI,
true);
1072 MI.addRegisterDead(PhysReg,
TRI,
true);
1074 MI.addRegisterDefined(PhysReg,
TRI);
1083void RegAllocFast::dumpState()
const {
1084 for (
unsigned Unit = 1, UnitE =
TRI->getNumRegUnits(); Unit != UnitE;
1086 switch (
unsigned VirtReg = RegUnitStates[Unit]) {
1089 case regPreAssigned:
1096 LiveRegMap::const_iterator
I = findLiveVirtReg(VirtReg);
1097 assert(
I != LiveVirtRegs.end() &&
"have LiveVirtRegs entry");
1098 if (
I->LiveOut ||
I->Reloaded) {
1100 if (
I->LiveOut)
dbgs() <<
'O';
1101 if (
I->Reloaded)
dbgs() <<
'R';
1104 assert(
TRI->hasRegUnit(
I->PhysReg, Unit) &&
"inverse mapping present");
1111 for (
const LiveReg &LR : LiveVirtRegs) {
1117 "mapped to physreg");
1119 assert(RegUnitStates[*UI] == VirtReg &&
"inverse map valid");
1127void RegAllocFast::addRegClassDefCounts(std::vector<unsigned> &RegClassDefCounts,
1129 assert(RegClassDefCounts.size() ==
TRI->getNumRegClasses());
1131 if (
Reg.isVirtual()) {
1132 if (!shouldAllocateRegister(Reg))
1135 for (
unsigned RCIdx = 0, RCIdxEnd =
TRI->getNumRegClasses();
1136 RCIdx != RCIdxEnd; ++RCIdx) {
1140 ++RegClassDefCounts[RCIdx];
1146 for (
unsigned RCIdx = 0, RCIdxEnd =
TRI->getNumRegClasses();
1147 RCIdx != RCIdxEnd; ++RCIdx) {
1151 ++RegClassDefCounts[RCIdx];
1161void RegAllocFast::findAndSortDefOperandIndexes(
const MachineInstr &
MI) {
1162 DefOperandIndexes.
clear();
1165 std::vector<unsigned> RegClassDefCounts(
TRI->getNumRegClasses(), 0);
1166 assert(RegClassDefCounts[0] == 0);
1169 for (
unsigned I = 0,
E =
MI.getNumOperands();
I <
E; ++
I) {
1175 if (
Reg.isPhysical()) {
1177 markPhysRegUsedInInstr(Reg);
1182 if (
Reg.isVirtual() && shouldAllocateRegister(Reg))
1185 addRegClassDefCounts(RegClassDefCounts, Reg);
1199 unsigned ClassSize0 = RegClassInfo.
getOrder(&RC0).
size();
1200 unsigned ClassSize1 = RegClassInfo.
getOrder(&RC1).
size();
1202 bool SmallClass0 = ClassSize0 < RegClassDefCounts[RC0.
getID()];
1203 bool SmallClass1 = ClassSize1 < RegClassDefCounts[RC1.
getID()];
1204 if (SmallClass0 > SmallClass1)
1206 if (SmallClass0 < SmallClass1)
1214 if (Livethrough0 > Livethrough1)
1216 if (Livethrough0 < Livethrough1)
1237 UsedInInstr.clear();
1239 BundleVirtRegsMap.
clear();
1243 unsigned TiedIdx =
MI.findTiedOperandIdx(
Idx);
1248 bool HasPhysRegUse =
false;
1249 bool HasRegMask =
false;
1250 bool HasVRegDef =
false;
1251 bool HasDef =
false;
1252 bool HasEarlyClobber =
false;
1253 bool NeedToAssignLiveThroughs =
false;
1254 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I) {
1258 if (
Reg.isVirtual()) {
1259 if (!shouldAllocateRegister(Reg))
1265 HasEarlyClobber =
true;
1266 NeedToAssignLiveThroughs =
true;
1268 if ((MO.
isTied() && !TiedOpIsUndef(MO,
I)) ||
1270 NeedToAssignLiveThroughs =
true;
1272 }
else if (
Reg.isPhysical()) {
1273 if (!
MRI->isReserved(Reg)) {
1276 bool displacedAny = definePhysReg(
MI, Reg);
1278 HasEarlyClobber =
true;
1283 HasPhysRegUse =
true;
1297 bool ReArrangedImplicitOps =
true;
1305 if (NeedToAssignLiveThroughs) {
1306 PhysRegUses.clear();
1308 while (ReArrangedImplicitOps) {
1309 ReArrangedImplicitOps =
false;
1310 findAndSortDefOperandIndexes(
MI);
1311 for (
uint16_t OpIdx : DefOperandIndexes) {
1316 (MO.
isTied() && !TiedOpIsUndef(MO, OpIdx)) ||
1318 ReArrangedImplicitOps = defineLiveThroughVirtReg(
MI, OpIdx, Reg);
1320 ReArrangedImplicitOps = defineVirtReg(
MI, OpIdx, Reg);
1322 if (ReArrangedImplicitOps) {
1331 while (ReArrangedImplicitOps) {
1332 ReArrangedImplicitOps =
false;
1333 for (
unsigned I = 0,
E =
MI.getNumOperands();
I <
E; ++
I) {
1338 if (
Reg.isVirtual()) {
1339 ReArrangedImplicitOps = defineVirtReg(
MI,
I, Reg);
1340 if (ReArrangedImplicitOps) {
1352 for (
signed I =
MI.getNumOperands() - 1;
I >= 0; --
I) {
1367 "tied def assigned to clobbered register");
1374 if (
Reg.isVirtual()) {
1375 assert(!shouldAllocateRegister(Reg));
1379 if (
MRI->isReserved(Reg))
1382 unmarkRegUsedInInstr(Reg);
1390 for (
const auto *RM : RegMasks)
1391 MRI->addPhysRegsUsedFromRegMask(RM);
1394 for (
const LiveReg &LR : LiveVirtRegs) {
1396 if (PhysReg != 0 && isClobberedByRegMasks(PhysReg))
1397 displacePhysReg(
MI, PhysReg);
1402 if (HasPhysRegUse) {
1407 if (!
Reg.isPhysical())
1409 if (
MRI->isReserved(Reg))
1411 bool displacedAny = usePhysReg(
MI, Reg);
1420 bool HasUndefUse =
false;
1421 bool ReArrangedImplicitMOs =
true;
1422 while (ReArrangedImplicitMOs) {
1423 ReArrangedImplicitMOs =
false;
1424 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I) {
1429 if (!
Reg.isVirtual() || !shouldAllocateRegister(Reg))
1443 ReArrangedImplicitMOs = useVirtReg(
MI,
I, Reg);
1444 if (ReArrangedImplicitMOs)
1455 if (!
Reg.isVirtual() || !shouldAllocateRegister(Reg))
1458 assert(MO.
isUndef() &&
"Should only have undef virtreg uses left");
1459 allocVirtRegUndef(MO);
1464 if (HasEarlyClobber) {
1468 assert(!MO.
getSubReg() &&
"should be already handled in def processing");
1473 if (
Reg.isVirtual()) {
1474 assert(!shouldAllocateRegister(Reg));
1477 assert(
Reg.isPhysical() &&
"should have register assigned");
1485 if (
MI.readsRegister(Reg,
TRI))
1493 if (
MI.isCopy() &&
MI.getOperand(0).getReg() ==
MI.getOperand(1).getReg() &&
1494 MI.getNumOperands() == 2) {
1504 if (!
Reg.isVirtual())
1506 if (!shouldAllocateRegister(Reg))
1510 int SS = StackSlotForVirtReg[
Reg];
1520 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
1525 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
1527 for (
auto &RegMO : DbgOps)
1528 setPhysReg(
MI, *RegMO, LRI->PhysReg);
1530 DanglingDbgValues[
Reg].push_back(&
MI);
1535 LiveDbgValueMap[
Reg].append(DbgOps.
begin(), DbgOps.
end());
1542 while (BundledMI->isBundledWithPred()) {
1548 if (!
Reg.isVirtual() || !shouldAllocateRegister(Reg))
1552 DI = BundleVirtRegsMap.
find(Reg);
1553 assert(DI != BundleVirtRegsMap.
end() &&
"Unassigned virtual register");
1555 setPhysReg(
MI, MO, DI->second);
1566 RegUnitStates.assign(
TRI->getNumRegUnits(), regFree);
1567 assert(LiveVirtRegs.empty() &&
"Mapping not cleared from last block?");
1570 setPhysRegState(LiveReg.PhysReg, regPreAssigned);
1577 dbgs() <<
"\n>> " <<
MI <<
"Regs:";
1583 if (
MI.isDebugValue()) {
1584 handleDebugValue(
MI);
1588 allocateInstruction(
MI);
1592 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
1598 dbgs() <<
"Begin Regs:";
1603 LLVM_DEBUG(
dbgs() <<
"Loading live registers at begin of block.\n");
1610 NumCoalesced += Coalesced.size();
1612 for (
auto &UDBGPair : DanglingDbgValues) {
1616 if (!
DbgValue->hasDebugOperandForReg(UDBGPair.first))
1623 DanglingDbgValues.clear();
1629 LLVM_DEBUG(
dbgs() <<
"********** FAST REGISTER ALLOCATION **********\n"
1630 <<
"********** Function: " << MF.
getName() <<
'\n');
1636 MRI->freezeReservedRegs(MF);
1638 unsigned NumRegUnits =
TRI->getNumRegUnits();
1639 UsedInInstr.clear();
1640 UsedInInstr.setUniverse(NumRegUnits);
1641 PhysRegUses.clear();
1642 PhysRegUses.setUniverse(NumRegUnits);
1646 unsigned NumVirtRegs =
MRI->getNumVirtRegs();
1647 StackSlotForVirtReg.
resize(NumVirtRegs);
1648 LiveVirtRegs.setUniverse(NumVirtRegs);
1649 MayLiveAcrossBlocks.
clear();
1650 MayLiveAcrossBlocks.
resize(NumVirtRegs);
1654 allocateBasicBlock(
MBB);
1656 if (ClearVirtRegs) {
1659 MRI->clearVirtRegs();
1662 StackSlotForVirtReg.
clear();
1663 LiveDbgValueMap.
clear();
1668 return new RegAllocFast();
1672 bool ClearVirtRegs) {
1673 return new RegAllocFast(Ftor, ClearVirtRegs);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
const HexagonInstrInfo * TII
This file implements an indexed map.
unsigned const TargetRegisterInfo * TRI
This file implements a map that provides insertion order iteration.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool dominates(MachineBasicBlock &MBB, MachineBasicBlock::const_iterator A, MachineBasicBlock::const_iterator B)
static bool isCoalescable(const MachineInstr &MI)
static cl::opt< bool > IgnoreMissingDefs("rafast-ignore-missing-defs", cl::Hidden)
static RegisterRegAlloc fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the SparseSet class derived from the version described in Briggs,...
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Class recording the (high level) value of a variable.
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
iterator find(const_arg_type_t< KeyT > Val)
Lightweight error class with error context and mandatory checking.
FunctionPass class - This class is used to implement most global optimizations.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
void resize(typename StorageT::size_type s)
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Wrapper class representing physical registers. Should be passed by value.
iterator_range< liveout_iterator > liveouts() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
iterator_range< livein_iterator > liveins() const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual MachineFunctionProperties getClearedProperties() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual MachineFunctionProperties getSetProperties() const
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
const MachineBasicBlock & front() const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isDebugValueList() const
const MachineBasicBlock * getParent() const
bool isNonListDebugValue() const
MachineOperand & getDebugOperand(unsigned Index)
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
void setIsRenamable(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
MachineBasicBlock * getMBB() const
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
Wrapper class representing virtual and physical registers.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
SparseSet - Fast set implementation for objects that can be identified by small unsigned keys.
typename DenseT::iterator iterator
typename DenseT::const_iterator const_iterator
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getID() const
Return the register class ID number.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Iterator for intrusive lists based on ilist_node.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ Kill
The last use of a register.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
static bool allocateAllRegClasses(const TargetRegisterInfo &, const TargetRegisterClass &)
Default register class filter function for register allocation.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
auto reverse(ContainerTy &&C)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
std::function< bool(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC)> RegClassFilterFunc
This struct is a compact representation of a valid (non-zero power of two) alignment.
Pair of physical register and lane mask.
A MapVector that performs no allocations if smaller than a certain size.