51#define DEBUG_TYPE "regalloc"
55STATISTIC(NumCoalesced,
"Number of copies coalesced");
68class InstrPosIndexes {
70 void unsetInitialized() { IsInitialized =
false; }
74 Instr2PosIndex.
clear();
77 LastIndex += InstrDist;
78 Instr2PosIndex[&
MI] = LastIndex;
93 assert(
MI.getParent() == CurMBB &&
"MI is not in CurMBB");
94 auto It = Instr2PosIndex.find(&
MI);
95 if (It != Instr2PosIndex.end()) {
109 unsigned Distance = 1;
111 End = std::next(Start);
112 while (Start != CurMBB->begin() &&
113 !Instr2PosIndex.count(&*std::prev(Start))) {
117 while (
End != CurMBB->end() && !Instr2PosIndex.count(&*(
End))) {
125 Start == CurMBB->begin() ? 0 : Instr2PosIndex.at(&*std::prev(Start));
127 if (
End == CurMBB->end())
128 Step =
static_cast<uint64_t>(InstrDist);
132 assert(EndIndex > LastIndex &&
"Index must be ascending order");
133 unsigned NumAvailableIndexes = EndIndex - LastIndex - 1;
152 Step = (NumAvailableIndexes + 1) / (Distance + 1);
157 if (
LLVM_UNLIKELY(!Step || (!LastIndex && Step == InstrDist))) {
159 Index = Instr2PosIndex.at(&
MI);
163 for (
auto I = Start;
I !=
End; ++
I) {
165 Instr2PosIndex[&*
I] = LastIndex;
167 Index = Instr2PosIndex.at(&
MI);
172 bool IsInitialized =
false;
173 enum { InstrDist = 1024 };
178class RegAllocFastImpl {
181 bool ClearVirtRegs_ =
true)
182 : ShouldAllocateRegisterImpl(
F), StackSlotForVirtReg(-1),
183 ClearVirtRegs(ClearVirtRegs_) {}
204 bool LiveOut =
false;
205 bool Reloaded =
false;
208 explicit LiveReg(
Register VirtReg) : VirtReg(VirtReg) {}
210 unsigned getSparseSetIndex()
const {
218 LiveRegMap LiveVirtRegs;
252 std::vector<unsigned> RegUnitStates;
277 InstrPosIndexes PosIndexes;
279 void setPhysRegState(
MCPhysReg PhysReg,
unsigned NewState);
280 bool isPhysRegFree(
MCPhysReg PhysReg)
const;
283 void markRegUsedInInstr(
MCPhysReg PhysReg) {
285 UsedInInstr[Unit] = InstrGen | 1;
289 bool isClobberedByRegMasks(
MCPhysReg PhysReg)
const {
296 bool isRegUsedInInstr(
MCPhysReg PhysReg,
bool LookAtPhysRegUses)
const {
297 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
300 if (UsedInInstr[Unit] >= (InstrGen | !LookAtPhysRegUses))
307 void markPhysRegUsedInInstr(
MCPhysReg PhysReg) {
309 assert(UsedInInstr[Unit] <= InstrGen &&
"non-phys use before phys use?");
310 UsedInInstr[Unit] = InstrGen;
315 void unmarkRegUsedInInstr(
MCPhysReg PhysReg) {
317 UsedInInstr[Unit] = 0;
324 spillImpossible = ~0
u
349 unsigned calcSpillCost(
MCPhysReg PhysReg)
const;
361 bool LookAtPhysRegUses =
false);
368 bool LookAtPhysRegUses =
false);
381 bool shouldAllocateRegister(
const Register Reg)
const;
382 int getStackSpaceFor(
Register VirtReg);
384 MCPhysReg AssignedReg,
bool Kill,
bool LiveOut);
391 void dumpState()
const;
395 RegAllocFastImpl Impl;
404 return Impl.runOnMachineFunction(MF);
416 MachineFunctionProperties::Property::NoPHIs);
420 if (Impl.ClearVirtRegs) {
422 MachineFunctionProperties::Property::NoVRegs);
430 MachineFunctionProperties::Property::IsSSA);
436char RegAllocFast::ID = 0;
443 if (!ShouldAllocateRegisterImpl)
446 return ShouldAllocateRegisterImpl(*
TRI, *
MRI, Reg);
449void RegAllocFastImpl::setPhysRegState(
MCPhysReg PhysReg,
unsigned NewState) {
451 RegUnitStates[Unit] = NewState;
454bool RegAllocFastImpl::isPhysRegFree(
MCPhysReg PhysReg)
const {
456 if (RegUnitStates[Unit] != regFree)
464int RegAllocFastImpl::getStackSpaceFor(
Register VirtReg) {
466 int SS = StackSlotForVirtReg[VirtReg];
473 unsigned Size =
TRI->getSpillSize(RC);
474 Align Alignment =
TRI->getSpillAlign(RC);
478 StackSlotForVirtReg[VirtReg] = FrameIdx;
485 PosIndexes.getIndex(
A, IndexA);
487 PosIndexes.getIndex(
A, IndexA);
488 return IndexA < IndexB;
492bool RegAllocFastImpl::mayLiveOut(
Register VirtReg) {
505 if (DefInst.getParent() !=
MBB) {
509 if (!SelfLoopDef ||
dominates(PosIndexes, DefInst, *SelfLoopDef))
510 SelfLoopDef = &DefInst;
521 static const unsigned Limit = 8;
523 for (
const MachineInstr &UseInst :
MRI->use_nodbg_instructions(VirtReg)) {
524 if (UseInst.getParent() !=
MBB || ++
C >= Limit) {
533 if (SelfLoopDef == &UseInst ||
534 !
dominates(PosIndexes, *SelfLoopDef, UseInst)) {
545bool RegAllocFastImpl::mayLiveIn(
Register VirtReg) {
550 static const unsigned Limit = 8;
553 if (DefInst.getParent() !=
MBB || ++
C >= Limit) {
569 int FI = getStackSpaceFor(VirtReg);
586 SpilledOperandsMap[MO->getParent()].push_back(MO);
587 for (
auto MISpilledOperands : SpilledOperandsMap) {
593 *
MBB,
Before, *MISpilledOperands.first, FI, MISpilledOperands.second);
596 LLVM_DEBUG(
dbgs() <<
"Inserting debug info due to spill:\n" << *NewDV);
605 LLVM_DEBUG(
dbgs() <<
"Cloning debug info due to live out spill\n");
621 LRIDbgOperands.clear();
629 int FI = getStackSpaceFor(VirtReg);
649 if (!
TII->isBasicBlockPrologue(*
I))
667 if (LiveVirtRegs.empty())
674 setPhysRegState(Reg, regLiveIn);
682 getMBBBeginInsertionPoint(
MBB, PrologLiveIns);
683 for (
const LiveReg &LR : LiveVirtRegs) {
689 if (RegUnitStates[FirstUnit] == regLiveIn)
693 "no reload in start block. Missing vreg def?");
695 if (PrologLiveIns.
count(PhysReg)) {
699 reload(
MBB.
begin(), LR.VirtReg, PhysReg);
701 reload(InsertBefore, LR.VirtReg, PhysReg);
703 LiveVirtRegs.clear();
711 bool displacedAny = displacePhysReg(
MI, Reg);
712 setPhysRegState(Reg, regPreAssigned);
713 markRegUsedInInstr(Reg);
718 bool displacedAny = displacePhysReg(
MI, Reg);
719 setPhysRegState(Reg, regPreAssigned);
727 bool displacedAny =
false;
730 switch (
unsigned VirtReg = RegUnitStates[Unit]) {
732 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
733 assert(LRI != LiveVirtRegs.end() &&
"datastructures in sync");
736 reload(ReloadBefore, VirtReg, LRI->PhysReg);
738 setPhysRegState(LRI->PhysReg, regFree);
740 LRI->Reloaded =
true;
745 RegUnitStates[Unit] = regFree;
755void RegAllocFastImpl::freePhysReg(
MCPhysReg PhysReg) {
759 switch (
unsigned VirtReg = RegUnitStates[FirstUnit]) {
765 setPhysRegState(PhysReg, regFree);
768 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
769 assert(LRI != LiveVirtRegs.end());
771 setPhysRegState(LRI->PhysReg, regFree);
782unsigned RegAllocFastImpl::calcSpillCost(
MCPhysReg PhysReg)
const {
784 switch (
unsigned VirtReg = RegUnitStates[Unit]) {
790 return spillImpossible;
792 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 ||
793 findLiveVirtReg(VirtReg)->LiveOut;
794 return SureSpill ? spillClean : spillDirty;
801void RegAllocFastImpl::assignDanglingDebugValues(
MachineInstr &Definition,
804 auto UDBGValIter = DanglingDbgValues.
find(VirtReg);
805 if (UDBGValIter == DanglingDbgValues.
end())
811 if (!
DbgValue->hasDebugOperandForReg(VirtReg))
820 if (
I->modifiesRegister(Reg,
TRI) || --Limit == 0) {
839void RegAllocFastImpl::assignVirtToPhysReg(
MachineInstr &AtMI, LiveReg &LR,
844 assert(LR.PhysReg == 0 &&
"Already assigned a physreg");
845 assert(PhysReg != 0 &&
"Trying to assign no register");
846 LR.PhysReg = PhysReg;
847 setPhysRegState(PhysReg, VirtReg);
849 assignDanglingDebugValues(AtMI, VirtReg, PhysReg);
855 static const unsigned ChainLengthLimit = 3;
858 if (
Reg.isPhysical())
866 }
while (++
C <= ChainLengthLimit);
874 static const unsigned DefLimit = 3;
879 Reg = traceCopyChain(Reg);
892 Register Hint0,
bool LookAtPhysRegUses) {
893 const Register VirtReg = LR.VirtReg;
898 <<
" in class " <<
TRI->getRegClassName(&RC)
903 !isRegUsedInInstr(Hint0, LookAtPhysRegUses)) {
905 if (isPhysRegFree(Hint0)) {
908 assignVirtToPhysReg(
MI, LR, Hint0);
919 Register Hint1 = traceCopies(VirtReg);
921 !isRegUsedInInstr(Hint1, LookAtPhysRegUses)) {
923 if (isPhysRegFree(Hint1)) {
926 assignVirtToPhysReg(
MI, LR, Hint1);
937 unsigned BestCost = spillImpossible;
941 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) {
946 unsigned Cost = calcSpillCost(PhysReg);
950 assignVirtToPhysReg(
MI, LR, PhysReg);
954 if (PhysReg == Hint0 || PhysReg == Hint1)
955 Cost -= spillPrefBonus;
957 if (
Cost < BestCost) {
966 if (
MI.isInlineAsm())
967 MI.emitError(
"inline assembly requires more registers than available");
969 MI.emitError(
"ran out of registers during register allocation");
976 displacePhysReg(
MI, BestReg);
977 assignVirtToPhysReg(
MI, LR, BestReg);
984 if (!shouldAllocateRegister(VirtReg))
987 LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
989 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
990 PhysReg = LRI->PhysReg;
999 if (SubRegIdx != 0) {
1000 PhysReg =
TRI->getSubReg(PhysReg, SubRegIdx);
1013 if (!shouldAllocateRegister(VirtReg))
1015 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
1016 if (LRI != LiveVirtRegs.end()) {
1018 if (PrevReg != 0 && isRegUsedInInstr(PrevReg,
true)) {
1020 <<
" (tied/earlyclobber resolution)\n");
1021 freePhysReg(PrevReg);
1023 allocVirtReg(
MI, *LRI, 0,
true);
1029 TII->get(TargetOpcode::COPY), PrevReg)
1037 return defineVirtReg(
MI, OpNum, VirtReg,
true);
1047bool RegAllocFastImpl::defineVirtReg(
MachineInstr &
MI,
unsigned OpNum,
1048 Register VirtReg,
bool LookAtPhysRegUses) {
1050 if (!shouldAllocateRegister(VirtReg))
1053 LiveRegMap::iterator LRI;
1055 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1058 if (mayLiveOut(VirtReg)) {
1059 LRI->LiveOut =
true;
1066 if (LRI->PhysReg == 0) {
1067 allocVirtReg(
MI, *LRI, 0, LookAtPhysRegUses);
1078 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) &&
1079 "TODO: preassign mismatch");
1081 <<
" use existing assignment to "
1086 if (LRI->Reloaded || LRI->LiveOut) {
1087 if (!
MI.isImplicitDef()) {
1091 <<
" RL: " << LRI->Reloaded <<
'\n');
1092 bool Kill = LRI->LastUse ==
nullptr;
1093 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
1097 if (
MI.getOpcode() == TargetOpcode::INLINEASM_BR) {
1098 int FI = StackSlotForVirtReg[VirtReg];
1111 LRI->LastUse =
nullptr;
1113 LRI->LiveOut =
false;
1114 LRI->Reloaded =
false;
1116 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
1117 BundleVirtRegsMap[VirtReg] = PhysReg;
1119 markRegUsedInInstr(PhysReg);
1120 return setPhysReg(
MI, MO, PhysReg);
1128 if (!shouldAllocateRegister(VirtReg))
1130 LiveRegMap::iterator LRI;
1132 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1135 if (mayLiveOut(VirtReg)) {
1136 LRI->LiveOut =
true;
1143 assert((!MO.
isKill() || LRI->LastUse == &
MI) &&
"Invalid kill flag");
1147 if (LRI->PhysReg == 0) {
1150 if (
MI.isCopy() &&
MI.getOperand(1).getSubReg() == 0) {
1151 Hint =
MI.getOperand(0).getReg();
1153 assert(!shouldAllocateRegister(Hint));
1157 "Copy destination should already be assigned");
1160 allocVirtReg(
MI, *LRI, Hint,
false);
1172 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
1173 BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1175 markRegUsedInInstr(LRI->PhysReg);
1176 return setPhysReg(
MI, MO, LRI->PhysReg);
1201 MI.addRegisterKilled(PhysReg,
TRI,
true);
1210 MI.addRegisterDead(PhysReg,
TRI,
true);
1212 MI.addRegisterDefined(PhysReg,
TRI);
1221void RegAllocFastImpl::dumpState()
const {
1222 for (
unsigned Unit = 1, UnitE =
TRI->getNumRegUnits(); Unit != UnitE;
1224 switch (
unsigned VirtReg = RegUnitStates[Unit]) {
1227 case regPreAssigned:
1234 LiveRegMap::const_iterator
I = findLiveVirtReg(VirtReg);
1235 assert(
I != LiveVirtRegs.end() &&
"have LiveVirtRegs entry");
1236 if (
I->LiveOut ||
I->Reloaded) {
1244 assert(
TRI->hasRegUnit(
I->PhysReg, Unit) &&
"inverse mapping present");
1251 for (
const LiveReg &LR : LiveVirtRegs) {
1258 assert(RegUnitStates[Unit] == VirtReg &&
"inverse map valid");
1266void RegAllocFastImpl::addRegClassDefCounts(
1268 assert(RegClassDefCounts.
size() ==
TRI->getNumRegClasses());
1270 if (
Reg.isVirtual()) {
1271 if (!shouldAllocateRegister(Reg))
1274 for (
unsigned RCIdx = 0, RCIdxEnd =
TRI->getNumRegClasses();
1275 RCIdx != RCIdxEnd; ++RCIdx) {
1279 ++RegClassDefCounts[RCIdx];
1285 for (
unsigned RCIdx = 0, RCIdxEnd =
TRI->getNumRegClasses();
1286 RCIdx != RCIdxEnd; ++RCIdx) {
1290 ++RegClassDefCounts[RCIdx];
1300void RegAllocFastImpl::findAndSortDefOperandIndexes(
const MachineInstr &
MI) {
1301 DefOperandIndexes.
clear();
1304 for (
unsigned I = 0, E =
MI.getNumOperands();
I < E; ++
I) {
1310 if (
Reg.isPhysical()) {
1312 markPhysRegUsedInInstr(Reg);
1316 if (MO.
isDef() &&
Reg.isVirtual() && shouldAllocateRegister(Reg))
1322 if (DefOperandIndexes.
size() <= 1)
1334 addRegClassDefCounts(RegClassDefCounts, MO.
getReg());
1336 llvm::sort(DefOperandIndexes, [&](
unsigned I0,
unsigned I1) {
1346 unsigned ClassSize0 = RegClassInfo.
getOrder(&RC0).
size();
1347 unsigned ClassSize1 = RegClassInfo.
getOrder(&RC1).
size();
1349 bool SmallClass0 = ClassSize0 < RegClassDefCounts[RC0.
getID()];
1350 bool SmallClass1 = ClassSize1 < RegClassDefCounts[RC1.
getID()];
1351 if (SmallClass0 > SmallClass1)
1353 if (SmallClass0 < SmallClass1)
1361 if (Livethrough0 > Livethrough1)
1363 if (Livethrough0 < Livethrough1)
1377 unsigned TiedIdx =
MI.findTiedOperandIdx(
MI.getOperandNo(&MO));
1402 BundleVirtRegsMap.
clear();
1405 bool HasPhysRegUse =
false;
1406 bool HasRegMask =
false;
1407 bool HasVRegDef =
false;
1408 bool HasDef =
false;
1409 bool HasEarlyClobber =
false;
1410 bool NeedToAssignLiveThroughs =
false;
1414 if (
Reg.isVirtual()) {
1415 if (!shouldAllocateRegister(Reg))
1421 HasEarlyClobber =
true;
1422 NeedToAssignLiveThroughs =
true;
1425 NeedToAssignLiveThroughs =
true;
1427 }
else if (
Reg.isPhysical()) {
1428 if (!
MRI->isReserved(Reg)) {
1431 bool displacedAny = definePhysReg(
MI, Reg);
1433 HasEarlyClobber =
true;
1438 HasPhysRegUse =
true;
1452 bool ReArrangedImplicitOps =
true;
1460 if (NeedToAssignLiveThroughs) {
1461 while (ReArrangedImplicitOps) {
1462 ReArrangedImplicitOps =
false;
1463 findAndSortDefOperandIndexes(
MI);
1464 for (
unsigned OpIdx : DefOperandIndexes) {
1470 ReArrangedImplicitOps = defineLiveThroughVirtReg(
MI, OpIdx, Reg);
1472 ReArrangedImplicitOps = defineVirtReg(
MI, OpIdx, Reg);
1476 if (ReArrangedImplicitOps)
1482 while (ReArrangedImplicitOps) {
1483 ReArrangedImplicitOps =
false;
1488 if (
Reg.isVirtual()) {
1489 ReArrangedImplicitOps =
1490 defineVirtReg(
MI,
MI.getOperandNo(&MO), Reg);
1491 if (ReArrangedImplicitOps)
1516 "tied def assigned to clobbered register");
1523 if (
Reg.isVirtual()) {
1524 assert(!shouldAllocateRegister(Reg));
1528 if (
MRI->isReserved(Reg))
1531 unmarkRegUsedInInstr(Reg);
1539 for (
const auto *RM : RegMasks)
1540 MRI->addPhysRegsUsedFromRegMask(RM);
1543 for (
const LiveReg &LR : LiveVirtRegs) {
1545 if (PhysReg != 0 && isClobberedByRegMasks(PhysReg))
1546 displacePhysReg(
MI, PhysReg);
1551 if (HasPhysRegUse) {
1556 if (!
Reg.isPhysical())
1558 if (
MRI->isReserved(Reg))
1560 if (!usePhysReg(
MI, Reg))
1568 bool HasUndefUse =
false;
1569 bool ReArrangedImplicitMOs =
true;
1570 while (ReArrangedImplicitMOs) {
1571 ReArrangedImplicitMOs =
false;
1576 if (!
Reg.isVirtual() || !shouldAllocateRegister(Reg))
1590 ReArrangedImplicitMOs = useVirtReg(
MI, MO, Reg);
1591 if (ReArrangedImplicitMOs)
1602 if (!
Reg.isVirtual() || !shouldAllocateRegister(Reg))
1605 assert(MO.
isUndef() &&
"Should only have undef virtreg uses left");
1606 allocVirtRegUndef(MO);
1611 if (HasEarlyClobber) {
1615 assert(!MO.
getSubReg() &&
"should be already handled in def processing");
1620 if (
Reg.isVirtual()) {
1621 assert(!shouldAllocateRegister(Reg));
1624 assert(
Reg.isPhysical() &&
"should have register assigned");
1632 if (
MI.readsRegister(Reg,
TRI))
1640 if (
MI.isCopy() &&
MI.getOperand(0).getReg() ==
MI.getOperand(1).getReg() &&
1641 MI.getNumOperands() == 2) {
1650 assert(
MI.isDebugValue() &&
"not a DBG_VALUE*");
1651 for (
const auto &MO :
MI.debug_operands()) {
1655 if (!
Reg.isVirtual())
1657 if (!shouldAllocateRegister(Reg))
1661 int SS = StackSlotForVirtReg[
Reg];
1671 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
1676 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
1678 for (
auto &RegMO : DbgOps)
1679 setPhysReg(
MI, *RegMO, LRI->PhysReg);
1681 DanglingDbgValues[
Reg].push_back(&
MI);
1686 LiveDbgValueMap[
Reg].append(DbgOps.
begin(), DbgOps.
end());
1693 while (BundledMI->isBundledWithPred()) {
1699 if (!
Reg.isVirtual() || !shouldAllocateRegister(Reg))
1703 DI = BundleVirtRegsMap.
find(Reg);
1704 assert(DI != BundleVirtRegsMap.
end() &&
"Unassigned virtual register");
1706 setPhysReg(
MI, MO, DI->second);
1717 PosIndexes.unsetInitialized();
1718 RegUnitStates.assign(
TRI->getNumRegUnits(), regFree);
1719 assert(LiveVirtRegs.empty() &&
"Mapping not cleared from last block?");
1722 setPhysRegState(LiveReg.PhysReg, regPreAssigned);
1732 if (
MI.isDebugValue()) {
1733 handleDebugValue(
MI);
1737 allocateInstruction(
MI);
1741 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
1749 LLVM_DEBUG(
dbgs() <<
"Loading live registers at begin of block.\n");
1756 NumCoalesced += Coalesced.size();
1758 for (
auto &UDBGPair : DanglingDbgValues) {
1762 if (!
DbgValue->hasDebugOperandForReg(UDBGPair.first))
1769 DanglingDbgValues.clear();
1775 LLVM_DEBUG(
dbgs() <<
"********** FAST REGISTER ALLOCATION **********\n"
1776 <<
"********** Function: " << MF.
getName() <<
'\n');
1782 MRI->freezeReservedRegs();
1784 unsigned NumRegUnits =
TRI->getNumRegUnits();
1786 UsedInInstr.
assign(NumRegUnits, 0);
1790 unsigned NumVirtRegs =
MRI->getNumVirtRegs();
1791 StackSlotForVirtReg.
resize(NumVirtRegs);
1792 LiveVirtRegs.setUniverse(NumVirtRegs);
1793 MayLiveAcrossBlocks.
clear();
1794 MayLiveAcrossBlocks.
resize(NumVirtRegs);
1798 allocateBasicBlock(
MBB);
1800 if (ClearVirtRegs) {
1803 MRI->clearVirtRegs();
1806 StackSlotForVirtReg.
clear();
1807 LiveDbgValueMap.
clear();
1815 bool Changed = Impl.runOnMachineFunction(MF);
1825 bool PrintFilterName = Opts.
FilterName !=
"all";
1827 bool PrintSemicolon = PrintFilterName && PrintNoClearVRegs;
1829 OS <<
"regallocfast";
1830 if (PrintFilterName || PrintNoClearVRegs) {
1832 if (PrintFilterName)
1836 if (PrintNoClearVRegs)
1837 OS <<
"no-clear-vregs";
1845 bool ClearVirtRegs) {
1846 return new RegAllocFast(Ftor, ClearVirtRegs);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
#define LLVM_UNLIKELY(EXPR)
This file defines the DenseMap class.
const HexagonInstrInfo * TII
This file implements an indexed map.
unsigned const TargetRegisterInfo * TRI
This file implements a map that provides insertion order iteration.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool isCoalescable(const MachineInstr &MI)
static cl::opt< bool > IgnoreMissingDefs("rafast-ignore-missing-defs", cl::Hidden)
static bool dominates(InstrPosIndexes &PosIndexes, const MachineInstr &A, const MachineInstr &B)
static bool isTiedToNotUndef(const MachineOperand &MO)
static RegisterRegAlloc fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the SparseSet class derived from the version described in Briggs,...
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Class recording the (high level) value of a variable.
A container for analyses that lazily runs them and caches their results.
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
Represents analyses that only rely on functions' control flow.
This class represents an Operation in the Expression.
iterator find(const_arg_type_t< KeyT > Val)
Lightweight error class with error context and mandatory checking.
FunctionPass class - This class is used to implement most global optimizations.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
void resize(typename StorageT::size_type s)
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
static constexpr unsigned NoRegister
An RAII based helper class to modify MachineFunctionProperties when running pass.
iterator_range< liveout_iterator > liveouts() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
iterator_range< livein_iterator > liveins() const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Instructions::iterator instr_iterator
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual MachineFunctionProperties getClearedProperties() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual MachineFunctionProperties getSetProperties() const
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
const MachineBasicBlock & front() const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isDebugValueList() const
const MachineBasicBlock * getParent() const
bool isNonListDebugValue() const
MachineOperand & getDebugOperand(unsigned Index)
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
void setIsRenamable(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
MachineBasicBlock * getMBB() const
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
A set of analyses that are preserved following a run of a transformation pass.
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &)
void printPipeline(raw_ostream &OS, function_ref< StringRef(StringRef)> MapClassName2PassName)
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
Wrapper class representing virtual and physical registers.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void assign(size_type NumElts, ValueParamT Elt)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
SparseSet - Fast set implementation for objects that can be identified by small unsigned keys.
typename DenseT::iterator iterator
typename DenseT::const_iterator const_iterator
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getID() const
Return the register class ID number.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
An efficient, type-erasing, non-owning reference to a callable.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ Kill
The last use of a register.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
std::function< bool(const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, const Register Reg)> RegAllocFilterFunc
Filter function for register classes during regalloc.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
auto reverse(ContainerTy &&C)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Pair of physical register and lane mask.
RegAllocFilterFunc Filter
A MapVector that performs no allocations if smaller than a certain size.