Go to the documentation of this file.
50 #define DEBUG_TYPE "regalloc"
52 STATISTIC(NumStores,
"Number of stores added");
53 STATISTIC(NumLoads ,
"Number of loads added");
54 STATISTIC(NumCoalesced,
"Number of copies coalesced");
70 bool ClearVirtRegs_ =
true) :
72 ShouldAllocateClass(
F),
73 StackSlotForVirtReg(-1),
74 ClearVirtRegs(ClearVirtRegs_) {
99 bool Reloaded =
false;
102 explicit LiveReg(
Register VirtReg) : VirtReg(VirtReg) {}
104 unsigned getSparseSetIndex()
const {
112 LiveRegMap LiveVirtRegs;
146 std::vector<unsigned> RegUnitStates;
153 RegUnitSet UsedInInstr;
154 RegUnitSet PhysRegUses;
159 void setPhysRegState(
MCPhysReg PhysReg,
unsigned NewState);
160 bool isPhysRegFree(
MCPhysReg PhysReg)
const;
163 void markRegUsedInInstr(
MCPhysReg PhysReg) {
165 UsedInInstr.insert(*Units);
169 bool isClobberedByRegMasks(
MCPhysReg PhysReg)
const {
176 bool isRegUsedInInstr(
MCPhysReg PhysReg,
bool LookAtPhysRegUses)
const {
177 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
180 if (UsedInInstr.count(*Units))
182 if (LookAtPhysRegUses && PhysRegUses.count(*Units))
190 void markPhysRegUsedInInstr(
MCPhysReg PhysReg) {
192 PhysRegUses.insert(*Units);
196 void unmarkRegUsedInInstr(
MCPhysReg PhysReg) {
198 UsedInInstr.erase(*Units);
205 spillImpossible = ~0u
209 StringRef getPassName()
const override {
return "Fast Register Allocator"; }
240 void addRegClassDefCounts(std::vector<unsigned> &RegClassDefCounts,
252 unsigned calcSpillCost(
MCPhysReg PhysReg)
const;
254 LiveRegMap::iterator findLiveVirtReg(
Register VirtReg) {
258 LiveRegMap::const_iterator findLiveVirtReg(
Register VirtReg)
const {
264 bool LookAtPhysRegUses =
false);
271 bool LookAtPhysRegUses =
false);
284 bool shouldAllocateRegister(
const Register Reg)
const;
285 int getStackSpaceFor(
Register VirtReg);
294 void dumpState()
const;
307 return ShouldAllocateClass(*
TRI, RC);
310 void RegAllocFast::setPhysRegState(
MCPhysReg PhysReg,
unsigned NewState) {
312 RegUnitStates[*UI] = NewState;
315 bool RegAllocFast::isPhysRegFree(
MCPhysReg PhysReg)
const {
317 if (RegUnitStates[*UI] != regFree)
325 int RegAllocFast::getStackSpaceFor(
Register VirtReg) {
327 int SS = StackSlotForVirtReg[VirtReg];
339 StackSlotForVirtReg[VirtReg] = FrameIdx;
351 for (; &*
I != A && &*
I !=
B; ++
I)
358 bool RegAllocFast::mayLiveOut(
Register VirtReg) {
371 if (DefInst.getParent() !=
MBB) {
376 SelfLoopDef = &DefInst;
387 static const unsigned Limit = 8;
390 if (UseInst.getParent() !=
MBB || ++
C >= Limit) {
399 if (SelfLoopDef == &UseInst ||
411 bool RegAllocFast::mayLiveIn(
Register VirtReg) {
416 static const unsigned Limit = 8;
419 if (DefInst.getParent() !=
MBB || ++
C >= Limit) {
434 int FI = getStackSpaceFor(VirtReg);
451 SpilledOperandsMap[MO->getParent()].push_back(MO);
452 for (
auto MISpilledOperands : SpilledOperandsMap) {
458 *
MBB, Before, *MISpilledOperands.first, FI, MISpilledOperands.second);
461 LLVM_DEBUG(
dbgs() <<
"Inserting debug info due to spill:\n" << *NewDV);
470 LLVM_DEBUG(
dbgs() <<
"Cloning debug info due to live out spill\n");
486 LRIDbgOperands.clear();
494 int FI = getStackSpaceFor(VirtReg);
505 RegAllocFast::getMBBBeginInsertionPoint(
515 if (!
TII->isBasicBlockPrologue(*
I))
533 if (LiveVirtRegs.empty())
540 setPhysRegState(
Reg, regLiveIn);
549 = getMBBBeginInsertionPoint(
MBB, PrologLiveIns);
550 for (
const LiveReg &LR : LiveVirtRegs) {
556 if (RegUnitStates[FirstUnit] == regLiveIn)
560 "no reload in start block. Missing vreg def?");
562 if (PrologLiveIns.
count(PhysReg)) {
566 reload(
MBB.
begin(), LR.VirtReg, PhysReg);
568 reload(InsertBefore, LR.VirtReg, PhysReg);
570 LiveVirtRegs.clear();
578 bool displacedAny = displacePhysReg(
MI,
Reg);
579 setPhysRegState(
Reg, regPreAssigned);
580 markRegUsedInInstr(
Reg);
585 bool displacedAny = displacePhysReg(
MI,
Reg);
586 setPhysRegState(
Reg, regPreAssigned);
594 bool displacedAny =
false;
598 switch (
unsigned VirtReg = RegUnitStates[Unit]) {
600 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
601 assert(LRI != LiveVirtRegs.end() &&
"datastructures in sync");
604 reload(ReloadBefore, VirtReg, LRI->PhysReg);
606 setPhysRegState(LRI->PhysReg, regFree);
608 LRI->Reloaded =
true;
613 RegUnitStates[Unit] = regFree;
623 void RegAllocFast::freePhysReg(
MCPhysReg PhysReg) {
627 switch (
unsigned VirtReg = RegUnitStates[FirstUnit]) {
633 setPhysRegState(PhysReg, regFree);
636 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
637 assert(LRI != LiveVirtRegs.end());
639 setPhysRegState(LRI->PhysReg, regFree);
650 unsigned RegAllocFast::calcSpillCost(
MCPhysReg PhysReg)
const {
652 switch (
unsigned VirtReg = RegUnitStates[*UI]) {
658 return spillImpossible;
660 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 ||
661 findLiveVirtReg(VirtReg)->LiveOut;
662 return SureSpill ? spillClean : spillDirty;
669 void RegAllocFast::assignDanglingDebugValues(
MachineInstr &Definition,
671 auto UDBGValIter = DanglingDbgValues.
find(VirtReg);
672 if (UDBGValIter == DanglingDbgValues.
end())
678 if (!
DbgValue->hasDebugOperandForReg(VirtReg))
686 if (
I->modifiesRegister(
Reg,
TRI) || --Limit == 0) {
705 void RegAllocFast::assignVirtToPhysReg(
MachineInstr &AtMI, LiveReg &LR,
710 assert(LR.PhysReg == 0 &&
"Already assigned a physreg");
711 assert(PhysReg != 0 &&
"Trying to assign no register");
712 LR.PhysReg = PhysReg;
713 setPhysRegState(PhysReg, VirtReg);
715 assignDanglingDebugValues(AtMI, VirtReg, PhysReg);
719 return MI.isFullCopy();
723 static const unsigned ChainLengthLimit = 3;
726 if (
Reg.isPhysical())
734 }
while (++
C <= ChainLengthLimit);
742 static const unsigned DefLimit = 3;
747 Reg = traceCopyChain(
Reg);
760 Register Hint0,
bool LookAtPhysRegUses) {
761 const Register VirtReg = LR.VirtReg;
771 !isRegUsedInInstr(Hint0, LookAtPhysRegUses)) {
773 if (isPhysRegFree(Hint0)) {
776 assignVirtToPhysReg(
MI, LR, Hint0);
788 Register Hint1 = traceCopies(VirtReg);
790 !isRegUsedInInstr(Hint1, LookAtPhysRegUses)) {
792 if (isPhysRegFree(Hint1)) {
795 assignVirtToPhysReg(
MI, LR, Hint1);
806 unsigned BestCost = spillImpossible;
810 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) {
815 unsigned Cost = calcSpillCost(PhysReg);
816 LLVM_DEBUG(
dbgs() <<
"Cost: " << Cost <<
" BestCost: " << BestCost <<
'\n');
819 assignVirtToPhysReg(
MI, LR, PhysReg);
823 if (PhysReg == Hint0 || PhysReg == Hint1)
824 Cost -= spillPrefBonus;
826 if (Cost < BestCost) {
835 if (
MI.isInlineAsm())
836 MI.emitError(
"inline assembly requires more registers than available");
838 MI.emitError(
"ran out of registers during register allocation");
845 displacePhysReg(
MI, BestReg);
846 assignVirtToPhysReg(
MI, LR, BestReg);
853 if (!shouldAllocateRegister(VirtReg))
856 LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
858 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
859 PhysReg = LRI->PhysReg;
868 if (SubRegIdx != 0) {
878 void RegAllocFast::defineLiveThroughVirtReg(
MachineInstr &
MI,
unsigned OpNum,
880 if (!shouldAllocateRegister(VirtReg))
882 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
883 if (LRI != LiveVirtRegs.end()) {
885 if (PrevReg != 0 && isRegUsedInInstr(PrevReg,
true)) {
887 <<
" (tied/earlyclobber resolution)\n");
888 freePhysReg(PrevReg);
890 allocVirtReg(
MI, *LRI, 0,
true);
896 TII->get(TargetOpcode::COPY), PrevReg)
904 return defineVirtReg(
MI, OpNum, VirtReg,
true);
912 void RegAllocFast::defineVirtReg(
MachineInstr &
MI,
unsigned OpNum,
913 Register VirtReg,
bool LookAtPhysRegUses) {
915 if (!shouldAllocateRegister(VirtReg))
918 LiveRegMap::iterator LRI;
920 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
923 if (mayLiveOut(VirtReg)) {
931 if (LRI->PhysReg == 0)
932 allocVirtReg(
MI, *LRI, 0, LookAtPhysRegUses);
934 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) &&
935 "TODO: preassign mismatch");
937 <<
" use existing assignment to "
942 assert(PhysReg != 0 &&
"Register not assigned");
943 if (LRI->Reloaded || LRI->LiveOut) {
944 if (!
MI.isImplicitDef()) {
947 LLVM_DEBUG(
dbgs() <<
"Spill Reason: LO: " << LRI->LiveOut <<
" RL: "
948 << LRI->Reloaded <<
'\n');
949 bool Kill = LRI->LastUse ==
nullptr;
950 spill(SpillBefore, VirtReg, PhysReg,
Kill, LRI->LiveOut);
951 LRI->LastUse =
nullptr;
953 LRI->LiveOut =
false;
954 LRI->Reloaded =
false;
956 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
957 BundleVirtRegsMap[VirtReg] = PhysReg;
959 markRegUsedInInstr(PhysReg);
960 setPhysReg(
MI, MO, PhysReg);
967 if (!shouldAllocateRegister(VirtReg))
970 LiveRegMap::iterator LRI;
972 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
976 if (mayLiveOut(VirtReg)) {
984 assert((!MO.
isKill() || LRI->LastUse == &
MI) &&
"Invalid kill flag");
988 if (LRI->PhysReg == 0) {
991 if (
MI.isCopy() &&
MI.getOperand(1).getSubReg() == 0) {
992 Hint =
MI.getOperand(0).getReg();
994 assert(!shouldAllocateRegister(Hint));
998 "Copy destination should already be assigned");
1001 allocVirtReg(
MI, *LRI, Hint,
false);
1012 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
1013 BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1015 markRegUsedInInstr(LRI->PhysReg);
1016 setPhysReg(
MI, MO, LRI->PhysReg);
1042 MI.addRegisterKilled(PhysReg,
TRI,
true);
1050 MI.addRegisterDead(PhysReg,
TRI,
true);
1052 MI.addRegisterDefined(PhysReg,
TRI);
1058 void RegAllocFast::dumpState()
const {
1061 switch (
unsigned VirtReg = RegUnitStates[Unit]) {
1064 case regPreAssigned:
1071 LiveRegMap::const_iterator
I = findLiveVirtReg(VirtReg);
1072 assert(
I != LiveVirtRegs.end() &&
"have LiveVirtRegs entry");
1073 if (
I->LiveOut ||
I->Reloaded) {
1075 if (
I->LiveOut)
dbgs() <<
'O';
1076 if (
I->Reloaded)
dbgs() <<
'R';
1086 for (
const LiveReg &LR : LiveVirtRegs) {
1092 "mapped to physreg");
1094 assert(RegUnitStates[*UI] == VirtReg &&
"inverse map valid");
1102 void RegAllocFast::addRegClassDefCounts(std::vector<unsigned> &RegClassDefCounts,
1106 if (
Reg.isVirtual()) {
1107 if (!shouldAllocateRegister(
Reg))
1111 RCIdx != RCIdxEnd; ++RCIdx) {
1115 ++RegClassDefCounts[RCIdx];
1122 RCIdx != RCIdxEnd; ++RCIdx) {
1126 ++RegClassDefCounts[RCIdx];
1146 UsedInInstr.clear();
1148 BundleVirtRegsMap.
clear();
1150 auto TiedOpIsUndef = [&](
const MachineOperand &MO,
unsigned Idx) {
1152 unsigned TiedIdx =
MI.findTiedOperandIdx(Idx);
1157 bool HasPhysRegUse =
false;
1158 bool HasRegMask =
false;
1159 bool HasVRegDef =
false;
1160 bool HasDef =
false;
1161 bool HasEarlyClobber =
false;
1162 bool NeedToAssignLiveThroughs =
false;
1163 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I) {
1167 if (
Reg.isVirtual()) {
1168 if (!shouldAllocateRegister(
Reg))
1174 HasEarlyClobber =
true;
1175 NeedToAssignLiveThroughs =
true;
1177 if ((MO.
isTied() && !TiedOpIsUndef(MO,
I)) ||
1179 NeedToAssignLiveThroughs =
true;
1181 }
else if (
Reg.isPhysical()) {
1185 bool displacedAny = definePhysReg(
MI,
Reg);
1187 HasEarlyClobber =
true;
1192 HasPhysRegUse =
true;
1210 if (NeedToAssignLiveThroughs) {
1211 DefOperandIndexes.
clear();
1212 PhysRegUses.clear();
1216 assert(RegClassDefCounts[0] == 0);
1219 for (
unsigned I = 0,
E =
MI.getNumOperands();
I <
E; ++
I) {
1225 if (
Reg.isPhysical()) {
1228 markPhysRegUsedInInstr(
Reg);
1233 if (
Reg.isVirtual() && shouldAllocateRegister(
Reg))
1234 DefOperandIndexes.push_back(
I);
1236 addRegClassDefCounts(RegClassDefCounts,
Reg);
1250 unsigned ClassSize0 = RegClassInfo.
getOrder(&RC0).
size();
1251 unsigned ClassSize1 = RegClassInfo.
getOrder(&RC1).
size();
1253 bool SmallClass0 = ClassSize0 < RegClassDefCounts[RC0.
getID()];
1254 bool SmallClass1 = ClassSize1 < RegClassDefCounts[RC1.
getID()];
1255 if (SmallClass0 > SmallClass1)
1257 if (SmallClass0 < SmallClass1)
1265 if (Livethrough0 > Livethrough1)
1267 if (Livethrough0 < Livethrough1)
1274 for (
uint16_t OpIdx : DefOperandIndexes) {
1279 (MO.
isTied() && !TiedOpIsUndef(MO, OpIdx)) ||
1281 defineLiveThroughVirtReg(
MI, OpIdx,
Reg);
1283 defineVirtReg(
MI, OpIdx,
Reg);
1288 for (
unsigned I = 0,
E =
MI.getNumOperands();
I <
E; ++
I) {
1293 if (
Reg.isVirtual())
1294 defineVirtReg(
MI,
I,
Reg);
1302 for (
signed I =
MI.getNumOperands() - 1;
I >= 0; --
I) {
1315 "tied def assigned to clobbered register");
1323 if (
Reg.isVirtual()) {
1331 unmarkRegUsedInInstr(
Reg);
1337 assert(!RegMasks.empty() &&
"expected RegMask");
1339 for (
const auto *
RM : RegMasks)
1343 for (
const LiveReg &LR : LiveVirtRegs) {
1345 if (PhysReg != 0 && isClobberedByRegMasks(PhysReg))
1346 displacePhysReg(
MI, PhysReg);
1351 if (HasPhysRegUse) {
1356 if (!
Reg.isPhysical())
1360 bool displacedAny = usePhysReg(
MI,
Reg);
1367 bool HasUndefUse =
false;
1368 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I) {
1373 if (!
Reg.isVirtual() || !shouldAllocateRegister(
Reg))
1400 if (!
Reg.isVirtual() || !shouldAllocateRegister(
Reg))
1403 assert(MO.
isUndef() &&
"Should only have undef virtreg uses left");
1404 allocVirtRegUndef(MO);
1409 if (HasEarlyClobber) {
1413 assert(!MO.
getSubReg() &&
"should be already handled in def processing");
1418 if (
Reg.isVirtual()) {
1422 assert(
Reg.isPhysical() &&
"should have register assigned");
1438 if (
MI.isCopy() &&
MI.getOperand(0).getReg() ==
MI.getOperand(1).getReg() &&
1439 MI.getNumOperands() == 2) {
1441 Coalesced.push_back(&
MI);
1449 if (!
Reg.isVirtual())
1451 if (!shouldAllocateRegister(
Reg))
1455 int SS = StackSlotForVirtReg[
Reg];
1465 LiveRegMap::iterator LRI = findLiveVirtReg(
Reg);
1468 DbgOps.push_back(&
Op);
1470 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
1472 for (
auto &RegMO : DbgOps)
1473 setPhysReg(
MI, *RegMO, LRI->PhysReg);
1475 DanglingDbgValues[
Reg].push_back(&
MI);
1480 LiveDbgValueMap[
Reg].append(DbgOps.begin(), DbgOps.end());
1487 while (BundledMI->isBundledWithPred()) {
1493 if (!
Reg.isVirtual() || !shouldAllocateRegister(
Reg))
1497 DI = BundleVirtRegsMap.
find(
Reg);
1498 assert(DI != BundleVirtRegsMap.
end() &&
"Unassigned virtual register");
1500 setPhysReg(
MI, MO, DI->second);
1512 assert(LiveVirtRegs.empty() &&
"Mapping not cleared from last block?");
1515 setPhysRegState(LiveReg.PhysReg, regPreAssigned);
1522 dbgs() <<
"\n>> " <<
MI <<
"Regs:";
1528 if (
MI.isDebugValue()) {
1529 handleDebugValue(
MI);
1533 allocateInstruction(
MI);
1537 if (
MI.getOpcode() == TargetOpcode::BUNDLE) {
1543 dbgs() <<
"Begin Regs:";
1548 LLVM_DEBUG(
dbgs() <<
"Loading live registers at begin of block.\n");
1555 NumCoalesced += Coalesced.size();
1557 for (
auto &UDBGPair : DanglingDbgValues) {
1561 if (!
DbgValue->hasDebugOperandForReg(UDBGPair.first))
1568 DanglingDbgValues.clear();
1574 LLVM_DEBUG(
dbgs() <<
"********** FAST REGISTER ALLOCATION **********\n"
1575 <<
"********** Function: " << MF.
getName() <<
'\n');
1584 UsedInInstr.clear();
1585 UsedInInstr.setUniverse(NumRegUnits);
1586 PhysRegUses.clear();
1587 PhysRegUses.setUniverse(NumRegUnits);
1592 StackSlotForVirtReg.
resize(NumVirtRegs);
1593 LiveVirtRegs.setUniverse(NumVirtRegs);
1594 MayLiveAcrossBlocks.
clear();
1595 MayLiveAcrossBlocks.
resize(NumVirtRegs);
1599 allocateBasicBlock(
MBB);
1601 if (ClearVirtRegs) {
1607 StackSlotForVirtReg.
clear();
1608 LiveDbgValueMap.
clear();
1613 return new RegAllocFast();
1617 bool ClearVirtRegs) {
1618 return new RegAllocFast(Ftor, ClearVirtRegs);
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
unsigned getID() const
Return the register class ID number.
This is an optimization pass for GlobalISel generic memory operations.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
virtual const TargetInstrInfo * getInstrInfo() const
void clear()
clear - Removes all bits from the bitvector.
void setIsKill(bool Val=true)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Reg
All possible values of the reg field in the ModR/M byte.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
iterator_range< livein_iterator > liveins() const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Properties which a MachineFunction may have at a given point in time.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
iterator_range< liveout_iterator > liveouts() const
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
const MachineBasicBlock & front() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
void setSubReg(unsigned subReg)
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
const HexagonInstrInfo * TII
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
INITIALIZE_PASS(RegAllocFast, "regallocfast", "Fast Register Allocator", false, false) bool RegAllocFast
Pair of physical register and lane mask.
STATISTIC(NumFunctions, "Total number of functions")
static bool dominates(MachineBasicBlock &MBB, MachineBasicBlock::const_iterator A, MachineBasicBlock::const_iterator B)
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isNonListDebugValue() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void sort(IteratorTy Start, IteratorTy End)
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
A MapVector that performs no allocations if smaller than a certain size.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Class recording the (high level) value of a variable.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
void setIsDead(bool Val=true)
MachineOperand & getDebugOperand(unsigned Index)
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
std::function< bool(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC)> RegClassFilterFunc
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
iterator find(const_arg_type_t< KeyT > Val)
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isEarlyClobber() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
if(llvm_vc STREQUAL "") set(fake_version_inc "$
void setIsRenamable(bool Val=true)
self_iterator getIterator()
const MachineBasicBlock * getParent() const
static cl::opt< bool > IgnoreMissingDefs("rafast-ignore-missing-defs", cl::Hidden)
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
bool test(unsigned Idx) const
static bool allocateAllRegClasses(const TargetRegisterInfo &, const TargetRegisterClass &)
Default register class filter function for register allocation.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
static RegisterRegAlloc fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Iterator for intrusive lists based on ilist_node.
Lightweight error class with error context and mandatory checking.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
unsigned getNumRegClasses() const
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
@ Kill
The last use of a register.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isInternalRead() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
auto reverse(ContainerTy &&C)
SparseSet - Fast set implementation for objects that can be identified by small unsigned keys.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
FunctionPass class - This class is used to implement most global optimizations.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
static bool isCoalescable(const MachineInstr &MI)
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too before RA runs At that point we don t whether there will be vector spill
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
bool isDebugValueList() const
void resize(typename StorageT::size_type s)
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.