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16 #ifndef LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
17 #define LLVM_LIB_CODEGEN_ALLOCATIONORDER_H
26 class RegisterClassInfo;
40 const int IterationLimit;
52 bool isHint()
const {
return Pos < 0; }
57 return AO.Hints.end()[Pos];
58 assert(Pos < AO.IterationLimit);
65 if (Pos < AO.IterationLimit)
67 while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos]))
74 return Pos ==
Other.Pos;
92 : Hints(
std::
move(Hints)), Order(Order),
93 IterationLimit(HardHints ? 0 : static_cast<
int>(Order.
size())) {}
96 return Iterator(*
this, -(
static_cast<int>(Hints.size())));
106 std::min(
static_cast<int>(OrderLimit) - 1, IterationLimit));
This is an optimization pass for GlobalISel generic memory operations.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
AllocationOrder(SmallVector< MCPhysReg, 16 > &&Hints, ArrayRef< MCPhysReg > Order, bool HardHints)
Create an AllocationOrder given the Hits, Order, and HardHits values.
Reg
All possible values of the reg field in the ModR/M byte.
bool operator==(const Iterator &Other) const
const_iterator end(StringRef path)
Get end iterator over path.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Forward iterator for an AllocationOrder.
Iterator(const AllocationOrder &AO, int Pos)
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Iterator & operator++()
Advance the iterator to the next position.
bool isHint() const
Return true if the curent position is that of a preferred register.
MCRegister operator*() const
Return the next physical register in the allocation order.
Iterator getOrderLimitEnd(unsigned OrderLimit) const
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
ArrayRef< MCPhysReg > getOrder() const
Get the allocation order without reordered hints.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library,...
Wrapper class representing virtual and physical registers.
bool isHint(Register Reg) const
Return true if Reg is a preferred physical register.
std::optional< std::vector< StOtherPiece > > Other
size_t size() const
size - Get the array size.
bool operator!=(const Iterator &Other) const
Wrapper class representing physical registers. Should be passed by value.