LLVM 19.0.0git
PHIElimination.cpp
Go to the documentation of this file.
1//===- PhiElimination.cpp - Eliminate PHI nodes by inserting copies -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass eliminates machine instruction PHI nodes by inserting copy
10// instructions. This destroys SSA information, but is the desired input for
11// some register allocators.
12//
13//===----------------------------------------------------------------------===//
14
16#include "PHIEliminationUtils.h"
17#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/Statistic.h"
38#include "llvm/Pass.h"
40#include "llvm/Support/Debug.h"
42#include <cassert>
43#include <iterator>
44#include <utility>
45
46using namespace llvm;
47
48#define DEBUG_TYPE "phi-node-elimination"
49
50static cl::opt<bool>
51 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
53 cl::desc("Disable critical edge splitting "
54 "during PHI elimination"));
55
56static cl::opt<bool>
57 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
59 cl::desc("Split all critical edges during "
60 "PHI elimination"));
61
63 "no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
64 cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
65
66namespace {
67
68class PHIEliminationImpl {
69 MachineRegisterInfo *MRI = nullptr; // Machine register information
70 LiveVariables *LV = nullptr;
71 LiveIntervals *LIS = nullptr;
72 MachineLoopInfo *MLI = nullptr;
73 MachineDominatorTree *MDT = nullptr;
74
75 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
76 /// in predecessor basic blocks.
77 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
78
79 void LowerPHINode(MachineBasicBlock &MBB,
81 bool AllEdgesCritical);
82
83 /// analyzePHINodes - Gather information about the PHI nodes in
84 /// here. In particular, we want to map the number of uses of a virtual
85 /// register which is used in a PHI node. We map that to the BB the
86 /// vreg is coming from. This is used later to determine when the vreg
87 /// is killed in the BB.
88 void analyzePHINodes(const MachineFunction &MF);
89
90 /// Split critical edges where necessary for good coalescer performance.
91 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
92 MachineLoopInfo *MLI,
93 std::vector<SparseBitVector<>> *LiveInSets);
94
95 // These functions are temporary abstractions around LiveVariables and
96 // LiveIntervals, so they can go away when LiveVariables does.
97 bool isLiveIn(Register Reg, const MachineBasicBlock *MBB);
98 bool isLiveOutPastPHIs(Register Reg, const MachineBasicBlock *MBB);
99
100 using BBVRegPair = std::pair<unsigned, Register>;
101 using VRegPHIUse = DenseMap<BBVRegPair, unsigned>;
102
103 // Count the number of non-undef PHI uses of each register in each BB.
104 VRegPHIUse VRegPHIUseCount;
105
106 // Defs of PHI sources which are implicit_def.
108
109 // Map reusable lowered PHI node -> incoming join register.
110 using LoweredPHIMap =
112 LoweredPHIMap LoweredPHIs;
113
114 MachineFunctionPass *P = nullptr;
115 MachineFunctionAnalysisManager *MFAM = nullptr;
116
117public:
118 PHIEliminationImpl(MachineFunctionPass *P) : P(P) {
119 auto *LVWrapper = P->getAnalysisIfAvailable<LiveVariablesWrapperPass>();
120 auto *LISWrapper = P->getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
121 auto *MLIWrapper = P->getAnalysisIfAvailable<MachineLoopInfoWrapperPass>();
122 auto *MDTWrapper =
123 P->getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>();
124 LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
125 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
126 MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
127 MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr;
128 }
129
130 PHIEliminationImpl(MachineFunction &MF, MachineFunctionAnalysisManager &AM)
131 : LV(AM.getCachedResult<LiveVariablesAnalysis>(MF)),
132 LIS(AM.getCachedResult<LiveIntervalsAnalysis>(MF)),
133 MLI(AM.getCachedResult<MachineLoopAnalysis>(MF)),
134 MDT(AM.getCachedResult<MachineDominatorTreeAnalysis>(MF)), MFAM(&AM) {}
135
136 bool run(MachineFunction &MF);
137};
138
139class PHIElimination : public MachineFunctionPass {
140public:
141 static char ID; // Pass identification, replacement for typeid
142
143 PHIElimination() : MachineFunctionPass(ID) {
145 }
146
147 bool runOnMachineFunction(MachineFunction &MF) override {
148 PHIEliminationImpl Impl(this);
149 return Impl.run(MF);
150 }
151
154 MachineFunctionProperties::Property::NoPHIs);
155 }
156
157 void getAnalysisUsage(AnalysisUsage &AU) const override;
158};
159
160} // end anonymous namespace
161
165 PHIEliminationImpl Impl(MF, MFAM);
166 bool Changed = Impl.run(MF);
167 if (!Changed)
168 return PreservedAnalyses::all();
170 PA.preserve<LiveIntervalsAnalysis>();
171 PA.preserve<LiveVariablesAnalysis>();
172 PA.preserve<SlotIndexesAnalysis>();
173 PA.preserve<MachineDominatorTreeAnalysis>();
174 PA.preserve<MachineLoopAnalysis>();
175 return PA;
176}
177
178STATISTIC(NumLowered, "Number of phis lowered");
179STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
180STATISTIC(NumReused, "Number of reused lowered phis");
181
182char PHIElimination::ID = 0;
183
184char &llvm::PHIEliminationID = PHIElimination::ID;
185
187 "Eliminate PHI nodes for register allocation", false,
188 false)
191 "Eliminate PHI nodes for register allocation", false, false)
192
193void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
194 AU.addUsedIfAvailable<LiveVariablesWrapperPass>();
195 AU.addPreserved<LiveVariablesWrapperPass>();
196 AU.addPreserved<SlotIndexesWrapperPass>();
197 AU.addPreserved<LiveIntervalsWrapperPass>();
198 AU.addPreserved<MachineDominatorTreeWrapperPass>();
199 AU.addPreserved<MachineLoopInfoWrapperPass>();
201}
202
203bool PHIEliminationImpl::run(MachineFunction &MF) {
204 MRI = &MF.getRegInfo();
205
206 bool Changed = false;
207
208 // Split critical edges to help the coalescer.
209 if (!DisableEdgeSplitting && (LV || LIS)) {
210 // A set of live-in regs for each MBB which is used to update LV
211 // efficiently also with large functions.
212 std::vector<SparseBitVector<>> LiveInSets;
213 if (LV) {
214 LiveInSets.resize(MF.size());
215 for (unsigned Index = 0, e = MRI->getNumVirtRegs(); Index != e; ++Index) {
216 // Set the bit for this register for each MBB where it is
217 // live-through or live-in (killed).
219 MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
220 if (!DefMI)
221 continue;
222 LiveVariables::VarInfo &VI = LV->getVarInfo(VirtReg);
223 SparseBitVector<>::iterator AliveBlockItr = VI.AliveBlocks.begin();
224 SparseBitVector<>::iterator EndItr = VI.AliveBlocks.end();
225 while (AliveBlockItr != EndItr) {
226 unsigned BlockNum = *(AliveBlockItr++);
227 LiveInSets[BlockNum].set(Index);
228 }
229 // The register is live into an MBB in which it is killed but not
230 // defined. See comment for VarInfo in LiveVariables.h.
231 MachineBasicBlock *DefMBB = DefMI->getParent();
232 if (VI.Kills.size() > 1 ||
233 (!VI.Kills.empty() && VI.Kills.front()->getParent() != DefMBB))
234 for (auto *MI : VI.Kills)
235 LiveInSets[MI->getParent()->getNumber()].set(Index);
236 }
237 }
238
239 for (auto &MBB : MF)
240 Changed |= SplitPHIEdges(MF, MBB, MLI, (LV ? &LiveInSets : nullptr));
241 }
242
243 // This pass takes the function out of SSA form.
244 MRI->leaveSSA();
245
246 // Populate VRegPHIUseCount
247 if (LV || LIS)
248 analyzePHINodes(MF);
249
250 // Eliminate PHI instructions by inserting copies into predecessor blocks.
251 for (auto &MBB : MF)
252 Changed |= EliminatePHINodes(MF, MBB);
253
254 // Remove dead IMPLICIT_DEF instructions.
255 for (MachineInstr *DefMI : ImpDefs) {
256 Register DefReg = DefMI->getOperand(0).getReg();
257 if (MRI->use_nodbg_empty(DefReg)) {
258 if (LIS)
261 }
262 }
263
264 // Clean up the lowered PHI instructions.
265 for (auto &I : LoweredPHIs) {
266 if (LIS)
267 LIS->RemoveMachineInstrFromMaps(*I.first);
268 MF.deleteMachineInstr(I.first);
269 }
270
271 // TODO: we should use the incremental DomTree updater here.
272 if (Changed && MDT)
273 MDT->getBase().recalculate(MF);
274
275 LoweredPHIs.clear();
276 ImpDefs.clear();
277 VRegPHIUseCount.clear();
278
279 MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
280
281 return Changed;
282}
283
284/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
285/// predecessor basic blocks.
286bool PHIEliminationImpl::EliminatePHINodes(MachineFunction &MF,
288 if (MBB.empty() || !MBB.front().isPHI())
289 return false; // Quick exit for basic blocks without PHIs.
290
291 // Get an iterator to the last PHI node.
293 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
294
295 // If all incoming edges are critical, we try to deduplicate identical PHIs so
296 // that we generate fewer copies. If at any edge is non-critical, we either
297 // have less than two predecessors (=> no PHIs) or a predecessor has only us
298 // as a successor (=> identical PHI node can't occur in different block).
299 bool AllEdgesCritical = MBB.pred_size() >= 2;
300 for (MachineBasicBlock *Pred : MBB.predecessors()) {
301 if (Pred->succ_size() < 2) {
302 AllEdgesCritical = false;
303 break;
304 }
305 }
306
307 while (MBB.front().isPHI())
308 LowerPHINode(MBB, LastPHIIt, AllEdgesCritical);
309
310 return true;
311}
312
313/// Return true if all defs of VirtReg are implicit-defs.
314/// This includes registers with no defs.
315static bool isImplicitlyDefined(unsigned VirtReg,
316 const MachineRegisterInfo &MRI) {
317 for (MachineInstr &DI : MRI.def_instructions(VirtReg))
318 if (!DI.isImplicitDef())
319 return false;
320 return true;
321}
322
323/// Return true if all sources of the phi node are implicit_def's, or undef's.
324static bool allPhiOperandsUndefined(const MachineInstr &MPhi,
325 const MachineRegisterInfo &MRI) {
326 for (unsigned I = 1, E = MPhi.getNumOperands(); I != E; I += 2) {
327 const MachineOperand &MO = MPhi.getOperand(I);
328 if (!isImplicitlyDefined(MO.getReg(), MRI) && !MO.isUndef())
329 return false;
330 }
331 return true;
332}
333/// LowerPHINode - Lower the PHI node at the top of the specified block.
334void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
336 bool AllEdgesCritical) {
337 ++NumLowered;
338
339 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
340
341 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
342 MachineInstr *MPhi = MBB.remove(&*MBB.begin());
343
344 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
345 Register DestReg = MPhi->getOperand(0).getReg();
346 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
347 bool isDead = MPhi->getOperand(0).isDead();
348
349 // Create a new register for the incoming PHI arguments.
351 unsigned IncomingReg = 0;
352 bool EliminateNow = true; // delay elimination of nodes in LoweredPHIs
353 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
354
355 // Insert a register to register copy at the top of the current block (but
356 // after any remaining phi nodes) which copies the new incoming register
357 // into the phi node destination.
358 MachineInstr *PHICopy = nullptr;
360 if (allPhiOperandsUndefined(*MPhi, *MRI))
361 // If all sources of a PHI node are implicit_def or undef uses, just emit an
362 // implicit_def instead of a copy.
363 PHICopy = BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
364 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
365 else {
366 // Can we reuse an earlier PHI node? This only happens for critical edges,
367 // typically those created by tail duplication. Typically, an identical PHI
368 // node can't occur, so avoid hashing/storing such PHIs, which is somewhat
369 // expensive.
370 unsigned *Entry = nullptr;
371 if (AllEdgesCritical)
372 Entry = &LoweredPHIs[MPhi];
373 if (Entry && *Entry) {
374 // An identical PHI node was already lowered. Reuse the incoming register.
375 IncomingReg = *Entry;
376 reusedIncoming = true;
377 ++NumReused;
378 LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for "
379 << *MPhi);
380 } else {
381 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
382 IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
383 if (Entry) {
384 EliminateNow = false;
385 *Entry = IncomingReg;
386 }
387 }
388
389 // Give the target possiblity to handle special cases fallthrough otherwise
390 PHICopy = TII->createPHIDestinationCopy(
391 MBB, AfterPHIsIt, MPhi->getDebugLoc(), IncomingReg, DestReg);
392 }
393
394 if (MPhi->peekDebugInstrNum()) {
395 // If referred to by debug-info, store where this PHI was.
397 unsigned ID = MPhi->peekDebugInstrNum();
398 auto P = MachineFunction::DebugPHIRegallocPos(&MBB, IncomingReg, 0);
399 auto Res = MF->DebugPHIPositions.insert({ID, P});
400 assert(Res.second);
401 (void)Res;
402 }
403
404 // Update live variable information if there is any.
405 if (LV) {
406 if (IncomingReg) {
407 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
408
409 MachineInstr *OldKill = nullptr;
410 bool IsPHICopyAfterOldKill = false;
411
412 if (reusedIncoming && (OldKill = VI.findKill(&MBB))) {
413 // Calculate whether the PHICopy is after the OldKill.
414 // In general, the PHICopy is inserted as the first non-phi instruction
415 // by default, so it's before the OldKill. But some Target hooks for
416 // createPHIDestinationCopy() may modify the default insert position of
417 // PHICopy.
418 for (auto I = MBB.SkipPHIsAndLabels(MBB.begin()), E = MBB.end(); I != E;
419 ++I) {
420 if (I == PHICopy)
421 break;
422
423 if (I == OldKill) {
424 IsPHICopyAfterOldKill = true;
425 break;
426 }
427 }
428 }
429
430 // When we are reusing the incoming register and it has been marked killed
431 // by OldKill, if the PHICopy is after the OldKill, we should remove the
432 // killed flag from OldKill.
433 if (IsPHICopyAfterOldKill) {
434 LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);
435 LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
437 }
438
439 // Add information to LiveVariables to know that the first used incoming
440 // value or the resued incoming value whose PHICopy is after the OldKIll
441 // is killed. Note that because the value is defined in several places
442 // (once each for each incoming block), the "def" block and instruction
443 // fields for the VarInfo is not filled in.
444 if (!OldKill || IsPHICopyAfterOldKill)
445 LV->addVirtualRegisterKilled(IncomingReg, *PHICopy);
446 }
447
448 // Since we are going to be deleting the PHI node, if it is the last use of
449 // any registers, or if the value itself is dead, we need to move this
450 // information over to the new copy we just inserted.
451 LV->removeVirtualRegistersKilled(*MPhi);
452
453 // If the result is dead, update LV.
454 if (isDead) {
455 LV->addVirtualRegisterDead(DestReg, *PHICopy);
456 LV->removeVirtualRegisterDead(DestReg, *MPhi);
457 }
458 }
459
460 // Update LiveIntervals for the new copy or implicit def.
461 if (LIS) {
462 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*PHICopy);
463
464 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
465 if (IncomingReg) {
466 // Add the region from the beginning of MBB to the copy instruction to
467 // IncomingReg's live interval.
468 LiveInterval &IncomingLI = LIS->getOrCreateEmptyInterval(IncomingReg);
469 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
470 if (!IncomingVNI)
471 IncomingVNI =
472 IncomingLI.getNextValue(MBBStartIndex, LIS->getVNInfoAllocator());
474 MBBStartIndex, DestCopyIndex.getRegSlot(), IncomingVNI));
475 }
476
477 LiveInterval &DestLI = LIS->getInterval(DestReg);
478 assert(!DestLI.empty() && "PHIs should have non-empty LiveIntervals.");
479
480 SlotIndex NewStart = DestCopyIndex.getRegSlot();
481
482 SmallVector<LiveRange *> ToUpdate({&DestLI});
483 for (auto &SR : DestLI.subranges())
484 ToUpdate.push_back(&SR);
485
486 for (auto LR : ToUpdate) {
487 auto DestSegment = LR->find(MBBStartIndex);
488 assert(DestSegment != LR->end() &&
489 "PHI destination must be live in block");
490
491 if (LR->endIndex().isDead()) {
492 // A dead PHI's live range begins and ends at the start of the MBB, but
493 // the lowered copy, which will still be dead, needs to begin and end at
494 // the copy instruction.
495 VNInfo *OrigDestVNI = LR->getVNInfoAt(DestSegment->start);
496 assert(OrigDestVNI && "PHI destination should be live at block entry.");
497 LR->removeSegment(DestSegment->start, DestSegment->start.getDeadSlot());
498 LR->createDeadDef(NewStart, LIS->getVNInfoAllocator());
499 LR->removeValNo(OrigDestVNI);
500 continue;
501 }
502
503 // Destination copies are not inserted in the same order as the PHI nodes
504 // they replace. Hence the start of the live range may need to be adjusted
505 // to match the actual slot index of the copy.
506 if (DestSegment->start > NewStart) {
507 VNInfo *VNI = LR->getVNInfoAt(DestSegment->start);
508 assert(VNI && "value should be defined for known segment");
509 LR->addSegment(
510 LiveInterval::Segment(NewStart, DestSegment->start, VNI));
511 } else if (DestSegment->start < NewStart) {
512 assert(DestSegment->start >= MBBStartIndex);
513 assert(DestSegment->end >= DestCopyIndex.getRegSlot());
514 LR->removeSegment(DestSegment->start, NewStart);
515 }
516 VNInfo *DestVNI = LR->getVNInfoAt(NewStart);
517 assert(DestVNI && "PHI destination should be live at its definition.");
518 DestVNI->def = NewStart;
519 }
520 }
521
522 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
523 if (LV || LIS) {
524 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
525 if (!MPhi->getOperand(i).isUndef()) {
526 --VRegPHIUseCount[BBVRegPair(
527 MPhi->getOperand(i + 1).getMBB()->getNumber(),
528 MPhi->getOperand(i).getReg())];
529 }
530 }
531 }
532
533 // Now loop over all of the incoming arguments, changing them to copy into the
534 // IncomingReg register in the corresponding predecessor basic block.
536 for (int i = NumSrcs - 1; i >= 0; --i) {
537 Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg();
538 unsigned SrcSubReg = MPhi->getOperand(i * 2 + 1).getSubReg();
539 bool SrcUndef = MPhi->getOperand(i * 2 + 1).isUndef() ||
540 isImplicitlyDefined(SrcReg, *MRI);
541 assert(SrcReg.isVirtual() &&
542 "Machine PHI Operands must all be virtual registers!");
543
544 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
545 // path the PHI.
546 MachineBasicBlock &opBlock = *MPhi->getOperand(i * 2 + 2).getMBB();
547
548 // Check to make sure we haven't already emitted the copy for this block.
549 // This can happen because PHI nodes may have multiple entries for the same
550 // basic block.
551 if (!MBBsInsertedInto.insert(&opBlock).second)
552 continue; // If the copy has already been emitted, we're done.
553
554 MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
555 if (SrcRegDef && TII->isUnspillableTerminator(SrcRegDef)) {
556 assert(SrcRegDef->getOperand(0).isReg() &&
557 SrcRegDef->getOperand(0).isDef() &&
558 "Expected operand 0 to be a reg def!");
559 // Now that the PHI's use has been removed (as the instruction was
560 // removed) there should be no other uses of the SrcReg.
561 assert(MRI->use_empty(SrcReg) &&
562 "Expected a single use from UnspillableTerminator");
563 SrcRegDef->getOperand(0).setReg(IncomingReg);
564
565 // Update LiveVariables.
566 if (LV) {
567 LiveVariables::VarInfo &SrcVI = LV->getVarInfo(SrcReg);
568 LiveVariables::VarInfo &IncomingVI = LV->getVarInfo(IncomingReg);
569 IncomingVI.AliveBlocks = std::move(SrcVI.AliveBlocks);
570 SrcVI.AliveBlocks.clear();
571 }
572
573 continue;
574 }
575
576 // Find a safe location to insert the copy, this may be the first terminator
577 // in the block (or end()).
579 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
580
581 // Insert the copy.
582 MachineInstr *NewSrcInstr = nullptr;
583 if (!reusedIncoming && IncomingReg) {
584 if (SrcUndef) {
585 // The source register is undefined, so there is no need for a real
586 // COPY, but we still need to ensure joint dominance by defs.
587 // Insert an IMPLICIT_DEF instruction.
588 NewSrcInstr =
589 BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
590 TII->get(TargetOpcode::IMPLICIT_DEF), IncomingReg);
591
592 // Clean up the old implicit-def, if there even was one.
593 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
594 if (DefMI->isImplicitDef())
595 ImpDefs.insert(DefMI);
596 } else {
597 // Delete the debug location, since the copy is inserted into a
598 // different basic block.
599 NewSrcInstr = TII->createPHISourceCopy(opBlock, InsertPos, nullptr,
600 SrcReg, SrcSubReg, IncomingReg);
601 }
602 }
603
604 // We only need to update the LiveVariables kill of SrcReg if this was the
605 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
606 // out of the predecessor. We can also ignore undef sources.
607 if (LV && !SrcUndef &&
608 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
609 !LV->isLiveOut(SrcReg, opBlock)) {
610 // We want to be able to insert a kill of the register if this PHI (aka,
611 // the copy we just inserted) is the last use of the source value. Live
612 // variable analysis conservatively handles this by saying that the value
613 // is live until the end of the block the PHI entry lives in. If the value
614 // really is dead at the PHI copy, there will be no successor blocks which
615 // have the value live-in.
616
617 // Okay, if we now know that the value is not live out of the block, we
618 // can add a kill marker in this block saying that it kills the incoming
619 // value!
620
621 // In our final twist, we have to decide which instruction kills the
622 // register. In most cases this is the copy, however, terminator
623 // instructions at the end of the block may also use the value. In this
624 // case, we should mark the last such terminator as being the killing
625 // block, not the copy.
626 MachineBasicBlock::iterator KillInst = opBlock.end();
627 for (MachineBasicBlock::iterator Term = InsertPos; Term != opBlock.end();
628 ++Term) {
629 if (Term->readsRegister(SrcReg, /*TRI=*/nullptr))
630 KillInst = Term;
631 }
632
633 if (KillInst == opBlock.end()) {
634 // No terminator uses the register.
635
636 if (reusedIncoming || !IncomingReg) {
637 // We may have to rewind a bit if we didn't insert a copy this time.
638 KillInst = InsertPos;
639 while (KillInst != opBlock.begin()) {
640 --KillInst;
641 if (KillInst->isDebugInstr())
642 continue;
643 if (KillInst->readsRegister(SrcReg, /*TRI=*/nullptr))
644 break;
645 }
646 } else {
647 // We just inserted this copy.
648 KillInst = NewSrcInstr;
649 }
650 }
651 assert(KillInst->readsRegister(SrcReg, /*TRI=*/nullptr) &&
652 "Cannot find kill instruction");
653
654 // Finally, mark it killed.
655 LV->addVirtualRegisterKilled(SrcReg, *KillInst);
656
657 // This vreg no longer lives all of the way through opBlock.
658 unsigned opBlockNum = opBlock.getNumber();
659 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
660 }
661
662 if (LIS) {
663 if (NewSrcInstr) {
664 LIS->InsertMachineInstrInMaps(*NewSrcInstr);
665 LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
666 }
667
668 if (!SrcUndef &&
669 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
670 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
671
672 bool isLiveOut = false;
673 for (MachineBasicBlock *Succ : opBlock.successors()) {
674 SlotIndex startIdx = LIS->getMBBStartIdx(Succ);
675 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
676
677 // Definitions by other PHIs are not truly live-in for our purposes.
678 if (VNI && VNI->def != startIdx) {
679 isLiveOut = true;
680 break;
681 }
682 }
683
684 if (!isLiveOut) {
685 MachineBasicBlock::iterator KillInst = opBlock.end();
686 for (MachineBasicBlock::iterator Term = InsertPos;
687 Term != opBlock.end(); ++Term) {
688 if (Term->readsRegister(SrcReg, /*TRI=*/nullptr))
689 KillInst = Term;
690 }
691
692 if (KillInst == opBlock.end()) {
693 // No terminator uses the register.
694
695 if (reusedIncoming || !IncomingReg) {
696 // We may have to rewind a bit if we didn't just insert a copy.
697 KillInst = InsertPos;
698 while (KillInst != opBlock.begin()) {
699 --KillInst;
700 if (KillInst->isDebugInstr())
701 continue;
702 if (KillInst->readsRegister(SrcReg, /*TRI=*/nullptr))
703 break;
704 }
705 } else {
706 // We just inserted this copy.
707 KillInst = std::prev(InsertPos);
708 }
709 }
710 assert(KillInst->readsRegister(SrcReg, /*TRI=*/nullptr) &&
711 "Cannot find kill instruction");
712
713 SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
714 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
715 LIS->getMBBEndIdx(&opBlock));
716 for (auto &SR : SrcLI.subranges()) {
717 SR.removeSegment(LastUseIndex.getRegSlot(),
718 LIS->getMBBEndIdx(&opBlock));
719 }
720 }
721 }
722 }
723 }
724
725 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
726 if (EliminateNow) {
727 if (LIS)
728 LIS->RemoveMachineInstrFromMaps(*MPhi);
729 MF.deleteMachineInstr(MPhi);
730 }
731}
732
733/// analyzePHINodes - Gather information about the PHI nodes in here. In
734/// particular, we want to map the number of uses of a virtual register which is
735/// used in a PHI node. We map that to the BB the vreg is coming from. This is
736/// used later to determine when the vreg is killed in the BB.
737void PHIEliminationImpl::analyzePHINodes(const MachineFunction &MF) {
738 for (const auto &MBB : MF) {
739 for (const auto &BBI : MBB) {
740 if (!BBI.isPHI())
741 break;
742 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
743 if (!BBI.getOperand(i).isUndef()) {
744 ++VRegPHIUseCount[BBVRegPair(
745 BBI.getOperand(i + 1).getMBB()->getNumber(),
746 BBI.getOperand(i).getReg())];
747 }
748 }
749 }
750 }
751}
752
753bool PHIEliminationImpl::SplitPHIEdges(
755 std::vector<SparseBitVector<>> *LiveInSets) {
756 if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
757 return false; // Quick exit for basic blocks without PHIs.
758
759 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
760 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
761
762 bool Changed = false;
763 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
764 BBI != BBE && BBI->isPHI(); ++BBI) {
765 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
766 Register Reg = BBI->getOperand(i).getReg();
767 MachineBasicBlock *PreMBB = BBI->getOperand(i + 1).getMBB();
768 // Is there a critical edge from PreMBB to MBB?
769 if (PreMBB->succ_size() == 1)
770 continue;
771
772 // Avoid splitting backedges of loops. It would introduce small
773 // out-of-line blocks into the loop which is very bad for code placement.
774 if (PreMBB == &MBB && !SplitAllCriticalEdges)
775 continue;
776 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
777 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
778 continue;
779
780 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
781 // when the source register is live-out for some other reason than a phi
782 // use. That means the copy we will insert in PreMBB won't be a kill, and
783 // there is a risk it may not be coalesced away.
784 //
785 // If the copy would be a kill, there is no need to split the edge.
786 bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
787 if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
788 continue;
789 if (ShouldSplit) {
790 LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
791 << printMBBReference(*PreMBB) << " -> "
792 << printMBBReference(MBB) << ": " << *BBI);
793 }
794
795 // If Reg is not live-in to MBB, it means it must be live-in to some
796 // other PreMBB successor, and we can avoid the interference by splitting
797 // the edge.
798 //
799 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
800 // is likely to be left after coalescing. If we are looking at a loop
801 // exiting edge, split it so we won't insert code in the loop, otherwise
802 // don't bother.
803 ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
804
805 // Check for a loop exiting edge.
806 if (!ShouldSplit && CurLoop != PreLoop) {
807 LLVM_DEBUG({
808 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
809 if (PreLoop)
810 dbgs() << "PreLoop: " << *PreLoop;
811 if (CurLoop)
812 dbgs() << "CurLoop: " << *CurLoop;
813 });
814 // This edge could be entering a loop, exiting a loop, or it could be
815 // both: Jumping directly form one loop to the header of a sibling
816 // loop.
817 // Split unless this edge is entering CurLoop from an outer loop.
818 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
819 }
820 if (!ShouldSplit && !SplitAllCriticalEdges)
821 continue;
822 if (!(P ? PreMBB->SplitCriticalEdge(&MBB, *P, LiveInSets)
823 : PreMBB->SplitCriticalEdge(&MBB, *MFAM, LiveInSets))) {
824 LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");
825 continue;
826 }
827 Changed = true;
828 ++NumCriticalEdgesSplit;
829 }
830 }
831 return Changed;
832}
833
834bool PHIEliminationImpl::isLiveIn(Register Reg, const MachineBasicBlock *MBB) {
835 assert((LV || LIS) &&
836 "isLiveIn() requires either LiveVariables or LiveIntervals");
837 if (LIS)
838 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
839 else
840 return LV->isLiveIn(Reg, *MBB);
841}
842
843bool PHIEliminationImpl::isLiveOutPastPHIs(Register Reg,
844 const MachineBasicBlock *MBB) {
845 assert((LV || LIS) &&
846 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
847 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
848 // so that a register used only in a PHI is not live out of the block. In
849 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather
850 // than in the predecessor basic block, so that a register used only in a PHI
851 // is live out of the block.
852 if (LIS) {
853 const LiveInterval &LI = LIS->getInterval(Reg);
854 for (const MachineBasicBlock *SI : MBB->successors())
855 if (LI.liveAt(LIS->getMBBStartIdx(SI)))
856 return true;
857 return false;
858 } else {
859 return LV->isLiveOut(Reg, *MBB);
860 }
861}
unsigned const MachineRegisterInfo * MRI
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
MachineInstrBuilder MachineInstrBuilder & DefMI
Rewrite undef for PHI
Unify divergent function exit nodes
MachineBasicBlock & MBB
#define LLVM_DEBUG(X)
Definition: Debug.h:101
This file defines the DenseMap class.
#define DEBUG_TYPE
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
static bool allPhiOperandsUndefined(const MachineInstr &MPhi, const MachineRegisterInfo &MRI)
Return true if all sources of the phi node are implicit_def's, or undef's.
Eliminate PHI nodes for register allocation
static cl::opt< bool > NoPhiElimLiveOutEarlyExit("no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden, cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."))
static bool isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo &MRI)
Return true if all defs of VirtReg are implicit-defs.
static cl::opt< bool > DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false), cl::Hidden, cl::desc("Disable critical edge splitting " "during PHI elimination"))
static cl::opt< bool > SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false), cl::Hidden, cl::desc("Split all critical edges during " "PHI elimination"))
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines the SmallPtrSet class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:253
Represent the analysis usage information of a pass.
void recalculate(ParentType &Func)
recalculate - compute a dominator tree for the given function
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:782
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
LiveInterval & getOrCreateEmptyInterval(Register Reg)
Return an existing interval for Reg.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
VNInfo::Allocator & getVNInfoAllocator()
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveInterval & getInterval(Register Reg)
LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB.
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
bool empty() const
Definition: LiveInterval.h:382
VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:331
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified interval from this live range.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
BlockT * getHeader() const
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
unsigned succ_size() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
iterator_range< pred_iterator > predecessors()
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<> > *LiveInSets=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
Analysis pass which computes a MachineDominatorTree.
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineDominatorTree & getBase()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual MachineFunctionProperties getSetProperties() const
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
Location of a PHI instruction that is also a debug-info variable value, for the duration of register ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void deleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
unsigned size() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
DenseMap< unsigned, DebugPHIRegallocPos > DebugPHIPositions
Map of debug instruction numbers to the position of their PHI instructions during register allocation...
Representation of each machine instruction.
Definition: MachineInstr.h:69
bool isImplicitDef() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:346
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:572
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:545
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:498
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool isPHI() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:579
Analysis pass that exposes the MachineLoopInfo for a machine function.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
A set of analyses that are preserved following a run of a transformation pass.
Definition: Analysis.h:111
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition: Analysis.h:117
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:65
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:237
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:344
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:479
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
SparseBitVectorIterator iterator
TargetInstrInfo - Interface to description of machine instruction set.
virtual const TargetInstrInfo * getInstrInfo() const
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
@ Entry
Definition: COFF.h:811
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
PointerTypeMap run(const Module &M)
Compute the PointerTypeMap for the module M.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
void initializePHIEliminationPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
MachineBasicBlock::iterator findPHICopyInsertPoint(MachineBasicBlock *MBB, MachineBasicBlock *SuccMBB, unsigned SrcReg)
findPHICopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg when following the CFG...
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:78
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
Definition: LiveVariables.h:83