LLVM  12.0.0git
DetectDeadLanes.cpp
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1 //===- DetectDeadLanes.cpp - SubRegister Lane Usage Analysis --*- C++ -*---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Analysis that tracks defined/used subregister lanes across COPY instructions
11 /// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
12 /// INSERT_SUBREG, EXTRACT_SUBREG).
13 /// The information is used to detect dead definitions and the usage of
14 /// (completely) undefined values and mark the operands as such.
15 /// This pass is necessary because the dead/undef status is not obvious anymore
16 /// when subregisters are involved.
17 ///
18 /// Example:
19 /// %0 = some definition
20 /// %1 = IMPLICIT_DEF
21 /// %2 = REG_SEQUENCE %0, sub0, %1, sub1
22 /// %3 = EXTRACT_SUBREG %2, sub1
23 /// = use %3
24 /// The %0 definition is dead and %3 contains an undefined value.
25 //
26 //===----------------------------------------------------------------------===//
27 
28 #include "llvm/ADT/BitVector.h"
31 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/Pass.h"
36 #include "llvm/PassRegistry.h"
37 #include "llvm/Support/Debug.h"
39 #include <deque>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "detect-dead-lanes"
44 
45 namespace {
46 
47 /// Contains a bitmask of which lanes of a given virtual register are
48 /// defined and which ones are actually used.
49 struct VRegInfo {
50  LaneBitmask UsedLanes;
51  LaneBitmask DefinedLanes;
52 };
53 
54 class DetectDeadLanes : public MachineFunctionPass {
55 public:
56  bool runOnMachineFunction(MachineFunction &MF) override;
57 
58  static char ID;
59  DetectDeadLanes() : MachineFunctionPass(ID) {}
60 
61  StringRef getPassName() const override { return "Detect Dead Lanes"; }
62 
63  void getAnalysisUsage(AnalysisUsage &AU) const override {
64  AU.setPreservesCFG();
66  }
67 
68 private:
69  /// Add used lane bits on the register used by operand \p MO. This translates
70  /// the bitmask based on the operands subregister, and puts the register into
71  /// the worklist if any new bits were added.
72  void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
73 
74  /// Given a bitmask \p UsedLanes for the used lanes on a def output of a
75  /// COPY-like instruction determine the lanes used on the use operands
76  /// and call addUsedLanesOnOperand() for them.
77  void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
78 
79  /// Given a use regiser operand \p Use and a mask of defined lanes, check
80  /// if the operand belongs to a lowersToCopies() instruction, transfer the
81  /// mask to the def and put the instruction into the worklist.
82  void transferDefinedLanesStep(const MachineOperand &Use,
83  LaneBitmask DefinedLanes);
84 
85  /// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
86  /// of COPY-like instruction, determine which lanes are defined at the output
87  /// operand \p Def.
88  LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
89  LaneBitmask DefinedLanes) const;
90 
91  /// Given a mask \p UsedLanes used from the output of instruction \p MI
92  /// determine which lanes are used from operand \p MO of this instruction.
93  LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
94  const MachineOperand &MO) const;
95 
96  bool runOnce(MachineFunction &MF);
97 
98  LaneBitmask determineInitialDefinedLanes(unsigned Reg);
99  LaneBitmask determineInitialUsedLanes(unsigned Reg);
100 
101  bool isUndefRegAtInput(const MachineOperand &MO,
102  const VRegInfo &RegInfo) const;
103 
104  bool isUndefInput(const MachineOperand &MO, bool *CrossCopy) const;
105 
106  const MachineRegisterInfo *MRI;
107  const TargetRegisterInfo *TRI;
108 
109  void PutInWorklist(unsigned RegIdx) {
110  if (WorklistMembers.test(RegIdx))
111  return;
112  WorklistMembers.set(RegIdx);
113  Worklist.push_back(RegIdx);
114  }
115 
116  VRegInfo *VRegInfos;
117  /// Worklist containing virtreg indexes.
118  std::deque<unsigned> Worklist;
119  BitVector WorklistMembers;
120  /// This bitvector is set for each vreg index where the vreg is defined
121  /// by an instruction where lowersToCopies()==true.
122  BitVector DefinedByCopy;
123 };
124 
125 } // end anonymous namespace
126 
127 char DetectDeadLanes::ID = 0;
129 
130 INITIALIZE_PASS(DetectDeadLanes, DEBUG_TYPE, "Detect Dead Lanes", false, false)
131 
132 /// Returns true if \p MI will get lowered to a series of COPY instructions.
133 /// We call this a COPY-like instruction.
135  // Note: We could support instructions with MCInstrDesc::isRegSequenceLike(),
136  // isExtractSubRegLike(), isInsertSubregLike() in the future even though they
137  // are not lowered to a COPY.
138  switch (MI.getOpcode()) {
139  case TargetOpcode::COPY:
140  case TargetOpcode::PHI:
141  case TargetOpcode::INSERT_SUBREG:
142  case TargetOpcode::REG_SEQUENCE:
143  case TargetOpcode::EXTRACT_SUBREG:
144  return true;
145  }
146  return false;
147 }
148 
150  const MachineInstr &MI,
151  const TargetRegisterClass *DstRC,
152  const MachineOperand &MO) {
154  Register SrcReg = MO.getReg();
155  const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
156  if (DstRC == SrcRC)
157  return false;
158 
159  unsigned SrcSubIdx = MO.getSubReg();
160 
161  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
162  unsigned DstSubIdx = 0;
163  switch (MI.getOpcode()) {
164  case TargetOpcode::INSERT_SUBREG:
165  if (MI.getOperandNo(&MO) == 2)
166  DstSubIdx = MI.getOperand(3).getImm();
167  break;
168  case TargetOpcode::REG_SEQUENCE: {
169  unsigned OpNum = MI.getOperandNo(&MO);
170  DstSubIdx = MI.getOperand(OpNum+1).getImm();
171  break;
172  }
173  case TargetOpcode::EXTRACT_SUBREG: {
174  unsigned SubReg = MI.getOperand(2).getImm();
175  SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
176  }
177  }
178 
179  unsigned PreA, PreB; // Unused.
180  if (SrcSubIdx && DstSubIdx)
181  return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
182  PreB);
183  if (SrcSubIdx)
184  return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
185  if (DstSubIdx)
186  return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
187  return !TRI.getCommonSubClass(SrcRC, DstRC);
188 }
189 
190 void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
191  LaneBitmask UsedLanes) {
192  if (!MO.readsReg())
193  return;
194  Register MOReg = MO.getReg();
195  if (!Register::isVirtualRegister(MOReg))
196  return;
197 
198  unsigned MOSubReg = MO.getSubReg();
199  if (MOSubReg != 0)
200  UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes);
201  UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg);
202 
203  unsigned MORegIdx = Register::virtReg2Index(MOReg);
204  VRegInfo &MORegInfo = VRegInfos[MORegIdx];
205  LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes;
206  // Any change at all?
207  if ((UsedLanes & ~PrevUsedLanes).none())
208  return;
209 
210  // Set UsedLanes and remember instruction for further propagation.
211  MORegInfo.UsedLanes = PrevUsedLanes | UsedLanes;
212  if (DefinedByCopy.test(MORegIdx))
213  PutInWorklist(MORegIdx);
214 }
215 
216 void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
217  LaneBitmask UsedLanes) {
218  for (const MachineOperand &MO : MI.uses()) {
219  if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
220  continue;
221  LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO);
222  addUsedLanesOnOperand(MO, UsedOnMO);
223  }
224 }
225 
226 LaneBitmask DetectDeadLanes::transferUsedLanes(const MachineInstr &MI,
227  LaneBitmask UsedLanes,
228  const MachineOperand &MO) const {
229  unsigned OpNum = MI.getOperandNo(&MO);
231  DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]);
232 
233  switch (MI.getOpcode()) {
234  case TargetOpcode::COPY:
235  case TargetOpcode::PHI:
236  return UsedLanes;
237  case TargetOpcode::REG_SEQUENCE: {
238  assert(OpNum % 2 == 1);
239  unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
240  return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
241  }
242  case TargetOpcode::INSERT_SUBREG: {
243  unsigned SubIdx = MI.getOperand(3).getImm();
244  LaneBitmask MO2UsedLanes =
245  TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
246  if (OpNum == 2)
247  return MO2UsedLanes;
248 
249  const MachineOperand &Def = MI.getOperand(0);
250  Register DefReg = Def.getReg();
251  const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
252  LaneBitmask MO1UsedLanes;
253  if (RC->CoveredBySubRegs)
254  MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
255  else
256  MO1UsedLanes = RC->LaneMask;
257 
258  assert(OpNum == 1);
259  return MO1UsedLanes;
260  }
261  case TargetOpcode::EXTRACT_SUBREG: {
262  assert(OpNum == 1);
263  unsigned SubIdx = MI.getOperand(2).getImm();
264  return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
265  }
266  default:
267  llvm_unreachable("function must be called with COPY-like instruction");
268  }
269 }
270 
271 void DetectDeadLanes::transferDefinedLanesStep(const MachineOperand &Use,
272  LaneBitmask DefinedLanes) {
273  if (!Use.readsReg())
274  return;
275  // Check whether the operand writes a vreg and is part of a COPY-like
276  // instruction.
277  const MachineInstr &MI = *Use.getParent();
278  if (MI.getDesc().getNumDefs() != 1)
279  return;
280  // FIXME: PATCHPOINT instructions announce a Def that does not always exist,
281  // they really need to be modeled differently!
282  if (MI.getOpcode() == TargetOpcode::PATCHPOINT)
283  return;
284  const MachineOperand &Def = *MI.defs().begin();
285  Register DefReg = Def.getReg();
286  if (!Register::isVirtualRegister(DefReg))
287  return;
288  unsigned DefRegIdx = Register::virtReg2Index(DefReg);
289  if (!DefinedByCopy.test(DefRegIdx))
290  return;
291 
292  unsigned OpNum = MI.getOperandNo(&Use);
293  DefinedLanes =
294  TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
295  DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);
296 
297  VRegInfo &RegInfo = VRegInfos[DefRegIdx];
298  LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes;
299  // Any change at all?
300  if ((DefinedLanes & ~PrevDefinedLanes).none())
301  return;
302 
303  RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes;
304  PutInWorklist(DefRegIdx);
305 }
306 
307 LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def,
308  unsigned OpNum, LaneBitmask DefinedLanes) const {
309  const MachineInstr &MI = *Def.getParent();
310  // Translate DefinedLanes if necessary.
311  switch (MI.getOpcode()) {
312  case TargetOpcode::REG_SEQUENCE: {
313  unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
314  DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
315  DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
316  break;
317  }
318  case TargetOpcode::INSERT_SUBREG: {
319  unsigned SubIdx = MI.getOperand(3).getImm();
320  if (OpNum == 2) {
321  DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
322  DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
323  } else {
324  assert(OpNum == 1 && "INSERT_SUBREG must have two operands");
325  // Ignore lanes defined by operand 2.
326  DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);
327  }
328  break;
329  }
330  case TargetOpcode::EXTRACT_SUBREG: {
331  unsigned SubIdx = MI.getOperand(2).getImm();
332  assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only");
333  DefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(SubIdx, DefinedLanes);
334  break;
335  }
336  case TargetOpcode::COPY:
337  case TargetOpcode::PHI:
338  break;
339  default:
340  llvm_unreachable("function must be called with COPY-like instruction");
341  }
342 
343  assert(Def.getSubReg() == 0 &&
344  "Should not have subregister defs in machine SSA phase");
345  DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());
346  return DefinedLanes;
347 }
348 
349 LaneBitmask DetectDeadLanes::determineInitialDefinedLanes(unsigned Reg) {
350  // Live-In or unused registers have no definition but are considered fully
351  // defined.
352  if (!MRI->hasOneDef(Reg))
353  return LaneBitmask::getAll();
354 
355  const MachineOperand &Def = *MRI->def_begin(Reg);
356  const MachineInstr &DefMI = *Def.getParent();
357  if (lowersToCopies(DefMI)) {
358  // Start optimisatically with no used or defined lanes for copy
359  // instructions. The following dataflow analysis will add more bits.
360  unsigned RegIdx = Register::virtReg2Index(Reg);
361  DefinedByCopy.set(RegIdx);
362  PutInWorklist(RegIdx);
363 
364  if (Def.isDead())
365  return LaneBitmask::getNone();
366 
367  // COPY/PHI can copy across unrelated register classes (example: float/int)
368  // with incompatible subregister structure. Do not include these in the
369  // dataflow analysis since we cannot transfer lanemasks in a meaningful way.
370  const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
371 
372  // Determine initially DefinedLanes.
373  LaneBitmask DefinedLanes;
374  for (const MachineOperand &MO : DefMI.uses()) {
375  if (!MO.isReg() || !MO.readsReg())
376  continue;
377  Register MOReg = MO.getReg();
378  if (!MOReg)
379  continue;
380 
381  LaneBitmask MODefinedLanes;
382  if (Register::isPhysicalRegister(MOReg)) {
383  MODefinedLanes = LaneBitmask::getAll();
384  } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
385  MODefinedLanes = LaneBitmask::getAll();
386  } else {
388  if (MRI->hasOneDef(MOReg)) {
389  const MachineOperand &MODef = *MRI->def_begin(MOReg);
390  const MachineInstr &MODefMI = *MODef.getParent();
391  // Bits from copy-like operations will be added later.
392  if (lowersToCopies(MODefMI) || MODefMI.isImplicitDef())
393  continue;
394  }
395  unsigned MOSubReg = MO.getSubReg();
396  MODefinedLanes = MRI->getMaxLaneMaskForVReg(MOReg);
397  MODefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(
398  MOSubReg, MODefinedLanes);
399  }
400 
401  unsigned OpNum = DefMI.getOperandNo(&MO);
402  DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);
403  }
404  return DefinedLanes;
405  }
406  if (DefMI.isImplicitDef() || Def.isDead())
407  return LaneBitmask::getNone();
408 
409  assert(Def.getSubReg() == 0 &&
410  "Should not have subregister defs in machine SSA phase");
411  return MRI->getMaxLaneMaskForVReg(Reg);
412 }
413 
414 LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
415  LaneBitmask UsedLanes = LaneBitmask::getNone();
416  for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
417  if (!MO.readsReg())
418  continue;
419 
420  const MachineInstr &UseMI = *MO.getParent();
421  if (UseMI.isKill())
422  continue;
423 
424  unsigned SubReg = MO.getSubReg();
425  if (lowersToCopies(UseMI)) {
426  assert(UseMI.getDesc().getNumDefs() == 1);
427  const MachineOperand &Def = *UseMI.defs().begin();
428  Register DefReg = Def.getReg();
429  // The used lanes of COPY-like instruction operands are determined by the
430  // following dataflow analysis.
431  if (Register::isVirtualRegister(DefReg)) {
432  // But ignore copies across incompatible register classes.
433  bool CrossCopy = false;
434  if (lowersToCopies(UseMI)) {
435  const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
436  CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
437  if (CrossCopy)
438  LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
439  }
440 
441  if (!CrossCopy)
442  continue;
443  }
444  }
445 
446  // Shortcut: All lanes are used.
447  if (SubReg == 0)
448  return MRI->getMaxLaneMaskForVReg(Reg);
449 
450  UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
451  }
452  return UsedLanes;
453 }
454 
455 bool DetectDeadLanes::isUndefRegAtInput(const MachineOperand &MO,
456  const VRegInfo &RegInfo) const {
457  unsigned SubReg = MO.getSubReg();
458  LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
459  return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none();
460 }
461 
462 bool DetectDeadLanes::isUndefInput(const MachineOperand &MO,
463  bool *CrossCopy) const {
464  if (!MO.isUse())
465  return false;
466  const MachineInstr &MI = *MO.getParent();
467  if (!lowersToCopies(MI))
468  return false;
469  const MachineOperand &Def = MI.getOperand(0);
470  Register DefReg = Def.getReg();
471  if (!Register::isVirtualRegister(DefReg))
472  return false;
473  unsigned DefRegIdx = Register::virtReg2Index(DefReg);
474  if (!DefinedByCopy.test(DefRegIdx))
475  return false;
476 
477  const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
478  LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
479  if (UsedLanes.any())
480  return false;
481 
482  Register MOReg = MO.getReg();
483  if (Register::isVirtualRegister(MOReg)) {
484  const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
485  *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
486  }
487  return true;
488 }
489 
490 bool DetectDeadLanes::runOnce(MachineFunction &MF) {
491  // First pass: Populate defs/uses of vregs with initial values
492  unsigned NumVirtRegs = MRI->getNumVirtRegs();
493  for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
494  unsigned Reg = Register::index2VirtReg(RegIdx);
495 
496  // Determine used/defined lanes and add copy instructions to worklist.
497  VRegInfo &Info = VRegInfos[RegIdx];
498  Info.DefinedLanes = determineInitialDefinedLanes(Reg);
499  Info.UsedLanes = determineInitialUsedLanes(Reg);
500  }
501 
502  // Iterate as long as defined lanes/used lanes keep changing.
503  while (!Worklist.empty()) {
504  unsigned RegIdx = Worklist.front();
505  Worklist.pop_front();
506  WorklistMembers.reset(RegIdx);
507  VRegInfo &Info = VRegInfos[RegIdx];
508  unsigned Reg = Register::index2VirtReg(RegIdx);
509 
510  // Transfer UsedLanes to operands of DefMI (backwards dataflow).
511  MachineOperand &Def = *MRI->def_begin(Reg);
512  const MachineInstr &MI = *Def.getParent();
513  transferUsedLanesStep(MI, Info.UsedLanes);
514  // Transfer DefinedLanes to users of Reg (forward dataflow).
515  for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
516  transferDefinedLanesStep(MO, Info.DefinedLanes);
517  }
518 
519  LLVM_DEBUG(dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0;
520  RegIdx < NumVirtRegs;
521  ++RegIdx) {
522  unsigned Reg = Register::index2VirtReg(RegIdx);
523  const VRegInfo &Info = VRegInfos[RegIdx];
524  dbgs() << printReg(Reg, nullptr)
525  << " Used: " << PrintLaneMask(Info.UsedLanes)
526  << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
527  } dbgs() << "\n";);
528 
529  bool Again = false;
530  // Mark operands as dead/unused.
531  for (MachineBasicBlock &MBB : MF) {
532  for (MachineInstr &MI : MBB) {
533  for (MachineOperand &MO : MI.operands()) {
534  if (!MO.isReg())
535  continue;
536  Register Reg = MO.getReg();
538  continue;
539  unsigned RegIdx = Register::virtReg2Index(Reg);
540  const VRegInfo &RegInfo = VRegInfos[RegIdx];
541  if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
542  LLVM_DEBUG(dbgs()
543  << "Marking operand '" << MO << "' as dead in " << MI);
544  MO.setIsDead();
545  }
546  if (MO.readsReg()) {
547  bool CrossCopy = false;
548  if (isUndefRegAtInput(MO, RegInfo)) {
549  LLVM_DEBUG(dbgs()
550  << "Marking operand '" << MO << "' as undef in " << MI);
551  MO.setIsUndef();
552  } else if (isUndefInput(MO, &CrossCopy)) {
553  LLVM_DEBUG(dbgs()
554  << "Marking operand '" << MO << "' as undef in " << MI);
555  MO.setIsUndef();
556  if (CrossCopy)
557  Again = true;
558  }
559  }
560  }
561  }
562  }
563 
564  return Again;
565 }
566 
567 bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
568  // Don't bother if we won't track subregister liveness later. This pass is
569  // required for correctness if subregister liveness is enabled because the
570  // register coalescer cannot deal with hidden dead defs. However without
571  // subregister liveness enabled, the expected benefits of this pass are small
572  // so we safe the compile time.
573  MRI = &MF.getRegInfo();
574  if (!MRI->subRegLivenessEnabled()) {
575  LLVM_DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
576  return false;
577  }
578 
579  TRI = MRI->getTargetRegisterInfo();
580 
581  unsigned NumVirtRegs = MRI->getNumVirtRegs();
582  VRegInfos = new VRegInfo[NumVirtRegs];
583  WorklistMembers.resize(NumVirtRegs);
584  DefinedByCopy.resize(NumVirtRegs);
585 
586  bool Again;
587  do {
588  Again = runOnce(MF);
589  } while(Again);
590 
591  DefinedByCopy.clear();
592  WorklistMembers.clear();
593  delete[] VRegInfos;
594  return true;
595 }
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
void setIsUndef(bool Val=true)
unsigned Reg
unsigned getSubReg() const
#define DEBUG_TYPE
unsigned const TargetRegisterInfo * TRI
void setIsDead(bool Val=true)
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:93
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
MachineBasicBlock & MBB
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
unsigned SubReg
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:83
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:82
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Analysis containing CSE Info
Definition: CSEInfo.cpp:25
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineInstrBuilder & UseMI
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
static bool lowersToCopies(const MachineInstr &MI)
Returns true if MI will get lowered to a series of COPY instructions.
Represent the analysis usage information of a pass.
bool isImplicitDef() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
static bool isCrossCopy(const MachineRegisterInfo &MRI, const MachineInstr &MI, const TargetRegisterClass *DstRC, const MachineOperand &MO)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Representation of each machine instruction.
Definition: MachineInstr.h:62
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
constexpr bool any() const
Definition: LaneBitmask.h:52
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Wrapper class representing virtual and physical registers.
Definition: Register.h:19