LLVM 18.0.0git
DeadMachineInstructionElim.cpp
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1//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is an extremely simple MachineInstr-level dead-code-elimination pass.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/Statistic.h"
20#include "llvm/Pass.h"
21#include "llvm/Support/Debug.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "dead-mi-elimination"
27
28STATISTIC(NumDeletes, "Number of dead instructions deleted");
29
30namespace {
31 class DeadMachineInstructionElim : public MachineFunctionPass {
32 bool runOnMachineFunction(MachineFunction &MF) override;
33
34 const MachineRegisterInfo *MRI = nullptr;
35 const TargetInstrInfo *TII = nullptr;
37
38 public:
39 static char ID; // Pass identification, replacement for typeid
40 DeadMachineInstructionElim() : MachineFunctionPass(ID) {
42 }
43
44 void getAnalysisUsage(AnalysisUsage &AU) const override {
45 AU.setPreservesCFG();
47 }
48
49 private:
50 bool isDead(const MachineInstr *MI) const;
51
52 bool eliminateDeadMI(MachineFunction &MF);
53 };
54}
55char DeadMachineInstructionElim::ID = 0;
56char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
57
58INITIALIZE_PASS(DeadMachineInstructionElim, DEBUG_TYPE,
59 "Remove dead machine instructions", false, false)
60
61bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
62 // Technically speaking inline asm without side effects and no defs can still
63 // be deleted. But there is so much bad inline asm code out there, we should
64 // let them be.
65 if (MI->isInlineAsm())
66 return false;
67
68 // Don't delete frame allocation labels.
69 if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
70 return false;
71
72 // Don't delete instructions with side effects.
73 bool SawStore = false;
74 if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI())
75 return false;
76
77 // Examine each operand.
78 for (const MachineOperand &MO : MI->all_defs()) {
79 Register Reg = MO.getReg();
80 if (Reg.isPhysical()) {
81 // Don't delete live physreg defs, or any reserved register defs.
82 if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
83 return false;
84 } else {
85 if (MO.isDead()) {
86#ifndef NDEBUG
87 // Basic check on the register. All of them should be 'undef'.
88 for (auto &U : MRI->use_nodbg_operands(Reg))
89 assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
90#endif
91 continue;
92 }
93 for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
94 if (&Use != MI)
95 // This def has a non-debug use. Don't delete the instruction!
96 return false;
97 }
98 }
99 }
100
101 // If there are no defs with uses, the instruction is dead.
102 return true;
103}
104
105bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
106 if (skipFunction(MF.getFunction()))
107 return false;
108
109 MRI = &MF.getRegInfo();
110
111 const TargetSubtargetInfo &ST = MF.getSubtarget();
112 TII = ST.getInstrInfo();
113 LivePhysRegs.init(*ST.getRegisterInfo());
114
115 bool AnyChanges = eliminateDeadMI(MF);
116 while (AnyChanges && eliminateDeadMI(MF))
117 ;
118 return AnyChanges;
119}
120
121bool DeadMachineInstructionElim::eliminateDeadMI(MachineFunction &MF) {
122 bool AnyChanges = false;
123
124 // Loop over all instructions in all blocks, from bottom to top, so that it's
125 // more likely that chains of dependent but ultimately dead instructions will
126 // be cleaned up.
127 for (MachineBasicBlock *MBB : post_order(&MF)) {
129
130 // Now scan the instructions and delete dead ones, tracking physreg
131 // liveness as we go.
133 // If the instruction is dead, delete it!
134 if (isDead(&MI)) {
135 LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << MI);
136 // It is possible that some DBG_VALUE instructions refer to this
137 // instruction. They will be deleted in the live debug variable
138 // analysis.
139 MI.eraseFromParent();
140 AnyChanges = true;
141 ++NumDeletes;
142 continue;
143 }
144
146 }
147 }
148
150 return AnyChanges;
151}
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
MachineBasicBlock & MBB
#define DEBUG_TYPE
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
A set of register units.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:269
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
void clear()
Clears the set.
Definition: LivePhysRegs.h:75
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void init(const TargetRegisterInfo &TRI)
(re-)initializes and clears the set.
Definition: LivePhysRegs.h:68
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetInstrInfo - Interface to description of machine instruction set.
TargetSubtargetInfo - Generic base class for all target subtargets.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:665
iterator_range< po_iterator< T > > post_order(const T &G)
void initializeDeadMachineInstructionElimPass(PassRegistry &)
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:428
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.