65#define DEBUG_TYPE "twoaddressinstruction"
67STATISTIC(NumTwoAddressInstrs,
"Number of two-address instructions");
68STATISTIC(NumCommuted ,
"Number of instructions commuted to coalesce");
69STATISTIC(NumAggrCommuted ,
"Number of instructions aggressively commuted");
70STATISTIC(NumConvertedTo3Addr,
"Number of instructions promoted to 3-address");
71STATISTIC(NumReSchedUps,
"Number of instructions re-scheduled up");
72STATISTIC(NumReSchedDowns,
"Number of instructions re-scheduled down");
77 cl::desc(
"Coalesce copies by rescheduling (default=true)"),
84 cl::desc(
"Maximum number of dataflow edges to traverse when evaluating "
85 "the benefit of commuting operands"));
123 bool noUseAfterLastDef(
Register Reg,
unsigned Dist,
unsigned &LastDef);
126 bool &IsSrcPhys,
bool &IsDstPhys)
const;
135 bool &IsDstPhys)
const;
150 unsigned RegBIdx,
unsigned RegCIdx,
unsigned Dist);
167 unsigned SrcIdx,
unsigned DstIdx,
168 unsigned &Dist,
bool shouldOnlyCommute);
183 void processTiedPairs(
MachineInstr *
MI, TiedPairList&,
unsigned &Dist);
185 bool processStatepoint(
MachineInstr *
MI, TiedOperandMap &TiedOperands);
212char TwoAddressInstructionPass::ID = 0;
217 "Two-Address instruction pass",
false,
false)
224TwoAddressInstructionPass::getSingleDef(
Register Reg,
228 if (
DefMI.getParent() != BB ||
DefMI.isDebugValue())
232 else if (Ret != &
DefMI)
245bool TwoAddressInstructionPass::isRevCopyChain(
Register FromReg,
Register ToReg,
248 for (
int i = 0; i < Maxlen; i++) {
250 if (!Def || !
Def->isCopy())
253 TmpReg =
Def->getOperand(1).getReg();
265bool TwoAddressInstructionPass::noUseAfterLastDef(
Register Reg,
unsigned Dist,
268 unsigned LastUse = Dist;
271 if (
MI->getParent() !=
MBB ||
MI->isDebugValue())
274 if (DI == DistanceMap.
end())
276 if (MO.isUse() && DI->second < LastUse)
277 LastUse = DI->second;
278 if (MO.isDef() && DI->second > LastDef)
279 LastDef = DI->second;
282 return !(LastUse > LastDef && LastUse < Dist);
290 bool &IsDstPhys)
const {
294 DstReg =
MI.getOperand(0).getReg();
295 SrcReg =
MI.getOperand(1).getReg();
296 }
else if (
MI.isInsertSubreg() ||
MI.isSubregToReg()) {
297 DstReg =
MI.getOperand(0).getReg();
298 SrcReg =
MI.getOperand(2).getReg();
310bool TwoAddressInstructionPass::isPlainlyKilled(
const MachineInstr *
MI,
327 assert(
I != LI.
end() &&
"Reg must be live-in to use.");
331 return MI->killsRegister(Reg);
336bool TwoAddressInstructionPass::isPlainlyKilled(
359 bool allowFalsePositives)
const {
363 if (
Reg.isPhysical() && (allowFalsePositives ||
MRI->hasOneUse(Reg)))
365 if (!isPlainlyKilled(
DefMI, Reg))
367 if (
Reg.isPhysical())
372 if (std::next(Begin) !=
MRI->def_end())
375 bool IsSrcPhys, IsDstPhys;
379 if (!isCopyToReg(*
DefMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
388 for (
unsigned i = 0, NumOps =
MI.getNumOperands(); i != NumOps; ++i) {
393 if (
MI.isRegTiedToDefOperand(i, &ti)) {
394 DstReg =
MI.getOperand(ti).getReg();
403MachineInstr *TwoAddressInstructionPass::findOnlyInterestingUse(
405 bool &IsDstPhys)
const {
409 if (
MI->getParent() !=
MBB)
411 if (isPlainlyKilled(
MI, Reg))
420 if (isCopyToReg(
UseMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
429 if (
UseMI.isCommutable()) {
432 if (
TII->findCommutedOpIndices(
UseMI, Src1, Src2)) {
448 while (Reg.isVirtual()) {
450 if (SI == RegMap.
end())
454 if (Reg.isPhysical())
460bool TwoAddressInstructionPass::regsAreCompatible(
Register RegA,
466 return TRI->regsOverlap(RegA, RegB);
470void TwoAddressInstructionPass::removeMapRegEntry(
474 "removeMapRegEntry must be called with a register or regmask operand.");
477 for (
auto SI : RegMap) {
484 if (
TRI->regsOverlap(ToReg, Reg))
490 for (
auto SrcReg : Srcs)
491 RegMap.erase(SrcReg);
502void TwoAddressInstructionPass::removeClobberedSrcRegMap(
MachineInstr *
MI) {
515 if (!Dst || Dst.isVirtual())
519 if (regsAreCompatible(Dst,
getMappedReg(Src, SrcRegMap)))
525 removeMapRegEntry(MO, SrcRegMap);
531 if (!Reg ||
Reg.isVirtual())
533 removeMapRegEntry(MO, SrcRegMap);
538bool TwoAddressInstructionPass::regOverlapsSet(
540 for (
unsigned R : Set)
541 if (
TRI->regsOverlap(R, Reg))
549bool TwoAddressInstructionPass::isProfitableToCommute(
Register RegA,
554 if (OptLevel == CodeGenOptLevel::None)
575 if (!isPlainlyKilled(
MI, RegC))
592 bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA);
593 bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA);
599 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
605 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
611 unsigned LastDefC = 0;
612 if (!noUseAfterLastDef(RegC, Dist, LastDefC))
617 unsigned LastDefB = 0;
618 if (!noUseAfterLastDef(RegB, Dist, LastDefB))
644 if (
TII->hasCommutePreference(*
MI, Commute))
649 return LastDefB && LastDefC && LastDefC > LastDefB;
654bool TwoAddressInstructionPass::commuteInstruction(
MachineInstr *
MI,
659 Register RegC =
MI->getOperand(RegCIdx).getReg();
663 if (NewMI ==
nullptr) {
670 "TargetInstrInfo::commuteInstruction() should not return a new "
671 "instruction unless it was requested.");
676 Register RegA =
MI->getOperand(DstIdx).getReg();
677 SrcRegMap[RegA] = FromRegC;
685bool TwoAddressInstructionPass::isProfitableToConv3Addr(
Register RegA,
697 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA));
702bool TwoAddressInstructionPass::convertInstTo3Addr(
714 if (
auto OldInstrNum = mi->peekDebugInstrNum()) {
715 assert(mi->getNumExplicitDefs() == 1);
719 unsigned OldIdx = mi->defs().begin()->getOperandNo();
720 unsigned NewIdx = NewMI->
defs().begin()->getOperandNo();
725 std::make_pair(NewInstrNum, NewIdx));
731 DistanceMap.
insert(std::make_pair(&
MI, Dist++));
737 SrcRegMap.
erase(RegA);
738 DstRegMap.
erase(RegB);
744void TwoAddressInstructionPass::scanUses(
Register DstReg) {
751 findOnlyInterestingUse(Reg,
MBB, IsCopy, NewReg, IsDstPhys)) {
756 if (DI != DistanceMap.
end())
764 SrcRegMap[NewReg] =
Reg;
769 if (!VirtRegPairs.
empty()) {
770 unsigned ToReg = VirtRegPairs.
back();
772 while (!VirtRegPairs.
empty()) {
774 bool isNew = DstRegMap.
insert(std::make_pair(FromReg, ToReg)).second;
776 assert(DstRegMap[FromReg] == ToReg &&
"Can't map to two dst registers!");
779 bool isNew = DstRegMap.
insert(std::make_pair(DstReg, ToReg)).second;
781 assert(DstRegMap[DstReg] == ToReg &&
"Can't map to two dst registers!");
801 bool IsSrcPhys, IsDstPhys;
803 if (!isCopyToReg(*
MI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
806 if (IsDstPhys && !IsSrcPhys) {
807 DstRegMap.
insert(std::make_pair(SrcReg, DstReg));
808 }
else if (!IsDstPhys && IsSrcPhys) {
809 bool isNew = SrcRegMap.
insert(std::make_pair(DstReg, SrcReg)).second;
811 assert(SrcRegMap[DstReg] == SrcReg &&
812 "Can't map to two src physical registers!");
823bool TwoAddressInstructionPass::rescheduleMIBelowKill(
833 if (DI == DistanceMap.
end())
841 "Reg should not have empty live interval.");
845 if (
I != LI.
end() &&
I->start < MBBEndIdx)
866 bool SeenStore =
true;
867 if (!
MI->isSafeToMove(AA, SeenStore))
886 Uses.push_back(MOReg);
887 if (MOReg != Reg && isPlainlyKilled(MO))
898 if (
End->isCopy() && regOverlapsSet(Defs,
End->getOperand(1).getReg()))
906 unsigned NumVisited = 0;
911 if (OtherMI.isDebugOrPseudoInstr())
916 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
917 OtherMI.isBranch() || OtherMI.isTerminator())
927 if (regOverlapsSet(
Uses, MOReg))
930 if (!MO.
isDead() && regOverlapsSet(Defs, MOReg))
936 if (regOverlapsSet(Defs, MOReg))
938 bool isKill = isPlainlyKilled(MO);
939 if (MOReg != Reg && ((isKill && regOverlapsSet(
Uses, MOReg)) ||
940 regOverlapsSet(Kills, MOReg)))
943 if (MOReg == Reg && !isKill)
947 assert((MOReg != Reg || &OtherMI == KillMI) &&
948 "Found multiple kills of a register in a basic block");
954 while (Begin !=
MBB->
begin() && std::prev(Begin)->isDebugInstr())
963 auto CopyMI =
MBBI++;
965 if (!CopyMI->isDebugOrPseudoInstr())
974 DistanceMap.
erase(DI);
990bool TwoAddressInstructionPass::isDefTooClose(
Register Reg,
unsigned Dist,
998 if (DDI == DistanceMap.
end())
1000 unsigned DefDist = DDI->second;
1001 assert(Dist > DefDist &&
"Visited def already?");
1011bool TwoAddressInstructionPass::rescheduleKillAboveMI(
1021 if (DI == DistanceMap.
end())
1029 "Reg should not have empty live interval.");
1033 if (
I != LI.
end() &&
I->start < MBBEndIdx)
1049 bool SeenStore =
true;
1064 if (isDefTooClose(MOReg, DI->second,
MI))
1066 bool isKill = isPlainlyKilled(MO);
1067 if (MOReg == Reg && !isKill)
1069 Uses.push_back(MOReg);
1070 if (isKill && MOReg != Reg)
1080 unsigned NumVisited = 0;
1084 if (OtherMI.isDebugOrPseudoInstr())
1086 if (NumVisited > 10)
1089 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1090 OtherMI.isBranch() || OtherMI.isTerminator())
1101 if (regOverlapsSet(Defs, MOReg))
1105 if (regOverlapsSet(Kills, MOReg))
1108 if (&OtherMI !=
MI && MOReg == Reg && !isPlainlyKilled(MO))
1116 for (
unsigned i = 0, e = OtherDefs.
size(); i != e; ++i) {
1118 if (regOverlapsSet(
Uses, MOReg))
1120 if (MOReg.
isPhysical() && regOverlapsSet(LiveDefs, MOReg))
1129 while (InsertPos !=
MBB->
begin() && std::prev(InsertPos)->isDebugInstr())
1133 while (std::prev(
From)->isDebugInstr())
1137 nmi = std::prev(InsertPos);
1138 DistanceMap.
erase(DI);
1164bool TwoAddressInstructionPass::tryInstructionCommute(
MachineInstr *
MI,
1169 if (!
MI->isCommutable())
1172 bool MadeChange =
false;
1173 Register DstOpReg =
MI->getOperand(DstOpIdx).getReg();
1174 Register BaseOpReg =
MI->getOperand(BaseOpIdx).getReg();
1175 unsigned OpsNum =
MI->getDesc().getNumOperands();
1176 unsigned OtherOpIdx =
MI->getDesc().getNumDefs();
1177 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1182 if (OtherOpIdx == BaseOpIdx || !
MI->getOperand(OtherOpIdx).isReg() ||
1183 !
TII->findCommutedOpIndices(*
MI, BaseOpIdx, OtherOpIdx))
1186 Register OtherOpReg =
MI->getOperand(OtherOpIdx).getReg();
1187 bool AggressiveCommute =
false;
1191 bool OtherOpKilled = isKilled(*
MI, OtherOpReg,
false);
1192 bool DoCommute = !BaseOpKilled && OtherOpKilled;
1195 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg,
MI, Dist)) {
1197 AggressiveCommute =
true;
1201 if (DoCommute && commuteInstruction(
MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1205 if (AggressiveCommute)
1212 BaseOpReg = OtherOpReg;
1213 BaseOpKilled = OtherOpKilled;
1216 OpsNum =
MI->getDesc().getNumOperands();
1229bool TwoAddressInstructionPass::
1232 unsigned SrcIdx,
unsigned DstIdx,
1233 unsigned &Dist,
bool shouldOnlyCommute) {
1234 if (OptLevel == CodeGenOptLevel::None)
1238 Register regA =
MI.getOperand(DstIdx).getReg();
1239 Register regB =
MI.getOperand(SrcIdx).getReg();
1241 assert(regB.
isVirtual() &&
"cannot make instruction into two-address form");
1242 bool regBKilled = isKilled(
MI, regB,
true);
1247 bool Commuted = tryInstructionCommute(&
MI, DstIdx, SrcIdx, regBKilled, Dist);
1257 if (Commuted && !
MI.isConvertibleTo3Addr())
1260 if (shouldOnlyCommute)
1273 regB =
MI.getOperand(SrcIdx).getReg();
1274 regBKilled = isKilled(
MI, regB,
true);
1277 if (
MI.isConvertibleTo3Addr()) {
1280 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1282 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1283 ++NumConvertedTo3Addr;
1308 if (
MI.mayLoad() && !regBKilled) {
1310 unsigned LoadRegIndex;
1312 TII->getOpcodeAfterMemoryUnfold(
MI.getOpcode(),
1322 TRI->getAllocatableClass(
1323 TII->getRegClass(UnfoldMCID, LoadRegIndex,
TRI, *MF));
1326 if (!
TII->unfoldMemoryOperand(*MF,
MI, Reg,
1333 "Unfolded a load into multiple instructions!");
1335 NewMIs[1]->addRegisterKilled(Reg,
TRI);
1341 DistanceMap.
insert(std::make_pair(NewMIs[0], Dist++));
1342 DistanceMap.
insert(std::make_pair(NewMIs[1], Dist));
1345 <<
"2addr: NEW INST: " << *NewMIs[1]);
1348 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1349 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1351 bool TransformResult =
1352 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist,
true);
1353 (void)TransformResult;
1354 assert(!TransformResult &&
1355 "tryInstructionTransform() should return false.");
1356 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1364 if (NewMIs[0]->killsRegister(MO.
getReg()))
1368 "Kill missing after load unfold!");
1373 if (NewMIs[1]->registerDefIsDead(MO.
getReg()))
1377 "Dead flag missing after load unfold!");
1396 MI.eraseFromParent();
1412 NewMIs[0]->eraseFromParent();
1413 NewMIs[1]->eraseFromParent();
1414 DistanceMap.
erase(NewMIs[0]);
1415 DistanceMap.
erase(NewMIs[1]);
1428bool TwoAddressInstructionPass::
1429collectTiedOperands(
MachineInstr *
MI, TiedOperandMap &TiedOperands) {
1430 bool AnyOps =
false;
1431 unsigned NumOps =
MI->getNumOperands();
1433 for (
unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1434 unsigned DstIdx = 0;
1435 if (!
MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1443 if (SrcReg == DstReg)
1446 assert(SrcReg && SrcMO.
isUse() &&
"two address instruction invalid");
1453 MRI->constrainRegClass(DstReg, RC);
1460 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1469 TiedPairList &TiedPairs,
1471 bool IsEarlyClobber =
llvm::any_of(TiedPairs, [
MI](
auto const &TP) {
1472 return MI->getOperand(TP.second).isEarlyClobber();
1475 bool RemovedKillFlag =
false;
1476 bool AllUsesCopied =
true;
1477 unsigned LastCopiedReg = 0;
1480 unsigned SubRegB = 0;
1481 for (
auto &TP : TiedPairs) {
1482 unsigned SrcIdx = TP.first;
1483 unsigned DstIdx = TP.second;
1490 RegB =
MI->getOperand(SrcIdx).getReg();
1491 SubRegB =
MI->getOperand(SrcIdx).getSubReg();
1497 AllUsesCopied =
false;
1500 LastCopiedReg = RegA;
1502 assert(RegB.
isVirtual() &&
"cannot make instruction into two-address form");
1508 for (
unsigned i = 0; i !=
MI->getNumOperands(); ++i)
1510 !
MI->getOperand(i).isReg() ||
1511 MI->getOperand(i).getReg() != RegA);
1516 TII->get(TargetOpcode::COPY), RegA);
1519 MIB.
addReg(RegB, 0, SubRegB);
1523 assert(
TRI->getMatchingSuperRegClass(RC,
MRI->getRegClass(RegA),
1525 "tied subregister must be a truncation");
1529 assert(
TRI->getMatchingSuperReg(RegA, SubRegB,
MRI->getRegClass(RegB))
1530 &&
"tied subregister must be a truncation");
1537 DistanceMap.
insert(std::make_pair(&*PrevMI, Dist));
1538 DistanceMap[
MI] = ++Dist;
1568 "inconsistent operand info for 2-reg pass");
1569 if (isPlainlyKilled(MO)) {
1571 RemovedKillFlag =
true;
1576 MRI->constrainRegClass(RegA, RC);
1584 if (AllUsesCopied) {
1588 if (MO.
getReg() == RegB) {
1589 if (MO.
getSubReg() == SubRegB && !IsEarlyClobber) {
1590 if (isPlainlyKilled(MO)) {
1592 RemovedKillFlag =
true;
1594 MO.
setReg(LastCopiedReg);
1597 RemainingUses |=
TRI->getSubRegIndexLaneMask(MO.
getSubReg());
1603 if (RemovedKillFlag && RemainingUses.
none() && LV &&
1610 if (RemovedKillFlag && RemainingUses.
none())
1611 SrcRegMap[LastCopiedReg] = RegB;
1620 if ((LaneMask & RemainingUses).any())
1624 S->
end = LastCopyIdx;
1629 bool ShrinkLI =
true;
1631 ShrinkLI &= Shrink(S, S.LaneMask);
1635 }
else if (RemovedKillFlag) {
1641 if (MO.
getReg() == RegB) {
1656bool TwoAddressInstructionPass::processStatepoint(
1659 bool NeedCopy =
false;
1660 for (
auto &TO : TiedOperands) {
1662 if (TO.second.size() != 1) {
1667 unsigned SrcIdx = TO.second[0].first;
1668 unsigned DstIdx = TO.second[0].second;
1673 assert(RegB ==
MI->getOperand(SrcIdx).getReg());
1686 if (DefLI.overlaps(UseLI)) {
1688 <<
" UseLI overlaps with DefLI\n");
1697 <<
" not killed by statepoint\n");
1702 if (!
MRI->constrainRegClass(RegB,
MRI->getRegClass(RegA))) {
1704 <<
" to register class of " <<
printReg(RegA,
TRI, 0)
1709 MRI->replaceRegWith(RegA, RegB);
1720 for (
auto &S :
Other) {
1729 if (
MI->getOperand(SrcIdx).isKill())
1735 for (
auto *KillMI : DstInfo.
Kills)
1743bool TwoAddressInstructionPass::runOnMachineFunction(
MachineFunction &Func) {
1750 LV = getAnalysisIfAvailable<LiveVariables>();
1751 LIS = getAnalysisIfAvailable<LiveIntervals>();
1752 if (
auto *AAPass = getAnalysisIfAvailable<AAResultsWrapperPass>())
1753 AA = &AAPass->getAAResults();
1756 OptLevel =
TM.getOptLevel();
1759 if (skipFunction(
Func.getFunction()))
1760 OptLevel = CodeGenOptLevel::None;
1762 bool MadeChange =
false;
1764 LLVM_DEBUG(
dbgs() <<
"********** REWRITING TWO-ADDR INSTRS **********\n");
1772 .
set(MachineFunctionProperties::Property::TiedOpsRewritten);
1774 TiedOperandMap TiedOperands;
1778 DistanceMap.
clear();
1786 if (mi->isDebugInstr()) {
1793 if (mi->isRegSequence())
1794 eliminateRegSequence(mi);
1796 DistanceMap.
insert(std::make_pair(&*mi, ++Dist));
1802 if (!collectTiedOperands(&*mi, TiedOperands)) {
1803 removeClobberedSrcRegMap(&*mi);
1808 ++NumTwoAddressInstrs;
1815 if (TiedOperands.size() == 1) {
1817 = TiedOperands.
begin()->second;
1818 if (TiedPairs.
size() == 1) {
1819 unsigned SrcIdx = TiedPairs[0].first;
1820 unsigned DstIdx = TiedPairs[0].second;
1821 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1822 Register DstReg = mi->getOperand(DstIdx).getReg();
1823 if (SrcReg != DstReg &&
1824 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist,
false)) {
1827 TiedOperands.clear();
1828 removeClobberedSrcRegMap(&*mi);
1835 if (mi->getOpcode() == TargetOpcode::STATEPOINT &&
1836 processStatepoint(&*mi, TiedOperands)) {
1837 TiedOperands.clear();
1844 for (
auto &TO : TiedOperands) {
1845 processTiedPairs(&*mi, TO.second, Dist);
1850 if (mi->isInsertSubreg()) {
1853 unsigned SubIdx = mi->getOperand(3).getImm();
1854 mi->removeOperand(3);
1855 assert(mi->getOperand(0).getSubReg() == 0 &&
"Unexpected subreg idx");
1856 mi->getOperand(0).setSubReg(SubIdx);
1857 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1858 mi->removeOperand(1);
1859 mi->setDesc(
TII->get(TargetOpcode::COPY));
1870 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg());
1873 if ((S.LaneMask & LaneMask).none()) {
1875 if (mi->getOperand(0).isUndef()) {
1876 S.removeValNo(DefSeg->valno);
1879 S.MergeValueNumberInto(DefSeg->valno, UseSeg->valno);
1897 TiedOperands.
clear();
1898 removeClobberedSrcRegMap(&*mi);
1916void TwoAddressInstructionPass::
1924 for (
unsigned i = 1, e =
MI.getNumOperands(); i < e; i += 2)
1928 bool DefEmitted =
false;
1929 for (
unsigned i = 1, e =
MI.getNumOperands(); i < e; i += 2) {
1932 unsigned SubIdx =
MI.getOperand(i+1).getImm();
1939 bool isKill = UseMO.
isKill();
1941 for (
unsigned j = i + 2;
j <
e;
j += 2)
1942 if (
MI.getOperand(j).getReg() == SrcReg) {
1943 MI.getOperand(j).setIsKill();
1951 TII->get(TargetOpcode::COPY))
1976 MI.setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
1977 for (
int j =
MI.getNumOperands() - 1, ee = 0; j > ee; --j)
1978 MI.removeOperand(j);
1984 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator MBBI
BlockVerifier::State From
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
std::optional< std::vector< StOtherPiece > > Other
Rewrite Partial Register Uses
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg)
Return true if the specified MI uses the specified register as a two-address use.
static MCRegister getMappedReg(Register Reg, DenseMap< Register, Register > &RegMap)
Return the physical register the specified virtual register might be mapped to.
Two Address instruction pass
static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
static cl::opt< unsigned > MaxDataFlowEdge("dataflow-edge-limit", cl::Hidden, cl::init(3), cl::desc("Maximum number of dataflow edges to traverse when evaluating " "the benefit of commuting operands"))
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Allocate memory in an ever growing pool, as if by bump-pointer.
iterator find(const_arg_type_t< KeyT > Val)
bool erase(const KeyT &Val)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
Itinerary data supplied by a subtarget to be used by a target.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
VNInfo::Allocator & getVNInfoAllocator()
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
void removeInterval(Register Reg)
Interval removal.
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
This class represents the liveness of a register, stack slot, etc.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
VNInfo * createValueCopy(const VNInfo *orig, VNInfo::Allocator &VNInfoAllocator)
Create a copy of the given value.
bool hasAtLeastOneValue() const
VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI)
removeVirtualRegisterDead - Remove the specified kill of the virtual register from the live variable ...
bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI)
removeVirtualRegisterKilled - Remove the specified kill of the virtual register from the live variabl...
void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterDead - Add information about the fact that the specified register is dead after bei...
void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterKilled - Add information about the fact that the specified register is killed after...
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Describe properties that are true of each instruction in the target description file.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Wrapper class representing physical registers. Should be passed by value.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, unsigned SubReg=0)
Create a substitution between one <instr,operand> value to a different, new value.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineInstrSpan provides an interface to get an iteration range containing the instruction it was in...
Representation of each machine instruction.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool isCall(QueryType Type=AnyInBundle) const
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
iterator_range< mop_iterator > operands()
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
static const unsigned CommuteAnyOperandIndex
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
VNInfo - Value Number Information.
unsigned id
The ID number of this value.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Define
Register definition.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< DefNode * > Def
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void initializeTwoAddressInstructionPassPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
CodeGenOptLevel
Code generation optimization level.
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static constexpr LaneBitmask getAll()
constexpr bool none() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.