65#define DEBUG_TYPE "twoaddressinstruction"
67STATISTIC(NumTwoAddressInstrs,
"Number of two-address instructions");
68STATISTIC(NumCommuted ,
"Number of instructions commuted to coalesce");
69STATISTIC(NumAggrCommuted ,
"Number of instructions aggressively commuted");
70STATISTIC(NumConvertedTo3Addr,
"Number of instructions promoted to 3-address");
71STATISTIC(NumReSchedUps,
"Number of instructions re-scheduled up");
72STATISTIC(NumReSchedDowns,
"Number of instructions re-scheduled down");
77 cl::desc(
"Coalesce copies by rescheduling (default=true)"),
84 cl::desc(
"Maximum number of dataflow edges to traverse when evaluating "
85 "the benefit of commuting operands"));
123 bool noUseAfterLastDef(
Register Reg,
unsigned Dist,
unsigned &LastDef);
129 unsigned RegBIdx,
unsigned RegCIdx,
unsigned Dist);
146 unsigned SrcIdx,
unsigned DstIdx,
147 unsigned &Dist,
bool shouldOnlyCommute);
162 void processTiedPairs(
MachineInstr *
MI, TiedPairList&,
unsigned &Dist);
164 bool processStatepoint(
MachineInstr *
MI, TiedOperandMap &TiedOperands);
191char TwoAddressInstructionPass::ID = 0;
196 "Two-Address instruction pass",
false,
false)
208 if (
DefMI.getParent() != BB ||
DefMI.isDebugValue())
212 else if (Ret != &
DefMI)
225bool TwoAddressInstructionPass::isRevCopyChain(
Register FromReg,
Register ToReg,
228 for (
int i = 0; i < Maxlen; i++) {
230 if (!Def || !
Def->isCopy())
233 TmpReg =
Def->getOperand(1).getReg();
245bool TwoAddressInstructionPass::noUseAfterLastDef(
Register Reg,
unsigned Dist,
248 unsigned LastUse = Dist;
251 if (
MI->getParent() !=
MBB ||
MI->isDebugValue())
254 if (DI == DistanceMap.
end())
256 if (MO.isUse() && DI->second < LastUse)
257 LastUse = DI->second;
258 if (MO.isDef() && DI->second > LastDef)
259 LastDef = DI->second;
262 return !(LastUse > LastDef && LastUse < Dist);
274 DstReg =
MI.getOperand(0).getReg();
275 SrcReg =
MI.getOperand(1).getReg();
276 }
else if (
MI.isInsertSubreg() ||
MI.isSubregToReg()) {
277 DstReg =
MI.getOperand(0).getReg();
278 SrcReg =
MI.getOperand(2).getReg();
307 assert(
I != LI.
end() &&
"Reg must be live-in to use.");
311 return MI->killsRegister(Reg);
337 if (Reg.isPhysical() && (allowFalsePositives ||
MRI->hasOneUse(Reg)))
341 if (Reg.isPhysical())
346 if (std::next(Begin) !=
MRI->def_end())
349 bool IsSrcPhys, IsDstPhys;
362 for (
unsigned i = 0, NumOps =
MI.getNumOperands(); i != NumOps; ++i) {
367 if (
MI.isRegTiedToDefOperand(i, &ti)) {
368 DstReg =
MI.getOperand(ti).getReg();
380 bool &IsCopy,
Register &DstReg,
bool &IsDstPhys,
385 if (
MI->getParent() !=
MBB)
405 if (
UseMI.isCommutable()) {
408 if (
TII->findCommutedOpIndices(
UseMI, Src1, Src2)) {
424 while (Reg.isVirtual()) {
426 if (
SI == RegMap.
end())
430 if (Reg.isPhysical())
442 return TRI->regsOverlap(RegA, RegB);
451 "removeMapRegEntry must be called with a register or regmask operand.");
454 for (
auto SI : RegMap) {
461 if (
TRI->regsOverlap(ToReg, Reg))
467 for (
auto SrcReg : Srcs)
468 RegMap.
erase(SrcReg);
479void TwoAddressInstructionPass::removeClobberedSrcRegMap(
MachineInstr *
MI) {
492 if (!Dst || Dst.isVirtual())
501 if (MO.isRegMask()) {
505 if (!MO.isReg() || !MO.isDef())
508 if (!Reg ||
Reg.isVirtual())
517 for (
unsigned R : Set)
518 if (
TRI->regsOverlap(R, Reg))
526bool TwoAddressInstructionPass::isProfitableToCommute(
Register RegA,
576 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
582 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
588 unsigned LastDefC = 0;
589 if (!noUseAfterLastDef(RegC, Dist, LastDefC))
594 unsigned LastDefB = 0;
595 if (!noUseAfterLastDef(RegB, Dist, LastDefB))
621 if (
TII->hasCommutePreference(*
MI, Commute))
626 return LastDefB && LastDefC && LastDefC > LastDefB;
631bool TwoAddressInstructionPass::commuteInstruction(
MachineInstr *
MI,
636 Register RegC =
MI->getOperand(RegCIdx).getReg();
640 if (NewMI ==
nullptr) {
647 "TargetInstrInfo::commuteInstruction() should not return a new "
648 "instruction unless it was requested.");
653 Register RegA =
MI->getOperand(DstIdx).getReg();
654 SrcRegMap[RegA] = FromRegC;
662bool TwoAddressInstructionPass::isProfitableToConv3Addr(
Register RegA,
679bool TwoAddressInstructionPass::convertInstTo3Addr(
691 if (
auto OldInstrNum = mi->peekDebugInstrNum()) {
692 assert(mi->getNumExplicitDefs() == 1);
696 unsigned OldIdx = mi->defs().begin()->getOperandNo();
697 unsigned NewIdx = NewMI->
defs().begin()->getOperandNo();
702 std::make_pair(NewInstrNum, NewIdx));
708 DistanceMap.
insert(std::make_pair(&
MI, Dist++));
714 SrcRegMap.
erase(RegA);
715 DstRegMap.
erase(RegB);
721void TwoAddressInstructionPass::scanUses(
Register DstReg) {
728 NewReg, IsDstPhys, LIS)) {
733 if (DI != DistanceMap.
end())
741 SrcRegMap[NewReg] =
Reg;
746 if (!VirtRegPairs.
empty()) {
747 unsigned ToReg = VirtRegPairs.
back();
749 while (!VirtRegPairs.
empty()) {
751 bool isNew = DstRegMap.
insert(std::make_pair(FromReg, ToReg)).second;
753 assert(DstRegMap[FromReg] == ToReg &&
"Can't map to two dst registers!");
756 bool isNew = DstRegMap.
insert(std::make_pair(DstReg, ToReg)).second;
758 assert(DstRegMap[DstReg] == ToReg &&
"Can't map to two dst registers!");
778 bool IsSrcPhys, IsDstPhys;
783 if (IsDstPhys && !IsSrcPhys) {
784 DstRegMap.
insert(std::make_pair(SrcReg, DstReg));
785 }
else if (!IsDstPhys && IsSrcPhys) {
786 bool isNew = SrcRegMap.
insert(std::make_pair(DstReg, SrcReg)).second;
788 assert(SrcRegMap[DstReg] == SrcReg &&
789 "Can't map to two src physical registers!");
800bool TwoAddressInstructionPass::rescheduleMIBelowKill(
810 if (DI == DistanceMap.
end())
818 "Reg should not have empty live interval.");
822 if (
I != LI.
end() &&
I->start < MBBEndIdx)
843 bool SeenStore =
true;
844 if (!
MI->isSafeToMove(AA, SeenStore))
863 Uses.push_back(MOReg);
864 if (MOReg != Reg && (MO.isKill() ||
874 while (End !=
MBB->
end()) {
877 Defs.
push_back(End->getOperand(0).getReg());
884 unsigned NumVisited = 0;
889 if (OtherMI.isDebugOrPseudoInstr())
894 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
895 OtherMI.isBranch() || OtherMI.isTerminator())
922 if (MOReg == Reg && !isKill)
926 assert((MOReg != Reg || &OtherMI == KillMI) &&
927 "Found multiple kills of a register in a basic block");
933 while (Begin !=
MBB->
begin() && std::prev(Begin)->isDebugInstr())
942 auto CopyMI =
MBBI++;
944 if (!CopyMI->isDebugOrPseudoInstr())
953 DistanceMap.
erase(DI);
969bool TwoAddressInstructionPass::isDefTooClose(
Register Reg,
unsigned Dist,
977 if (DDI == DistanceMap.
end())
979 unsigned DefDist = DDI->second;
980 assert(Dist > DefDist &&
"Visited def already?");
990bool TwoAddressInstructionPass::rescheduleKillAboveMI(
1000 if (DI == DistanceMap.
end())
1008 "Reg should not have empty live interval.");
1012 if (
I != LI.
end() &&
I->start < MBBEndIdx)
1028 bool SeenStore =
true;
1043 if (isDefTooClose(MOReg, DI->second,
MI))
1045 bool isKill = MO.isKill() || (LIS &&
isPlainlyKilled(KillMI, MOReg, LIS));
1046 if (MOReg == Reg && !isKill)
1048 Uses.push_back(MOReg);
1049 if (isKill && MOReg != Reg)
1059 unsigned NumVisited = 0;
1063 if (OtherMI.isDebugOrPseudoInstr())
1065 if (NumVisited > 10)
1068 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1069 OtherMI.isBranch() || OtherMI.isTerminator())
1087 if (&OtherMI !=
MI && MOReg == Reg &&
1096 for (
unsigned i = 0, e = OtherDefs.
size(); i !=
e; ++i) {
1109 while (InsertPos !=
MBB->
begin() && std::prev(InsertPos)->isDebugInstr())
1113 while (std::prev(
From)->isDebugInstr())
1117 nmi = std::prev(InsertPos);
1118 DistanceMap.
erase(DI);
1144bool TwoAddressInstructionPass::tryInstructionCommute(
MachineInstr *
MI,
1149 if (!
MI->isCommutable())
1152 bool MadeChange =
false;
1153 Register DstOpReg =
MI->getOperand(DstOpIdx).getReg();
1154 Register BaseOpReg =
MI->getOperand(BaseOpIdx).getReg();
1155 unsigned OpsNum =
MI->getDesc().getNumOperands();
1156 unsigned OtherOpIdx =
MI->getDesc().getNumDefs();
1157 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1162 if (OtherOpIdx == BaseOpIdx || !
MI->getOperand(OtherOpIdx).isReg() ||
1163 !
TII->findCommutedOpIndices(*
MI, BaseOpIdx, OtherOpIdx))
1166 Register OtherOpReg =
MI->getOperand(OtherOpIdx).getReg();
1167 bool AggressiveCommute =
false;
1172 bool DoCommute = !BaseOpKilled && OtherOpKilled;
1175 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg,
MI, Dist)) {
1177 AggressiveCommute =
true;
1181 if (DoCommute && commuteInstruction(
MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1185 if (AggressiveCommute)
1192 BaseOpReg = OtherOpReg;
1193 BaseOpKilled = OtherOpKilled;
1196 OpsNum =
MI->getDesc().getNumOperands();
1209bool TwoAddressInstructionPass::
1212 unsigned SrcIdx,
unsigned DstIdx,
1213 unsigned &Dist,
bool shouldOnlyCommute) {
1218 Register regA =
MI.getOperand(DstIdx).getReg();
1219 Register regB =
MI.getOperand(SrcIdx).getReg();
1221 assert(regB.
isVirtual() &&
"cannot make instruction into two-address form");
1227 bool Commuted = tryInstructionCommute(&
MI, DstIdx, SrcIdx, regBKilled, Dist);
1237 if (Commuted && !
MI.isConvertibleTo3Addr())
1240 if (shouldOnlyCommute)
1253 regB =
MI.getOperand(SrcIdx).getReg();
1257 if (
MI.isConvertibleTo3Addr()) {
1260 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1262 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1263 ++NumConvertedTo3Addr;
1288 if (
MI.mayLoad() && !regBKilled) {
1290 unsigned LoadRegIndex;
1292 TII->getOpcodeAfterMemoryUnfold(
MI.getOpcode(),
1302 TRI->getAllocatableClass(
1303 TII->getRegClass(UnfoldMCID, LoadRegIndex,
TRI, *MF));
1306 if (!
TII->unfoldMemoryOperand(*MF,
MI, Reg,
1313 "Unfolded a load into multiple instructions!");
1315 NewMIs[1]->addRegisterKilled(Reg,
TRI);
1321 DistanceMap.
insert(std::make_pair(NewMIs[0], Dist++));
1322 DistanceMap.
insert(std::make_pair(NewMIs[1], Dist));
1325 <<
"2addr: NEW INST: " << *NewMIs[1]);
1328 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1329 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1331 bool TransformResult =
1332 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist,
true);
1333 (void)TransformResult;
1334 assert(!TransformResult &&
1335 "tryInstructionTransform() should return false.");
1336 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1341 if (MO.isReg() && MO.getReg().isVirtual()) {
1344 if (NewMIs[0]->killsRegister(MO.getReg()))
1347 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1348 "Kill missing after load unfold!");
1353 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1356 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1357 "Dead flag missing after load unfold!");
1376 MI.eraseFromParent();
1392 NewMIs[0]->eraseFromParent();
1393 NewMIs[1]->eraseFromParent();
1394 DistanceMap.
erase(NewMIs[0]);
1395 DistanceMap.
erase(NewMIs[1]);
1408bool TwoAddressInstructionPass::
1409collectTiedOperands(
MachineInstr *
MI, TiedOperandMap &TiedOperands) {
1410 bool AnyOps =
false;
1411 unsigned NumOps =
MI->getNumOperands();
1413 for (
unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1414 unsigned DstIdx = 0;
1415 if (!
MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1423 if (SrcReg == DstReg)
1426 assert(SrcReg && SrcMO.
isUse() &&
"two address instruction invalid");
1433 MRI->constrainRegClass(DstReg, RC);
1440 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1449 TiedPairList &TiedPairs,
1451 bool IsEarlyClobber =
llvm::any_of(TiedPairs, [
MI](
auto const &TP) {
1452 return MI->getOperand(TP.second).isEarlyClobber();
1455 bool RemovedKillFlag =
false;
1456 bool AllUsesCopied =
true;
1457 unsigned LastCopiedReg = 0;
1460 unsigned SubRegB = 0;
1461 for (
auto &TP : TiedPairs) {
1462 unsigned SrcIdx = TP.first;
1463 unsigned DstIdx = TP.second;
1470 RegB =
MI->getOperand(SrcIdx).getReg();
1471 SubRegB =
MI->getOperand(SrcIdx).getSubReg();
1477 AllUsesCopied =
false;
1480 LastCopiedReg = RegA;
1482 assert(RegB.
isVirtual() &&
"cannot make instruction into two-address form");
1488 for (
unsigned i = 0; i !=
MI->getNumOperands(); ++i)
1490 !
MI->getOperand(i).isReg() ||
1491 MI->getOperand(i).getReg() != RegA);
1496 TII->get(TargetOpcode::COPY), RegA);
1499 MIB.
addReg(RegB, 0, SubRegB);
1503 assert(
TRI->getMatchingSuperRegClass(RC,
MRI->getRegClass(RegA),
1505 "tied subregister must be a truncation");
1509 assert(
TRI->getMatchingSuperReg(RegA, SubRegB,
MRI->getRegClass(RegB))
1510 &&
"tied subregister must be a truncation");
1517 DistanceMap.
insert(std::make_pair(&*PrevMI, Dist));
1518 DistanceMap[
MI] = ++Dist;
1548 "inconsistent operand info for 2-reg pass");
1551 RemovedKillFlag =
true;
1556 MRI->constrainRegClass(RegA, RC);
1564 if (AllUsesCopied) {
1569 if (MO.
getSubReg() == SubRegB && !IsEarlyClobber) {
1572 RemovedKillFlag =
true;
1574 MO.
setReg(LastCopiedReg);
1577 RemainingUses |=
TRI->getSubRegIndexLaneMask(MO.
getSubReg());
1583 if (RemovedKillFlag && RemainingUses.
none() && LV &&
1590 if (RemovedKillFlag && RemainingUses.
none())
1591 SrcRegMap[LastCopiedReg] = RegB;
1600 if ((LaneMask & RemainingUses).any())
1604 S->
end = LastCopyIdx;
1609 bool ShrinkLI =
true;
1611 ShrinkLI &= Shrink(S, S.LaneMask);
1615 }
else if (RemovedKillFlag) {
1636bool TwoAddressInstructionPass::processStatepoint(
1639 bool NeedCopy =
false;
1640 for (
auto &TO : TiedOperands) {
1642 if (TO.second.size() != 1) {
1647 unsigned SrcIdx = TO.second[0].first;
1648 unsigned DstIdx = TO.second[0].second;
1653 assert(RegB ==
MI->getOperand(SrcIdx).getReg());
1666 if (DefLI.overlaps(UseLI)) {
1668 <<
" UseLI overlaps with DefLI\n");
1677 <<
" not killed by statepoint\n");
1682 if (!
MRI->constrainRegClass(RegB,
MRI->getRegClass(RegA))) {
1684 <<
" to register class of " <<
printReg(RegA,
TRI, 0)
1689 MRI->replaceRegWith(RegA, RegB);
1700 for (
auto &S :
Other) {
1709 if (
MI->getOperand(SrcIdx).isKill())
1715 for (
auto *KillMI : DstInfo.
Kills)
1723bool TwoAddressInstructionPass::runOnMachineFunction(
MachineFunction &Func) {
1730 LV = getAnalysisIfAvailable<LiveVariables>();
1731 LIS = getAnalysisIfAvailable<LiveIntervals>();
1732 if (
auto *AAPass = getAnalysisIfAvailable<AAResultsWrapperPass>())
1733 AA = &AAPass->getAAResults();
1736 OptLevel =
TM.getOptLevel();
1739 if (skipFunction(
Func.getFunction()))
1742 bool MadeChange =
false;
1744 LLVM_DEBUG(
dbgs() <<
"********** REWRITING TWO-ADDR INSTRS **********\n");
1752 .
set(MachineFunctionProperties::Property::TiedOpsRewritten);
1754 TiedOperandMap TiedOperands;
1758 DistanceMap.
clear();
1766 if (mi->isDebugInstr()) {
1773 if (mi->isRegSequence())
1774 eliminateRegSequence(mi);
1776 DistanceMap.
insert(std::make_pair(&*mi, ++Dist));
1782 if (!collectTiedOperands(&*mi, TiedOperands)) {
1783 removeClobberedSrcRegMap(&*mi);
1788 ++NumTwoAddressInstrs;
1795 if (TiedOperands.size() == 1) {
1797 = TiedOperands.
begin()->second;
1798 if (TiedPairs.
size() == 1) {
1799 unsigned SrcIdx = TiedPairs[0].first;
1800 unsigned DstIdx = TiedPairs[0].second;
1801 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1802 Register DstReg = mi->getOperand(DstIdx).getReg();
1803 if (SrcReg != DstReg &&
1804 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist,
false)) {
1807 TiedOperands.clear();
1808 removeClobberedSrcRegMap(&*mi);
1815 if (mi->getOpcode() == TargetOpcode::STATEPOINT &&
1816 processStatepoint(&*mi, TiedOperands)) {
1817 TiedOperands.clear();
1824 for (
auto &TO : TiedOperands) {
1825 processTiedPairs(&*mi, TO.second, Dist);
1830 if (mi->isInsertSubreg()) {
1833 unsigned SubIdx = mi->getOperand(3).getImm();
1834 mi->removeOperand(3);
1835 assert(mi->getOperand(0).getSubReg() == 0 &&
"Unexpected subreg idx");
1836 mi->getOperand(0).setSubReg(SubIdx);
1837 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1838 mi->removeOperand(1);
1839 mi->setDesc(
TII->get(TargetOpcode::COPY));
1850 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg());
1853 if ((S.LaneMask & LaneMask).none()) {
1856 S.MergeValueNumberInto(DefSeg->valno, UseSeg->valno);
1873 TiedOperands.
clear();
1874 removeClobberedSrcRegMap(&*mi);
1892void TwoAddressInstructionPass::
1900 for (
unsigned i = 1, e =
MI.getNumOperands(); i < e; i += 2)
1904 bool DefEmitted =
false;
1905 for (
unsigned i = 1, e =
MI.getNumOperands(); i < e; i += 2) {
1908 unsigned SubIdx =
MI.getOperand(i+1).getImm();
1915 bool isKill = UseMO.
isKill();
1917 for (
unsigned j = i + 2;
j <
e;
j += 2)
1918 if (
MI.getOperand(j).getReg() == SrcReg) {
1919 MI.getOperand(j).setIsKill();
1927 TII->get(TargetOpcode::COPY))
1952 MI.setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
1953 for (
int j =
MI.getNumOperands() - 1, ee = 0; j > ee; --j)
1954 MI.removeOperand(j);
1960 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator MBBI
SmallPtrSet< MachineInstr *, 2 > Uses
BlockVerifier::State From
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
std::optional< std::vector< StOtherPiece > > Other
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg)
Return true if the specified MI uses the specified register as a two-address use.
static MCRegister getMappedReg(Register Reg, DenseMap< Register, Register > &RegMap)
Return the physical register the specified virtual register might be mapped to.
Two Address instruction pass
static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, Register &SrcReg, Register &DstReg, bool &IsSrcPhys, bool &IsDstPhys)
Return true if the specified MI is a copy instruction or an extract_subreg instruction.
static MachineInstr * findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, Register &DstReg, bool &IsDstPhys, LiveIntervals *LIS)
Given a register, if all its uses are in the same basic block, return the last use instruction if it'...
static void removeMapRegEntry(const MachineOperand &MO, DenseMap< Register, Register > &RegMap, const TargetRegisterInfo *TRI)
From RegMap remove entries mapped to a physical register which overlaps MO.
static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
static cl::opt< unsigned > MaxDataFlowEdge("dataflow-edge-limit", cl::Hidden, cl::init(3), cl::desc("Maximum number of dataflow edges to traverse when evaluating " "the benefit of commuting operands"))
static bool regsAreCompatible(Register RegA, Register RegB, const TargetRegisterInfo *TRI)
Return true if the two registers are equal or aliased.
Two Address instruction static false bool isPlainlyKilled(MachineInstr *MI, Register Reg, LiveIntervals *LIS)
Test if the given register value, which is used by the given instruction, is killed by the given inst...
static bool regOverlapsSet(const SmallVectorImpl< Register > &Set, Register Reg, const TargetRegisterInfo *TRI)
static bool isKilled(MachineInstr &MI, Register Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives)
Test if the given register value, which is used by the given instruction, is killed by the given inst...
static MachineInstr * getSingleDef(Register Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI)
Return the MachineInstr* if it is the single def of the Reg in current BB.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Allocate memory in an ever growing pool, as if by bump-pointer.
iterator find(const_arg_type_t< KeyT > Val)
bool erase(const KeyT &Val)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
Itinerary data supplied by a subtarget to be used by a target.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
VNInfo::Allocator & getVNInfoAllocator()
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
void removeInterval(Register Reg)
Interval removal.
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
This class represents the liveness of a register, stack slot, etc.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
VNInfo * createValueCopy(const VNInfo *orig, VNInfo::Allocator &VNInfoAllocator)
Create a copy of the given value.
bool hasAtLeastOneValue() const
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI)
removeVirtualRegisterDead - Remove the specified kill of the virtual register from the live variable ...
bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI)
removeVirtualRegisterKilled - Remove the specified kill of the virtual register from the live variabl...
void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterDead - Add information about the fact that the specified register is dead after bei...
void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterKilled - Add information about the fact that the specified register is killed after...
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Describe properties that are true of each instruction in the target description file.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Wrapper class representing physical registers. Should be passed by value.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, unsigned SubReg=0)
Create a substitution between one <instr,operand> value to a different, new value.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineInstrSpan provides an interface to get an iteration range containing the instruction it was in...
Representation of each machine instruction.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool isCall(QueryType Type=AnyInBundle) const
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
iterator_range< mop_iterator > operands()
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
static const unsigned CommuteAnyOperandIndex
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
VNInfo - Value Number Information.
unsigned id
The ID number of this value.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Level
Code generation optimization level.
@ Define
Register definition.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void initializeTwoAddressInstructionPassPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static constexpr LaneBitmask getAll()
constexpr bool none() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.