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MipsISelLowering.h
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1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 
20 #include "Mips.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/IR/Type.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <deque>
36 #include <string>
37 #include <utility>
38 #include <vector>
39 
40 namespace llvm {
41 
42 class Argument;
43 class FastISel;
44 class FunctionLoweringInfo;
45 class MachineBasicBlock;
46 class MachineFrameInfo;
47 class MachineInstr;
48 class MipsCCState;
49 class MipsFunctionInfo;
50 class MipsSubtarget;
51 class MipsTargetMachine;
52 class TargetLibraryInfo;
53 class TargetRegisterClass;
54 
55  namespace MipsISD {
56 
57  enum NodeType : unsigned {
58  // Start the numbering from where ISD NodeType finishes.
60 
61  // Jump and link (call)
63 
64  // Tail call
66 
67  // Get the Highest (63-48) 16 bits from a 64-bit immediate
69 
70  // Get the Higher (47-32) 16 bits from a 64-bit immediate
72 
73  // Get the High 16 bits from a 32/64-bit immediate
74  // No relation with Mips Hi register
75  Hi,
76 
77  // Get the Lower 16 bits from a 32/64-bit immediate
78  // No relation with Mips Lo register
79  Lo,
80 
81  // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
83 
84  // Get the High 16 bits from a 32-bit immediate for accessing TLS.
86 
87  // Handle gp_rel (small data/bss sections) relocation.
89 
90  // Thread Pointer
92 
93  // Vector Floating Point Multiply and Subtract
94  FMS,
95 
96  // Floating Point Branch Conditional
98 
99  // Floating Point Compare
101 
102  // Floating point Abs
104 
105  // Floating point select
107 
108  // Node used to generate an MTC1 i32 to f64 instruction
110 
111  // Floating Point Conditional Moves
114 
115  // FP-to-int truncation node.
117 
118  // Return
120 
121  // Interrupt, exception, error trap Return
123 
124  // Software Exception Return.
126 
127  // Node used to extract integer from accumulator.
130 
131  // Node used to insert integers to accumulator.
133 
134  // Mult nodes.
137 
138  // MAdd/Sub nodes
143 
144  // DivRem(u)
149 
152 
154 
156 
158 
162 
163  // EXTR.W intrinsic nodes.
172 
173  // DPA.W intrinsic nodes.
196 
203 
204  // DSP shift nodes.
208 
209  // DSP setcc and select_cc nodes.
212 
213  // Vector comparisons.
214  // These take a vector and return a boolean.
219 
220  // These take a vector and return a vector bitmask.
226 
227  // Vector Shuffle with mask as an operand
228  VSHF, // Generic shuffle
229  SHF, // 4-element set shuffle.
230  ILVEV, // Interleave even elements
231  ILVOD, // Interleave odd elements
232  ILVL, // Interleave left elements
233  ILVR, // Interleave right elements
234  PCKEV, // Pack even elements
235  PCKOD, // Pack odd elements
236 
237  // Vector Lane Copy
238  INSVE, // Copy element from one vector to another
239 
240  // Combined (XOR (OR $a, $b), -1)
242 
243  // Extended vector element extraction
246 
247  // Load/Store Left/Right nodes.
256  };
257 
258  } // ene namespace MipsISD
259 
260  //===--------------------------------------------------------------------===//
261  // TargetLowering Implementation
262  //===--------------------------------------------------------------------===//
263 
265  bool isMicroMips;
266 
267  public:
268  explicit MipsTargetLowering(const MipsTargetMachine &TM,
269  const MipsSubtarget &STI);
270 
271  static const MipsTargetLowering *create(const MipsTargetMachine &TM,
272  const MipsSubtarget &STI);
273 
274  /// createFastISel - This method returns a target specific FastISel object,
275  /// or null if the target does not support "fast" ISel.
277  const TargetLibraryInfo *libInfo) const override;
278 
279  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
280  return MVT::i32;
281  }
282 
284  ISD::NodeType) const override;
285 
286  bool isCheapToSpeculateCttz() const override;
287  bool isCheapToSpeculateCtlz() const override;
288  bool hasBitTest(SDValue X, SDValue Y) const override;
290  CombineLevel Level) const override;
291 
292  /// Return the register type for a given MVT, ensuring vectors are treated
293  /// as a series of gpr sized integers.
295  EVT VT) const override;
296 
297  /// Return the number of registers for a given MVT, ensuring vectors are
298  /// treated as a series of gpr sized integers.
300  CallingConv::ID CC,
301  EVT VT) const override;
302 
303  /// Break down vectors to the correct number of gpr sized integers.
305  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
306  unsigned &NumIntermediates, MVT &RegisterVT) const override;
307 
308  /// Return the correct alignment for the current calling convention.
310  const DataLayout &DL) const override {
311  const Align ABIAlign = DL.getABITypeAlign(ArgTy);
312  if (ArgTy->isVectorTy())
313  return std::min(ABIAlign, Align(8));
314  return ABIAlign;
315  }
316 
318  return ISD::SIGN_EXTEND;
319  }
320 
321  /// LowerOperation - Provide custom lowering hooks for some operations.
322  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
323 
324  /// ReplaceNodeResults - Replace the results of node with an illegal result
325  /// type with new values built out of custom code.
326  ///
328  SelectionDAG &DAG) const override;
329 
330  /// getTargetNodeName - This method returns the name of a target specific
331  // DAG node.
332  const char *getTargetNodeName(unsigned Opcode) const override;
333 
334  /// getSetCCResultType - get the ISD::SETCC result ValueType
336  EVT VT) const override;
337 
338  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
339 
342  MachineBasicBlock *MBB) const override;
343 
345  SDNode *Node) const override;
346 
347  void HandleByVal(CCState *, unsigned &, Align) const override;
348 
349  Register getRegisterByName(const char* RegName, LLT VT,
350  const MachineFunction &MF) const override;
351 
352  /// If a physical register, this returns the register that receives the
353  /// exception address on entry to an EH pad.
354  Register
355  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
356  return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
357  }
358 
359  /// If a physical register, this returns the register that receives the
360  /// exception typeid on entry to a landing pad.
361  Register
362  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
363  return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
364  }
365 
366  bool isJumpTableRelative() const override {
368  }
369 
370  CCAssignFn *CCAssignFnForCall() const;
371 
373 
374  protected:
375  SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
376 
377  // This method creates the following nodes, which are necessary for
378  // computing a local symbol's address:
379  //
380  // (add (load (wrapper $gp, %got(sym)), %lo(sym))
381  template <class NodeTy>
382  SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
383  bool IsN32OrN64) const {
384  unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
385  SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
386  getTargetNode(N, Ty, DAG, GOTFlag));
387  SDValue Load =
388  DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
390  unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
391  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
392  getTargetNode(N, Ty, DAG, LoFlag));
393  return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
394  }
395 
396  // This method creates the following nodes, which are necessary for
397  // computing a global symbol's address:
398  //
399  // (load (wrapper $gp, %got(sym)))
400  template <class NodeTy>
401  SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
402  unsigned Flag, SDValue Chain,
403  const MachinePointerInfo &PtrInfo) const {
404  SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
405  getTargetNode(N, Ty, DAG, Flag));
406  return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
407  }
408 
409  // This method creates the following nodes, which are necessary for
410  // computing a global symbol's address in large-GOT mode:
411  //
412  // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
413  template <class NodeTy>
414  SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
415  SelectionDAG &DAG, unsigned HiFlag,
416  unsigned LoFlag, SDValue Chain,
417  const MachinePointerInfo &PtrInfo) const {
418  SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
419  getTargetNode(N, Ty, DAG, HiFlag));
420  Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
421  SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
422  getTargetNode(N, Ty, DAG, LoFlag));
423  return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
424  }
425 
426  // This method creates the following nodes, which are necessary for
427  // computing a symbol's address in non-PIC mode:
428  //
429  // (add %hi(sym), %lo(sym))
430  //
431  // This method covers O32, N32 and N64 in sym32 mode.
432  template <class NodeTy>
433  SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
434  SelectionDAG &DAG) const {
435  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
436  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
437  return DAG.getNode(ISD::ADD, DL, Ty,
438  DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
439  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
440  }
441 
442  // This method creates the following nodes, which are necessary for
443  // computing a symbol's address in non-PIC mode for N64.
444  //
445  // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
446  // 16), %lo(%sym))
447  //
448  // FIXME: This method is not efficent for (micro)MIPS64R6.
449  template <class NodeTy>
450  SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
451  SelectionDAG &DAG) const {
452  SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
453  SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
454 
455  SDValue Highest =
456  DAG.getNode(MipsISD::Highest, DL, Ty,
457  getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
458  SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
459  SDValue HigherPart =
460  DAG.getNode(ISD::ADD, DL, Ty, Highest,
461  DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
462  SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
463  SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
464  SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
465  DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
466  SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
467 
468  return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
469  DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
470  }
471 
472  // This method creates the following nodes, which are necessary for
473  // computing a symbol's address using gp-relative addressing:
474  //
475  // (add $gp, %gp_rel(sym))
476  template <class NodeTy>
477  SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
478  SelectionDAG &DAG, bool IsN64) const {
479  SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
480  return DAG.getNode(
481  ISD::ADD, DL, Ty,
482  DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
483  DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
484  }
485 
486  /// This function fills Ops, which is the list of operands that will later
487  /// be used when a function call node is created. It also generates
488  /// copyToReg nodes to set up argument registers.
489  virtual void
491  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
492  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
493  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
494  SDValue Chain) const;
495 
496  protected:
497  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
499 
500  // Subtarget Info
502  // Cache the ABI from the TargetMachine, we use it everywhere.
503  const MipsABIInfo &ABI;
504 
505  private:
506  // Create a TargetGlobalAddress node.
507  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
508  unsigned Flag) const;
509 
510  // Create a TargetExternalSymbol node.
511  SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
512  unsigned Flag) const;
513 
514  // Create a TargetBlockAddress node.
515  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
516  unsigned Flag) const;
517 
518  // Create a TargetJumpTable node.
519  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
520  unsigned Flag) const;
521 
522  // Create a TargetConstantPool node.
523  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
524  unsigned Flag) const;
525 
526  // Lower Operand helpers
527  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
528  CallingConv::ID CallConv, bool isVarArg,
530  const SDLoc &dl, SelectionDAG &DAG,
531  SmallVectorImpl<SDValue> &InVals,
533 
534  // Lower Operand specifics
535  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
537  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
538  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
539  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
540  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
541  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
542  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
543  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
544  SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
545  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
546  SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
547  SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
548  bool HasExtractInsert) const;
549  SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
550  bool HasExtractInsert) const;
551  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
552  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
553  SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
554  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
555  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
556  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
557  bool IsSRA) const;
558  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
559  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
560 
561  /// isEligibleForTailCallOptimization - Check whether the call is eligible
562  /// for tail call optimization.
563  virtual bool
564  isEligibleForTailCallOptimization(const CCState &CCInfo,
565  unsigned NextStackOffset,
566  const MipsFunctionInfo &FI) const = 0;
567 
568  /// copyByValArg - Copy argument registers which were used to pass a byval
569  /// argument to the stack. Create a stack frame object for the byval
570  /// argument.
571  void copyByValRegs(SDValue Chain, const SDLoc &DL,
572  std::vector<SDValue> &OutChains, SelectionDAG &DAG,
573  const ISD::ArgFlagsTy &Flags,
574  SmallVectorImpl<SDValue> &InVals,
575  const Argument *FuncArg, unsigned FirstReg,
576  unsigned LastReg, const CCValAssign &VA,
577  MipsCCState &State) const;
578 
579  /// passByValArg - Pass a byval argument in registers or on stack.
580  void passByValArg(SDValue Chain, const SDLoc &DL,
581  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
582  SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
584  unsigned FirstReg, unsigned LastReg,
585  const ISD::ArgFlagsTy &Flags, bool isLittle,
586  const CCValAssign &VA) const;
587 
588  /// writeVarArgRegs - Write variable function arguments passed in registers
589  /// to the stack. Also create a stack frame object for the first variable
590  /// argument.
591  void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
592  const SDLoc &DL, SelectionDAG &DAG,
593  CCState &State) const;
594 
595  SDValue
596  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
598  const SDLoc &dl, SelectionDAG &DAG,
599  SmallVectorImpl<SDValue> &InVals) const override;
600 
601  SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
602  SDValue Arg, const SDLoc &DL, bool IsTailCall,
603  SelectionDAG &DAG) const;
604 
606  SmallVectorImpl<SDValue> &InVals) const override;
607 
608  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
609  bool isVarArg,
611  LLVMContext &Context) const override;
612 
613  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
615  const SmallVectorImpl<SDValue> &OutVals,
616  const SDLoc &dl, SelectionDAG &DAG) const override;
617 
618  SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
619  const SDLoc &DL, SelectionDAG &DAG) const;
620 
621  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
622 
623  // Inline asm support
624  ConstraintType getConstraintType(StringRef Constraint) const override;
625 
626  /// Examine constraint string and operand type and determine a weight value.
627  /// The operand object must already have been set up with the operand type.
628  ConstraintWeight getSingleConstraintMatchWeight(
629  AsmOperandInfo &info, const char *constraint) const override;
630 
631  /// This function parses registers that appear in inline-asm constraints.
632  /// It returns pair (0, 0) on failure.
633  std::pair<unsigned, const TargetRegisterClass *>
634  parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
635 
636  std::pair<unsigned, const TargetRegisterClass *>
637  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
638  StringRef Constraint, MVT VT) const override;
639 
640  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
641  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
642  /// true it means one of the asm constraint of the inline asm instruction
643  /// being processed is 'm'.
644  void LowerAsmOperandForConstraint(SDValue Op,
645  std::string &Constraint,
646  std::vector<SDValue> &Ops,
647  SelectionDAG &DAG) const override;
648 
649  unsigned
650  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
651  if (ConstraintCode == "o")
653  if (ConstraintCode == "R")
655  if (ConstraintCode == "ZC")
657  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
658  }
659 
660  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
661  Type *Ty, unsigned AS,
662  Instruction *I = nullptr) const override;
663 
664  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
665 
666  EVT getOptimalMemOpType(const MemOp &Op,
667  const AttributeList &FuncAttributes) const override;
668 
669  /// isFPImmLegal - Returns true if the target can instruction select the
670  /// specified FP immediate natively. If false, the legalizer will
671  /// materialize the FP immediate as a load from a constant pool.
672  bool isFPImmLegal(const APFloat &Imm, EVT VT,
673  bool ForCodeSize) const override;
674 
675  unsigned getJumpTableEncoding() const override;
676  bool useSoftFloat() const override;
677 
678  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
679  return true;
680  }
681 
682  /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
683  MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
684  MachineBasicBlock *BB,
685  unsigned Size, unsigned DstReg,
686  unsigned SrcRec) const;
687 
688  MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
689  MachineBasicBlock *BB) const;
690  MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
691  MachineBasicBlock *BB,
692  unsigned Size) const;
693  MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
694  MachineBasicBlock *BB) const;
695  MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
696  MachineBasicBlock *BB,
697  unsigned Size) const;
698  MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
699  MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
700  bool isFPCmp, unsigned Opc) const;
701  MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
702  MachineBasicBlock *BB) const;
703  MachineBasicBlock *emitLDR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
704  MachineBasicBlock *emitLDR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
705  MachineBasicBlock *emitSTR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
706  MachineBasicBlock *emitSTR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
707  };
708 
709  /// Create MipsTargetLowering objects.
710  const MipsTargetLowering *
711  createMips16TargetLowering(const MipsTargetMachine &TM,
712  const MipsSubtarget &STI);
713  const MipsTargetLowering *
714  createMipsSETargetLowering(const MipsTargetMachine &TM,
715  const MipsSubtarget &STI);
716 
717 namespace Mips {
718 
719 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
720  const TargetLibraryInfo *libInfo);
721 
722 } // end namespace Mips
723 
724 } // end namespace llvm
725 
726 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::MipsTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: MipsISelLowering.cpp:99
llvm::MipsABIInfo::IsN64
bool IsN64() const
Definition: MipsABIInfo.h:42
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm::MipsISD::EH_RETURN
@ EH_RETURN
Definition: MipsISelLowering.h:125
MipsBaseInfo.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MipsISD::VEXTRACT_SEXT_ELT
@ VEXTRACT_SEXT_ELT
Definition: MipsISelLowering.h:244
llvm::MipsISD::JmpLink
@ JmpLink
Definition: MipsISelLowering.h:62
llvm::MipsISD::DPSU_H_QBL
@ DPSU_H_QBL
Definition: MipsISelLowering.h:181
llvm::MipsISD::VALL_ZERO
@ VALL_ZERO
Definition: MipsISelLowering.h:215
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4407
llvm::MipsTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: MipsISelLowering.h:362
llvm::MipsTargetLowering::HandleByVal
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
Definition: MipsISelLowering.cpp:4536
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::MipsISD::VCLT_U
@ VCLT_U
Definition: MipsISelLowering.h:225
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
llvm::MipsISD::NodeType
NodeType
Definition: MipsISelLowering.h:57
llvm::MipsTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: MipsISelLowering.cpp:109
llvm::Mips::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: MipsFastISel.cpp:2143
llvm::MipsTargetLowering::getAddrGlobalLargeGOT
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
Definition: MipsISelLowering.h:414
llvm::MipsISD::FPBrcond
@ FPBrcond
Definition: MipsISelLowering.h:97
llvm::MipsISD::LDL
@ LDL
Definition: MipsISelLowering.h:252
Wrapper
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
Definition: AMDGPUAliasAnalysis.cpp:31
InlineAsm.h
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9108
llvm::MipsISD::PCKEV
@ PCKEV
Definition: MipsISelLowering.h:234
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::MipsISD::VANY_NONZERO
@ VANY_NONZERO
Definition: MipsISelLowering.h:218
llvm::MipsISD::ILVR
@ ILVR
Definition: MipsISelLowering.h:233
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::MemOp
Definition: TargetLowering.h:111
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::MipsISD::MULTU
@ MULTU
Definition: MipsISelLowering.h:198
Shift
bool Shift
Definition: README.txt:468
llvm::MipsISD::ExtractElementF64
@ ExtractElementF64
Definition: MipsISelLowering.h:151
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AttributeList
Definition: Attributes.h:425
llvm::MipsTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: MipsISelLowering.cpp:1175
llvm::MipsTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: MipsISelLowering.cpp:1145
llvm::MipsISD::SDL
@ SDL
Definition: MipsISelLowering.h:254
llvm::MipsTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: MipsISelLowering.h:355
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::MipsISD::Multu
@ Multu
Definition: MipsISelLowering.h:136
llvm::MipsTargetLowering::MipsTargetLowering
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: MipsISelLowering.cpp:287
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::MipsISD::LWR
@ LWR
Definition: MipsISelLowering.h:249
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2165
llvm::MipsISD::MFHI
@ MFHI
Definition: MipsISelLowering.h:128
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1622
llvm::MipsTargetLowering::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
Definition: MipsISelLowering.cpp:521
llvm::MipsISD::MAQ_SA_W_PHL
@ MAQ_SA_W_PHL
Definition: MipsISelLowering.h:177
llvm::MipsISD::MFLO
@ MFLO
Definition: MipsISelLowering.h:129
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
llvm::MipsTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: MipsISelLowering.cpp:1285
llvm::MipsTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: MipsISelLowering.h:317
llvm::MipsISD::MAdd
@ MAdd
Definition: MipsISelLowering.h:139
llvm::MipsTargetLowering::getAddrGlobal
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
Definition: MipsISelLowering.h:401
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2061
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
MachineValueType.h
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::InlineAsm::Constraint_o
@ Constraint_o
Definition: InlineAsm.h:256
llvm::MipsTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
Definition: MipsISelLowering.cpp:1201
llvm::MipsTargetLowering::lowerSTORE
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition: MipsISelLowering.cpp:2799
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
TargetLowering.h
llvm::MipsISD::EXTR_RS_W
@ EXTR_RS_W
Definition: MipsISelLowering.h:169
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7754
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2207
llvm::MipsII::MO_GOT_OFST
@ MO_GOT_OFST
Definition: MipsBaseInfo.h:81
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
TargetMachine.h
llvm::MipsISD::DPSU_H_QBR
@ DPSU_H_QBR
Definition: MipsISelLowering.h:182
llvm::MipsISD::MTHLIP
@ MTHLIP
Definition: MipsISelLowering.h:171
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
SelectionDAGNodes.h
llvm::MipsISD::MULT
@ MULT
Definition: MipsISelLowering.h:197
llvm::MipsTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: MipsISelLowering.cpp:4738
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MipsISD::MADD_DSP
@ MADD_DSP
Definition: MipsISelLowering.h:199
llvm::MipsISD::VEXTRACT_ZEXT_ELT
@ VEXTRACT_ZEXT_ELT
Definition: MipsISelLowering.h:245
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1449
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1837
llvm::MipsTargetLowering::getAddrGPRel
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
Definition: MipsISelLowering.h:477
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3400
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::MipsTargetLowering::getOpndList
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
Definition: MipsISelLowering.cpp:3032
llvm::MipsISD::VCLE_S
@ VCLE_S
Definition: MipsISelLowering.h:222
Mips.h
llvm::MipsISD::MADDU_DSP
@ MADDU_DSP
Definition: MipsISelLowering.h:200
llvm::MipsISD::CMovFP_T
@ CMovFP_T
Definition: MipsISelLowering.h:112
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1015
llvm::MipsII::MO_HIGHEST
@ MO_HIGHEST
Definition: MipsBaseInfo.h:86
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::MipsISD::DPAU_H_QBR
@ DPAU_H_QBR
Definition: MipsISelLowering.h:180
llvm::MipsISD::LWL
@ LWL
Definition: MipsISelLowering.h:248
llvm::Instruction
Definition: Instruction.h:42
llvm::MipsISD::Highest
@ Highest
Definition: MipsISelLowering.h:68
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MipsISD::DPAX_W_PH
@ DPAX_W_PH
Definition: MipsISelLowering.h:191
llvm::MipsISD::FAbs
@ FAbs
Definition: MipsISelLowering.h:103
llvm::MipsISD::DivRem
@ DivRem
Definition: MipsISelLowering.h:145
llvm::MipsISD::DynAlloc
@ DynAlloc
Definition: MipsISelLowering.h:155
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MipsII::MO_ABS_LO
@ MO_ABS_LO
Definition: MipsBaseInfo.h:53
llvm::MipsISD::ThreadPointer
@ ThreadPointer
Definition: MipsISelLowering.h:91
llvm::MipsISD::MTLOHI
@ MTLOHI
Definition: MipsISelLowering.h:132
llvm::MipsISD::MSUBU_DSP
@ MSUBU_DSP
Definition: MipsISelLowering.h:202
llvm::MipsTargetLowering::getAddrNonPIC
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
Definition: MipsISelLowering.h:433
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MipsISD::FSELECT
@ FSELECT
Definition: MipsISelLowering.h:106
Type.h
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MipsTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: MipsISelLowering.h:279
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::MipsISD::SHLL_DSP
@ SHLL_DSP
Definition: MipsISelLowering.h:205
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::MipsISD::PCKOD
@ PCKOD
Definition: MipsISelLowering.h:235
llvm::APFloat
Definition: APFloat.h:701
llvm::MipsISD::MSub
@ MSub
Definition: MipsISelLowering.h:141
llvm::MipsISD::Ext
@ Ext
Definition: MipsISelLowering.h:159
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::InlineAsm::Constraint_ZC
@ Constraint_ZC
Definition: InlineAsm.h:272
llvm::MipsTargetLowering::shouldFoldConstantShiftPairToMask
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Definition: MipsISelLowering.cpp:1193
llvm::MipsISD::ILVL
@ ILVL
Definition: MipsISelLowering.h:232
llvm::MipsISD::CIns
@ CIns
Definition: MipsISelLowering.h:161
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Definition: MipsISelLowering.cpp:117
llvm::MipsTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Definition: MipsISelLowering.cpp:1208
llvm::MipsTargetLowering::lowerLOAD
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Definition: MipsISelLowering.cpp:2673
llvm::MipsTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: MipsISelLowering.cpp:1179
llvm::MipsTargetLowering::CCAssignFnForCall
CCAssignFn * CCAssignFnForCall() const
Definition: MipsISelLowering.cpp:3002
llvm::MipsTargetLowering::getAddrNonPICSym64
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
Definition: MipsISelLowering.h:450
llvm::MipsTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
Definition: MipsISelLowering.cpp:540
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MipsISD::VALL_NONZERO
@ VALL_NONZERO
Definition: MipsISelLowering.h:217
llvm::MipsTargetLowering::getTypeForExtReturn
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Definition: MipsISelLowering.cpp:4034
llvm::MipsISD::DPSX_W_PH
@ DPSX_W_PH
Definition: MipsISelLowering.h:192
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8838
llvm::MipsISD::MAQ_S_W_PHL
@ MAQ_S_W_PHL
Definition: MipsISelLowering.h:175
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4434
llvm::MipsISD::DPSQ_SA_L_W
@ DPSQ_SA_L_W
Definition: MipsISelLowering.h:186
llvm::MipsISD::VSHF
@ VSHF
Definition: MipsISelLowering.h:228
llvm::InlineAsm::Constraint_R
@ Constraint_R
Definition: InlineAsm.h:260
llvm::createMipsSETargetLowering
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: MipsSEISelLowering.cpp:296
llvm::MipsISD::ILVOD
@ ILVOD
Definition: MipsISelLowering.h:231
llvm::MipsISD::MAQ_SA_W_PHR
@ MAQ_SA_W_PHR
Definition: MipsISelLowering.h:178
llvm::MipsISD::SWR
@ SWR
Definition: MipsISelLowering.h:251
llvm::MipsISD::DivRem16
@ DivRem16
Definition: MipsISelLowering.h:147
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3997
llvm::MipsTargetLowering::isJumpTableRelative
bool isJumpTableRelative() const override
Definition: MipsISelLowering.h:366
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MipsISD::VCLE_U
@ VCLE_U
Definition: MipsISelLowering.h:223
MipsMCTargetDesc.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MipsISD::Sync
@ Sync
Definition: MipsISelLowering.h:157
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::MipsISD::SHRL_DSP
@ SHRL_DSP
Definition: MipsISelLowering.h:207
llvm::MipsTargetLowering::getAddrLocal
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
Definition: MipsISelLowering.h:382
info
lazy value info
Definition: LazyValueInfo.cpp:58
llvm::MipsISD::ILVEV
@ ILVEV
Definition: MipsISelLowering.h:230
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MipsISD::DPAQX_S_W_PH
@ DPAQX_S_W_PH
Definition: MipsISelLowering.h:189
llvm::MipsISD::SHRA_DSP
@ SHRA_DSP
Definition: MipsISelLowering.h:206
llvm::MipsISD::DPSQX_S_W_PH
@ DPSQX_S_W_PH
Definition: MipsISelLowering.h:193
llvm::MipsISD::INSVE
@ INSVE
Definition: MipsISelLowering.h:238
llvm::MipsII::MO_GOT
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
llvm::MipsISD::EXTP
@ EXTP
Definition: MipsISelLowering.h:164
llvm::MipsISD::EXTR_W
@ EXTR_W
Definition: MipsISelLowering.h:167
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1858
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MipsISD::GPRel
@ GPRel
Definition: MipsISelLowering.h:88
llvm::MipsTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: MipsISelLowering.cpp:3089
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::MipsISD::SETCC_DSP
@ SETCC_DSP
Definition: MipsISelLowering.h:210
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::MipsISD::MULSAQ_S_W_PH
@ MULSAQ_S_W_PH
Definition: MipsISelLowering.h:174
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1294
llvm::MipsISD::SELECT_CC_DSP
@ SELECT_CC_DSP
Definition: MipsISelLowering.h:211
Node
Definition: ItaniumDemangle.h:155
llvm::MipsTargetLowering::hasBitTest
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Definition: MipsISelLowering.cpp:1183
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::MipsISD::TailCall
@ TailCall
Definition: MipsISelLowering.h:65
llvm::MipsTargetLowering
Definition: MipsISelLowering.h:264
llvm::MipsISD::CMovFP_F
@ CMovFP_F
Definition: MipsISelLowering.h:113
llvm::MipsISD::SWL
@ SWL
Definition: MipsISelLowering.h:250
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MipsISD::MAQ_S_W_PHR
@ MAQ_S_W_PHR
Definition: MipsISelLowering.h:176
llvm::MipsISD::VCEQ
@ VCEQ
Definition: MipsISelLowering.h:221
llvm::MipsTargetLowering::create
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Definition: MipsISelLowering.cpp:511
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:347
llvm::MipsISD::GotHi
@ GotHi
Definition: MipsISelLowering.h:82
llvm::MipsISD::VNOR
@ VNOR
Definition: MipsISelLowering.h:241
llvm::MipsISD::Wrapper
@ Wrapper
Definition: MipsISelLowering.h:153
llvm::MipsISD::Mult
@ Mult
Definition: MipsISelLowering.h:135
llvm::MipsTargetLowering::Subtarget
const MipsSubtarget & Subtarget
Definition: MipsISelLowering.h:501
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::MipsISD::DPSQX_SA_W_PH
@ DPSQX_SA_W_PH
Definition: MipsISelLowering.h:194
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:531
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4417
MipsABIInfo.h
llvm::MipsISD::DPAQX_SA_W_PH
@ DPAQX_SA_W_PH
Definition: MipsISelLowering.h:190
ISDOpcodes.h
llvm::MipsISD::MTC1_D64
@ MTC1_D64
Definition: MipsISelLowering.h:109
llvm::MipsISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: MipsISelLowering.h:59
llvm::MipsISD::LDR
@ LDR
Definition: MipsISelLowering.h:253
llvm::MipsISD::EXTR_R_W
@ EXTR_R_W
Definition: MipsISelLowering.h:168
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::MipsISD::DivRemU
@ DivRemU
Definition: MipsISelLowering.h:146
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:222
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::MipsISD::SDR
@ SDR
Definition: MipsISelLowering.h:255
llvm::MipsISD::EXTR_S_H
@ EXTR_S_H
Definition: MipsISelLowering.h:166
llvm::MipsISD::BuildPairF64
@ BuildPairF64
Definition: MipsISelLowering.h:150
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::MipsISD::DPS_W_PH
@ DPS_W_PH
Definition: MipsISelLowering.h:188
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::MipsISD::SHILO
@ SHILO
Definition: MipsISelLowering.h:170
llvm::createMips16TargetLowering
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
Definition: Mips16ISelLowering.cpp:153
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::MipsISD::EXTPDP
@ EXTPDP
Definition: MipsISelLowering.h:165
llvm::MipsII::MO_ABS_HI
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
llvm::MipsISD::MSubu
@ MSubu
Definition: MipsISelLowering.h:142
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::MipsISD::DPA_W_PH
@ DPA_W_PH
Definition: MipsISelLowering.h:187
llvm::MipsISD::DPSQ_S_W_PH
@ DPSQ_S_W_PH
Definition: MipsISelLowering.h:184
llvm::MipsISD::Higher
@ Higher
Definition: MipsISelLowering.h:71
llvm::MipsISD::DPAU_H_QBL
@ DPAU_H_QBL
Definition: MipsISelLowering.h:179
llvm::MipsII::MO_GPREL
@ MO_GPREL
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1306
llvm::MipsTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
Definition: MipsISelLowering.cpp:167
llvm::MipsISD::DPAQ_SA_L_W
@ DPAQ_SA_L_W
Definition: MipsISelLowering.h:185
N
#define N
llvm::MipsISD::MULSA_W_PH
@ MULSA_W_PH
Definition: MipsISelLowering.h:195
llvm::MipsISD::VCLT_S
@ VCLT_S
Definition: MipsISelLowering.h:224
llvm::MipsISD::DPAQ_S_W_PH
@ DPAQ_S_W_PH
Definition: MipsISelLowering.h:183
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4509
llvm::MipsISD::FPCmp
@ FPCmp
Definition: MipsISelLowering.h:100
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
RegName
#define RegName(no)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:449
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MipsCCState
Definition: MipsCCState.h:20
llvm::MipsISD::MAddu
@ MAddu
Definition: MipsISelLowering.h:140
llvm::MipsISD::MSUB_DSP
@ MSUB_DSP
Definition: MipsISelLowering.h:201
llvm::MipsII::MO_HIGHER
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
Definition: MipsBaseInfo.h:85
llvm::MipsTargetLowering::getGlobalReg
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
Definition: MipsISelLowering.cpp:130
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::MipsTargetLowering::getABIAlignmentForCallingConv
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
Definition: MipsISelLowering.h:309
llvm::MipsISD::TlsHi
@ TlsHi
Definition: MipsISelLowering.h:85
llvm::MipsISD::SHF
@ SHF
Definition: MipsISelLowering.h:229
llvm::MipsISD::FMS
@ FMS
Definition: MipsISelLowering.h:94
llvm::MipsII::MO_GOT_PAGE
@ MO_GOT_PAGE
Definition: MipsBaseInfo.h:80
llvm::MipsISD::DivRemU16
@ DivRemU16
Definition: MipsISelLowering.h:148
llvm::MipsISD::ERet
@ ERet
Definition: MipsISelLowering.h:122
llvm::MipsTargetLowering::CCAssignFnForReturn
CCAssignFn * CCAssignFnForReturn() const
Definition: MipsISelLowering.cpp:3006
llvm::MipsTargetLowering::ABI
const MipsABIInfo & ABI
Definition: MipsISelLowering.h:503
llvm::MipsISD::TruncIntFP
@ TruncIntFP
Definition: MipsISelLowering.h:116
llvm::MipsISD::VANY_ZERO
@ VANY_ZERO
Definition: MipsISelLowering.h:216
llvm::LLT
Definition: LowLevelTypeImpl.h:39