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14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
44 class FunctionLoweringInfo;
45 class MachineBasicBlock;
46 class MachineFrameInfo;
49 class MipsFunctionInfo;
51 class MipsTargetMachine;
52 class TargetLibraryInfo;
53 class TargetRegisterClass;
295 EVT VT)
const override;
301 EVT VT)
const override;
306 unsigned &NumIntermediates,
MVT &RegisterVT)
const override;
311 const Align ABIAlign =
DL.getABITypeAlign(ArgTy);
336 EVT VT)
const override;
356 return ABI.
IsN64() ? Mips::A0_64 : Mips::A0;
363 return ABI.
IsN64() ? Mips::A1_64 : Mips::A1;
381 template <
class NodeTy>
383 bool IsN32OrN64)
const {
386 getTargetNode(
N, Ty, DAG, GOTFlag));
392 getTargetNode(
N, Ty, DAG, LoFlag));
400 template <
class NodeTy>
405 getTargetNode(
N, Ty, DAG,
Flag));
406 return DAG.
getLoad(Ty,
DL, Chain, Tgt, PtrInfo);
413 template <
class NodeTy>
416 unsigned LoFlag,
SDValue Chain,
419 getTargetNode(
N, Ty, DAG, HiFlag));
422 getTargetNode(
N, Ty, DAG, LoFlag));
432 template <
class NodeTy>
449 template <
class NodeTy>
476 template <
class NodeTy>
482 DAG.
getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
491 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
492 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
493 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
508 unsigned Flag)
const;
512 unsigned Flag)
const;
516 unsigned Flag)
const;
520 unsigned Flag)
const;
524 unsigned Flag)
const;
548 bool HasExtractInsert)
const;
550 bool HasExtractInsert)
const;
564 isEligibleForTailCallOptimization(
const CCState &CCInfo,
565 unsigned NextStackOffset,
575 const Argument *FuncArg,
unsigned FirstReg,
581 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
584 unsigned FirstReg,
unsigned LastReg,
591 void writeVarArgRegs(std::vector<SDValue> &OutChains,
SDValue Chain,
621 bool shouldSignExtendTypeInLibCall(
EVT Type,
bool IsSigned)
const override;
633 std::pair<unsigned, const TargetRegisterClass *>
636 std::pair<unsigned, const TargetRegisterClass *>
644 void LowerAsmOperandForConstraint(
SDValue Op,
645 std::string &Constraint,
646 std::vector<SDValue> &Ops,
650 getInlineAsmMemConstraint(
StringRef ConstraintCode)
const override {
651 if (ConstraintCode ==
"o")
653 if (ConstraintCode ==
"R")
655 if (ConstraintCode ==
"ZC")
661 Type *Ty,
unsigned AS,
673 bool ForCodeSize)
const override;
675 unsigned getJumpTableEncoding()
const override;
676 bool useSoftFloat()
const override;
678 bool shouldInsertFencesForAtomic(
const Instruction *
I)
const override {
683 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &
MI,
684 MachineBasicBlock *
BB,
685 unsigned Size,
unsigned DstReg,
686 unsigned SrcRec)
const;
688 MachineBasicBlock *emitAtomicBinary(MachineInstr &
MI,
689 MachineBasicBlock *
BB)
const;
690 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &
MI,
691 MachineBasicBlock *
BB,
692 unsigned Size)
const;
693 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &
MI,
694 MachineBasicBlock *
BB)
const;
695 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &
MI,
696 MachineBasicBlock *
BB,
697 unsigned Size)
const;
698 MachineBasicBlock *emitSEL_D(MachineInstr &
MI, MachineBasicBlock *
BB)
const;
699 MachineBasicBlock *emitPseudoSELECT(MachineInstr &
MI, MachineBasicBlock *
BB,
700 bool isFPCmp,
unsigned Opc)
const;
701 MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &
MI,
702 MachineBasicBlock *
BB)
const;
703 MachineBasicBlock *emitLDR_W(MachineInstr &
MI, MachineBasicBlock *
BB)
const;
704 MachineBasicBlock *emitLDR_D(MachineInstr &
MI, MachineBasicBlock *
BB)
const;
705 MachineBasicBlock *emitSTR_W(MachineInstr &
MI, MachineBasicBlock *
BB)
const;
706 MachineBasicBlock *emitSTR_D(MachineInstr &
MI, MachineBasicBlock *
BB)
const;
710 const MipsTargetLowering *
712 const MipsSubtarget &STI);
713 const MipsTargetLowering *
715 const MipsSubtarget &STI);
720 const TargetLibraryInfo *libInfo);
726 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
This class represents an incoming formal argument to a Function.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
This is an optimization pass for GlobalISel generic memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Function Alias Analysis Results
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
unsigned const TargetRegisterInfo * TRI
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue getRegister(unsigned Reg, EVT VT)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
CCValAssign - Represent assignment of one arg/retval to a location.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
(vector float) vec_cmpeq(*A, *B) C
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue >> &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
bool isVectorTy() const
True if this is an instance of VectorType.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
This struct is a compact representation of a valid (non-zero power of two) alignment.
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
bool isPositionIndependent() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
This is an important base class in LLVM.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
Representation of each machine instruction.
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
CCAssignFn * CCAssignFnForCall() const
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
This contains information for each constraint that we are lowering.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
This structure contains all information that is necessary for lowering calls.
bool isJumpTableRelative() const override
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
StringRef - Represent a constant reference to a string, i.e.
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Wrapper class representing virtual and physical registers.
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
const TargetMachine & getTargetMachine() const
const MipsSubtarget & Subtarget
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Provides information about what library functions are available for the current target.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
@ ADD
Simple integer binary arithmetic operators.
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
@ SHL
Shift and rotation operations.
@ MO_GPREL
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const char LLVMTargetMachineRef TM
MachineFunction & getMachineFunction() const
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
@ SIGN_EXTEND
Conversion operators.
Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override
Return the correct alignment for the current calling convention.
CCAssignFn * CCAssignFnForReturn() const