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MipsFastISel.cpp
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1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the MIPS-specific support for the FastISel class.
11 /// Some of the target-specific code is generated by tablegen in the file
12 /// MipsGenFastISel.inc, which is #included here.
13 ///
14 //===----------------------------------------------------------------------===//
15 
18 #include "MipsCCState.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMachineFunction.h"
22 #include "MipsSubtarget.h"
23 #include "MipsTargetMachine.h"
24 #include "llvm/ADT/APInt.h"
25 #include "llvm/ADT/ArrayRef.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/CodeGen/FastISel.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/CallingConv.h"
43 #include "llvm/IR/Constant.h"
44 #include "llvm/IR/Constants.h"
45 #include "llvm/IR/DataLayout.h"
46 #include "llvm/IR/Function.h"
48 #include "llvm/IR/GlobalValue.h"
49 #include "llvm/IR/GlobalVariable.h"
50 #include "llvm/IR/InstrTypes.h"
51 #include "llvm/IR/Instruction.h"
52 #include "llvm/IR/Instructions.h"
53 #include "llvm/IR/IntrinsicInst.h"
54 #include "llvm/IR/Operator.h"
55 #include "llvm/IR/Type.h"
56 #include "llvm/IR/User.h"
57 #include "llvm/IR/Value.h"
58 #include "llvm/MC/MCContext.h"
59 #include "llvm/MC/MCInstrDesc.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/MC/MCSymbol.h"
62 #include "llvm/Support/Casting.h"
63 #include "llvm/Support/Compiler.h"
64 #include "llvm/Support/Debug.h"
69 #include <algorithm>
70 #include <array>
71 #include <cassert>
72 #include <cstdint>
73 
74 #define DEBUG_TYPE "mips-fastisel"
75 
76 using namespace llvm;
77 
79 
80 namespace {
81 
82 class MipsFastISel final : public FastISel {
83 
84  // All possible address modes.
85  class Address {
86  public:
87  using BaseKind = enum { RegBase, FrameIndexBase };
88 
89  private:
90  BaseKind Kind = RegBase;
91  union {
92  unsigned Reg;
93  int FI;
94  } Base;
95 
96  int64_t Offset = 0;
97 
98  const GlobalValue *GV = nullptr;
99 
100  public:
101  // Innocuous defaults for our address.
102  Address() { Base.Reg = 0; }
103 
104  void setKind(BaseKind K) { Kind = K; }
105  BaseKind getKind() const { return Kind; }
106  bool isRegBase() const { return Kind == RegBase; }
107  bool isFIBase() const { return Kind == FrameIndexBase; }
108 
109  void setReg(unsigned Reg) {
110  assert(isRegBase() && "Invalid base register access!");
111  Base.Reg = Reg;
112  }
113 
114  unsigned getReg() const {
115  assert(isRegBase() && "Invalid base register access!");
116  return Base.Reg;
117  }
118 
119  void setFI(unsigned FI) {
120  assert(isFIBase() && "Invalid base frame index access!");
121  Base.FI = FI;
122  }
123 
124  unsigned getFI() const {
125  assert(isFIBase() && "Invalid base frame index access!");
126  return Base.FI;
127  }
128 
129  void setOffset(int64_t Offset_) { Offset = Offset_; }
130  int64_t getOffset() const { return Offset; }
131  void setGlobalValue(const GlobalValue *G) { GV = G; }
132  const GlobalValue *getGlobalValue() { return GV; }
133  };
134 
135  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
136  /// make the right decision when generating code for different targets.
137  const TargetMachine &TM;
138  const MipsSubtarget *Subtarget;
139  const TargetInstrInfo &TII;
140  const TargetLowering &TLI;
141  MipsFunctionInfo *MFI;
142 
143  // Convenience variables to avoid some queries.
145 
146  bool fastLowerArguments() override;
147  bool fastLowerCall(CallLoweringInfo &CLI) override;
148  bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
149 
150  bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
151  // floating point but not reject doing fast-isel in other
152  // situations
153 
154 private:
155  // Selection routines.
156  bool selectLogicalOp(const Instruction *I);
157  bool selectLoad(const Instruction *I);
158  bool selectStore(const Instruction *I);
159  bool selectBranch(const Instruction *I);
160  bool selectSelect(const Instruction *I);
161  bool selectCmp(const Instruction *I);
162  bool selectFPExt(const Instruction *I);
163  bool selectFPTrunc(const Instruction *I);
164  bool selectFPToInt(const Instruction *I, bool IsSigned);
165  bool selectRet(const Instruction *I);
166  bool selectTrunc(const Instruction *I);
167  bool selectIntExt(const Instruction *I);
168  bool selectShift(const Instruction *I);
169  bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
170 
171  // Utility helper routines.
172  bool isTypeLegal(Type *Ty, MVT &VT);
173  bool isTypeSupported(Type *Ty, MVT &VT);
174  bool isLoadTypeLegal(Type *Ty, MVT &VT);
175  bool computeAddress(const Value *Obj, Address &Addr);
176  bool computeCallAddress(const Value *V, Address &Addr);
177  void simplifyAddress(Address &Addr);
178 
179  // Emit helper routines.
180  bool emitCmp(unsigned DestReg, const CmpInst *CI);
181  bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
182  unsigned Alignment = 0);
183  bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
184  MachineMemOperand *MMO = nullptr);
185  bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
186  unsigned Alignment = 0);
187  unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188  bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
189 
190  bool IsZExt);
191  bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
192 
193  bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194  bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
195  unsigned DestReg);
196  bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
197  unsigned DestReg);
198 
199  unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
200 
201  unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
202  const Value *RHS);
203 
204  unsigned materializeFP(const ConstantFP *CFP, MVT VT);
205  unsigned materializeGV(const GlobalValue *GV, MVT VT);
206  unsigned materializeInt(const Constant *C, MVT VT);
207  unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
208  unsigned materializeExternalCallSym(MCSymbol *Syn);
209 
210  MachineInstrBuilder emitInst(unsigned Opc) {
211  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
212  }
213 
214  MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
215  return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
216  DstReg);
217  }
218 
219  MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
220  unsigned MemReg, int64_t MemOffset) {
221  return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
222  }
223 
224  MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
225  unsigned MemReg, int64_t MemOffset) {
226  return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
227  }
228 
229  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
230  const TargetRegisterClass *RC,
231  unsigned Op0, bool Op0IsKill,
232  unsigned Op1, bool Op1IsKill);
233 
234  // for some reason, this default is not generated by tablegen
235  // so we explicitly generate it here.
236  unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
237  unsigned Op0, bool Op0IsKill, uint64_t imm1,
238  uint64_t imm2, unsigned Op3, bool Op3IsKill) {
239  return 0;
240  }
241 
242  // Call handling routines.
243 private:
244  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
245  bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
246  unsigned &NumBytes);
247  bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
248 
249  const MipsABIInfo &getABI() const {
250  return static_cast<const MipsTargetMachine &>(TM).getABI();
251  }
252 
253 public:
254  // Backend specific FastISel code.
255  explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
256  const TargetLibraryInfo *libInfo)
257  : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
258  Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
259  TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
260  MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
261  Context = &funcInfo.Fn->getContext();
262  UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
263  }
264 
265  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
266  unsigned fastMaterializeConstant(const Constant *C) override;
267  bool fastSelectInstruction(const Instruction *I) override;
268 
269 #include "MipsGenFastISel.inc"
270 };
271 
272 } // end anonymous namespace
273 
274 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
275  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
277 
278 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
279  CCValAssign::LocInfo LocInfo,
280  ISD::ArgFlagsTy ArgFlags, CCState &State) {
281  llvm_unreachable("should not be called");
282 }
283 
284 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
285  CCValAssign::LocInfo LocInfo,
286  ISD::ArgFlagsTy ArgFlags, CCState &State) {
287  llvm_unreachable("should not be called");
288 }
289 
290 #include "MipsGenCallingConv.inc"
291 
292 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
293  return CC_MipsO32;
294 }
295 
296 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
297  const Value *LHS, const Value *RHS) {
298  // Canonicalize immediates to the RHS first.
299  if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
300  std::swap(LHS, RHS);
301 
302  unsigned Opc;
303  switch (ISDOpc) {
304  case ISD::AND:
305  Opc = Mips::AND;
306  break;
307  case ISD::OR:
308  Opc = Mips::OR;
309  break;
310  case ISD::XOR:
311  Opc = Mips::XOR;
312  break;
313  default:
314  llvm_unreachable("unexpected opcode");
315  }
316 
317  unsigned LHSReg = getRegForValue(LHS);
318  if (!LHSReg)
319  return 0;
320 
321  unsigned RHSReg;
322  if (const auto *C = dyn_cast<ConstantInt>(RHS))
323  RHSReg = materializeInt(C, MVT::i32);
324  else
325  RHSReg = getRegForValue(RHS);
326  if (!RHSReg)
327  return 0;
328 
329  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
330  if (!ResultReg)
331  return 0;
332 
333  emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
334  return ResultReg;
335 }
336 
337 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
338  assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
339  "Alloca should always return a pointer.");
340 
342  FuncInfo.StaticAllocaMap.find(AI);
343 
344  if (SI != FuncInfo.StaticAllocaMap.end()) {
345  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
346  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
347  ResultReg)
348  .addFrameIndex(SI->second)
349  .addImm(0);
350  return ResultReg;
351  }
352 
353  return 0;
354 }
355 
356 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
357  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
358  return 0;
359  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
360  const ConstantInt *CI = cast<ConstantInt>(C);
361  return materialize32BitInt(CI->getZExtValue(), RC);
362 }
363 
364 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
365  const TargetRegisterClass *RC) {
366  unsigned ResultReg = createResultReg(RC);
367 
368  if (isInt<16>(Imm)) {
369  unsigned Opc = Mips::ADDiu;
370  emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
371  return ResultReg;
372  } else if (isUInt<16>(Imm)) {
373  emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
374  return ResultReg;
375  }
376  unsigned Lo = Imm & 0xFFFF;
377  unsigned Hi = (Imm >> 16) & 0xFFFF;
378  if (Lo) {
379  // Both Lo and Hi have nonzero bits.
380  unsigned TmpReg = createResultReg(RC);
381  emitInst(Mips::LUi, TmpReg).addImm(Hi);
382  emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
383  } else {
384  emitInst(Mips::LUi, ResultReg).addImm(Hi);
385  }
386  return ResultReg;
387 }
388 
389 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
390  if (UnsupportedFPMode)
391  return 0;
392  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
393  if (VT == MVT::f32) {
394  const TargetRegisterClass *RC = &Mips::FGR32RegClass;
395  unsigned DestReg = createResultReg(RC);
396  unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
397  emitInst(Mips::MTC1, DestReg).addReg(TempReg);
398  return DestReg;
399  } else if (VT == MVT::f64) {
400  const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
401  unsigned DestReg = createResultReg(RC);
402  unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
403  unsigned TempReg2 =
404  materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
405  emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
406  return DestReg;
407  }
408  return 0;
409 }
410 
411 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
412  // For now 32-bit only.
413  if (VT != MVT::i32)
414  return 0;
415  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
416  unsigned DestReg = createResultReg(RC);
417  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
418  bool IsThreadLocal = GVar && GVar->isThreadLocal();
419  // TLS not supported at this time.
420  if (IsThreadLocal)
421  return 0;
422  emitInst(Mips::LW, DestReg)
423  .addReg(MFI->getGlobalBaseReg())
424  .addGlobalAddress(GV, 0, MipsII::MO_GOT);
425  if ((GV->hasInternalLinkage() ||
426  (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
427  unsigned TempReg = createResultReg(RC);
428  emitInst(Mips::ADDiu, TempReg)
429  .addReg(DestReg)
430  .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
431  DestReg = TempReg;
432  }
433  return DestReg;
434 }
435 
436 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
437  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
438  unsigned DestReg = createResultReg(RC);
439  emitInst(Mips::LW, DestReg)
440  .addReg(MFI->getGlobalBaseReg())
441  .addSym(Sym, MipsII::MO_GOT);
442  return DestReg;
443 }
444 
445 // Materialize a constant into a register, and return the register
446 // number (or zero if we failed to handle it).
447 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
448  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
449 
450  // Only handle simple types.
451  if (!CEVT.isSimple())
452  return 0;
453  MVT VT = CEVT.getSimpleVT();
454 
455  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
456  return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
457  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
458  return materializeGV(GV, VT);
459  else if (isa<ConstantInt>(C))
460  return materializeInt(C, VT);
461 
462  return 0;
463 }
464 
465 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
466  const User *U = nullptr;
467  unsigned Opcode = Instruction::UserOp1;
468  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
469  // Don't walk into other basic blocks unless the object is an alloca from
470  // another block, otherwise it may not have a virtual register assigned.
471  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
472  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
473  Opcode = I->getOpcode();
474  U = I;
475  }
476  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
477  Opcode = C->getOpcode();
478  U = C;
479  }
480  switch (Opcode) {
481  default:
482  break;
483  case Instruction::BitCast:
484  // Look through bitcasts.
485  return computeAddress(U->getOperand(0), Addr);
486  case Instruction::GetElementPtr: {
487  Address SavedAddr = Addr;
488  int64_t TmpOffset = Addr.getOffset();
489  // Iterate through the GEP folding the constants into offsets where
490  // we can.
492  for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
493  ++i, ++GTI) {
494  const Value *Op = *i;
495  if (StructType *STy = GTI.getStructTypeOrNull()) {
496  const StructLayout *SL = DL.getStructLayout(STy);
497  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
498  TmpOffset += SL->getElementOffset(Idx);
499  } else {
500  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
501  while (true) {
502  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
503  // Constant-offset addressing.
504  TmpOffset += CI->getSExtValue() * S;
505  break;
506  }
507  if (canFoldAddIntoGEP(U, Op)) {
508  // A compatible add with a constant operand. Fold the constant.
509  ConstantInt *CI =
510  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
511  TmpOffset += CI->getSExtValue() * S;
512  // Iterate on the other operand.
513  Op = cast<AddOperator>(Op)->getOperand(0);
514  continue;
515  }
516  // Unsupported
517  goto unsupported_gep;
518  }
519  }
520  }
521  // Try to grab the base operand now.
522  Addr.setOffset(TmpOffset);
523  if (computeAddress(U->getOperand(0), Addr))
524  return true;
525  // We failed, restore everything and try the other options.
526  Addr = SavedAddr;
527  unsupported_gep:
528  break;
529  }
530  case Instruction::Alloca: {
531  const AllocaInst *AI = cast<AllocaInst>(Obj);
533  FuncInfo.StaticAllocaMap.find(AI);
534  if (SI != FuncInfo.StaticAllocaMap.end()) {
535  Addr.setKind(Address::FrameIndexBase);
536  Addr.setFI(SI->second);
537  return true;
538  }
539  break;
540  }
541  }
542  Addr.setReg(getRegForValue(Obj));
543  return Addr.getReg() != 0;
544 }
545 
546 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
547  const User *U = nullptr;
548  unsigned Opcode = Instruction::UserOp1;
549 
550  if (const auto *I = dyn_cast<Instruction>(V)) {
551  // Check if the value is defined in the same basic block. This information
552  // is crucial to know whether or not folding an operand is valid.
553  if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
554  Opcode = I->getOpcode();
555  U = I;
556  }
557  } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
558  Opcode = C->getOpcode();
559  U = C;
560  }
561 
562  switch (Opcode) {
563  default:
564  break;
565  case Instruction::BitCast:
566  // Look past bitcasts if its operand is in the same BB.
567  return computeCallAddress(U->getOperand(0), Addr);
568  break;
569  case Instruction::IntToPtr:
570  // Look past no-op inttoptrs if its operand is in the same BB.
571  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
572  TLI.getPointerTy(DL))
573  return computeCallAddress(U->getOperand(0), Addr);
574  break;
575  case Instruction::PtrToInt:
576  // Look past no-op ptrtoints if its operand is in the same BB.
577  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
578  return computeCallAddress(U->getOperand(0), Addr);
579  break;
580  }
581 
582  if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
583  Addr.setGlobalValue(GV);
584  return true;
585  }
586 
587  // If all else fails, try to materialize the value in a register.
588  if (!Addr.getGlobalValue()) {
589  Addr.setReg(getRegForValue(V));
590  return Addr.getReg() != 0;
591  }
592 
593  return false;
594 }
595 
596 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
597  EVT evt = TLI.getValueType(DL, Ty, true);
598  // Only handle simple types.
599  if (evt == MVT::Other || !evt.isSimple())
600  return false;
601  VT = evt.getSimpleVT();
602 
603  // Handle all legal types, i.e. a register that will directly hold this
604  // value.
605  return TLI.isTypeLegal(VT);
606 }
607 
608 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
609  if (Ty->isVectorTy())
610  return false;
611 
612  if (isTypeLegal(Ty, VT))
613  return true;
614 
615  // If this is a type than can be sign or zero-extended to a basic operation
616  // go ahead and accept it now.
617  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
618  return true;
619 
620  return false;
621 }
622 
623 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
624  if (isTypeLegal(Ty, VT))
625  return true;
626  // We will extend this in a later patch:
627  // If this is a type than can be sign or zero-extended to a basic operation
628  // go ahead and accept it now.
629  if (VT == MVT::i8 || VT == MVT::i16)
630  return true;
631  return false;
632 }
633 
634 // Because of how EmitCmp is called with fast-isel, you can
635 // end up with redundant "andi" instructions after the sequences emitted below.
636 // We should try and solve this issue in the future.
637 //
638 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
639  const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
640  bool IsUnsigned = CI->isUnsigned();
641  unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
642  if (LeftReg == 0)
643  return false;
644  unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
645  if (RightReg == 0)
646  return false;
648 
649  switch (P) {
650  default:
651  return false;
652  case CmpInst::ICMP_EQ: {
653  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
654  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
655  emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
656  break;
657  }
658  case CmpInst::ICMP_NE: {
659  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
660  emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
661  emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
662  break;
663  }
664  case CmpInst::ICMP_UGT:
665  emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
666  break;
667  case CmpInst::ICMP_ULT:
668  emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
669  break;
670  case CmpInst::ICMP_UGE: {
671  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
672  emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
673  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
674  break;
675  }
676  case CmpInst::ICMP_ULE: {
677  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
678  emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
679  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
680  break;
681  }
682  case CmpInst::ICMP_SGT:
683  emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
684  break;
685  case CmpInst::ICMP_SLT:
686  emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
687  break;
688  case CmpInst::ICMP_SGE: {
689  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
690  emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
691  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
692  break;
693  }
694  case CmpInst::ICMP_SLE: {
695  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
696  emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
697  emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
698  break;
699  }
700  case CmpInst::FCMP_OEQ:
701  case CmpInst::FCMP_UNE:
702  case CmpInst::FCMP_OLT:
703  case CmpInst::FCMP_OLE:
704  case CmpInst::FCMP_OGT:
705  case CmpInst::FCMP_OGE: {
706  if (UnsupportedFPMode)
707  return false;
708  bool IsFloat = Left->getType()->isFloatTy();
709  bool IsDouble = Left->getType()->isDoubleTy();
710  if (!IsFloat && !IsDouble)
711  return false;
712  unsigned Opc, CondMovOpc;
713  switch (P) {
714  case CmpInst::FCMP_OEQ:
715  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
716  CondMovOpc = Mips::MOVT_I;
717  break;
718  case CmpInst::FCMP_UNE:
719  Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
720  CondMovOpc = Mips::MOVF_I;
721  break;
722  case CmpInst::FCMP_OLT:
723  Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
724  CondMovOpc = Mips::MOVT_I;
725  break;
726  case CmpInst::FCMP_OLE:
727  Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
728  CondMovOpc = Mips::MOVT_I;
729  break;
730  case CmpInst::FCMP_OGT:
731  Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
732  CondMovOpc = Mips::MOVF_I;
733  break;
734  case CmpInst::FCMP_OGE:
735  Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
736  CondMovOpc = Mips::MOVF_I;
737  break;
738  default:
739  llvm_unreachable("Only switching of a subset of CCs.");
740  }
741  unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
742  unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
743  emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
744  emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
745  emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
746  .addReg(RightReg);
747  emitInst(CondMovOpc, ResultReg)
748  .addReg(RegWithOne)
749  .addReg(Mips::FCC0)
750  .addReg(RegWithZero);
751  break;
752  }
753  }
754  return true;
755 }
756 
757 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
758  unsigned Alignment) {
759  //
760  // more cases will be handled here in following patches.
761  //
762  unsigned Opc;
763  switch (VT.SimpleTy) {
764  case MVT::i32:
765  ResultReg = createResultReg(&Mips::GPR32RegClass);
766  Opc = Mips::LW;
767  break;
768  case MVT::i16:
769  ResultReg = createResultReg(&Mips::GPR32RegClass);
770  Opc = Mips::LHu;
771  break;
772  case MVT::i8:
773  ResultReg = createResultReg(&Mips::GPR32RegClass);
774  Opc = Mips::LBu;
775  break;
776  case MVT::f32:
777  if (UnsupportedFPMode)
778  return false;
779  ResultReg = createResultReg(&Mips::FGR32RegClass);
780  Opc = Mips::LWC1;
781  break;
782  case MVT::f64:
783  if (UnsupportedFPMode)
784  return false;
785  ResultReg = createResultReg(&Mips::AFGR64RegClass);
786  Opc = Mips::LDC1;
787  break;
788  default:
789  return false;
790  }
791  if (Addr.isRegBase()) {
792  simplifyAddress(Addr);
793  emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
794  return true;
795  }
796  if (Addr.isFIBase()) {
797  unsigned FI = Addr.getFI();
798  unsigned Align = 4;
799  int64_t Offset = Addr.getOffset();
800  MachineFrameInfo &MFI = MF->getFrameInfo();
801  MachineMemOperand *MMO = MF->getMachineMemOperand(
803  MFI.getObjectSize(FI), Align);
804  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
805  .addFrameIndex(FI)
806  .addImm(Offset)
807  .addMemOperand(MMO);
808  return true;
809  }
810  return false;
811 }
812 
813 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
814  unsigned Alignment) {
815  //
816  // more cases will be handled here in following patches.
817  //
818  unsigned Opc;
819  switch (VT.SimpleTy) {
820  case MVT::i8:
821  Opc = Mips::SB;
822  break;
823  case MVT::i16:
824  Opc = Mips::SH;
825  break;
826  case MVT::i32:
827  Opc = Mips::SW;
828  break;
829  case MVT::f32:
830  if (UnsupportedFPMode)
831  return false;
832  Opc = Mips::SWC1;
833  break;
834  case MVT::f64:
835  if (UnsupportedFPMode)
836  return false;
837  Opc = Mips::SDC1;
838  break;
839  default:
840  return false;
841  }
842  if (Addr.isRegBase()) {
843  simplifyAddress(Addr);
844  emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
845  return true;
846  }
847  if (Addr.isFIBase()) {
848  unsigned FI = Addr.getFI();
849  unsigned Align = 4;
850  int64_t Offset = Addr.getOffset();
851  MachineFrameInfo &MFI = MF->getFrameInfo();
852  MachineMemOperand *MMO = MF->getMachineMemOperand(
854  MFI.getObjectSize(FI), Align);
855  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
856  .addReg(SrcReg)
857  .addFrameIndex(FI)
858  .addImm(Offset)
859  .addMemOperand(MMO);
860  return true;
861  }
862  return false;
863 }
864 
865 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
866  MVT VT;
867  if (!isTypeSupported(I->getType(), VT))
868  return false;
869 
870  unsigned ResultReg;
871  switch (I->getOpcode()) {
872  default:
873  llvm_unreachable("Unexpected instruction.");
874  case Instruction::And:
875  ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
876  break;
877  case Instruction::Or:
878  ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
879  break;
880  case Instruction::Xor:
881  ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
882  break;
883  }
884 
885  if (!ResultReg)
886  return false;
887 
888  updateValueMap(I, ResultReg);
889  return true;
890 }
891 
892 bool MipsFastISel::selectLoad(const Instruction *I) {
893  // Atomic loads need special handling.
894  if (cast<LoadInst>(I)->isAtomic())
895  return false;
896 
897  // Verify we have a legal type before going any further.
898  MVT VT;
899  if (!isLoadTypeLegal(I->getType(), VT))
900  return false;
901 
902  // See if we can handle this address.
903  Address Addr;
904  if (!computeAddress(I->getOperand(0), Addr))
905  return false;
906 
907  unsigned ResultReg;
908  if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
909  return false;
910  updateValueMap(I, ResultReg);
911  return true;
912 }
913 
914 bool MipsFastISel::selectStore(const Instruction *I) {
915  Value *Op0 = I->getOperand(0);
916  unsigned SrcReg = 0;
917 
918  // Atomic stores need special handling.
919  if (cast<StoreInst>(I)->isAtomic())
920  return false;
921 
922  // Verify we have a legal type before going any further.
923  MVT VT;
924  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
925  return false;
926 
927  // Get the value to be stored into a register.
928  SrcReg = getRegForValue(Op0);
929  if (SrcReg == 0)
930  return false;
931 
932  // See if we can handle this address.
933  Address Addr;
934  if (!computeAddress(I->getOperand(1), Addr))
935  return false;
936 
937  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
938  return false;
939  return true;
940 }
941 
942 // This can cause a redundant sltiu to be generated.
943 // FIXME: try and eliminate this in a future patch.
944 bool MipsFastISel::selectBranch(const Instruction *I) {
945  const BranchInst *BI = cast<BranchInst>(I);
946  MachineBasicBlock *BrBB = FuncInfo.MBB;
947  //
948  // TBB is the basic block for the case where the comparison is true.
949  // FBB is the basic block for the case where the comparison is false.
950  // if (cond) goto TBB
951  // goto FBB
952  // TBB:
953  //
954  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
955  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
956 
957  // Fold the common case of a conditional branch with a comparison
958  // in the same block.
959  unsigned ZExtCondReg = 0;
960  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
961  if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
962  ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
963  if (!emitCmp(ZExtCondReg, CI))
964  return false;
965  }
966  }
967 
968  // For the general case, we need to mask with 1.
969  if (ZExtCondReg == 0) {
970  unsigned CondReg = getRegForValue(BI->getCondition());
971  if (CondReg == 0)
972  return false;
973 
974  ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true);
975  if (ZExtCondReg == 0)
976  return false;
977  }
978 
979  BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
980  .addReg(ZExtCondReg)
981  .addMBB(TBB);
982  finishCondBranch(BI->getParent(), TBB, FBB);
983  return true;
984 }
985 
986 bool MipsFastISel::selectCmp(const Instruction *I) {
987  const CmpInst *CI = cast<CmpInst>(I);
988  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
989  if (!emitCmp(ResultReg, CI))
990  return false;
991  updateValueMap(I, ResultReg);
992  return true;
993 }
994 
995 // Attempt to fast-select a floating-point extend instruction.
996 bool MipsFastISel::selectFPExt(const Instruction *I) {
997  if (UnsupportedFPMode)
998  return false;
999  Value *Src = I->getOperand(0);
1000  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1001  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1002 
1003  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1004  return false;
1005 
1006  unsigned SrcReg =
1007  getRegForValue(Src); // this must be a 32bit floating point register class
1008  // maybe we should handle this differently
1009  if (!SrcReg)
1010  return false;
1011 
1012  unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
1013  emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1014  updateValueMap(I, DestReg);
1015  return true;
1016 }
1017 
1018 bool MipsFastISel::selectSelect(const Instruction *I) {
1019  assert(isa<SelectInst>(I) && "Expected a select instruction.");
1020 
1021  LLVM_DEBUG(dbgs() << "selectSelect\n");
1022 
1023  MVT VT;
1024  if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
1025  LLVM_DEBUG(
1026  dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1027  return false;
1028  }
1029 
1030  unsigned CondMovOpc;
1031  const TargetRegisterClass *RC;
1032 
1033  if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1034  CondMovOpc = Mips::MOVN_I_I;
1035  RC = &Mips::GPR32RegClass;
1036  } else if (VT == MVT::f32) {
1037  CondMovOpc = Mips::MOVN_I_S;
1038  RC = &Mips::FGR32RegClass;
1039  } else if (VT == MVT::f64) {
1040  CondMovOpc = Mips::MOVN_I_D32;
1041  RC = &Mips::AFGR64RegClass;
1042  } else
1043  return false;
1044 
1045  const SelectInst *SI = cast<SelectInst>(I);
1046  const Value *Cond = SI->getCondition();
1047  unsigned Src1Reg = getRegForValue(SI->getTrueValue());
1048  unsigned Src2Reg = getRegForValue(SI->getFalseValue());
1049  unsigned CondReg = getRegForValue(Cond);
1050 
1051  if (!Src1Reg || !Src2Reg || !CondReg)
1052  return false;
1053 
1054  unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1055  if (!ZExtCondReg)
1056  return false;
1057 
1058  if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true))
1059  return false;
1060 
1061  unsigned ResultReg = createResultReg(RC);
1062  unsigned TempReg = createResultReg(RC);
1063 
1064  if (!ResultReg || !TempReg)
1065  return false;
1066 
1067  emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1068  emitInst(CondMovOpc, ResultReg)
1069  .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1070  updateValueMap(I, ResultReg);
1071  return true;
1072 }
1073 
1074 // Attempt to fast-select a floating-point truncate instruction.
1075 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1076  if (UnsupportedFPMode)
1077  return false;
1078  Value *Src = I->getOperand(0);
1079  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1080  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1081 
1082  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1083  return false;
1084 
1085  unsigned SrcReg = getRegForValue(Src);
1086  if (!SrcReg)
1087  return false;
1088 
1089  unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1090  if (!DestReg)
1091  return false;
1092 
1093  emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1094  updateValueMap(I, DestReg);
1095  return true;
1096 }
1097 
1098 // Attempt to fast-select a floating-point-to-integer conversion.
1099 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1100  if (UnsupportedFPMode)
1101  return false;
1102  MVT DstVT, SrcVT;
1103  if (!IsSigned)
1104  return false; // We don't handle this case yet. There is no native
1105  // instruction for this but it can be synthesized.
1106  Type *DstTy = I->getType();
1107  if (!isTypeLegal(DstTy, DstVT))
1108  return false;
1109 
1110  if (DstVT != MVT::i32)
1111  return false;
1112 
1113  Value *Src = I->getOperand(0);
1114  Type *SrcTy = Src->getType();
1115  if (!isTypeLegal(SrcTy, SrcVT))
1116  return false;
1117 
1118  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1119  return false;
1120 
1121  unsigned SrcReg = getRegForValue(Src);
1122  if (SrcReg == 0)
1123  return false;
1124 
1125  // Determine the opcode for the conversion, which takes place
1126  // entirely within FPRs.
1127  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1128  unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1129  unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1130 
1131  // Generate the convert.
1132  emitInst(Opc, TempReg).addReg(SrcReg);
1133  emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1134 
1135  updateValueMap(I, DestReg);
1136  return true;
1137 }
1138 
1139 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1140  SmallVectorImpl<MVT> &OutVTs,
1141  unsigned &NumBytes) {
1142  CallingConv::ID CC = CLI.CallConv;
1144  CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1145  CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1146  // Get a count of how many bytes are to be pushed on the stack.
1147  NumBytes = CCInfo.getNextStackOffset();
1148  // This is the minimum argument area used for A0-A3.
1149  if (NumBytes < 16)
1150  NumBytes = 16;
1151 
1152  emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1153  // Process the args.
1154  MVT firstMVT;
1155  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1156  CCValAssign &VA = ArgLocs[i];
1157  const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1158  MVT ArgVT = OutVTs[VA.getValNo()];
1159 
1160  if (i == 0) {
1161  firstMVT = ArgVT;
1162  if (ArgVT == MVT::f32) {
1163  VA.convertToReg(Mips::F12);
1164  } else if (ArgVT == MVT::f64) {
1165  if (Subtarget->isFP64bit())
1166  VA.convertToReg(Mips::D6_64);
1167  else
1168  VA.convertToReg(Mips::D6);
1169  }
1170  } else if (i == 1) {
1171  if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1172  if (ArgVT == MVT::f32) {
1173  VA.convertToReg(Mips::F14);
1174  } else if (ArgVT == MVT::f64) {
1175  if (Subtarget->isFP64bit())
1176  VA.convertToReg(Mips::D7_64);
1177  else
1178  VA.convertToReg(Mips::D7);
1179  }
1180  }
1181  }
1182  if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1183  (ArgVT == MVT::i8)) &&
1184  VA.isMemLoc()) {
1185  switch (VA.getLocMemOffset()) {
1186  case 0:
1187  VA.convertToReg(Mips::A0);
1188  break;
1189  case 4:
1190  VA.convertToReg(Mips::A1);
1191  break;
1192  case 8:
1193  VA.convertToReg(Mips::A2);
1194  break;
1195  case 12:
1196  VA.convertToReg(Mips::A3);
1197  break;
1198  default:
1199  break;
1200  }
1201  }
1202  unsigned ArgReg = getRegForValue(ArgVal);
1203  if (!ArgReg)
1204  return false;
1205 
1206  // Handle arg promotion: SExt, ZExt, AExt.
1207  switch (VA.getLocInfo()) {
1208  case CCValAssign::Full:
1209  break;
1210  case CCValAssign::AExt:
1211  case CCValAssign::SExt: {
1212  MVT DestVT = VA.getLocVT();
1213  MVT SrcVT = ArgVT;
1214  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1215  if (!ArgReg)
1216  return false;
1217  break;
1218  }
1219  case CCValAssign::ZExt: {
1220  MVT DestVT = VA.getLocVT();
1221  MVT SrcVT = ArgVT;
1222  ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1223  if (!ArgReg)
1224  return false;
1225  break;
1226  }
1227  default:
1228  llvm_unreachable("Unknown arg promotion!");
1229  }
1230 
1231  // Now copy/store arg to correct locations.
1232  if (VA.isRegLoc() && !VA.needsCustom()) {
1233  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1234  TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1235  CLI.OutRegs.push_back(VA.getLocReg());
1236  } else if (VA.needsCustom()) {
1237  llvm_unreachable("Mips does not use custom args.");
1238  return false;
1239  } else {
1240  //
1241  // FIXME: This path will currently return false. It was copied
1242  // from the AArch64 port and should be essentially fine for Mips too.
1243  // The work to finish up this path will be done in a follow-on patch.
1244  //
1245  assert(VA.isMemLoc() && "Assuming store on stack.");
1246  // Don't emit stores for undef values.
1247  if (isa<UndefValue>(ArgVal))
1248  continue;
1249 
1250  // Need to store on the stack.
1251  // FIXME: This alignment is incorrect but this path is disabled
1252  // for now (will return false). We need to determine the right alignment
1253  // based on the normal alignment for the underlying machine type.
1254  //
1255  unsigned ArgSize = alignTo(ArgVT.getSizeInBits(), 4);
1256 
1257  unsigned BEAlign = 0;
1258  if (ArgSize < 8 && !Subtarget->isLittle())
1259  BEAlign = 8 - ArgSize;
1260 
1261  Address Addr;
1262  Addr.setKind(Address::RegBase);
1263  Addr.setReg(Mips::SP);
1264  Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1265 
1266  unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1267  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1268  MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
1269  MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1270  (void)(MMO);
1271  // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1272  return false; // can't store on the stack yet.
1273  }
1274  }
1275 
1276  return true;
1277 }
1278 
1279 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1280  unsigned NumBytes) {
1281  CallingConv::ID CC = CLI.CallConv;
1282  emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1283  if (RetVT != MVT::isVoid) {
1285  MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1286 
1287  CCInfo.AnalyzeCallResult(CLI.Ins, RetCC_Mips, CLI.RetTy,
1288  CLI.Symbol ? CLI.Symbol->getName().data()
1289  : nullptr);
1290 
1291  // Only handle a single return value.
1292  if (RVLocs.size() != 1)
1293  return false;
1294  // Copy all of the result registers out of their specified physreg.
1295  MVT CopyVT = RVLocs[0].getValVT();
1296  // Special handling for extended integers.
1297  if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1298  CopyVT = MVT::i32;
1299 
1300  unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1301  if (!ResultReg)
1302  return false;
1303  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1304  TII.get(TargetOpcode::COPY),
1305  ResultReg).addReg(RVLocs[0].getLocReg());
1306  CLI.InRegs.push_back(RVLocs[0].getLocReg());
1307 
1308  CLI.ResultReg = ResultReg;
1309  CLI.NumResultRegs = 1;
1310  }
1311  return true;
1312 }
1313 
1314 bool MipsFastISel::fastLowerArguments() {
1315  LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1316 
1317  if (!FuncInfo.CanLowerReturn) {
1318  LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1319  return false;
1320  }
1321 
1322  const Function *F = FuncInfo.Fn;
1323  if (F->isVarArg()) {
1324  LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1325  return false;
1326  }
1327 
1328  CallingConv::ID CC = F->getCallingConv();
1329  if (CC != CallingConv::C) {
1330  LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1331  return false;
1332  }
1333 
1334  std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1335  Mips::A3}};
1336  std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1337  std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1338  auto NextGPR32 = GPR32ArgRegs.begin();
1339  auto NextFGR32 = FGR32ArgRegs.begin();
1340  auto NextAFGR64 = AFGR64ArgRegs.begin();
1341 
1342  struct AllocatedReg {
1343  const TargetRegisterClass *RC;
1344  unsigned Reg;
1345  AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1346  : RC(RC), Reg(Reg) {}
1347  };
1348 
1349  // Only handle simple cases. i.e. All arguments are directly mapped to
1350  // registers of the appropriate type.
1351  SmallVector<AllocatedReg, 4> Allocation;
1352  for (const auto &FormalArg : F->args()) {
1353  if (FormalArg.hasAttribute(Attribute::InReg) ||
1354  FormalArg.hasAttribute(Attribute::StructRet) ||
1355  FormalArg.hasAttribute(Attribute::ByVal)) {
1356  LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1357  return false;
1358  }
1359 
1360  Type *ArgTy = FormalArg.getType();
1361  if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1362  LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1363  return false;
1364  }
1365 
1366  EVT ArgVT = TLI.getValueType(DL, ArgTy);
1367  LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1368  << ArgVT.getEVTString() << "\n");
1369  if (!ArgVT.isSimple()) {
1370  LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1371  return false;
1372  }
1373 
1374  switch (ArgVT.getSimpleVT().SimpleTy) {
1375  case MVT::i1:
1376  case MVT::i8:
1377  case MVT::i16:
1378  if (!FormalArg.hasAttribute(Attribute::SExt) &&
1379  !FormalArg.hasAttribute(Attribute::ZExt)) {
1380  // It must be any extend, this shouldn't happen for clang-generated IR
1381  // so just fall back on SelectionDAG.
1382  LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1383  return false;
1384  }
1385 
1386  if (NextGPR32 == GPR32ArgRegs.end()) {
1387  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1388  return false;
1389  }
1390 
1391  LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1392  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1393 
1394  // Allocating any GPR32 prohibits further use of floating point arguments.
1395  NextFGR32 = FGR32ArgRegs.end();
1396  NextAFGR64 = AFGR64ArgRegs.end();
1397  break;
1398 
1399  case MVT::i32:
1400  if (FormalArg.hasAttribute(Attribute::ZExt)) {
1401  // The O32 ABI does not permit a zero-extended i32.
1402  LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1403  return false;
1404  }
1405 
1406  if (NextGPR32 == GPR32ArgRegs.end()) {
1407  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1408  return false;
1409  }
1410 
1411  LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1412  Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1413 
1414  // Allocating any GPR32 prohibits further use of floating point arguments.
1415  NextFGR32 = FGR32ArgRegs.end();
1416  NextAFGR64 = AFGR64ArgRegs.end();
1417  break;
1418 
1419  case MVT::f32:
1420  if (UnsupportedFPMode) {
1421  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1422  return false;
1423  }
1424  if (NextFGR32 == FGR32ArgRegs.end()) {
1425  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1426  return false;
1427  }
1428  LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1429  Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1430  // Allocating an FGR32 also allocates the super-register AFGR64, and
1431  // ABI rules require us to skip the corresponding GPR32.
1432  if (NextGPR32 != GPR32ArgRegs.end())
1433  NextGPR32++;
1434  if (NextAFGR64 != AFGR64ArgRegs.end())
1435  NextAFGR64++;
1436  break;
1437 
1438  case MVT::f64:
1439  if (UnsupportedFPMode) {
1440  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1441  return false;
1442  }
1443  if (NextAFGR64 == AFGR64ArgRegs.end()) {
1444  LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1445  return false;
1446  }
1447  LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1448  Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1449  // Allocating an FGR32 also allocates the super-register AFGR64, and
1450  // ABI rules require us to skip the corresponding GPR32 pair.
1451  if (NextGPR32 != GPR32ArgRegs.end())
1452  NextGPR32++;
1453  if (NextGPR32 != GPR32ArgRegs.end())
1454  NextGPR32++;
1455  if (NextFGR32 != FGR32ArgRegs.end())
1456  NextFGR32++;
1457  break;
1458 
1459  default:
1460  LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1461  return false;
1462  }
1463  }
1464 
1465  for (const auto &FormalArg : F->args()) {
1466  unsigned ArgNo = FormalArg.getArgNo();
1467  unsigned SrcReg = Allocation[ArgNo].Reg;
1468  unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1469  // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1470  // Without this, EmitLiveInCopies may eliminate the livein if its only
1471  // use is a bitcast (which isn't turned into an instruction).
1472  unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);
1473  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1474  TII.get(TargetOpcode::COPY), ResultReg)
1475  .addReg(DstReg, getKillRegState(true));
1476  updateValueMap(&FormalArg, ResultReg);
1477  }
1478 
1479  // Calculate the size of the incoming arguments area.
1480  // We currently reject all the cases where this would be non-zero.
1481  unsigned IncomingArgSizeInBytes = 0;
1482 
1483  // Account for the reserved argument area on ABI's that have one (O32).
1484  // It seems strange to do this on the caller side but it's necessary in
1485  // SelectionDAG's implementation.
1486  IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1487  IncomingArgSizeInBytes);
1488 
1489  MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes,
1490  false);
1491 
1492  return true;
1493 }
1494 
1495 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1496  CallingConv::ID CC = CLI.CallConv;
1497  bool IsTailCall = CLI.IsTailCall;
1498  bool IsVarArg = CLI.IsVarArg;
1499  const Value *Callee = CLI.Callee;
1500  MCSymbol *Symbol = CLI.Symbol;
1501 
1502  // Do not handle FastCC.
1503  if (CC == CallingConv::Fast)
1504  return false;
1505 
1506  // Allow SelectionDAG isel to handle tail calls.
1507  if (IsTailCall)
1508  return false;
1509 
1510  // Let SDISel handle vararg functions.
1511  if (IsVarArg)
1512  return false;
1513 
1514  // FIXME: Only handle *simple* calls for now.
1515  MVT RetVT;
1516  if (CLI.RetTy->isVoidTy())
1517  RetVT = MVT::isVoid;
1518  else if (!isTypeSupported(CLI.RetTy, RetVT))
1519  return false;
1520 
1521  for (auto Flag : CLI.OutFlags)
1522  if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1523  return false;
1524 
1525  // Set up the argument vectors.
1526  SmallVector<MVT, 16> OutVTs;
1527  OutVTs.reserve(CLI.OutVals.size());
1528 
1529  for (auto *Val : CLI.OutVals) {
1530  MVT VT;
1531  if (!isTypeLegal(Val->getType(), VT) &&
1532  !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1533  return false;
1534 
1535  // We don't handle vector parameters yet.
1536  if (VT.isVector() || VT.getSizeInBits() > 64)
1537  return false;
1538 
1539  OutVTs.push_back(VT);
1540  }
1541 
1542  Address Addr;
1543  if (!computeCallAddress(Callee, Addr))
1544  return false;
1545 
1546  // Handle the arguments now that we've gotten them.
1547  unsigned NumBytes;
1548  if (!processCallArgs(CLI, OutVTs, NumBytes))
1549  return false;
1550 
1551  if (!Addr.getGlobalValue())
1552  return false;
1553 
1554  // Issue the call.
1555  unsigned DestAddress;
1556  if (Symbol)
1557  DestAddress = materializeExternalCallSym(Symbol);
1558  else
1559  DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1560  emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1561  MachineInstrBuilder MIB =
1562  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1563  Mips::RA).addReg(Mips::T9);
1564 
1565  // Add implicit physical register uses to the call.
1566  for (auto Reg : CLI.OutRegs)
1568 
1569  // Add a register mask with the call-preserved registers.
1570  // Proper defs for return values will be added by setPhysRegsDeadExcept().
1571  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1572 
1573  CLI.Call = MIB;
1574 
1575  if (EmitJalrReloc && !Subtarget->inMips16Mode()) {
1576  // Attach callee address to the instruction, let asm printer emit
1577  // .reloc R_MIPS_JALR.
1578  if (Symbol)
1579  MIB.addSym(Symbol, MipsII::MO_JALR);
1580  else
1581  MIB.addSym(FuncInfo.MF->getContext().getOrCreateSymbol(
1582  Addr.getGlobalValue()->getName()), MipsII::MO_JALR);
1583  }
1584 
1585  // Finish off the call including any return values.
1586  return finishCall(CLI, RetVT, NumBytes);
1587 }
1588 
1589 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1590  switch (II->getIntrinsicID()) {
1591  default:
1592  return false;
1593  case Intrinsic::bswap: {
1594  Type *RetTy = II->getCalledFunction()->getReturnType();
1595 
1596  MVT VT;
1597  if (!isTypeSupported(RetTy, VT))
1598  return false;
1599 
1600  unsigned SrcReg = getRegForValue(II->getOperand(0));
1601  if (SrcReg == 0)
1602  return false;
1603  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1604  if (DestReg == 0)
1605  return false;
1606  if (VT == MVT::i16) {
1607  if (Subtarget->hasMips32r2()) {
1608  emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1609  updateValueMap(II, DestReg);
1610  return true;
1611  } else {
1612  unsigned TempReg[3];
1613  for (int i = 0; i < 3; i++) {
1614  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1615  if (TempReg[i] == 0)
1616  return false;
1617  }
1618  emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1619  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1620  emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1621  emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1622  updateValueMap(II, DestReg);
1623  return true;
1624  }
1625  } else if (VT == MVT::i32) {
1626  if (Subtarget->hasMips32r2()) {
1627  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1628  emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1629  emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1630  updateValueMap(II, DestReg);
1631  return true;
1632  } else {
1633  unsigned TempReg[8];
1634  for (int i = 0; i < 8; i++) {
1635  TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1636  if (TempReg[i] == 0)
1637  return false;
1638  }
1639 
1640  emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1641  emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1642  emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1643  emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1644 
1645  emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1646  emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1647 
1648  emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1649  emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1650  emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1651  updateValueMap(II, DestReg);
1652  return true;
1653  }
1654  }
1655  return false;
1656  }
1657  case Intrinsic::memcpy:
1658  case Intrinsic::memmove: {
1659  const auto *MTI = cast<MemTransferInst>(II);
1660  // Don't handle volatile.
1661  if (MTI->isVolatile())
1662  return false;
1663  if (!MTI->getLength()->getType()->isIntegerTy(32))
1664  return false;
1665  const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1666  return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 1);
1667  }
1668  case Intrinsic::memset: {
1669  const MemSetInst *MSI = cast<MemSetInst>(II);
1670  // Don't handle volatile.
1671  if (MSI->isVolatile())
1672  return false;
1673  if (!MSI->getLength()->getType()->isIntegerTy(32))
1674  return false;
1675  return lowerCallTo(II, "memset", II->getNumArgOperands() - 1);
1676  }
1677  }
1678  return false;
1679 }
1680 
1681 bool MipsFastISel::selectRet(const Instruction *I) {
1682  const Function &F = *I->getParent()->getParent();
1683  const ReturnInst *Ret = cast<ReturnInst>(I);
1684 
1685  LLVM_DEBUG(dbgs() << "selectRet\n");
1686 
1687  if (!FuncInfo.CanLowerReturn)
1688  return false;
1689 
1690  // Build a list of return value registers.
1691  SmallVector<unsigned, 4> RetRegs;
1692 
1693  if (Ret->getNumOperands() > 0) {
1695 
1696  // Do not handle FastCC.
1697  if (CC == CallingConv::Fast)
1698  return false;
1699 
1701  GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1702 
1703  // Analyze operands of the call, assigning locations to each operand.
1705  MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1706  I->getContext());
1707  CCAssignFn *RetCC = RetCC_Mips;
1708  CCInfo.AnalyzeReturn(Outs, RetCC);
1709 
1710  // Only handle a single return value for now.
1711  if (ValLocs.size() != 1)
1712  return false;
1713 
1714  CCValAssign &VA = ValLocs[0];
1715  const Value *RV = Ret->getOperand(0);
1716 
1717  // Don't bother handling odd stuff for now.
1718  if ((VA.getLocInfo() != CCValAssign::Full) &&
1719  (VA.getLocInfo() != CCValAssign::BCvt))
1720  return false;
1721 
1722  // Only handle register returns for now.
1723  if (!VA.isRegLoc())
1724  return false;
1725 
1726  unsigned Reg = getRegForValue(RV);
1727  if (Reg == 0)
1728  return false;
1729 
1730  unsigned SrcReg = Reg + VA.getValNo();
1731  Register DestReg = VA.getLocReg();
1732  // Avoid a cross-class copy. This is very unlikely.
1733  if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1734  return false;
1735 
1736  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1737  if (!RVEVT.isSimple())
1738  return false;
1739 
1740  if (RVEVT.isVector())
1741  return false;
1742 
1743  MVT RVVT = RVEVT.getSimpleVT();
1744  if (RVVT == MVT::f128)
1745  return false;
1746 
1747  // Do not handle FGR64 returns for now.
1748  if (RVVT == MVT::f64 && UnsupportedFPMode) {
1749  LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1750  return false;
1751  }
1752 
1753  MVT DestVT = VA.getValVT();
1754  // Special handling for extended integers.
1755  if (RVVT != DestVT) {
1756  if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1757  return false;
1758 
1759  if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1760  bool IsZExt = Outs[0].Flags.isZExt();
1761  SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1762  if (SrcReg == 0)
1763  return false;
1764  }
1765  }
1766 
1767  // Make the copy.
1768  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1769  TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1770 
1771  // Add register to return instruction.
1772  RetRegs.push_back(VA.getLocReg());
1773  }
1774  MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1775  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1776  MIB.addReg(RetRegs[i], RegState::Implicit);
1777  return true;
1778 }
1779 
1780 bool MipsFastISel::selectTrunc(const Instruction *I) {
1781  // The high bits for a type smaller than the register size are assumed to be
1782  // undefined.
1783  Value *Op = I->getOperand(0);
1784 
1785  EVT SrcVT, DestVT;
1786  SrcVT = TLI.getValueType(DL, Op->getType(), true);
1787  DestVT = TLI.getValueType(DL, I->getType(), true);
1788 
1789  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1790  return false;
1791  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1792  return false;
1793 
1794  unsigned SrcReg = getRegForValue(Op);
1795  if (!SrcReg)
1796  return false;
1797 
1798  // Because the high bits are undefined, a truncate doesn't generate
1799  // any code.
1800  updateValueMap(I, SrcReg);
1801  return true;
1802 }
1803 
1804 bool MipsFastISel::selectIntExt(const Instruction *I) {
1805  Type *DestTy = I->getType();
1806  Value *Src = I->getOperand(0);
1807  Type *SrcTy = Src->getType();
1808 
1809  bool isZExt = isa<ZExtInst>(I);
1810  unsigned SrcReg = getRegForValue(Src);
1811  if (!SrcReg)
1812  return false;
1813 
1814  EVT SrcEVT, DestEVT;
1815  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1816  DestEVT = TLI.getValueType(DL, DestTy, true);
1817  if (!SrcEVT.isSimple())
1818  return false;
1819  if (!DestEVT.isSimple())
1820  return false;
1821 
1822  MVT SrcVT = SrcEVT.getSimpleVT();
1823  MVT DestVT = DestEVT.getSimpleVT();
1824  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1825 
1826  if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1827  return false;
1828  updateValueMap(I, ResultReg);
1829  return true;
1830 }
1831 
1832 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1833  unsigned DestReg) {
1834  unsigned ShiftAmt;
1835  switch (SrcVT.SimpleTy) {
1836  default:
1837  return false;
1838  case MVT::i8:
1839  ShiftAmt = 24;
1840  break;
1841  case MVT::i16:
1842  ShiftAmt = 16;
1843  break;
1844  }
1845  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1846  emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1847  emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1848  return true;
1849 }
1850 
1851 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1852  unsigned DestReg) {
1853  switch (SrcVT.SimpleTy) {
1854  default:
1855  return false;
1856  case MVT::i8:
1857  emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1858  break;
1859  case MVT::i16:
1860  emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1861  break;
1862  }
1863  return true;
1864 }
1865 
1866 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1867  unsigned DestReg) {
1868  if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1869  return false;
1870  if (Subtarget->hasMips32r2())
1871  return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1872  return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1873 }
1874 
1875 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1876  unsigned DestReg) {
1877  int64_t Imm;
1878 
1879  switch (SrcVT.SimpleTy) {
1880  default:
1881  return false;
1882  case MVT::i1:
1883  Imm = 1;
1884  break;
1885  case MVT::i8:
1886  Imm = 0xff;
1887  break;
1888  case MVT::i16:
1889  Imm = 0xffff;
1890  break;
1891  }
1892 
1893  emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1894  return true;
1895 }
1896 
1897 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1898  unsigned DestReg, bool IsZExt) {
1899  // FastISel does not have plumbing to deal with extensions where the SrcVT or
1900  // DestVT are odd things, so test to make sure that they are both types we can
1901  // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1902  // bail out to SelectionDAG.
1903  if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1904  ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1905  return false;
1906  if (IsZExt)
1907  return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1908  return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1909 }
1910 
1911 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1912  bool isZExt) {
1913  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1914  bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1915  return Success ? DestReg : 0;
1916 }
1917 
1918 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1919  EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
1920  if (!DestEVT.isSimple())
1921  return false;
1922 
1923  MVT DestVT = DestEVT.getSimpleVT();
1924  if (DestVT != MVT::i32)
1925  return false;
1926 
1927  unsigned DivOpc;
1928  switch (ISDOpcode) {
1929  default:
1930  return false;
1931  case ISD::SDIV:
1932  case ISD::SREM:
1933  DivOpc = Mips::SDIV;
1934  break;
1935  case ISD::UDIV:
1936  case ISD::UREM:
1937  DivOpc = Mips::UDIV;
1938  break;
1939  }
1940 
1941  unsigned Src0Reg = getRegForValue(I->getOperand(0));
1942  unsigned Src1Reg = getRegForValue(I->getOperand(1));
1943  if (!Src0Reg || !Src1Reg)
1944  return false;
1945 
1946  emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1947  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1948 
1949  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1950  if (!ResultReg)
1951  return false;
1952 
1953  unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1954  ? Mips::MFHI
1955  : Mips::MFLO;
1956  emitInst(MFOpc, ResultReg);
1957 
1958  updateValueMap(I, ResultReg);
1959  return true;
1960 }
1961 
1962 bool MipsFastISel::selectShift(const Instruction *I) {
1963  MVT RetVT;
1964 
1965  if (!isTypeSupported(I->getType(), RetVT))
1966  return false;
1967 
1968  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1969  if (!ResultReg)
1970  return false;
1971 
1972  unsigned Opcode = I->getOpcode();
1973  const Value *Op0 = I->getOperand(0);
1974  unsigned Op0Reg = getRegForValue(Op0);
1975  if (!Op0Reg)
1976  return false;
1977 
1978  // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1979  if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1980  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1981  if (!TempReg)
1982  return false;
1983 
1984  MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT();
1985  bool IsZExt = Opcode == Instruction::LShr;
1986  if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1987  return false;
1988 
1989  Op0Reg = TempReg;
1990  }
1991 
1992  if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1993  uint64_t ShiftVal = C->getZExtValue();
1994 
1995  switch (Opcode) {
1996  default:
1997  llvm_unreachable("Unexpected instruction.");
1998  case Instruction::Shl:
1999  Opcode = Mips::SLL;
2000  break;
2001  case Instruction::AShr:
2002  Opcode = Mips::SRA;
2003  break;
2004  case Instruction::LShr:
2005  Opcode = Mips::SRL;
2006  break;
2007  }
2008 
2009  emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
2010  updateValueMap(I, ResultReg);
2011  return true;
2012  }
2013 
2014  unsigned Op1Reg = getRegForValue(I->getOperand(1));
2015  if (!Op1Reg)
2016  return false;
2017 
2018  switch (Opcode) {
2019  default:
2020  llvm_unreachable("Unexpected instruction.");
2021  case Instruction::Shl:
2022  Opcode = Mips::SLLV;
2023  break;
2024  case Instruction::AShr:
2025  Opcode = Mips::SRAV;
2026  break;
2027  case Instruction::LShr:
2028  Opcode = Mips::SRLV;
2029  break;
2030  }
2031 
2032  emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2033  updateValueMap(I, ResultReg);
2034  return true;
2035 }
2036 
2037 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2038  switch (I->getOpcode()) {
2039  default:
2040  break;
2041  case Instruction::Load:
2042  return selectLoad(I);
2043  case Instruction::Store:
2044  return selectStore(I);
2045  case Instruction::SDiv:
2046  if (!selectBinaryOp(I, ISD::SDIV))
2047  return selectDivRem(I, ISD::SDIV);
2048  return true;
2049  case Instruction::UDiv:
2050  if (!selectBinaryOp(I, ISD::UDIV))
2051  return selectDivRem(I, ISD::UDIV);
2052  return true;
2053  case Instruction::SRem:
2054  if (!selectBinaryOp(I, ISD::SREM))
2055  return selectDivRem(I, ISD::SREM);
2056  return true;
2057  case Instruction::URem:
2058  if (!selectBinaryOp(I, ISD::UREM))
2059  return selectDivRem(I, ISD::UREM);
2060  return true;
2061  case Instruction::Shl:
2062  case Instruction::LShr:
2063  case Instruction::AShr:
2064  return selectShift(I);
2065  case Instruction::And:
2066  case Instruction::Or:
2067  case Instruction::Xor:
2068  return selectLogicalOp(I);
2069  case Instruction::Br:
2070  return selectBranch(I);
2071  case Instruction::Ret:
2072  return selectRet(I);
2073  case Instruction::Trunc:
2074  return selectTrunc(I);
2075  case Instruction::ZExt:
2076  case Instruction::SExt:
2077  return selectIntExt(I);
2078  case Instruction::FPTrunc:
2079  return selectFPTrunc(I);
2080  case Instruction::FPExt:
2081  return selectFPExt(I);
2082  case Instruction::FPToSI:
2083  return selectFPToInt(I, /*isSigned*/ true);
2084  case Instruction::FPToUI:
2085  return selectFPToInt(I, /*isSigned*/ false);
2086  case Instruction::ICmp:
2087  case Instruction::FCmp:
2088  return selectCmp(I);
2089  case Instruction::Select:
2090  return selectSelect(I);
2091  }
2092  return false;
2093 }
2094 
2095 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2096  bool IsUnsigned) {
2097  unsigned VReg = getRegForValue(V);
2098  if (VReg == 0)
2099  return 0;
2100  MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
2101 
2102  if (VMVT == MVT::i1)
2103  return 0;
2104 
2105  if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2106  unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2107  if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2108  return 0;
2109  VReg = TempReg;
2110  }
2111  return VReg;
2112 }
2113 
2114 void MipsFastISel::simplifyAddress(Address &Addr) {
2115  if (!isInt<16>(Addr.getOffset())) {
2116  unsigned TempReg =
2117  materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2118  unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2119  emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2120  Addr.setReg(DestReg);
2121  Addr.setOffset(0);
2122  }
2123 }
2124 
2125 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2126  const TargetRegisterClass *RC,
2127  unsigned Op0, bool Op0IsKill,
2128  unsigned Op1, bool Op1IsKill) {
2129  // We treat the MUL instruction in a special way because it clobbers
2130  // the HI0 & LO0 registers. The TableGen definition of this instruction can
2131  // mark these registers only as implicitly defined. As a result, the
2132  // register allocator runs out of registers when this instruction is
2133  // followed by another instruction that defines the same registers too.
2134  // We can fix this by explicitly marking those registers as dead.
2135  if (MachineInstOpcode == Mips::MUL) {
2136  unsigned ResultReg = createResultReg(RC);
2137  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2138  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2139  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2140  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2141  .addReg(Op0, getKillRegState(Op0IsKill))
2142  .addReg(Op1, getKillRegState(Op1IsKill))
2145  return ResultReg;
2146  }
2147 
2148  return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
2149  Op1IsKill);
2150 }
2151 
2152 namespace llvm {
2153 
2155  const TargetLibraryInfo *libInfo) {
2156  return new MipsFastISel(funcInfo, libInfo);
2157 }
2158 
2159 } // end namespace llvm
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
uint64_t CallInst * C
Return a value (possibly void), from a function.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
bool hasLocalLinkage() const
Definition: GlobalValue.h:445
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1571
LLVMContext & Context
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
bool isVector() const
Return true if this is a vector value type.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
const MipsInstrInfo * getInstrInfo() const override
const Value * getTrueValue() const
unsigned less or equal
Definition: InstrTypes.h:758
unsigned less than
Definition: InstrTypes.h:757
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:738
unsigned getValNo() const
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:743
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:748
This class wraps the llvm.memset intrinsic.
BasicBlock * getSuccessor(unsigned i) const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:342
unsigned const TargetRegisterInfo * TRI
F(f)
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:230
void reserve(size_type N)
Definition: SmallVector.h:369
Value * getLength() const
op_iterator op_begin()
Definition: User.h:229
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
bool isMemLoc() const
bool needsCustom() const
SI optimize exec mask operations pre RA
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:585
A description of a memory reference used in the backend.
This class represents the LLVM &#39;select&#39; instruction.
const HexagonInstrInfo * TII
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:96
Class to represent struct types.
Definition: DerivedTypes.h:238
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isUnsigned() const
Definition: InstrTypes.h:908
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:739
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getSizeInBits() const
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:888
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:246
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:119
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Value * getOperand(unsigned i) const
Definition: User.h:169
unsigned getKillRegState(bool B)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:147
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV)...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
#define P(N)
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:148
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
op_iterator op_end()
Definition: User.h:231
bool hasInternalLinkage() const
Definition: GlobalValue.h:443
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:180
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
constexpr double e
Definition: MathExtras.h:57
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:114
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const Value * getCondition() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
Extended Value Type.
Definition: ValueTypes.h:33
size_t size() const
Definition: SmallVector.h:52
static bool isAtomic(Instruction *I)
bool isVolatile() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
signed greater than
Definition: InstrTypes.h:759
The memory access writes data.
const APFloat & getValueAPF() const
Definition: Constants.h:302
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:50
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:736
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:37
unsigned getNumOperands() const
Definition: User.h:191
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
signed less than
Definition: InstrTypes.h:761
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Definition: FastISel.cpp:2066
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:241
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
signed less or equal
Definition: InstrTypes.h:762
amdgpu Simplify well known AMD library false FunctionCallee Callee
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
This file defines the FastISel class.
const MipsTargetLowering * getTargetLowering() const override
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
const Value * getFalseValue() const
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:807
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:163
unsigned getNumArgOperands() const
Definition: InstrTypes.h:1239
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:426
cl::opt< bool > EmitJalrReloc
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:607
unsigned getLocMemOffset() const
unsigned greater or equal
Definition: InstrTypes.h:756
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1287
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:382
bool isRegLoc() const
static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:735
LLVM Value Representation.
Definition: Value.h:74
bool useSoftFloat() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
bool isThreadLocal() const
If the value is "Thread Local", its value isn&#39;t shared by the threads.
Definition: GlobalValue.h:250
bool hasOneUse() const
Return true if there is exactly one user of this value.
Definition: Value.h:433
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
unsigned greater than
Definition: InstrTypes.h:755
APInt bitcastToAPInt() const
Definition: APFloat.h:1109
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:156
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
#define LLVM_DEBUG(X)
Definition: Debug.h:122
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:737
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:150
bool isFP64bit() const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void convertToReg(unsigned RegNo)
iterator_range< arg_iterator > args()
Definition: Function.h:724
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:218
signed greater or equal
Definition: InstrTypes.h:760
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:221
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:66
an instruction to allocate memory on the stack
Definition: Instructions.h:59
Helper operand used to generate R_MIPS_JALR.
Definition: MipsBaseInfo.h:94
gep_type_iterator gep_type_begin(const User *GEP)