MipsISelLowering.cpp File Reference

#include "MipsISelLowering.h"
#include "MCTargetDesc/MipsBaseInfo.h"
#include "MCTargetDesc/MipsInstPrinter.h"
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "MipsCCState.h"
#include "MipsInstrInfo.h"
#include "MipsMachineFunction.h"
#include "MipsRegisterInfo.h"
#include "MipsSubtarget.h"
#include "MipsTargetMachine.h"
#include "MipsTargetObjectFile.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cctype>
#include <cstdint>
#include <deque>
#include <iterator>
#include <regex>
#include <string>
#include <utility>
#include <vector>
#include "MipsGenCallingConv.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "mips-lower"

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static SDValue	performDivRemCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static Mips::CondCode	condCodeToFCC (ISD::CondCode CC)
static bool	invertFPCondCodeUser (Mips::CondCode CC)
	This function returns true if the floating point conditional branches and conditional moves which use condition code CC should be inverted.
static SDValue	createFPCmp (SelectionDAG &DAG, const SDValue &Op)
static SDValue	createCMovFP (SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
static SDValue	performSELECTCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue	performCMovFPCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue	performANDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue	performORCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue	performMADD_MSUBCombine (SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget)
static SDValue	performSUBCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue	performADDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue	performSHLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue	performSignExtendCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static unsigned	addLiveIn (MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
static MachineBasicBlock *	insertDivByZeroTrap (MachineInstr &MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit, bool IsMicroMips)
static SDValue	lowerFCOPYSIGN32 (SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static SDValue	lowerFCOPYSIGN64 (SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static SDValue	createLoadLR (unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
static SDValue	createStoreLR (unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
static SDValue	lowerUnalignedIntStore (StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
static SDValue	lowerFP_TO_SINT_STORE (StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat)
static bool	CC_MipsO32 (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State, ArrayRef< MCPhysReg > F64Regs)
static bool	CC_MipsO32_FP32 (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)
static bool	CC_MipsO32_FP64 (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)
static bool	CC_MipsO32 (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)
static SDValue	UnpackFromArgumentSlot (SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
static std::pair< bool, bool >	parsePhysicalReg (StringRef C, StringRef &Prefix, unsigned long long &Reg)
	This is a helper function to parse a physical register string and split it into non-numeric and numeric parts (Prefix and Reg).

Variables
cl::opt< bool >	EmitJalrReloc
cl::opt< bool >	NoZeroDivCheck
static const MCPhysReg	Mips64DPRegs [8]

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "mips-lower"

Definition at line 82 of file MipsISelLowering.cpp.

Function Documentation

addLiveIn()

unsigned addLiveIn ( MachineFunction & MF, unsigned PReg, const TargetRegisterClass * RC )

static

Definition at line 1266 of file MipsISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), llvm::MachineRegisterInfo::createVirtualRegister(), and llvm::MachineFunction::getRegInfo().

CC_MipsO32() [1/2]

bool CC_MipsO32 ( unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type * OrigTy, CCState & State )

static

CC_MipsO32() [2/2]

bool CC_MipsO32 ( unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type * OrigTy, CCState & State, ArrayRef< MCPhysReg > F64Regs )

static

Definition at line 2969 of file MipsISelLowering.cpp.

References llvm::CCValAssign::AExt, llvm::CCValAssign::AExtUpper, assert(), F32Regs, llvm::CCValAssign::getCustomReg(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::MVT::getStoreSize(), IntRegs, llvm::ISD::ArgFlagsTy::isByVal(), llvm::MVT::isFloatingPoint(), llvm::Type::isFPOrFPVectorTy(), llvm::ISD::ArgFlagsTy::isInReg(), llvm::MipsSubtarget::isLittle(), llvm::ISD::ArgFlagsTy::isSExt(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::Type::isVectorTy(), llvm::ISD::ArgFlagsTy::isZExt(), llvm_unreachable, llvm::Offset, Reg, llvm::CCValAssign::SExt, llvm::CCValAssign::SExtUpper, llvm::CCValAssign::ZExt, and llvm::CCValAssign::ZExtUpper.

Referenced by CC_MipsO32_FP32(), and CC_MipsO32_FP64().

CC_MipsO32_FP32()

bool CC_MipsO32_FP32 ( unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type * OrigTy, CCState & State )

static

Definition at line 3090 of file MipsISelLowering.cpp.

References CC_MipsO32().

CC_MipsO32_FP64()

bool CC_MipsO32_FP64 ( unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type * OrigTy, CCState & State )

static

Definition at line 3100 of file MipsISelLowering.cpp.

References CC_MipsO32().

condCodeToFCC()

Mips::CondCode condCodeToFCC ( ISD::CondCode CC )

static

Definition at line 509 of file MipsISelLowering.cpp.

References llvm::Mips::FCOND_OEQ, llvm::Mips::FCOND_OGE, llvm::Mips::FCOND_OGT, llvm::Mips::FCOND_OLE, llvm::Mips::FCOND_OLT, llvm::Mips::FCOND_ONE, llvm::Mips::FCOND_OR, llvm::Mips::FCOND_UEQ, llvm::Mips::FCOND_UGE, llvm::Mips::FCOND_UGT, llvm::Mips::FCOND_ULE, llvm::Mips::FCOND_ULT, llvm::Mips::FCOND_UN, llvm::Mips::FCOND_UNE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

Referenced by createFPCmp().

createCMovFP()

SDValue createCMovFP ( SelectionDAG & DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc & DL )

static

Definition at line 572 of file MipsISelLowering.cpp.

References llvm::cast(), Cond, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getValueType(), and invertFPCondCodeUser().

createFPCmp()

SDValue createFPCmp ( SelectionDAG & DAG, const SDValue & Op )

static

Definition at line 549 of file MipsISelLowering.cpp.

References llvm::cast(), condCodeToFCC(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), LHS, RHS, llvm::ISD::SETCC, llvm::ISD::STRICT_FSETCC, and llvm::ISD::STRICT_FSETCCS.

createLoadLR()

SDValue createLoadLR ( unsigned Opc, SelectionDAG & DAG, LoadSDNode * LD, SDValue Chain, SDValue Src, unsigned Offset )

static

Definition at line 2747 of file MipsISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::Offset, and Opc.

Referenced by llvm::MipsTargetLowering::lowerLOAD().

createStoreLR()

SDValue createStoreLR ( unsigned Opc, SelectionDAG & DAG, StoreSDNode * SD, SDValue Chain, unsigned Offset )

static

Definition at line 2829 of file MipsISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, DL, llvm::StoreSDNode::getBasePtr(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::Offset, and Opc.

Referenced by lowerUnalignedIntStore().

insertDivByZeroTrap()

MachineBasicBlock * insertDivByZeroTrap ( MachineInstr & MI, MachineBasicBlock & MBB, const TargetInstrInfo & TII, bool Is64Bit, bool IsMicroMips )

static

Definition at line 1273 of file MipsISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isKill(), MBB, MI, NoZeroDivCheck, llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setSubReg(), and TII.

invertFPCondCodeUser()

bool invertFPCondCodeUser ( Mips::CondCode CC )

static

This function returns true if the floating point conditional branches and conditional moves which use condition code CC should be inverted.

Definition at line 537 of file MipsISelLowering.cpp.

References assert(), llvm::Mips::FCOND_F, llvm::Mips::FCOND_GT, llvm::Mips::FCOND_NGT, and llvm::Mips::FCOND_T.

Referenced by createCMovFP().

lowerFCOPYSIGN32()

SDValue lowerFCOPYSIGN32 ( SDValue Op, SelectionDAG & DAG, bool HasExtractInsert )

static

Definition at line 2397 of file MipsISelLowering.cpp.

References llvm::ISD::BITCAST, DL, E(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRL, X, and Y.

lowerFCOPYSIGN64()

SDValue lowerFCOPYSIGN64 ( SDValue Op, SelectionDAG & DAG, bool HasExtractInsert )

static

Definition at line 2444 of file MipsISelLowering.cpp.

References llvm::ISD::BITCAST, DL, E(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), I, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::TRUNCATE, X, Y, and llvm::ISD::ZERO_EXTEND.

lowerFP_TO_SINT_STORE()

SDValue lowerFP_TO_SINT_STORE ( StoreSDNode * SD, SelectionDAG & DAG, bool SingleFloat )

static

Definition at line 2875 of file MipsISelLowering.cpp.

References llvm::ISD::FP_TO_SINT, llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getFloatingPointVT(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueSizeInBits(), and SDValue().

Referenced by llvm::MipsTargetLowering::lowerSTORE().

lowerUnalignedIntStore()

SDValue lowerUnalignedIntStore ( StoreSDNode * SD, SelectionDAG & DAG, bool IsLittle )

static

Definition at line 2846 of file MipsISelLowering.cpp.

References assert(), createStoreLR(), llvm::MemSDNode::getChain(), llvm::StoreSDNode::getValue(), and llvm::StoreSDNode::isTruncatingStore().

Referenced by llvm::MipsTargetLowering::lowerSTORE().

parsePhysicalReg()

std::pair< bool, bool > parsePhysicalReg ( StringRef C, StringRef & Prefix, unsigned long long & Reg )

static

This is a helper function to parse a physical register string and split it into non-numeric and numeric parts (Prefix and Reg).

The first boolean flag that is returned indicates whether parsing was successful. The second flag is true if the numeric part exists.

Definition at line 4123 of file MipsISelLowering.cpp.

References B(), llvm::CallingConv::C, E(), llvm::getAsUnsignedInteger(), I, and Reg.

performADDCombine()

SDValue performADDCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 1024 of file MipsISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MipsSubtarget::hasMips32(), llvm::MipsSubtarget::hasMips32r6(), llvm::MipsSubtarget::inMips16Mode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::Lo, N, llvm::Other, performMADD_MSUBCombine(), SDValue(), std::swap(), and llvm::ISD::TargetJumpTable.

Referenced by llvm::MipsTargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().

performANDCombine()

SDValue performANDCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 690 of file MipsISelLowering.cpp.

References DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsSubtarget::hasCnMips(), llvm::MipsSubtarget::hasExtractInsert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, Opc, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

performCMovFPCombine()

SDValue performCMovFPCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 663 of file MipsISelLowering.cpp.

References llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, Opc, and SDValue().

Referenced by llvm::MipsTargetLowering::PerformDAGCombine().

performDivRemCombine()

SDValue performDivRemCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 472 of file MipsISelLowering.cpp.

References DL, llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, Opc, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SDIVREM, and SDValue().

Referenced by llvm::MipsTargetLowering::PerformDAGCombine().

performMADD_MSUBCombine()

SDValue performMADD_MSUBCombine ( SDNode * ROOTNode, SelectionDAG & CurDAG, const MipsSubtarget & Subtarget )

static

Definition at line 914 of file MipsISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MipsSubtarget::hasMips64(), llvm::SDValue::hasOneUse(), llvm::EVT::isVector(), llvm::ISD::MUL, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::SplitScalar(), llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by performADDCombine(), and performSUBCombine().

performORCombine()

SDValue performORCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 773 of file MipsISelLowering.cpp.

References llvm::ISD::AND, assert(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsSubtarget::hasExtractInsert(), llvm::MipsSubtarget::hasMips64r2(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, SDValue(), llvm::ISD::SHL, and llvm::ISD::SRL.

performSELECTCombine()

SDValue performSELECTCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 582 of file MipsISelLowering.cpp.

References llvm::ISD::ADD, llvm::cast(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isInteger(), N, SDValue(), llvm::ISD::SELECT, and llvm::ISD::SETCC.

Referenced by llvm::MipsTargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().

performSHLCombine()

SDValue performSHLCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 1063 of file MipsISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsSubtarget::hasCnMips(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, and SDValue().

performSignExtendCombine()

SDValue performSignExtendCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 1115 of file MipsISelLowering.cpp.

References llvm::AfterLegalizeDAG, llvm::ISD::Constant, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::MipsSubtarget::isGP64bit(), llvm::TargetLowering::DAGCombinerInfo::Level, N, SDValue(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::TRUNCATE, and llvm::ISD::XOR.

Referenced by llvm::MipsTargetLowering::PerformDAGCombine().

performSUBCombine()

SDValue performSUBCombine ( SDNode * N, SelectionDAG & DAG, TargetLowering::DAGCombinerInfo & DCI, const MipsSubtarget & Subtarget )

static

Definition at line 1009 of file MipsISelLowering.cpp.

References llvm::MipsSubtarget::hasMips32(), llvm::MipsSubtarget::hasMips32r6(), llvm::MipsSubtarget::inMips16Mode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, performMADD_MSUBCombine(), and SDValue().

Referenced by llvm::MipsTargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"	)

References EmitJalrReloc, and NoZeroDivCheck.

UnpackFromArgumentSlot()

SDValue UnpackFromArgumentSlot ( SDValue Val, const CCValAssign & VA, EVT ArgVT, const SDLoc & DL, SelectionDAG & DAG )

static

Definition at line 3676 of file MipsISelLowering.cpp.

References llvm::CCValAssign::AExt, llvm::CCValAssign::AExtUpper, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getConstant(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::CCValAssign::getValVT(), llvm_unreachable, llvm::CCValAssign::SExt, llvm::CCValAssign::SExtUpper, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::CCValAssign::ZExt, and llvm::CCValAssign::ZExtUpper.

Variable Documentation

EmitJalrReloc

cl::opt<bool> EmitJalrReloc

extern

Mips64DPRegs

const MCPhysReg Mips64DPRegs[8]

static

Initial value:

= {
  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
}

Definition at line 89 of file MipsISelLowering.cpp.

Referenced by llvm::MipsTargetLowering::HandleByVal().

NoZeroDivCheck

cl::opt<bool> NoZeroDivCheck

extern