LLVM 19.0.0git
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#include "MipsISelLowering.h"
#include "MCTargetDesc/MipsBaseInfo.h"
#include "MCTargetDesc/MipsInstPrinter.h"
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "MipsCCState.h"
#include "MipsInstrInfo.h"
#include "MipsMachineFunction.h"
#include "MipsRegisterInfo.h"
#include "MipsSubtarget.h"
#include "MipsTargetMachine.h"
#include "MipsTargetObjectFile.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cctype>
#include <cstdint>
#include <deque>
#include <iterator>
#include <utility>
#include <vector>
#include "MipsGenCallingConv.inc"
Go to the source code of this file.
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#define | DEBUG_TYPE "mips-lower" |
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static cl::opt< bool > | NoZeroDivCheck ("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false)) |
cl::opt< bool > | EmitJalrReloc |
static const MCPhysReg | Mips64DPRegs [8] |
#define DEBUG_TYPE "mips-lower" |
Definition at line 82 of file MipsISelLowering.cpp.
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Definition at line 1287 of file MipsISelLowering.cpp.
References llvm::MachineRegisterInfo::addLiveIn(), llvm::MachineRegisterInfo::createVirtualRegister(), and llvm::MachineFunction::getRegInfo().
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Definition at line 2899 of file MipsISelLowering.cpp.
References llvm::CCState::addLoc(), llvm::CCValAssign::AExt, llvm::CCValAssign::AExtUpper, llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), assert(), F32Regs, llvm::CCValAssign::getCustomReg(), llvm::CCState::getFirstUnallocated(), llvm::CCState::getMachineFunction(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::MVT::getStoreSize(), llvm::MachineFunction::getSubtarget(), IntRegs, llvm::ISD::ArgFlagsTy::isByVal(), llvm::MVT::isFloatingPoint(), llvm::ISD::ArgFlagsTy::isInReg(), llvm::MipsSubtarget::isLittle(), llvm::ISD::ArgFlagsTy::isSExt(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::CCState::isVarArg(), llvm::ISD::ArgFlagsTy::isZExt(), llvm_unreachable, llvm::Offset, llvm::CCValAssign::SExt, llvm::CCValAssign::SExtUpper, llvm::MipsCCState::WasOriginalArgVectorFloat(), llvm::CCValAssign::ZExt, and llvm::CCValAssign::ZExtUpper.
Referenced by CC_MipsO32_FP32(), and CC_MipsO32_FP64().
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Definition at line 3021 of file MipsISelLowering.cpp.
References CC_MipsO32().
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Definition at line 3029 of file MipsISelLowering.cpp.
References CC_MipsO32().
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Definition at line 623 of file MipsISelLowering.cpp.
References CC, llvm::Mips::FCOND_OEQ, llvm::Mips::FCOND_OGE, llvm::Mips::FCOND_OGT, llvm::Mips::FCOND_OLE, llvm::Mips::FCOND_OLT, llvm::Mips::FCOND_ONE, llvm::Mips::FCOND_OR, llvm::Mips::FCOND_UEQ, llvm::Mips::FCOND_UGE, llvm::Mips::FCOND_UGT, llvm::Mips::FCOND_ULE, llvm::Mips::FCOND_ULT, llvm::Mips::FCOND_UN, llvm::Mips::FCOND_UNE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.
Referenced by createFPCmp().
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Definition at line 685 of file MipsISelLowering.cpp.
References CC, llvm::MipsISD::CMovFP_F, llvm::MipsISD::CMovFP_T, Cond, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getValueType(), and invertFPCondCodeUser().
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Definition at line 663 of file MipsISelLowering.cpp.
References CC, condCodeToFCC(), DL, llvm::MipsISD::FPCmp, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), LHS, RHS, and llvm::ISD::SETCC.
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Definition at line 2696 of file MipsISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::Offset, and Ptr.
Referenced by llvm::MipsTargetLowering::lowerLOAD().
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Definition at line 2778 of file MipsISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::StoreSDNode::getBasePtr(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::StoreSDNode::getValue(), llvm::SelectionDAG::getVTList(), llvm::Offset, and Ptr.
Referenced by lowerUnalignedIntStore().
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Definition at line 1294 of file MipsISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isKill(), MBB, MI, NoZeroDivCheck, llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setSubReg(), and TII.
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This function returns true if the floating point conditional branches and conditional moves which use condition code CC should be inverted.
Definition at line 651 of file MipsISelLowering.cpp.
References assert(), CC, llvm::Mips::FCOND_F, llvm::Mips::FCOND_GT, llvm::Mips::FCOND_NGT, and llvm::Mips::FCOND_T.
Referenced by createCMovFP().
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Definition at line 2357 of file MipsISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::MipsISD::BuildPairF64, DL, llvm::MipsISD::Ext, llvm::MipsISD::ExtractElementF64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MipsISD::Ins, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRL, X, and Y.
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Definition at line 2404 of file MipsISelLowering.cpp.
References llvm::ISD::BITCAST, DL, llvm::MipsISD::Ext, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), I, llvm::MipsISD::Ins, llvm::Or, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::TRUNCATE, X, Y, and llvm::ISD::ZERO_EXTEND.
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Definition at line 2824 of file MipsISelLowering.cpp.
References llvm::ISD::FP_TO_SINT, llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getFloatingPointVT(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueSizeInBits(), and llvm::MipsISD::TruncIntFP.
Referenced by llvm::MipsTargetLowering::lowerSTORE().
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Definition at line 2795 of file MipsISelLowering.cpp.
References assert(), createStoreLR(), llvm::MemSDNode::getChain(), llvm::StoreSDNode::getValue(), llvm::StoreSDNode::isTruncatingStore(), llvm::MipsISD::SDL, llvm::MipsISD::SDR, llvm::MipsISD::SWL, and llvm::MipsISD::SWR.
Referenced by llvm::MipsTargetLowering::lowerSTORE().
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This is a helper function to parse a physical register string and split it into non-numeric and numeric parts (Prefix and Reg).
The first boolean flag that is returned indicates whether parsing was successful. The second flag is true if the numeric part exists.
Definition at line 4043 of file MipsISelLowering.cpp.
References B, llvm::CallingConv::C, llvm::getAsUnsignedInteger(), and I.
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Definition at line 1095 of file MipsISelLowering.cpp.
References llvm::Add, llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::MipsSubtarget::hasMips32(), llvm::MipsSubtarget::hasMips32r6(), llvm::MipsSubtarget::inMips16Mode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::MipsISD::Lo, llvm::Lo, N, performMADD_MSUBCombine(), and llvm::ISD::TargetJumpTable.
Referenced by llvm::MipsTargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 803 of file MipsISelLowering.cpp.
References llvm::MipsISD::CIns, DL, llvm::MipsISD::Ext, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsSubtarget::hasCnMips(), llvm::MipsSubtarget::hasExtractInsert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
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Definition at line 776 of file MipsISelLowering.cpp.
References llvm::MipsISD::CMovFP_F, llvm::MipsISD::CMovFP_T, llvm::SelectionDAG::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and N.
Referenced by llvm::MipsTargetLowering::PerformDAGCombine().
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Definition at line 586 of file MipsISelLowering.cpp.
References llvm::MipsISD::DivRem16, llvm::MipsISD::DivRemU16, DL, llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and llvm::ISD::SDIVREM.
Referenced by llvm::MipsTargetLowering::PerformDAGCombine().
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Definition at line 984 of file MipsISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MipsSubtarget::hasMips64(), llvm::EVT::isVector(), llvm::MipsISD::MAdd, llvm::MipsISD::MAddu, llvm::MipsISD::MFHI, llvm::MipsISD::MFLO, llvm::MipsISD::MSub, llvm::MipsISD::MSubu, llvm::MipsISD::MTLOHI, llvm::ISD::MUL, llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::SplitScalar(), llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by performADDCombine(), and performSUBCombine().
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Definition at line 886 of file MipsISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsSubtarget::hasExtractInsert(), llvm::MipsSubtarget::hasMips64r2(), llvm::MipsISD::Ins, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
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Definition at line 695 of file MipsISelLowering.cpp.
References llvm::ISD::ADD, CC, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isInteger(), N, llvm::ISD::SELECT, and llvm::ISD::SETCC.
Referenced by llvm::MipsTargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().
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Definition at line 1127 of file MipsISelLowering.cpp.
References llvm::ISD::AND, llvm::MipsISD::CIns, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsSubtarget::hasCnMips(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), and N.
Referenced by llvm::MipsTargetLowering::PerformDAGCombine(), and llvm::MipsSETargetLowering::PerformDAGCombine().
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Definition at line 1080 of file MipsISelLowering.cpp.
References llvm::MipsSubtarget::hasMips32(), llvm::MipsSubtarget::hasMips32r6(), llvm::MipsSubtarget::inMips16Mode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, and performMADD_MSUBCombine().
Referenced by llvm::MipsTargetLowering::PerformDAGCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().
STATISTIC | ( | NumTailCalls | , |
"Number of tail calls" | |||
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Definition at line 3596 of file MipsISelLowering.cpp.
References llvm::CCValAssign::AExt, llvm::CCValAssign::AExtUpper, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getConstant(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::CCValAssign::getValVT(), llvm_unreachable, llvm::CCValAssign::SExt, llvm::CCValAssign::SExtUpper, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::CCValAssign::ZExt, and llvm::CCValAssign::ZExtUpper.
Definition at line 93 of file MipsISelLowering.cpp.
Referenced by llvm::MipsTargetLowering::HandleByVal().
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Referenced by insertDivByZeroTrap().