LLVM  16.0.0git
MipsMCTargetDesc.h
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1 //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 
18 #include <memory>
19 
20 namespace llvm {
21 class MCAsmBackend;
22 class MCCodeEmitter;
23 class MCContext;
24 class MCInstrInfo;
25 class MCObjectTargetWriter;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class MCTargetOptions;
29 class StringRef;
30 class Target;
31 class Triple;
32 
33 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
34  MCContext &Ctx);
35 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
36  MCContext &Ctx);
37 
38 MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
39  const MCRegisterInfo &MRI,
40  const MCTargetOptions &Options);
41 
42 std::unique_ptr<MCObjectTargetWriter>
43 createMipsELFObjectWriter(const Triple &TT, bool IsN32);
44 
45 namespace MIPS_MC {
46 StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
47 }
48 
49 } // End llvm namespace
50 
51 // Defines symbolic names for Mips registers. This defines a mapping from
52 // register name to register number.
53 #define GET_REGINFO_ENUM
54 #include "MipsGenRegisterInfo.inc"
55 
56 // Defines symbolic names for the Mips instructions.
57 #define GET_INSTRINFO_ENUM
58 #define GET_INSTRINFO_MC_HELPER_DECLS
59 #include "MipsGenInstrInfo.inc"
60 
61 #define GET_SUBTARGETINFO_ENUM
62 #include "MipsGenSubtargetInfo.inc"
63 
64 #endif
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::createMipsAsmBackend
MCAsmBackend * createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: MipsAsmBackend.cpp:598
llvm::createMipsMCCodeEmitterEL
MCCodeEmitter * createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: MipsMCCodeEmitter.cpp:49
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:858
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createMipsMCCodeEmitterEB
MCCodeEmitter * createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: MipsMCCodeEmitter.cpp:44
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createMipsELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createMipsELFObjectWriter(const Triple &TT, bool IsN32)
Definition: MipsELFObjectWriter.cpp:666
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MIPS_MC::selectMipsCPU
StringRef selectMipsCPU(const Triple &TT, StringRef CPU)
Select the Mips CPU for the given triple and cpu name.
Definition: MipsMCTargetDesc.cpp:49
DataTypes.h