36#define DEBUG_TYPE "mccodeemitter"
38#define GET_INSTRMAP_INFO
39#include "MipsGenInstrInfo.inc"
40#undef GET_INSTRMAP_INFO
90void MipsMCCodeEmitter::LowerCompactBranch(
MCInst& Inst)
const {
101 assert(Reg0 != Reg1 &&
"Instruction has bad operands ($rs == $rt)!");
107 }
else if (Inst.
getOpcode() == Mips::BNVC_MMR6 ||
119 return STI.
hasFeature(Mips::FeatureMicroMips);
137 if (IsLittleEndian &&
Size == 4 && isMicroMips(STI)) {
141 for (
unsigned i = 0; i <
Size; ++i) {
142 unsigned Shift = IsLittleEndian ? i * 8 : (
Size - 1 - i) * 8;
160 switch (
MI.getOpcode()) {
174 case Mips::BOVC_MMR6:
176 case Mips::BNVC_MMR6:
177 LowerCompactBranch(TmpInst);
180 size_t N = Fixups.size();
186 const unsigned Opcode = TmpInst.
getOpcode();
187 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
188 (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary)
192 if (isMicroMips(STI)) {
193 if (isMips32r6(STI)) {
194 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
196 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
199 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
203 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
205 if (NewOpcode != -1) {
206 if (Fixups.size() >
N)
213 if (((
MI.getOpcode() == Mips::MOVEP_MM) ||
214 (
MI.getOpcode() == Mips::MOVEP_MMR6))) {
216 Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7);
243 "getBranchTargetOpValue expects only expressions or immediates");
265 "getBranchTargetOpValue expects only expressions or immediates");
288 "getBranchTargetOpValueMMR6 expects only expressions or immediates");
311 "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates");
333 "getBranchTargetOpValueMM expects only expressions or immediates");
354 "getBranchTargetOpValuePC10 expects only expressions or immediates");
375 "getBranchTargetOpValueMM expects only expressions or immediates");
380 fixup_MICROMIPS_PC16_S1)));
397 "getBranchTarget21OpValue expects only expressions or immediates");
419 "getBranchTarget21OpValueMM expects only expressions or immediates");
441 "getBranchTarget26OpValue expects only expressions or immediates");
463 "getBranchTarget26OpValueMM expects only expressions or immediates");
484 "getJumpOffset16OpValue expects only expressions or an immediate");
505 "getJumpTargetOpValue expects only expressions or an immediate");
522 "getJumpTargetOpValueMM expects only expressions or an immediate");
543 "getUImm5Lsl2Encoding expects only expressions or an immediate");
580 unsigned Binary = (MO.
getImm() >> 2) & 0x0000ffff;
581 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
592 if (Expr->evaluateAsAbsolute(Res))
597 return cast<MCConstantExpr>(Expr)->getValue();
603 Res +=
getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
608 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
736 unsigned Reg = MO.
getReg();
739 }
else if (MO.
isImm()) {
740 return static_cast<unsigned>(MO.
getImm());
742 return static_cast<unsigned>(bit_cast<double>(MO.
getDFPImm()));
751template <
unsigned ShiftAmount>
756 assert(
MI.getOperand(OpNo).isReg());
762 OffBits >>= ShiftAmount;
764 return (OffBits & 0xFFFF) | RegBits;
772 assert(
MI.getOperand(OpNo).isReg());
778 return (OffBits & 0xF) | RegBits;
786 assert(
MI.getOperand(OpNo).isReg());
792 return (OffBits & 0xF) | RegBits;
800 assert(
MI.getOperand(OpNo).isReg());
806 return (OffBits & 0xF) | RegBits;
814 assert(
MI.getOperand(OpNo).isReg() &&
815 (
MI.getOperand(OpNo).getReg() == Mips::SP ||
816 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
817 "Unexpected base register!");
821 return OffBits & 0x1F;
829 assert(
MI.getOperand(OpNo).isReg() &&
830 MI.getOperand(OpNo).getReg() == Mips::GP &&
831 "Unexpected base register!");
836 return OffBits & 0x7F;
844 assert(
MI.getOperand(OpNo).isReg());
850 return (OffBits & 0x1FF) | RegBits;
858 assert(
MI.getOperand(OpNo).isReg());
863 return (OffBits & 0x07FF) | RegBits;
872 switch (
MI.getOpcode()) {
877 OpNo =
MI.getNumOperands() - 2;
882 assert(
MI.getOperand(OpNo).isReg());
887 return (OffBits & 0x0FFF) | RegBits;
895 assert(
MI.getOperand(OpNo).isReg());
900 return (OffBits & 0xFFFF) | RegBits;
909 switch (
MI.getOpcode()) {
913 case Mips::SWM16_MMR6:
915 case Mips::LWM16_MMR6:
916 OpNo =
MI.getNumOperands() - 2;
921 assert(
MI.getOperand(OpNo).isReg());
923 assert(
MI.getOperand(OpNo+1).isImm());
926 return ((OffBits >> 2) & 0x0F);
935 assert(
MI.getOperand(OpNo-1).isImm());
936 assert(
MI.getOperand(OpNo).isImm());
940 return Position +
Size - 1;
943template <
unsigned Bits,
int Offset>
948 assert(
MI.getOperand(OpNo).isImm());
967 "getSimm19Lsl2Encoding expects only expressions or an immediate");
989 "getSimm18Lsl2Encoding expects only expressions or an immediate");
1002 assert(
MI.getOperand(OpNo).isImm());
1011 assert(
MI.getOperand(OpNo).isImm());
1015 case 128:
return 0x0;
1022 case 15:
return 0x7;
1023 case 16:
return 0x8;
1024 case 31:
return 0x9;
1025 case 32:
return 0xa;
1026 case 63:
return 0xb;
1027 case 64:
return 0xc;
1028 case 255:
return 0xd;
1029 case 32768:
return 0xe;
1030 case 65535:
return 0xf;
1044 for (
unsigned I = OpNo,
E =
MI.getNumOperands() - 2;
I <
E; ++
I) {
1045 unsigned Reg =
MI.getOperand(
I).getReg();
1059 return (
MI.getNumOperands() - 4);
1068 if (
MI.getOperand(0).getReg() == Mips::A1 &&
1069 MI.getOperand(1).getReg() == Mips::A2)
1071 else if (
MI.getOperand(0).getReg() == Mips::A1 &&
1072 MI.getOperand(1).getReg() == Mips::A3)
1074 else if (
MI.getOperand(0).getReg() == Mips::A2 &&
1075 MI.getOperand(1).getReg() == Mips::A3)
1077 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1078 MI.getOperand(1).getReg() == Mips::S5)
1080 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1081 MI.getOperand(1).getReg() == Mips::S6)
1083 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1084 MI.getOperand(1).getReg() == Mips::A1)
1086 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1087 MI.getOperand(1).getReg() == Mips::A2)
1089 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1090 MI.getOperand(1).getReg() == Mips::A3)
1100 assert(((OpNo == 2) || (OpNo == 3)) &&
1101 "Unexpected OpNo for movep operand encoding!");
1104 assert(Op.isReg() &&
"Operand of movep is not a register!");
1105 switch (Op.getReg()) {
1108 case Mips::ZERO:
return 0;
1109 case Mips::S1:
return 1;
1110 case Mips::V0:
return 2;
1111 case Mips::V1:
return 3;
1112 case Mips::S0:
return 4;
1113 case Mips::S2:
return 5;
1114 case Mips::S3:
return 6;
1115 case Mips::S4:
return 7;
1124 assert(MO.
isImm() &&
"getSimm23Lsl2Encoding expects only an immediate");
1126 unsigned Res =
static_cast<unsigned>(MO.
getImm());
1131#include "MipsGenMCCodeEmitter.inc"
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static void LowerLargeShift(MCInst &Inst)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
void reportError(SMLoc L, const Twine &Msg)
Base class for the full range of assembler expressions which are needed for parsing.
@ Constant
Constant expressions.
@ SymbolRef
References to labels and assigned expressions.
@ Target
Target specific expression.
@ Binary
Binary expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
void setReg(unsigned Reg)
Set the register number.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
uint64_t getDFPImm() const
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch target operand.
unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget21OpValue - Return binary encoding of the branch target operand.
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getMachineOpValue - Return binary encoding of operand.
unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Subtract Offset then encode as a N-bit unsigned integer.
unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueMMR6 - Return binary encoding of the branch target operand.
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue - Return binary encoding of the branch target operand.
unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Return binary encoding of memory related operand.
unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget26OpValue - Return binary encoding of the branch target operand.
unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget26OpValueMM - Return binary encoding of the branch target operand.
unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue1SImm16 - Return binary encoding of the branch target operand.
unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
encodeInstruction - Emit the instruction.
unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getJumpOffset16OpValue - Return binary encoding of the jump target operand.
unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand.
unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getJumpTargetOpValue - Return binary encoding of the jump target operand.
unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand.
unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget21OpValueMM - Return binary encoding of the branch target operand for microMIPS.
unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand.
unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const
void EmitByte(unsigned char C, raw_ostream &OS) const
unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
const MCExpr * getSubExpr() const
Get the child of this expression.
MipsExprKind getKind() const
Get the kind of this expression.
bool isGpOff(MipsExprKind &Kind) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ fixup_MICROMIPS_TLS_TPREL_LO16
@ fixup_MICROMIPS_GOT_PAGE
@ fixup_MICROMIPS_TLS_TPREL_HI16
@ fixup_MICROMIPS_PC21_S1
@ fixup_MICROMIPS_GPOFF_LO
@ fixup_MICROMIPS_PC19_S2
@ fixup_MICROMIPS_TLS_LDM
@ fixup_MICROMIPS_GOT_OFST
@ fixup_MICROMIPS_TLS_DTPREL_HI16
@ fixup_MICROMIPS_PC10_S1
@ fixup_MICROMIPS_HIGHEST
@ fixup_MICROMIPS_GOT_DISP
@ fixup_MICROMIPS_PC18_S3
@ fixup_MICROMIPS_PC26_S1
@ fixup_MICROMIPS_GOTTPREL
@ fixup_MICROMIPS_TLS_DTPREL_LO16
@ fixup_MICROMIPS_GPOFF_HI
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCContext &Ctx)
MCCodeEmitter * createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, MCContext &Ctx)
MCFixupKind
Extensible enumeration to represent the type of a fixup.