LLVM 18.0.0git
MipsMCCodeEmitter.cpp
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1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the MipsMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsMCCodeEmitter.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCFixup.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrDesc.h"
25#include "llvm/MC/MCInstrInfo.h"
32#include <cassert>
33#include <cstdint>
34
35using namespace llvm;
36
37#define DEBUG_TYPE "mccodeemitter"
38
39#define GET_INSTRMAP_INFO
40#include "MipsGenInstrInfo.inc"
41#undef GET_INSTRMAP_INFO
42
43namespace llvm {
44
46 MCContext &Ctx) {
47 return new MipsMCCodeEmitter(MCII, Ctx, false);
48}
49
51 MCContext &Ctx) {
52 return new MipsMCCodeEmitter(MCII, Ctx, true);
53}
54
55} // end namespace llvm
56
57// If the D<shift> instruction has a shift amount that is greater
58// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
59static void LowerLargeShift(MCInst& Inst) {
60 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
61 assert(Inst.getOperand(2).isImm());
62
63 int64_t Shift = Inst.getOperand(2).getImm();
64 if (Shift <= 31)
65 return; // Do nothing
66 Shift -= 32;
67
68 // saminus32
69 Inst.getOperand(2).setImm(Shift);
70
71 switch (Inst.getOpcode()) {
72 default:
73 // Calling function is not synchronized
74 llvm_unreachable("Unexpected shift instruction");
75 case Mips::DSLL:
76 Inst.setOpcode(Mips::DSLL32);
77 return;
78 case Mips::DSRL:
79 Inst.setOpcode(Mips::DSRL32);
80 return;
81 case Mips::DSRA:
82 Inst.setOpcode(Mips::DSRA32);
83 return;
84 case Mips::DROTR:
85 Inst.setOpcode(Mips::DROTR32);
86 return;
87 }
88}
89
90// Fix a bad compact branch encoding for beqc/bnec.
91void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
92 // Encoding may be illegal !(rs < rt), but this situation is
93 // easily fixed.
94 unsigned RegOp0 = Inst.getOperand(0).getReg();
95 unsigned RegOp1 = Inst.getOperand(1).getReg();
96
97 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
98 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
99
100 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
101 Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
102 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
103 if (Reg0 < Reg1)
104 return;
105 } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
106 if (Reg0 >= Reg1)
107 return;
108 } else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||
109 Inst.getOpcode() == Mips::BOVC_MMR6) {
110 if (Reg1 >= Reg0)
111 return;
112 } else
113 llvm_unreachable("Cannot rewrite unknown branch!");
114
115 Inst.getOperand(0).setReg(RegOp1);
116 Inst.getOperand(1).setReg(RegOp0);
117}
118
119bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
120 return STI.hasFeature(Mips::FeatureMicroMips);
121}
122
123bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
124 return STI.hasFeature(Mips::FeatureMips32r6);
125}
126
127void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
128 OS << (char)C;
129}
130
131/// encodeInstruction - Emit the instruction.
132/// Size the instruction with Desc.getSize().
136 const MCSubtargetInfo &STI) const {
137 // Non-pseudo instructions that get changed for direct object
138 // only based on operand values.
139 // If this list of instructions get much longer we will move
140 // the check to a function call. Until then, this is more efficient.
141 MCInst TmpInst = MI;
142 switch (MI.getOpcode()) {
143 // If shift amount is >= 32 it the inst needs to be lowered further
144 case Mips::DSLL:
145 case Mips::DSRL:
146 case Mips::DSRA:
147 case Mips::DROTR:
148 LowerLargeShift(TmpInst);
149 break;
150 // Compact branches, enforce encoding restrictions.
151 case Mips::BEQC:
152 case Mips::BNEC:
153 case Mips::BEQC64:
154 case Mips::BNEC64:
155 case Mips::BOVC:
156 case Mips::BOVC_MMR6:
157 case Mips::BNVC:
158 case Mips::BNVC_MMR6:
159 LowerCompactBranch(TmpInst);
160 }
161
162 size_t N = Fixups.size();
163 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
164
165 // Check for unimplemented opcodes.
166 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
167 // so we have to special check for them.
168 const unsigned Opcode = TmpInst.getOpcode();
169 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
170 (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary)
171 llvm_unreachable("unimplemented opcode in encodeInstruction()");
172
173 int NewOpcode = -1;
174 if (isMicroMips(STI)) {
175 if (isMips32r6(STI)) {
176 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
177 if (NewOpcode == -1)
178 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
179 }
180 else
181 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
182
183 // Check whether it is Dsp instruction.
184 if (NewOpcode == -1)
185 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
186
187 if (NewOpcode != -1) {
188 if (Fixups.size() > N)
189 Fixups.pop_back();
190
191 TmpInst.setOpcode (NewOpcode);
192 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
193 }
194
195 if (((MI.getOpcode() == Mips::MOVEP_MM) ||
196 (MI.getOpcode() == Mips::MOVEP_MMR6))) {
197 unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI);
198 Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7);
199 }
200 }
201
202 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
203
204 // Get byte count of instruction
205 unsigned Size = Desc.getSize();
206 if (!Size)
207 llvm_unreachable("Desc.getSize() returns 0");
208
209 auto Endian = IsLittleEndian ? support::little : support::big;
210 if (Size == 2) {
211 support::endian::write<uint16_t>(CB, Binary, Endian);
212 } else if (IsLittleEndian && isMicroMips(STI)) {
213 support::endian::write<uint16_t>(CB, Binary >> 16, Endian);
214 support::endian::write<uint16_t>(CB, Binary & 0xffff, Endian);
215 } else {
216 support::endian::write<uint32_t>(CB, Binary, Endian);
217 }
218}
219
220/// getBranchTargetOpValue - Return binary encoding of the branch
221/// target operand. If the machine operand requires relocation,
222/// record the relocation and return zero.
224getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
226 const MCSubtargetInfo &STI) const {
227 const MCOperand &MO = MI.getOperand(OpNo);
228
229 // If the destination is an immediate, divide by 4.
230 if (MO.isImm()) return MO.getImm() >> 2;
231
232 assert(MO.isExpr() &&
233 "getBranchTargetOpValue expects only expressions or immediates");
234
235 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
236 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
237 Fixups.push_back(MCFixup::create(0, FixupExpression,
239 return 0;
240}
241
242/// getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
243/// target operand. If the machine operand requires relocation,
244/// record the relocation and return zero.
246getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
248 const MCSubtargetInfo &STI) const {
249 const MCOperand &MO = MI.getOperand(OpNo);
250
251 // If the destination is an immediate, divide by 2.
252 if (MO.isImm()) return MO.getImm() >> 1;
253
254 assert(MO.isExpr() &&
255 "getBranchTargetOpValue expects only expressions or immediates");
256
257 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
258 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
259 Fixups.push_back(MCFixup::create(0, FixupExpression,
261 return 0;
262}
263
264/// getBranchTargetOpValueMMR6 - Return binary encoding of the branch
265/// target operand. If the machine operand requires relocation,
266/// record the relocation and return zero.
268getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
270 const MCSubtargetInfo &STI) const {
271 const MCOperand &MO = MI.getOperand(OpNo);
272
273 // If the destination is an immediate, divide by 2.
274 if (MO.isImm())
275 return MO.getImm() >> 1;
276
277 assert(MO.isExpr() &&
278 "getBranchTargetOpValueMMR6 expects only expressions or immediates");
279
280 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
281 MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
282 Fixups.push_back(MCFixup::create(0, FixupExpression,
284 return 0;
285}
286
287/// getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch
288/// target operand. If the machine operand requires relocation,
289/// record the relocation and return zero.
291getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
293 const MCSubtargetInfo &STI) const {
294 const MCOperand &MO = MI.getOperand(OpNo);
295
296 // If the destination is an immediate, divide by 4.
297 if (MO.isImm())
298 return MO.getImm() >> 2;
299
300 assert(MO.isExpr() &&
301 "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates");
302
303 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
304 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
305 Fixups.push_back(MCFixup::create(0, FixupExpression,
307 return 0;
308}
309
310/// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
311/// target operand. If the machine operand requires relocation,
312/// record the relocation and return zero.
314getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
316 const MCSubtargetInfo &STI) const {
317 const MCOperand &MO = MI.getOperand(OpNo);
318
319 // If the destination is an immediate, divide by 2.
320 if (MO.isImm()) return MO.getImm() >> 1;
321
322 assert(MO.isExpr() &&
323 "getBranchTargetOpValueMM expects only expressions or immediates");
324
325 const MCExpr *Expr = MO.getExpr();
326 Fixups.push_back(MCFixup::create(0, Expr,
328 return 0;
329}
330
331/// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
332/// 10-bit branch target operand. If the machine operand requires relocation,
333/// record the relocation and return zero.
335getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
337 const MCSubtargetInfo &STI) const {
338 const MCOperand &MO = MI.getOperand(OpNo);
339
340 // If the destination is an immediate, divide by 2.
341 if (MO.isImm()) return MO.getImm() >> 1;
342
343 assert(MO.isExpr() &&
344 "getBranchTargetOpValuePC10 expects only expressions or immediates");
345
346 const MCExpr *Expr = MO.getExpr();
347 Fixups.push_back(MCFixup::create(0, Expr,
349 return 0;
350}
351
352/// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
353/// target operand. If the machine operand requires relocation,
354/// record the relocation and return zero.
356getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
358 const MCSubtargetInfo &STI) const {
359 const MCOperand &MO = MI.getOperand(OpNo);
360
361 // If the destination is an immediate, divide by 2.
362 if (MO.isImm()) return MO.getImm() >> 1;
363
364 assert(MO.isExpr() &&
365 "getBranchTargetOpValueMM expects only expressions or immediates");
366
367 const MCExpr *Expr = MO.getExpr();
368 Fixups.push_back(MCFixup::create(0, Expr,
369 MCFixupKind(Mips::
370 fixup_MICROMIPS_PC16_S1)));
371 return 0;
372}
373
374/// getBranchTarget21OpValue - Return binary encoding of the branch
375/// target operand. If the machine operand requires relocation,
376/// record the relocation and return zero.
378getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
380 const MCSubtargetInfo &STI) const {
381 const MCOperand &MO = MI.getOperand(OpNo);
382
383 // If the destination is an immediate, divide by 4.
384 if (MO.isImm()) return MO.getImm() >> 2;
385
386 assert(MO.isExpr() &&
387 "getBranchTarget21OpValue expects only expressions or immediates");
388
389 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
390 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
391 Fixups.push_back(MCFixup::create(0, FixupExpression,
393 return 0;
394}
395
396/// getBranchTarget21OpValueMM - Return binary encoding of the branch
397/// target operand for microMIPS. If the machine operand requires
398/// relocation, record the relocation and return zero.
400getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
402 const MCSubtargetInfo &STI) const {
403 const MCOperand &MO = MI.getOperand(OpNo);
404
405 // If the destination is an immediate, divide by 4.
406 if (MO.isImm()) return MO.getImm() >> 2;
407
408 assert(MO.isExpr() &&
409 "getBranchTarget21OpValueMM expects only expressions or immediates");
410
411 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
412 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
413 Fixups.push_back(MCFixup::create(0, FixupExpression,
415 return 0;
416}
417
418/// getBranchTarget26OpValue - Return binary encoding of the branch
419/// target operand. If the machine operand requires relocation,
420/// record the relocation and return zero.
422getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
424 const MCSubtargetInfo &STI) const {
425 const MCOperand &MO = MI.getOperand(OpNo);
426
427 // If the destination is an immediate, divide by 4.
428 if (MO.isImm()) return MO.getImm() >> 2;
429
430 assert(MO.isExpr() &&
431 "getBranchTarget26OpValue expects only expressions or immediates");
432
433 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
434 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
435 Fixups.push_back(MCFixup::create(0, FixupExpression,
437 return 0;
438}
439
440/// getBranchTarget26OpValueMM - Return binary encoding of the branch
441/// target operand. If the machine operand requires relocation,
442/// record the relocation and return zero.
444 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
445 const MCSubtargetInfo &STI) const {
446 const MCOperand &MO = MI.getOperand(OpNo);
447
448 // If the destination is an immediate, divide by 2.
449 if (MO.isImm())
450 return MO.getImm() >> 1;
451
452 assert(MO.isExpr() &&
453 "getBranchTarget26OpValueMM expects only expressions or immediates");
454
455 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
456 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
457 Fixups.push_back(MCFixup::create(0, FixupExpression,
459 return 0;
460}
461
462/// getJumpOffset16OpValue - Return binary encoding of the jump
463/// target operand. If the machine operand requires relocation,
464/// record the relocation and return zero.
466getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
468 const MCSubtargetInfo &STI) const {
469 const MCOperand &MO = MI.getOperand(OpNo);
470
471 if (MO.isImm()) return MO.getImm();
472
473 assert(MO.isExpr() &&
474 "getJumpOffset16OpValue expects only expressions or an immediate");
475
476 const MCExpr *Expr = MO.getExpr();
477 Mips::Fixups FixupKind =
479 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
480 return 0;
481}
482
483/// getJumpTargetOpValue - Return binary encoding of the jump
484/// target operand. If the machine operand requires relocation,
485/// record the relocation and return zero.
487getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
489 const MCSubtargetInfo &STI) const {
490 const MCOperand &MO = MI.getOperand(OpNo);
491 // If the destination is an immediate, divide by 4.
492 if (MO.isImm()) return MO.getImm()>>2;
493
494 assert(MO.isExpr() &&
495 "getJumpTargetOpValue expects only expressions or an immediate");
496
497 const MCExpr *Expr = MO.getExpr();
498 Fixups.push_back(MCFixup::create(0, Expr,
500 return 0;
501}
502
504getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
506 const MCSubtargetInfo &STI) const {
507 const MCOperand &MO = MI.getOperand(OpNo);
508 // If the destination is an immediate, divide by 2.
509 if (MO.isImm()) return MO.getImm() >> 1;
510
511 assert(MO.isExpr() &&
512 "getJumpTargetOpValueMM expects only expressions or an immediate");
513
514 const MCExpr *Expr = MO.getExpr();
515 Fixups.push_back(MCFixup::create(0, Expr,
517 return 0;
518}
519
521getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
523 const MCSubtargetInfo &STI) const {
524 const MCOperand &MO = MI.getOperand(OpNo);
525 if (MO.isImm()) {
526 // The immediate is encoded as 'immediate << 2'.
527 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
528 assert((Res & 3) == 0);
529 return Res >> 2;
530 }
531
532 assert(MO.isExpr() &&
533 "getUImm5Lsl2Encoding expects only expressions or an immediate");
534
535 return 0;
536}
537
539getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
541 const MCSubtargetInfo &STI) const {
542 const MCOperand &MO = MI.getOperand(OpNo);
543 if (MO.isImm()) {
544 int Value = MO.getImm();
545 return Value >> 2;
546 }
547
548 return 0;
549}
550
552getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
554 const MCSubtargetInfo &STI) const {
555 const MCOperand &MO = MI.getOperand(OpNo);
556 if (MO.isImm()) {
557 unsigned Value = MO.getImm();
558 return Value >> 2;
559 }
560
561 return 0;
562}
563
565getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
567 const MCSubtargetInfo &STI) const {
568 const MCOperand &MO = MI.getOperand(OpNo);
569 if (MO.isImm()) {
570 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
571 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
572 }
573
574 return 0;
575}
576
579 const MCSubtargetInfo &STI) const {
580 int64_t Res;
581
582 if (Expr->evaluateAsAbsolute(Res))
583 return Res;
584
585 MCExpr::ExprKind Kind = Expr->getKind();
586 if (Kind == MCExpr::Constant) {
587 return cast<MCConstantExpr>(Expr)->getValue();
588 }
589
590 if (Kind == MCExpr::Binary) {
591 unsigned Res =
592 getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
593 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
594 return Res;
595 }
596
597 if (Kind == MCExpr::Target) {
598 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
599
600 Mips::Fixups FixupKind = Mips::Fixups(0);
601 switch (MipsExpr->getKind()) {
604 llvm_unreachable("Unhandled fixup kind!");
605 break;
607 // MEK_DTPREL is used for marking TLS DIEExpr only
608 // and contains a regular sub-expression.
609 return getExprOpValue(MipsExpr->getSubExpr(), Fixups, STI);
611 FixupKind = Mips::fixup_Mips_CALL_HI16;
612 break;
614 FixupKind = Mips::fixup_Mips_CALL_LO16;
615 break;
617 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
619 break;
621 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
623 break;
625 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOTTPREL
627 break;
629 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
631 break;
633 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
635 break;
637 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
639 break;
641 FixupKind = Mips::fixup_Mips_GOT_HI16;
642 break;
644 FixupKind = Mips::fixup_Mips_GOT_LO16;
645 break;
647 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
649 break;
651 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
653 break;
655 FixupKind = Mips::fixup_Mips_GPREL16;
656 break;
658 // Check for %lo(%neg(%gp_rel(X)))
659 if (MipsExpr->isGpOff())
660 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GPOFF_LO
662 else
663 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
665 break;
667 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HIGHEST
669 break;
671 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HIGHER
673 break;
675 // Check for %hi(%neg(%gp_rel(X)))
676 if (MipsExpr->isGpOff())
677 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GPOFF_HI
679 else
680 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
682 break;
684 FixupKind = Mips::fixup_MIPS_PCHI16;
685 break;
687 FixupKind = Mips::fixup_MIPS_PCLO16;
688 break;
690 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
692 break;
694 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
696 break;
698 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
700 break;
702 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
704 break;
706 FixupKind =
708 break;
709 }
710 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
711 return 0;
712 }
713
714 if (Kind == MCExpr::SymbolRef)
715 Ctx.reportError(Expr->getLoc(), "expected an immediate");
716 return 0;
717}
718
719/// getMachineOpValue - Return binary encoding of operand. If the machine
720/// operand requires relocation, record the relocation and return zero.
722getMachineOpValue(const MCInst &MI, const MCOperand &MO,
724 const MCSubtargetInfo &STI) const {
725 if (MO.isReg()) {
726 unsigned Reg = MO.getReg();
727 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
728 return RegNo;
729 } else if (MO.isImm()) {
730 return static_cast<unsigned>(MO.getImm());
731 } else if (MO.isDFPImm()) {
732 return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
733 }
734 // MO must be an Expr.
735 assert(MO.isExpr());
736 return getExprOpValue(MO.getExpr(),Fixups, STI);
737}
738
739/// Return binary encoding of memory related operand.
740/// If the offset operand requires relocation, record the relocation.
741template <unsigned ShiftAmount>
742unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
744 const MCSubtargetInfo &STI) const {
745 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
746 assert(MI.getOperand(OpNo).isReg());
747 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
748 << 16;
749 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
750
751 // Apply the scale factor if there is one.
752 OffBits >>= ShiftAmount;
753
754 return (OffBits & 0xFFFF) | RegBits;
755}
756
758getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
760 const MCSubtargetInfo &STI) const {
761 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
762 assert(MI.getOperand(OpNo).isReg());
763 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
764 Fixups, STI) << 4;
765 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
766 Fixups, STI);
767
768 return (OffBits & 0xF) | RegBits;
769}
770
772getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
774 const MCSubtargetInfo &STI) const {
775 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
776 assert(MI.getOperand(OpNo).isReg());
777 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
778 Fixups, STI) << 4;
779 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
780 Fixups, STI) >> 1;
781
782 return (OffBits & 0xF) | RegBits;
783}
784
786getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
788 const MCSubtargetInfo &STI) const {
789 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
790 assert(MI.getOperand(OpNo).isReg());
791 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
792 Fixups, STI) << 4;
793 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
794 Fixups, STI) >> 2;
795
796 return (OffBits & 0xF) | RegBits;
797}
798
800getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
802 const MCSubtargetInfo &STI) const {
803 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
804 assert(MI.getOperand(OpNo).isReg() &&
805 (MI.getOperand(OpNo).getReg() == Mips::SP ||
806 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
807 "Unexpected base register!");
808 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
809 Fixups, STI) >> 2;
810
811 return OffBits & 0x1F;
812}
813
815getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
817 const MCSubtargetInfo &STI) const {
818 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
819 assert(MI.getOperand(OpNo).isReg() &&
820 MI.getOperand(OpNo).getReg() == Mips::GP &&
821 "Unexpected base register!");
822
823 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
824 Fixups, STI) >> 2;
825
826 return OffBits & 0x7F;
827}
828
830getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
832 const MCSubtargetInfo &STI) const {
833 // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
834 assert(MI.getOperand(OpNo).isReg());
835 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
836 STI) << 16;
837 unsigned OffBits =
838 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
839
840 return (OffBits & 0x1FF) | RegBits;
841}
842
844getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
846 const MCSubtargetInfo &STI) const {
847 // Base register is encoded in bits 20-16, offset is encoded in bits 10-0.
848 assert(MI.getOperand(OpNo).isReg());
849 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
850 STI) << 16;
851 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
852
853 return (OffBits & 0x07FF) | RegBits;
854}
855
857getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
859 const MCSubtargetInfo &STI) const {
860 // opNum can be invalid if instruction had reglist as operand.
861 // MemOperand is always last operand of instruction (base + offset).
862 switch (MI.getOpcode()) {
863 default:
864 break;
865 case Mips::SWM32_MM:
866 case Mips::LWM32_MM:
867 OpNo = MI.getNumOperands() - 2;
868 break;
869 }
870
871 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
872 assert(MI.getOperand(OpNo).isReg());
873 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
874 << 16;
875 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
876
877 return (OffBits & 0x0FFF) | RegBits;
878}
879
881getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
883 const MCSubtargetInfo &STI) const {
884 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
885 assert(MI.getOperand(OpNo).isReg());
886 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
887 STI) << 16;
888 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
889
890 return (OffBits & 0xFFFF) | RegBits;
891}
892
894getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
896 const MCSubtargetInfo &STI) const {
897 // opNum can be invalid if instruction had reglist as operand
898 // MemOperand is always last operand of instruction (base + offset)
899 switch (MI.getOpcode()) {
900 default:
901 break;
902 case Mips::SWM16_MM:
903 case Mips::SWM16_MMR6:
904 case Mips::LWM16_MM:
905 case Mips::LWM16_MMR6:
906 OpNo = MI.getNumOperands() - 2;
907 break;
908 }
909
910 // Offset is encoded in bits 4-0.
911 assert(MI.getOperand(OpNo).isReg());
912 // Base register is always SP - thus it is not encoded.
913 assert(MI.getOperand(OpNo+1).isImm());
914 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
915
916 return ((OffBits >> 2) & 0x0F);
917}
918
919// FIXME: should be called getMSBEncoding
920//
921unsigned
924 const MCSubtargetInfo &STI) const {
925 assert(MI.getOperand(OpNo-1).isImm());
926 assert(MI.getOperand(OpNo).isImm());
927 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
928 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
929
930 return Position + Size - 1;
931}
932
933template <unsigned Bits, int Offset>
934unsigned
937 const MCSubtargetInfo &STI) const {
938 assert(MI.getOperand(OpNo).isImm());
939 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
940 Value -= Offset;
941 return Value;
942}
943
944unsigned
947 const MCSubtargetInfo &STI) const {
948 const MCOperand &MO = MI.getOperand(OpNo);
949 if (MO.isImm()) {
950 // The immediate is encoded as 'immediate << 2'.
951 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
952 assert((Res & 3) == 0);
953 return Res >> 2;
954 }
955
956 assert(MO.isExpr() &&
957 "getSimm19Lsl2Encoding expects only expressions or an immediate");
958
959 const MCExpr *Expr = MO.getExpr();
960 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
962 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
963 return 0;
964}
965
966unsigned
969 const MCSubtargetInfo &STI) const {
970 const MCOperand &MO = MI.getOperand(OpNo);
971 if (MO.isImm()) {
972 // The immediate is encoded as 'immediate << 3'.
973 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
974 assert((Res & 7) == 0);
975 return Res >> 3;
976 }
977
978 assert(MO.isExpr() &&
979 "getSimm18Lsl2Encoding expects only expressions or an immediate");
980
981 const MCExpr *Expr = MO.getExpr();
982 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
984 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
985 return 0;
986}
987
988unsigned
991 const MCSubtargetInfo &STI) const {
992 assert(MI.getOperand(OpNo).isImm());
993 const MCOperand &MO = MI.getOperand(OpNo);
994 return MO.getImm() % 8;
995}
996
997unsigned
1000 const MCSubtargetInfo &STI) const {
1001 assert(MI.getOperand(OpNo).isImm());
1002 const MCOperand &MO = MI.getOperand(OpNo);
1003 unsigned Value = MO.getImm();
1004 switch (Value) {
1005 case 128: return 0x0;
1006 case 1: return 0x1;
1007 case 2: return 0x2;
1008 case 3: return 0x3;
1009 case 4: return 0x4;
1010 case 7: return 0x5;
1011 case 8: return 0x6;
1012 case 15: return 0x7;
1013 case 16: return 0x8;
1014 case 31: return 0x9;
1015 case 32: return 0xa;
1016 case 63: return 0xb;
1017 case 64: return 0xc;
1018 case 255: return 0xd;
1019 case 32768: return 0xe;
1020 case 65535: return 0xf;
1021 }
1022 llvm_unreachable("Unexpected value");
1023}
1024
1025unsigned
1028 const MCSubtargetInfo &STI) const {
1029 unsigned res = 0;
1030
1031 // Register list operand is always first operand of instruction and it is
1032 // placed before memory operand (register + imm).
1033
1034 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
1035 unsigned Reg = MI.getOperand(I).getReg();
1036 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
1037 if (RegNo != 31)
1038 res++;
1039 else
1040 res |= 0x10;
1041 }
1042 return res;
1043}
1044
1045unsigned
1048 const MCSubtargetInfo &STI) const {
1049 return (MI.getNumOperands() - 4);
1050}
1051
1052unsigned
1055 const MCSubtargetInfo &STI) const {
1056 unsigned res = 0;
1057
1058 if (MI.getOperand(0).getReg() == Mips::A1 &&
1059 MI.getOperand(1).getReg() == Mips::A2)
1060 res = 0;
1061 else if (MI.getOperand(0).getReg() == Mips::A1 &&
1062 MI.getOperand(1).getReg() == Mips::A3)
1063 res = 1;
1064 else if (MI.getOperand(0).getReg() == Mips::A2 &&
1065 MI.getOperand(1).getReg() == Mips::A3)
1066 res = 2;
1067 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1068 MI.getOperand(1).getReg() == Mips::S5)
1069 res = 3;
1070 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1071 MI.getOperand(1).getReg() == Mips::S6)
1072 res = 4;
1073 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1074 MI.getOperand(1).getReg() == Mips::A1)
1075 res = 5;
1076 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1077 MI.getOperand(1).getReg() == Mips::A2)
1078 res = 6;
1079 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1080 MI.getOperand(1).getReg() == Mips::A3)
1081 res = 7;
1082
1083 return res;
1084}
1085
1086unsigned
1089 const MCSubtargetInfo &STI) const {
1090 assert(((OpNo == 2) || (OpNo == 3)) &&
1091 "Unexpected OpNo for movep operand encoding!");
1092
1093 MCOperand Op = MI.getOperand(OpNo);
1094 assert(Op.isReg() && "Operand of movep is not a register!");
1095 switch (Op.getReg()) {
1096 default:
1097 llvm_unreachable("Unknown register for movep!");
1098 case Mips::ZERO: return 0;
1099 case Mips::S1: return 1;
1100 case Mips::V0: return 2;
1101 case Mips::V1: return 3;
1102 case Mips::S0: return 4;
1103 case Mips::S2: return 5;
1104 case Mips::S3: return 6;
1105 case Mips::S4: return 7;
1106 }
1107}
1108
1109unsigned
1112 const MCSubtargetInfo &STI) const {
1113 const MCOperand &MO = MI.getOperand(OpNo);
1114 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
1115 // The immediate is encoded as 'immediate >> 2'.
1116 unsigned Res = static_cast<unsigned>(MO.getImm());
1117 assert((Res & 3) == 0);
1118 return Res >> 2;
1119}
1120
1121#include "MipsGenMCCodeEmitter.inc"
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static void LowerLargeShift(MCInst &Inst)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
endianness Endian
raw_pwrite_stream & OS
This file defines the SmallVector class.
This class represents an Operation in the Expression.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:528
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:448
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1059
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ Constant
Constant expressions.
Definition: MCExpr.h:39
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
@ Target
Target specific expression.
Definition: MCExpr.h:42
@ Binary
Binary expressions.
Definition: MCExpr.h:38
ExprKind getKind() const
Definition: MCExpr.h:81
SMLoc getLoc() const
Definition: MCExpr.h:82
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:86
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
void setImm(int64_t Val)
Definition: MCInst.h:85
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:75
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
bool isDFPImm() const
Definition: MCInst.h:64
const MCExpr * getExpr() const
Definition: MCInst.h:114
uint64_t getDFPImm() const
Definition: MCInst.h:100
bool isExpr() const
Definition: MCInst.h:65
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch target operand.
unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget21OpValue - Return binary encoding of the branch target operand.
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getMachineOpValue - Return binary encoding of operand.
unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Subtract Offset then encode as a N-bit unsigned integer.
unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueMMR6 - Return binary encoding of the branch target operand.
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue - Return binary encoding of the branch target operand.
unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Return binary encoding of memory related operand.
unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget26OpValue - Return binary encoding of the branch target operand.
unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget26OpValueMM - Return binary encoding of the branch target operand.
unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue1SImm16 - Return binary encoding of the branch target operand.
unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getJumpOffset16OpValue - Return binary encoding of the jump target operand.
unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand.
unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getJumpTargetOpValue - Return binary encoding of the jump target operand.
unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand.
unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void encodeInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
encodeInstruction - Emit the instruction.
unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget21OpValueMM - Return binary encoding of the branch target operand for microMIPS.
unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand.
unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void EmitByte(unsigned char C, raw_ostream &OS) const
unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
const MCExpr * getSubExpr() const
Get the child of this expression.
Definition: MipsMCExpr.h:67
MipsExprKind getKind() const
Get the kind of this expression.
Definition: MipsMCExpr.h:64
bool isGpOff(MipsExprKind &Kind) const
Definition: MipsMCExpr.cpp:291
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ fixup_MICROMIPS_TLS_TPREL_LO16
@ fixup_Mips_DTPREL_HI
@ fixup_MICROMIPS_PC7_S1
@ fixup_MICROMIPS_GOT_PAGE
@ fixup_MICROMIPS_HIGHER
@ fixup_MICROMIPS_TLS_TPREL_HI16
@ fixup_MICROMIPS_PC21_S1
@ fixup_MICROMIPS_GPOFF_LO
@ fixup_MICROMIPS_PC19_S2
@ fixup_MICROMIPS_CALL16
@ fixup_MICROMIPS_TLS_LDM
@ fixup_MICROMIPS_GOT_OFST
@ fixup_MICROMIPS_TLS_DTPREL_HI16
@ fixup_MICROMIPS_PC10_S1
@ fixup_MICROMIPS_TLS_GD
@ fixup_MICROMIPS_HIGHEST
@ fixup_MICROMIPS_GOT_DISP
@ fixup_Mips_DTPREL_LO
@ fixup_MICROMIPS_PC18_S3
@ fixup_MICROMIPS_PC26_S1
@ fixup_MICROMIPS_GOTTPREL
@ fixup_MICROMIPS_TLS_DTPREL_LO16
@ fixup_MICROMIPS_GPOFF_HI
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCContext &Ctx)
MCCodeEmitter * createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, MCContext &Ctx)
@ Offset
Definition: DWP.cpp:440
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
#define N
Description of the encoding of one expression Op.