39 #define DEBUG_TYPE "riscv-lower" 41 STATISTIC(NumTailCalls,
"Number of tail calls");
154 for (
auto CC : FPCCToExtend)
159 for (
auto Op : FPOpToExtend)
169 for (
auto CC : FPCCToExtend)
176 for (
auto Op : FPOpToExtend)
219 unsigned Intrinsic)
const {
223 case Intrinsic::riscv_masked_atomicrmw_xchg_i32:
224 case Intrinsic::riscv_masked_atomicrmw_add_i32:
225 case Intrinsic::riscv_masked_atomicrmw_sub_i32:
226 case Intrinsic::riscv_masked_atomicrmw_nand_i32:
227 case Intrinsic::riscv_masked_atomicrmw_max_i32:
228 case Intrinsic::riscv_masked_atomicrmw_min_i32:
229 case Intrinsic::riscv_masked_atomicrmw_umax_i32:
230 case Intrinsic::riscv_masked_atomicrmw_umin_i32:
231 case Intrinsic::riscv_masked_cmpxchg_i32:
271 return isInt<12>(Imm);
275 return isInt<12>(Imm);
286 return (SrcBits == 64 && DestBits == 32);
295 return (SrcBits == 64 && DestBits == 32);
300 if (
auto *
LD = dyn_cast<LoadSDNode>(Val)) {
301 EVT MemVT =
LD->getMemoryVT();
366 return lowerGlobalAddress(Op, DAG);
368 return lowerBlockAddress(Op, DAG);
370 return lowerConstantPool(Op, DAG);
372 return lowerGlobalTLSAddress(Op, DAG);
374 return lowerSELECT(Op, DAG);
376 return lowerVASTART(Op, DAG);
378 return lowerFRAMEADDR(Op, DAG);
380 return lowerRETURNADDR(Op, DAG);
382 return lowerShiftLeftParts(Op, DAG);
384 return lowerShiftRightParts(Op, DAG,
true);
386 return lowerShiftRightParts(Op, DAG,
false);
389 "Unexpected custom legalisation");
418 template <
class NodeTy>
420 bool IsLocal)
const {
469 SDValue Addr = getAddr(N, DAG, IsLocal);
485 return getAddr(N, DAG);
492 return getAddr(N, DAG);
531 DAG.
getMachineNode(RISCV::PseudoAddTPRel, DL, Ty, MNHi, TPReg, AddrAdd),
555 Args.push_back(Entry);
584 Addr = getStaticTLSAddr(N, DAG,
false);
587 Addr = getStaticTLSAddr(N, DAG,
true);
591 Addr = getDynamicTLSAddr(N, DAG);
622 auto CC = cast<CondCodeSDNode>(CondV.
getOperand(2));
629 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
640 SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
667 int XLenInBytes = Subtarget.
getXLen() / 8;
672 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
674 int Offset = -(XLenInBytes * 2);
690 int XLenInBytes = Subtarget.
getXLen() / 8;
697 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
699 int Off = -XLenInBytes;
700 SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);
791 SDValue LoFalse = DAG.
getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen);
861 "READCYCLECOUNTER only has custom type legalization on riscv32");
876 "Unexpected custom legalisation");
885 "Unexpected custom legalisation");
894 Subtarget.
hasStdExtM() &&
"Unexpected custom legalisation");
902 Subtarget.
hasStdExtF() &&
"Unexpected custom legalisation");
935 APInt V =
C->getValueAPF().bitcastToAPInt();
1028 APInt C1Int = C1->getAPIntValue();
1029 APInt ShiftedC1Int = C1Int << C2->getAPIntValue();
1053 if (C1Cost < ShiftedC1Cost)
1062 unsigned Depth)
const {
1083 assert(MI.
getOpcode() == RISCV::ReadCycleWide &&
"Unexpected instruction");
1120 BuildMI(LoopMBB, DL, TII->
get(RISCV::CSRRS), HiReg)
1123 BuildMI(LoopMBB, DL, TII->
get(RISCV::CSRRS), LoReg)
1126 BuildMI(LoopMBB, DL, TII->
get(RISCV::CSRRS), ReadAgainReg)
1145 assert(MI.
getOpcode() == RISCV::SplitF64Pseudo &&
"Unexpected instruction");
1162 BuildMI(*BB, MI, DL, TII.
get(RISCV::LW), LoReg)
1166 BuildMI(*BB, MI, DL, TII.
get(RISCV::LW), HiReg)
1177 "Unexpected instruction");
1211 case RISCV::Select_GPR_Using_CC_GPR:
1212 case RISCV::Select_FPR32_Using_CC_GPR:
1213 case RISCV::Select_FPR64_Using_CC_GPR:
1255 SequenceMBBI !=
E; ++SequenceMBBI) {
1256 if (SequenceMBBI->isDebugInstr())
1259 if (SequenceMBBI->getOperand(1).getReg() != LHS ||
1260 SequenceMBBI->getOperand(2).getReg() != RHS ||
1261 SequenceMBBI->getOperand(3).getImm() != CC ||
1262 SelectDests.
count(SequenceMBBI->getOperand(4).getReg()) ||
1263 SelectDests.
count(SequenceMBBI->getOperand(5).getReg()))
1265 LastSelectPseudo = &*SequenceMBBI;
1267 SelectDests.
insert(SequenceMBBI->getOperand(0).getReg());
1269 if (SequenceMBBI->hasUnmodeledSideEffects() ||
1270 SequenceMBBI->mayLoadOrStore())
1273 return MO.isReg() && MO.isUse() && SelectDests.
count(MO.getReg());
1289 F->
insert(I, IfFalseMBB);
1294 TailMBB->
push_back(DebugInstr->removeFromParent());
1298 TailMBB->
splice(TailMBB->
end(), HeadMBB,
1320 auto SelectEnd = std::next(LastSelectPseudo->
getIterator());
1321 auto InsertionPoint = TailMBB->
begin();
1322 while (SelectMBBI != SelectEnd) {
1323 auto Next = std::next(SelectMBBI);
1326 BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(),
1327 TII.
get(RISCV::PHI), SelectMBBI->getOperand(0).getReg())
1328 .addReg(SelectMBBI->getOperand(4).getReg())
1330 .
addReg(SelectMBBI->getOperand(5).getReg())
1331 .addMBB(IfFalseMBB);
1347 case RISCV::ReadCycleWide:
1349 "ReadCycleWrite is only to be used on riscv32");
1351 case RISCV::Select_GPR_Using_CC_GPR:
1352 case RISCV::Select_FPR32_Using_CC_GPR:
1353 case RISCV::Select_FPR64_Using_CC_GPR:
1355 case RISCV::BuildPairF64Pseudo:
1357 case RISCV::SplitF64Pseudo:
1388 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
1389 RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
1392 RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
1393 RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
1396 RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
1397 RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
1406 unsigned XLenInBytes = XLen / 8;
1419 ValNo2, ValVT2, State.
AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
1431 ValNo2, ValVT2, State.
AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
1442 bool IsRet,
Type *OrigTy) {
1444 assert(XLen == 32 || XLen == 64);
1449 if (IsRet && ValNo > 1)
1454 bool UseGPRForF32 =
true;
1457 bool UseGPRForF64 =
true;
1467 UseGPRForF32 = !IsFixed;
1471 UseGPRForF32 = !IsFixed;
1472 UseGPRForF64 = !IsFixed;
1477 UseGPRForF32 =
true;
1479 UseGPRForF64 =
true;
1484 if (UseGPRForF32 && ValVT ==
MVT::f32) {
1487 }
else if (UseGPRForF64 && XLen == 64 && ValVT ==
MVT::f64) {
1499 unsigned TwoXLenInBytes = (2 * XLen) / 8;
1500 if (!IsFixed && ArgFlags.
getOrigAlign() == TwoXLenInBytes &&
1513 "PendingLocs and PendingArgFlags out of sync");
1517 if (UseGPRForF64 && XLen == 32 && ValVT ==
MVT::f64) {
1519 "Can't lower f64 if it is split");
1554 assert(PendingLocs.
size() == 2 &&
"Unexpected PendingLocs.size()");
1559 PendingLocs.
clear();
1560 PendingArgFlags.
clear();
1567 if (ValVT ==
MVT::f32 && !UseGPRForF32)
1569 else if (ValVT ==
MVT::f64 && !UseGPRForF64)
1577 if (!PendingLocs.
empty()) {
1579 assert(PendingLocs.
size() > 2 &&
"Unexpected PendingLocs.size()");
1581 for (
auto &It : PendingLocs) {
1583 It.convertToReg(Reg);
1585 It.convertToMem(StackOffset);
1588 PendingLocs.clear();
1589 PendingArgFlags.
clear();
1593 assert((!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) &&
1594 "Expected an XLenVT at this stage");
1610 void RISCVTargetLowering::analyzeInputArgs(
1613 unsigned NumArgs = Ins.
size();
1616 for (
unsigned i = 0; i != NumArgs; ++i) {
1617 MVT ArgVT = Ins[i].VT;
1620 Type *ArgTy =
nullptr;
1623 else if (Ins[i].isOrigArg())
1628 ArgFlags, CCInfo,
true, IsRet, ArgTy)) {
1630 <<
EVT(ArgVT).getEVTString() <<
'\n');
1636 void RISCVTargetLowering::analyzeOutputArgs(
1639 CallLoweringInfo *CLI)
const {
1640 unsigned NumArgs = Outs.
size();
1642 for (
unsigned i = 0; i != NumArgs; i++) {
1643 MVT ArgVT = Outs[i].VT;
1645 Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty :
nullptr;
1649 ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
1650 LLVM_DEBUG(
dbgs() <<
"OutputArg #" << i <<
" has unhandled type " 1651 <<
EVT(ArgVT).getEVTString() <<
"\n");
1692 RC = &RISCV::GPRRegClass;
1695 RC = &RISCV::FPR32RegClass;
1698 RC = &RISCV::FPR64RegClass;
1757 ExtType, DL, LocVT, Chain, FIN,
1808 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14,
1809 RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28,
1810 RISCV::X29, RISCV::X30, RISCV::X31};
1819 RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F,
1820 RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F0_F, RISCV::F1_F,
1821 RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F,
1822 RISCV::F7_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F};
1831 RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D,
1832 RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F0_D, RISCV::F1_D,
1833 RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D,
1834 RISCV::F7_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D};
1857 SDValue RISCVTargetLowering::LowerFormalArguments(
1876 "Functions with the interrupt attribute cannot have arguments!");
1881 if (!(Kind ==
"user" || Kind ==
"supervisor" || Kind ==
"machine"))
1883 "Function interrupt attribute argument not supported!");
1888 unsigned XLenInBytes = Subtarget.
getXLen() / 8;
1890 std::vector<SDValue> OutChains;
1899 analyzeInputArgs(MF, CCInfo, Ins,
false);
1901 for (
unsigned i = 0,
e = ArgLocs.
size(); i !=
e; ++i) {
1919 unsigned ArgIndex = Ins[i].OrigArgIndex;
1920 assert(Ins[i].PartOffset == 0);
1921 while (i + 1 !=
e && Ins[i + 1].OrigArgIndex == ArgIndex) {
1923 unsigned PartOffset = Ins[i + 1].PartOffset;
1946 int VaArgOffset, VarArgsSaveSize;
1950 if (ArgRegs.
size() == Idx) {
1952 VarArgsSaveSize = 0;
1954 VarArgsSaveSize = XLenInBytes * (ArgRegs.
size() - Idx);
1955 VaArgOffset = -VarArgsSaveSize;
1968 VarArgsSaveSize += XLenInBytes;
1973 for (
unsigned I = Idx;
I < ArgRegs.
size();
1974 ++
I, VaArgOffset += XLenInBytes) {
1982 cast<StoreSDNode>(Store.
getNode())
1984 ->setValue((
Value *)
nullptr);
1985 OutChains.push_back(Store);
1992 if (!OutChains.empty()) {
1993 OutChains.push_back(Chain);
2003 bool RISCVTargetLowering::isEligibleForTailCallOptimization(
2007 auto &
Callee = CLI.Callee;
2008 auto CalleeCC = CLI.CallConv;
2009 auto &Outs = CLI.Outs;
2011 auto CallerCC = Caller.getCallingConv();
2014 if (Caller.getFnAttribute(
"disable-tail-calls").getValueAsString() ==
"true")
2022 if (Caller.hasFnAttribute(
"interrupt"))
2037 for (
auto &VA : ArgLocs)
2043 auto IsCallerStructRet = Caller.hasStructRetAttr();
2044 auto IsCalleeStructRet = Outs.
empty() ?
false : Outs[0].Flags.isSRet();
2045 if (IsCallerStructRet || IsCalleeStructRet)
2061 if (CalleeCC != CallerCC) {
2063 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2070 for (
auto &
Arg : Outs)
2071 if (
Arg.Flags.isByVal())
2079 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
2088 bool &IsTailCall = CLI.IsTailCall;
2090 bool IsVarArg = CLI.IsVarArg;
2103 analyzeOutputArgs(MF, ArgCCInfo, Outs,
false, &CLI);
2107 IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs);
2111 else if (CLI.CS && CLI.CS.isMustTailCall())
2113 "site marked musttail");
2116 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
2120 for (
unsigned i = 0,
e = Outs.
size(); i !=
e; ++i) {
2133 Chain = DAG.
getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
2148 for (
unsigned i = 0, j = 0,
e = ArgLocs.
size(); i !=
e; ++i) {
2150 SDValue ArgValue = OutVals[i];
2154 bool IsF64OnRV32DSoftABI =
2156 if (IsF64OnRV32DSoftABI && VA.
isRegLoc()) {
2163 RegsToPass.
push_back(std::make_pair(RegLo, Lo));
2165 if (RegLo == RISCV::X17) {
2175 assert(RegLo < RISCV::X31 &&
"Invalid register pair");
2177 RegsToPass.
push_back(std::make_pair(RegHigh, Hi));
2190 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2192 DAG.
getStore(Chain, DL, ArgValue, SpillSlot,
2196 unsigned ArgIndex = Outs[i].OrigArgIndex;
2197 assert(Outs[i].PartOffset == 0);
2198 while (i + 1 !=
e && Outs[i + 1].OrigArgIndex == ArgIndex) {
2199 SDValue PartValue = OutVals[i + 1];
2200 unsigned PartOffset = Outs[i + 1].PartOffset;
2204 DAG.
getStore(Chain, DL, PartValue, Address,
2208 ArgValue = SpillSlot;
2215 ArgValue = ByValArgs[j++];
2222 assert(!IsTailCall &&
"Tail call not allowed if stack is used " 2223 "for passing parameters");
2239 if (!MemOpChains.
empty())
2245 for (
auto &
Reg : RegsToPass) {
2278 for (
auto &
Reg : RegsToPass)
2285 assert(Mask &&
"Missing call preserved mask for calling convention");
2314 analyzeInputArgs(MF, RetCCInfo, Ins,
true);
2317 for (
auto &VA : RVLocs) {
2320 DAG.
getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
2326 assert(VA.getLocReg() ==
ArgGPRs[0] &&
"Unexpected reg assignment");
2343 bool RISCVTargetLowering::CanLowerReturn(
2347 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2348 for (
unsigned i = 0,
e = Outs.
size(); i !=
e; ++i) {
2349 MVT VT = Outs[i].VT;
2353 ArgFlags, CCInfo,
true,
true,
nullptr))
2379 for (
unsigned i = 0,
e = RVLocs.
size(); i <
e; ++i) {
2392 assert(RegLo < RISCV::X31 &&
"Invalid register pair");
2414 if (Glue.getNode()) {
2423 "Functions with the interrupt attribute must have void return type!");
2432 else if (Kind ==
"supervisor")
2448 return "RISCVISD::RET_FLAG";
2450 return "RISCVISD::URET_FLAG";
2452 return "RISCVISD::SRET_FLAG";
2454 return "RISCVISD::MRET_FLAG";
2456 return "RISCVISD::CALL";
2458 return "RISCVISD::SELECT_CC";
2460 return "RISCVISD::BuildPairF64";
2462 return "RISCVISD::SplitF64";
2464 return "RISCVISD::TAIL";
2466 return "RISCVISD::SLLW";
2468 return "RISCVISD::SRAW";
2470 return "RISCVISD::SRLW";
2472 return "RISCVISD::DIVW";
2474 return "RISCVISD::DIVUW";
2476 return "RISCVISD::REMUW";
2478 return "RISCVISD::FMV_W_X_RV64";
2480 return "RISCVISD::FMV_X_ANYEXTW_RV64";
2482 return "RISCVISD::READ_CYCLE_WIDE";
2491 if (Constraint.
size() == 1) {
2492 switch (Constraint[0]) {
2508 std::pair<unsigned, const TargetRegisterClass *>
2514 if (Constraint.
size() == 1) {
2515 switch (Constraint[0]) {
2517 return std::make_pair(0U, &RISCV::GPRRegClass);
2520 return std::make_pair(0U, &RISCV::FPR32RegClass);
2522 return std::make_pair(0U, &RISCV::FPR64RegClass);
2534 .Case(
"{zero}", RISCV::X0)
2535 .
Case(
"{ra}", RISCV::X1)
2536 .
Case(
"{sp}", RISCV::X2)
2537 .
Case(
"{gp}", RISCV::X3)
2538 .
Case(
"{tp}", RISCV::X4)
2539 .
Case(
"{t0}", RISCV::X5)
2540 .
Case(
"{t1}", RISCV::X6)
2541 .
Case(
"{t2}", RISCV::X7)
2542 .
Cases(
"{s0}",
"{fp}", RISCV::X8)
2543 .
Case(
"{s1}", RISCV::X9)
2544 .
Case(
"{a0}", RISCV::X10)
2545 .
Case(
"{a1}", RISCV::X11)
2546 .
Case(
"{a2}", RISCV::X12)
2547 .
Case(
"{a3}", RISCV::X13)
2548 .
Case(
"{a4}", RISCV::X14)
2549 .
Case(
"{a5}", RISCV::X15)
2550 .
Case(
"{a6}", RISCV::X16)
2551 .
Case(
"{a7}", RISCV::X17)
2552 .
Case(
"{s2}", RISCV::X18)
2553 .
Case(
"{s3}", RISCV::X19)
2554 .
Case(
"{s4}", RISCV::X20)
2555 .
Case(
"{s5}", RISCV::X21)
2556 .
Case(
"{s6}", RISCV::X22)
2557 .
Case(
"{s7}", RISCV::X23)
2558 .
Case(
"{s8}", RISCV::X24)
2559 .
Case(
"{s9}", RISCV::X25)
2560 .
Case(
"{s10}", RISCV::X26)
2561 .
Case(
"{s11}", RISCV::X27)
2562 .
Case(
"{t3}", RISCV::X28)
2563 .
Case(
"{t4}", RISCV::X29)
2564 .
Case(
"{t5}", RISCV::X30)
2565 .
Case(
"{t6}", RISCV::X31)
2567 if (XRegFromAlias != RISCV::NoRegister)
2568 return std::make_pair(XRegFromAlias, &RISCV::GPRRegClass);
2578 std::pair<Register, Register> FReg =
2580 .Cases(
"{f0}",
"{ft0}", {RISCV::F0_F, RISCV::F0_D})
2581 .Cases(
"{f1}",
"{ft1}", {RISCV::F1_F, RISCV::F1_D})
2582 .Cases(
"{f2}",
"{ft2}", {RISCV::F2_F, RISCV::F2_D})
2583 .Cases(
"{f3}",
"{ft3}", {RISCV::F3_F, RISCV::F3_D})
2584 .Cases(
"{f4}",
"{ft4}", {RISCV::F4_F, RISCV::F4_D})
2585 .Cases(
"{f5}",
"{ft5}", {RISCV::F5_F, RISCV::F5_D})
2586 .Cases(
"{f6}",
"{ft6}", {RISCV::F6_F, RISCV::F6_D})
2587 .Cases(
"{f7}",
"{ft7}", {RISCV::F7_F, RISCV::F7_D})
2588 .Cases(
"{f8}",
"{fs0}", {RISCV::F8_F, RISCV::F8_D})
2589 .Cases(
"{f9}",
"{fs1}", {RISCV::F9_F, RISCV::F9_D})
2590 .Cases(
"{f10}",
"{fa0}", {RISCV::F10_F, RISCV::F10_D})
2591 .Cases(
"{f11}",
"{fa1}", {RISCV::F11_F, RISCV::F11_D})
2592 .Cases(
"{f12}",
"{fa2}", {RISCV::F12_F, RISCV::F12_D})
2593 .Cases(
"{f13}",
"{fa3}", {RISCV::F13_F, RISCV::F13_D})
2594 .Cases(
"{f14}",
"{fa4}", {RISCV::F14_F, RISCV::F14_D})
2595 .Cases(
"{f15}",
"{fa5}", {RISCV::F15_F, RISCV::F15_D})
2596 .Cases(
"{f16}",
"{fa6}", {RISCV::F16_F, RISCV::F16_D})
2597 .Cases(
"{f17}",
"{fa7}", {RISCV::F17_F, RISCV::F17_D})
2598 .Cases(
"{f18}",
"{fs2}", {RISCV::F18_F, RISCV::F18_D})
2599 .Cases(
"{f19}",
"{fs3}", {RISCV::F19_F, RISCV::F19_D})
2600 .Cases(
"{f20}",
"{fs4}", {RISCV::F20_F, RISCV::F20_D})
2601 .Cases(
"{f21}",
"{fs5}", {RISCV::F21_F, RISCV::F21_D})
2602 .Cases(
"{f22}",
"{fs6}", {RISCV::F22_F, RISCV::F22_D})
2603 .Cases(
"{f23}",
"{fs7}", {RISCV::F23_F, RISCV::F23_D})
2604 .Cases(
"{f24}",
"{fs8}", {RISCV::F24_F, RISCV::F24_D})
2605 .Cases(
"{f25}",
"{fs9}", {RISCV::F25_F, RISCV::F25_D})
2606 .Cases(
"{f26}",
"{fs10}", {RISCV::F26_F, RISCV::F26_D})
2607 .Cases(
"{f27}",
"{fs11}", {RISCV::F27_F, RISCV::F27_D})
2608 .Cases(
"{f28}",
"{ft8}", {RISCV::F28_F, RISCV::F28_D})
2609 .Cases(
"{f29}",
"{ft9}", {RISCV::F29_F, RISCV::F29_D})
2610 .Cases(
"{f30}",
"{ft10}", {RISCV::F30_F, RISCV::F30_D})
2611 .Cases(
"{f31}",
"{ft11}", {RISCV::F31_F, RISCV::F31_D})
2612 .
Default({RISCV::NoRegister, RISCV::NoRegister});
2613 if (FReg.first != RISCV::NoRegister)
2615 ? std::make_pair(FReg.second, &RISCV::FPR64RegClass)
2616 : std::make_pair(FReg.first, &RISCV::FPR32RegClass);
2625 if (ConstraintCode.
size() == 1) {
2626 switch (ConstraintCode[0]) {
2638 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2641 if (Constraint.length() == 1) {
2642 switch (Constraint[0]) {
2645 if (
auto *
C = dyn_cast<ConstantSDNode>(Op)) {
2646 uint64_t CVal =
C->getSExtValue();
2647 if (isInt<12>(CVal))
2654 if (
auto *
C = dyn_cast<ConstantSDNode>(Op))
2655 if (
C->getZExtValue() == 0)
2661 if (
auto *
C = dyn_cast<ConstantSDNode>(Op)) {
2662 uint64_t CVal =
C->getZExtValue();
2663 if (isUInt<5>(CVal))
2694 RISCVTargetLowering::shouldExpandAtomicRMWInIR(
AtomicRMWInst *AI)
const {
2702 if (Size == 8 || Size == 16)
2714 return Intrinsic::riscv_masked_atomicrmw_xchg_i32;
2716 return Intrinsic::riscv_masked_atomicrmw_add_i32;
2718 return Intrinsic::riscv_masked_atomicrmw_sub_i32;
2720 return Intrinsic::riscv_masked_atomicrmw_nand_i32;
2722 return Intrinsic::riscv_masked_atomicrmw_max_i32;
2724 return Intrinsic::riscv_masked_atomicrmw_min_i32;
2726 return Intrinsic::riscv_masked_atomicrmw_umax_i32;
2728 return Intrinsic::riscv_masked_atomicrmw_umin_i32;
2737 return Intrinsic::riscv_masked_atomicrmw_xchg_i64;
2739 return Intrinsic::riscv_masked_atomicrmw_add_i64;
2741 return Intrinsic::riscv_masked_atomicrmw_sub_i64;
2743 return Intrinsic::riscv_masked_atomicrmw_nand_i64;
2745 return Intrinsic::riscv_masked_atomicrmw_max_i64;
2747 return Intrinsic::riscv_masked_atomicrmw_min_i64;
2749 return Intrinsic::riscv_masked_atomicrmw_umax_i64;
2751 return Intrinsic::riscv_masked_atomicrmw_umin_i64;
2758 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
2761 unsigned XLen = Subtarget.
getXLen();
2790 {AlignedAddr, Incr,
Mask, SextShamt, Ordering});
2793 Builder.
CreateCall(LrwOpScwLoop, {AlignedAddr, Incr,
Mask, Ordering});
2802 RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
2805 if (Size == 8 || Size == 16)
2810 Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
2813 unsigned XLen = Subtarget.
getXLen();
2814 Value *Ordering = Builder.
getIntN(XLen, static_cast<uint64_t>(Ord));
2815 Intrinsic::ID CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i32;
2820 CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i64;
2826 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal,
Mask, Ordering});
2833 const Constant *PersonalityFn)
const {
2838 const Constant *PersonalityFn)
const {
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
A parsed version of the target data layout string in and methods for querying it. ...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
RISCVABI::ABI getTargetABI() const
void collectDebugValues(SmallVectorImpl< MachineInstr *> &DbgValues)
Scan instructions following MI and collect any matching DBG_VALUEs.
const GlobalValue * getGlobal() const
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
APInt sext(unsigned width) const
Sign extend to a new width.
*p = old <signed v ? old : v
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
StackOffset is a wrapper around scalable and non-scalable offsets and is used in several functions su...
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue CombineTo(SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
BR_CC - Conditional branch.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
MachineFunctionProperties & reset(Property P)
Register getLocReg() const
Type * getParamType(unsigned i) const
Parameter type accessors.
Register getFrameRegister(const MachineFunction &MF) const override
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
An instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const MachineFunctionProperties & getProperties() const
Get the function properties.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void push_back(const T &Elt)
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
MachineMemOperand::Flags flags
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
This class represents a function call, abstracting a target machine's calling convention.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
static SDValue customLegalizeToWOpWithSExt(SDNode *N, SelectionDAG &DAG)
const RISCVRegisterInfo * getRegisterInfo() const override
*p = old <unsigned v ? old : v
Function Alias Analysis Results
*p = old >unsigned v ? old : v
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
unsigned getValNo() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
void setVarArgsFrameIndex(int Index)
APInt trunc(unsigned width) const
Truncate to new width.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Value * CreateSExt(Value *V, Type *DestTy, const Twine &Name="")
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
static const MCPhysReg ArgFPR32s[]
bool hasExternalWeakLinkage() const
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
*p = old >signed v ? old : v
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
StringSwitch & Case(StringLiteral S, T Value)
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
TypeSize getTypeStoreSizeInBits(Type *Ty) const
Returns the maximum number of bits that may be overwritten by storing the specified type; always a mu...
static MachineBasicBlock * emitReadCycleWidePseudo(MachineInstr &MI, MachineBasicBlock *BB)
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
IntegerType * getInt32Ty()
Fetch the type representing a 32-bit integer.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Value * getArgOperand(unsigned i) const
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
bool hasOneUse() const
Return true if there is exactly one use of this node.
A description of a memory reference used in the backend.
static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
const HexagonInstrInfo * TII
IntegerType * getInt64Ty()
Fetch the type representing a 64-bit integer.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Shift and rotation operations.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
BinOp getOperation() const
CallLoweringInfo & setChain(SDValue InChain)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
LLVM_NODISCARD R Default(T Value)
static MachineBasicBlock * emitSplitF64Pseudo(MachineInstr &MI, MachineBasicBlock *BB)
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
const BlockAddress * getBlockAddress() const
LocInfo getLocInfo() const
static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
AtomicOrdering
Atomic ordering for LLVM's memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Class to represent function types.
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
int64_t getSExtValue() const
Get sign extended value.
Type * getType() const
All values are typed, get the type of this value.
MachineFunction & getMachineFunction() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
SDValue getRegisterMask(const uint32_t *RegMask)
BinOp
This enumeration lists the possible modifications atomicrmw can make.
SmallVectorImpl< CCValAssign > & getPendingLocs()
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Simple integer binary arithmetic operators.
static MachineBasicBlock * emitBuildPairF64Pseudo(MachineInstr &MI, MachineBasicBlock *BB)
SmallVectorImpl< ISD::ArgFlagsTy > & getPendingArgFlags()
LLVM_NODISCARD size_t size() const
size - Get the string size.
static const MCPhysReg ArgFPR64s[]
Value * CreateSub(Value *LHS, Value *RHS, const Twine &Name="", bool HasNUW=false, bool HasNSW=false)
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
virtual const TargetInstrInfo * getInstrInfo() const
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Analysis containing CSE Info
ConstantInt * getIntN(unsigned N, uint64_t C)
Get a constant N-bit value, zero extended or truncated from a 64-bit value.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Class to represent pointers.
unsigned getByValSize() const
unsigned getKillRegState(bool B)
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. ...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
TargetInstrInfo - Interface to description of machine instruction set.
static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool isVoidTy() const
Return true if this is 'void'.
The memory access is volatile.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
C - The default llvm calling convention, compatible with C.
A switch()-like statement whose cases are string literals.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
MachineInstrBundleIterator< MachineInstr > iterator
Type * getReturnType() const
Returns the type of the ret val.
int64_t getOffset() const
static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode)
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
LLVM Basic Block Representation.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
unsigned getOrigAlign() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
bool isFloatingPointOperation() const
Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Value * getCompareOperand()
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
static MachineBasicBlock * emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
unsigned getLargestLegalIntTypeSizeInBits() const
Returns the size of largest legal integer type size, or 0 if none are set.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
self_iterator getIterator()
Class to represent integer types.
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
static bool CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
std::vector< ArgListEntry > ArgListTy
unsigned getAlignment() const
static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
bool isPositionIndependent() const
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp(unsigned XLen, AtomicRMWInst::BinOp BinOp)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Value * CreateTrunc(Value *V, Type *DestTy, const Twine &Name="")
This struct is a compact representation of a valid (non-zero power of two) alignment.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
The memory access writes data.
bool isReleaseOrStronger(AtomicOrdering ao)
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand...
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
static const MCPhysReg ArgGPRs[]
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned TargetFlags=0)
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Align max(MaybeAlign Lhs, Align Rhs)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MachineOperand class - Representation of each machine instruction operand.
static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG)
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
Look at Op.
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Byte Swap and Counting operators.
Type * getReturnType() const
static bool isSelectPseudo(MachineInstr &MI)
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
FunctionType * getFunctionType() const
Returns the FunctionType for me.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Class for arbitrary precision integers.
unsigned getByValAlign() const
CodeModel::Model getCodeModel() const
Returns the code model.
amdgpu Simplify well known AMD library false FunctionCallee Callee
Select(COND, TRUEVAL, FALSEVAL).
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
const SysReg * lookupSysRegByName(StringRef)
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64)
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isVector() const
Return true if this is a vector value type.
unsigned AllocateStack(unsigned Size, unsigned Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
LLVM_NODISCARD bool empty() const
StringRef getValueAsString() const
Return the attribute's value as a string.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
int64_t getOffset() const
static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
void push_back(MachineInstr *MI)
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
unsigned getOpcode() const
FSINCOS - Compute both fsin and fcos as a single operation.
SDValue getValue(unsigned R) const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
LLVM_NODISCARD std::string lower() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getMinSignedBits() const
Get the minimum bit size for this signed APInt.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
SDValue getRegister(unsigned Reg, EVT VT)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue getValueType(EVT)
void setVarArgsSaveSize(int Size)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Primary interface to the complete machine description for the target machine.
int getVarArgsFrameIndex() const
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
Register getReg() const
getReg - Returns the register number.
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
TRUNCATE - Completely drop the high bits.
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Perform various unary floating-point operations inspired by libm.
Function Alias Analysis false
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
LLVMContext * getContext() const
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Type * getElementType() const
Wrapper class representing virtual and physical registers.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...