28namespace RISCVSysReg {
29#define GET_SysRegsList_IMPL
30#include "RISCVGenSearchableTables.inc"
33namespace RISCVInsnOpcode {
34#define GET_RISCVOpcodesList_IMPL
35#include "RISCVGenSearchableTables.inc"
42 bool IsRV64 = TT.isArch64Bit();
43 bool IsRVE = FeatureBits[RISCV::FeatureRVE];
48 <<
"' is not a recognized ABI for this target (ignoring target-abi)\n";
49 }
else if (ABIName.
starts_with(
"ilp32") && IsRV64) {
50 errs() <<
"32-bit ABIs are not supported for 64-bit targets (ignoring "
53 }
else if (ABIName.
starts_with(
"lp64") && !IsRV64) {
54 errs() <<
"64-bit ABIs are not supported for 32-bit targets (ignoring "
57 }
else if (!IsRV64 && IsRVE && TargetABI !=
ABI_ILP32E &&
61 <<
"Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
63 }
else if (IsRV64 && IsRVE && TargetABI !=
ABI_LP64E &&
67 <<
"Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
73 FeatureBits[RISCV::FeatureStdExtD])
110namespace RISCVFeatures {
113 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
115 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
117 if (FeatureBits[RISCV::Feature32Bit] &&
118 FeatureBits[RISCV::Feature64Bit])
124 unsigned XLen = IsRV64 ? 64 : 32;
125 std::vector<std::string> FeatureVector;
128 if (FeatureBits[Feature.Value] &&
130 FeatureVector.push_back(std::string(
"+") + Feature.Key);
138#define GEN_UNCOMPRESS_INSTR
139#define GEN_COMPRESS_INSTR
140#include "RISCVGenCompressInstEmitter.inc"
144 return compressInst(OutInst,
MI, STI);
149 return uncompressInst(OutInst,
MI, STI);
154 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
155 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
156 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
157 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
158 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
159 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
160 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
161 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
162 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
163 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
170 "Unexpected semantics");
185 if (Imm.extractBitsAsZExtValue(21, 0) != 0)
188 bool Sign = Imm.extractBitsAsZExtValue(1, 31);
189 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);
190 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);
194 EMI->second != Mantissa)
211 assert(Imm != 1 && Imm != 30 && Imm != 31 &&
"Unsupported immediate");
223 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
224 return bit_cast<float>(
I);
229 if (SlistEncode > 4) {
231 if (SlistEncode == 15)
233 else if (SlistEncode > 5 && SlistEncode <= 14)
234 OS <<
"-s" << (SlistEncode - 5);
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
const fltSemantics & getSemantics() const
APInt bitcastToAPInt() const
bool isSmallestNormalized() const
Class for arbitrary precision integers.
Tagged union holding either a T or a Error.
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
static bool isSupportedExtensionFeature(StringRef Ext)
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatures(unsigned XLen, const std::vector< std::string > &Features)
Parse RISC-V ISA info from feature vector.
StringRef - Represent a constant reference to a string, i.e.
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
constexpr bool empty() const
empty - Check if the string is empty.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
This class implements an extremely fast bulk output stream that can only output to a stream.
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
void printSpimm(int64_t Spimm, raw_ostream &OS)
This is an optimization pass for GlobalISel generic memory operations.
static constexpr std::pair< uint8_t, uint8_t > LoadFP32ImmArr[]
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
static const fltSemantics & IEEEsingle() LLVM_READNONE
static constexpr roundingMode rmNearestTiesToEven
static const fltSemantics & IEEEdouble() LLVM_READNONE
static const fltSemantics & IEEEhalf() LLVM_READNONE
opStatus
IEEE-754R 7: Default exception handling.
Used to provide key value pairs for feature and CPU bit flags.