LLVM  14.0.0git
RISCVBaseInfo.cpp
Go to the documentation of this file.
1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVBaseInfo.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/Triple.h"
20 
21 namespace llvm {
22 
23 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
24 
25 namespace RISCVSysReg {
26 #define GET_SysRegsList_IMPL
27 #include "RISCVGenSearchableTables.inc"
28 } // namespace RISCVSysReg
29 
30 namespace RISCVABI {
31 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
32  StringRef ABIName) {
33  auto TargetABI = getTargetABI(ABIName);
34  bool IsRV64 = TT.isArch64Bit();
35  bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
36 
37  if (!ABIName.empty() && TargetABI == ABI_Unknown) {
38  errs()
39  << "'" << ABIName
40  << "' is not a recognized ABI for this target (ignoring target-abi)\n";
41  } else if (ABIName.startswith("ilp32") && IsRV64) {
42  errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
43  "target-abi)\n";
44  TargetABI = ABI_Unknown;
45  } else if (ABIName.startswith("lp64") && !IsRV64) {
46  errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
47  "target-abi)\n";
48  TargetABI = ABI_Unknown;
49  } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
50  // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
51  errs()
52  << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
53  TargetABI = ABI_Unknown;
54  }
55 
56  if (TargetABI != ABI_Unknown)
57  return TargetABI;
58 
59  // For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given
60  // or an invalid/unrecognised string is given. In the future, it might be
61  // worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when
62  // hardware support for floating point is present.
63  if (IsRV32E)
64  return ABI_ILP32E;
65  if (IsRV64)
66  return ABI_LP64;
67  return ABI_ILP32;
68 }
69 
71  auto TargetABI = StringSwitch<ABI>(ABIName)
72  .Case("ilp32", ABI_ILP32)
73  .Case("ilp32f", ABI_ILP32F)
74  .Case("ilp32d", ABI_ILP32D)
75  .Case("ilp32e", ABI_ILP32E)
76  .Case("lp64", ABI_LP64)
77  .Case("lp64f", ABI_LP64F)
78  .Case("lp64d", ABI_LP64D)
80  return TargetABI;
81 }
82 
83 // To avoid the BP value clobbered by a function call, we need to choose a
84 // callee saved register to save the value. RV32E only has X8 and X9 as callee
85 // saved registers and X8 will be used as fp. So we choose X9 as bp.
86 MCRegister getBPReg() { return RISCV::X9; }
87 
88 // Returns the register holding shadow call stack pointer.
89 MCRegister getSCSPReg() { return RISCV::X18; }
90 
91 } // namespace RISCVABI
92 
93 namespace RISCVFeatures {
94 
95 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
96  if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
97  report_fatal_error("RV64 target requires an RV64 CPU");
98  if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit])
99  report_fatal_error("RV32 target requires an RV32 CPU");
100  if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
101  report_fatal_error("RV32E can't be enabled for an RV64 target");
102 }
103 
104 void toFeatureVector(std::vector<std::string> &FeatureVector,
105  const FeatureBitset &FeatureBits) {
106  for (auto Feature : RISCVFeatureKV) {
107  if (FeatureBits[Feature.Value] &&
109  FeatureVector.push_back(std::string("+") + Feature.Key);
110  }
111 }
112 
113 } // namespace RISCVFeatures
114 
115 // Encode VTYPE into the binary format used by the the VSETVLI instruction which
116 // is used by our MC layer representation.
117 //
118 // Bits | Name | Description
119 // -----+------------+------------------------------------------------
120 // 7 | vma | Vector mask agnostic
121 // 6 | vta | Vector tail agnostic
122 // 5:3 | vsew[2:0] | Standard element width (SEW) setting
123 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
125  bool TailAgnostic, bool MaskAgnostic) {
126  assert(isValidSEW(SEW) && "Invalid SEW");
127  unsigned VLMULBits = static_cast<unsigned>(VLMUL);
128  unsigned VSEWBits = Log2_32(SEW) - 3;
129  unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
130  if (TailAgnostic)
131  VTypeI |= 0x40;
132  if (MaskAgnostic)
133  VTypeI |= 0x80;
134 
135  return VTypeI;
136 }
137 
138 std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
139  switch (VLMUL) {
140  default:
141  llvm_unreachable("Unexpected LMUL value!");
146  return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
150  return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
151  }
152 }
153 
154 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
155  unsigned Sew = getSEW(VType);
156  OS << "e" << Sew;
157 
158  unsigned LMul;
159  bool Fractional;
160  std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
161 
162  if (Fractional)
163  OS << ", mf";
164  else
165  OS << ", m";
166  OS << LMul;
167 
168  if (isTailAgnostic(VType))
169  OS << ", ta";
170  else
171  OS << ", tu";
172 
173  if (isMaskAgnostic(VType))
174  OS << ", ma";
175  else
176  OS << ", mu";
177 }
178 
179 } // namespace llvm
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::RISCVII::LMUL_1
@ LMUL_1
Definition: RISCVBaseInfo.h:101
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:310
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:286
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:70
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::RISCVII::LMUL_8
@ LMUL_8
Definition: RISCVBaseInfo.h:104
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:344
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:374
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:95
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:86
llvm::RISCVVType::getSEW
static unsigned getSEW(unsigned VType)
Definition: RISCVBaseInfo.h:369
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:305
llvm::RISCVII::LMUL_4
@ LMUL_4
Definition: RISCVBaseInfo.h:103
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:309
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:596
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:307
MCSubtargetInfo.h
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:308
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:89
llvm::SubtargetFeatureKV
Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:34
llvm::RISCVVType::decodeVLMUL
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
Definition: RISCVBaseInfo.cpp:138
RISCVISAInfo.h
ArrayRef.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RISCVFeatures::toFeatureVector
void toFeatureVector(std::vector< std::string > &FeatureVector, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:104
Triple.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::RISCVII::LMUL_2
@ LMUL_2
Definition: RISCVBaseInfo.h:102
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:154
llvm::RISCVVType::getVLMUL
static RISCVII::VLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:356
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:311
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:376
llvm::RISCVVType::encodeVTYPE
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.cpp:124
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:31
llvm::RISCVISAInfo::isSupportedExtensionFeature
static bool isSupportedExtensionFeature(StringRef Ext)
Definition: RISCVISAInfo.cpp:139
RISCVBaseInfo.h
llvm::RISCVII::LMUL_F8
@ LMUL_F8
Definition: RISCVBaseInfo.h:106
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:312
llvm::RISCVII::LMUL_F4
@ LMUL_F4
Definition: RISCVBaseInfo.h:107
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:100
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:306
llvm::RISCVFeatureKV
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
Definition: RISCVBaseInfo.cpp:23
raw_ostream.h
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:304
llvm::RISCVII::LMUL_F2
@ LMUL_F2
Definition: RISCVBaseInfo.h:108
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24