LLVM  16.0.0git
RISCVBaseInfo.cpp
Go to the documentation of this file.
1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVBaseInfo.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/Triple.h"
21 
22 namespace llvm {
23 
24 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
25 
26 namespace RISCVSysReg {
27 #define GET_SysRegsList_IMPL
28 #include "RISCVGenSearchableTables.inc"
29 } // namespace RISCVSysReg
30 
31 namespace RISCVInsnOpcode {
32 #define GET_RISCVOpcodesList_IMPL
33 #include "RISCVGenSearchableTables.inc"
34 } // namespace RISCVInsnOpcode
35 
36 namespace RISCVABI {
37 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
38  StringRef ABIName) {
39  auto TargetABI = getTargetABI(ABIName);
40  bool IsRV64 = TT.isArch64Bit();
41  bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
42 
43  if (!ABIName.empty() && TargetABI == ABI_Unknown) {
44  errs()
45  << "'" << ABIName
46  << "' is not a recognized ABI for this target (ignoring target-abi)\n";
47  } else if (ABIName.startswith("ilp32") && IsRV64) {
48  errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
49  "target-abi)\n";
50  TargetABI = ABI_Unknown;
51  } else if (ABIName.startswith("lp64") && !IsRV64) {
52  errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
53  "target-abi)\n";
54  TargetABI = ABI_Unknown;
55  } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
56  // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
57  errs()
58  << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
59  TargetABI = ABI_Unknown;
60  }
61 
62  if (TargetABI != ABI_Unknown)
63  return TargetABI;
64 
65  // If no explicit ABI is given, try to compute the default ABI.
66  auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
67  if (!ISAInfo)
68  report_fatal_error(ISAInfo.takeError());
69  return getTargetABI((*ISAInfo)->computeDefaultABI());
70 }
71 
73  auto TargetABI = StringSwitch<ABI>(ABIName)
74  .Case("ilp32", ABI_ILP32)
75  .Case("ilp32f", ABI_ILP32F)
76  .Case("ilp32d", ABI_ILP32D)
77  .Case("ilp32e", ABI_ILP32E)
78  .Case("lp64", ABI_LP64)
79  .Case("lp64f", ABI_LP64F)
80  .Case("lp64d", ABI_LP64D)
82  return TargetABI;
83 }
84 
85 // To avoid the BP value clobbered by a function call, we need to choose a
86 // callee saved register to save the value. RV32E only has X8 and X9 as callee
87 // saved registers and X8 will be used as fp. So we choose X9 as bp.
88 MCRegister getBPReg() { return RISCV::X9; }
89 
90 // Returns the register holding shadow call stack pointer.
91 MCRegister getSCSPReg() { return RISCV::X18; }
92 
93 } // namespace RISCVABI
94 
95 namespace RISCVFeatures {
96 
97 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
98  if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
99  report_fatal_error("RV64 target requires an RV64 CPU");
100  if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
101  report_fatal_error("RV32 target requires an RV32 CPU");
102  if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
103  report_fatal_error("RV32E can't be enabled for an RV64 target");
104  if (FeatureBits[RISCV::Feature32Bit] &&
105  FeatureBits[RISCV::Feature64Bit])
106  report_fatal_error("RV32 and RV64 can't be combined");
107 }
108 
110 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
111  unsigned XLen = IsRV64 ? 64 : 32;
112  std::vector<std::string> FeatureVector;
113  // Convert FeatureBitset to FeatureVector.
114  for (auto Feature : RISCVFeatureKV) {
115  if (FeatureBits[Feature.Value] &&
117  FeatureVector.push_back(std::string("+") + Feature.Key);
118  }
119  return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
120 }
121 
122 } // namespace RISCVFeatures
123 
124 // Encode VTYPE into the binary format used by the the VSETVLI instruction which
125 // is used by our MC layer representation.
126 //
127 // Bits | Name | Description
128 // -----+------------+------------------------------------------------
129 // 7 | vma | Vector mask agnostic
130 // 6 | vta | Vector tail agnostic
131 // 5:3 | vsew[2:0] | Standard element width (SEW) setting
132 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
134  bool TailAgnostic, bool MaskAgnostic) {
135  assert(isValidSEW(SEW) && "Invalid SEW");
136  unsigned VLMULBits = static_cast<unsigned>(VLMUL);
137  unsigned VSEWBits = encodeSEW(SEW);
138  unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
139  if (TailAgnostic)
140  VTypeI |= 0x40;
141  if (MaskAgnostic)
142  VTypeI |= 0x80;
143 
144  return VTypeI;
145 }
146 
147 std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
148  switch (VLMUL) {
149  default:
150  llvm_unreachable("Unexpected LMUL value!");
155  return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
159  return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
160  }
161 }
162 
163 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
164  unsigned Sew = getSEW(VType);
165  OS << "e" << Sew;
166 
167  unsigned LMul;
168  bool Fractional;
169  std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
170 
171  if (Fractional)
172  OS << ", mf";
173  else
174  OS << ", m";
175  OS << LMul;
176 
177  if (isTailAgnostic(VType))
178  OS << ", ta";
179  else
180  OS << ", tu";
181 
182  if (isMaskAgnostic(VType))
183  OS << ", ma";
184  else
185  OS << ", mu";
186 }
187 
189  unsigned LMul;
190  bool Fractional;
191  std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
192 
193  // Convert LMul to a fixed point value with 3 fractional bits.
194  LMul = Fractional ? (8 / LMul) : (LMul * 8);
195 
196  assert(SEW >= 8 && "Unexpected SEW value");
197  return (SEW * 8) / LMul;
198 }
199 
200 } // namespace llvm
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::RISCVII::LMUL_1
@ LMUL_1
Definition: RISCVBaseInfo.h:109
llvm::RISCVABI::ABI_LP64F
@ ABI_LP64F
Definition: RISCVBaseInfo.h:378
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:72
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::RISCVII::LMUL_8
@ LMUL_8
Definition: RISCVBaseInfo.h:112
llvm::RISCVVType::isValidSEW
static bool isValidSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:411
llvm::RISCVVType::isTailAgnostic
static bool isTailAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:452
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:41
TargetParser.h
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:97
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:88
llvm::RISCVVType::getSEW
static unsigned getSEW(unsigned VType)
Definition: RISCVBaseInfo.h:447
llvm::RISCVABI::ABI_ILP32
@ ABI_ILP32
Definition: RISCVBaseInfo.h:373
llvm::RISCVII::LMUL_4
@ LMUL_4
Definition: RISCVBaseInfo.h:111
llvm::RISCVABI::ABI_LP64
@ ABI_LP64
Definition: RISCVBaseInfo.h:377
llvm::StringRef::startswith
bool startswith(StringRef Prefix) const
Definition: StringRef.h:260
llvm::RISCVVType::encodeSEW
static unsigned encodeSEW(unsigned SEW)
Definition: RISCVBaseInfo.h:442
MaskAgnostic
bool MaskAgnostic
Definition: RISCVInsertVSETVLI.cpp:599
llvm::RISCVABI::ABI_ILP32D
@ ABI_ILP32D
Definition: RISCVBaseInfo.h:375
MCSubtargetInfo.h
llvm::RISCVISAInfo::parseFeatures
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatures(unsigned XLen, const std::vector< std::string > &Features)
Parse RISCV ISA info from feature vector.
Definition: RISCVISAInfo.cpp:455
llvm::RISCVABI::ABI_ILP32E
@ ABI_ILP32E
Definition: RISCVBaseInfo.h:376
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:91
llvm::RISCVFeatures::parseFeatureBits
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:110
llvm::SubtargetFeatureKV
Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:35
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::RISCVVType::decodeVLMUL
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
Definition: RISCVBaseInfo.cpp:147
RISCVISAInfo.h
ArrayRef.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Triple.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RISCVII::LMUL_2
@ LMUL_2
Definition: RISCVBaseInfo.h:110
TailAgnostic
bool TailAgnostic
Definition: RISCVInsertVSETVLI.cpp:599
llvm::RISCVVType::printVType
void printVType(unsigned VType, raw_ostream &OS)
Definition: RISCVBaseInfo.cpp:163
llvm::RISCVVType::getVLMUL
static RISCVII::VLMUL getVLMUL(unsigned VType)
Definition: RISCVBaseInfo.h:423
llvm::RISCVABI::ABI_LP64D
@ ABI_LP64D
Definition: RISCVBaseInfo.h:379
llvm::RISCVVType::isMaskAgnostic
static bool isMaskAgnostic(unsigned VType)
Definition: RISCVBaseInfo.h:454
llvm::RISCVVType::encodeVTYPE
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
Definition: RISCVBaseInfo.cpp:133
llvm::RISCVABI::computeTargetABI
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
Definition: RISCVBaseInfo.cpp:37
llvm::RISCVISAInfo::isSupportedExtensionFeature
static bool isSupportedExtensionFeature(StringRef Ext)
Definition: RISCVISAInfo.cpp:214
RISCVBaseInfo.h
VLMul
RISCVII::VLMUL VLMul
Definition: RISCVInsertVSETVLI.cpp:639
SEW
unsigned SEW
Definition: RISCVInsertVSETVLI.cpp:643
llvm::RISCVII::LMUL_F8
@ LMUL_F8
Definition: RISCVBaseInfo.h:114
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:380
llvm::RISCVII::LMUL_F4
@ LMUL_F4
Definition: RISCVBaseInfo.h:115
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:108
llvm::RISCVVType::getSEWLMULRatio
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
Definition: RISCVBaseInfo.cpp:188
llvm::StringSwitch::Default
R Default(T Value)
Definition: StringSwitch.h:182
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::RISCVABI::ABI_ILP32F
@ ABI_ILP32F
Definition: RISCVBaseInfo.h:374
llvm::RISCVFeatureKV
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
Definition: RISCVBaseInfo.cpp:24
raw_ostream.h
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:372
llvm::RISCVII::LMUL_F2
@ LMUL_F2
Definition: RISCVBaseInfo.h:116
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24