LLVM 18.0.0git
RISCVBaseInfo.cpp
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1//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVBaseInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCInst.h"
23
24namespace llvm {
25
26extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
27
28namespace RISCVSysReg {
29#define GET_SysRegsList_IMPL
30#define GET_SiFiveRegsList_IMPL
31#include "RISCVGenSearchableTables.inc"
32} // namespace RISCVSysReg
33
34namespace RISCVInsnOpcode {
35#define GET_RISCVOpcodesList_IMPL
36#include "RISCVGenSearchableTables.inc"
37} // namespace RISCVInsnOpcode
38
39namespace RISCVABI {
40ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
41 StringRef ABIName) {
42 auto TargetABI = getTargetABI(ABIName);
43 bool IsRV64 = TT.isArch64Bit();
44 bool IsRVE = FeatureBits[RISCV::FeatureRVE];
45
46 if (!ABIName.empty() && TargetABI == ABI_Unknown) {
47 errs()
48 << "'" << ABIName
49 << "' is not a recognized ABI for this target (ignoring target-abi)\n";
50 } else if (ABIName.startswith("ilp32") && IsRV64) {
51 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
52 "target-abi)\n";
53 TargetABI = ABI_Unknown;
54 } else if (ABIName.startswith("lp64") && !IsRV64) {
55 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
56 "target-abi)\n";
57 TargetABI = ABI_Unknown;
58 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&
59 TargetABI != ABI_Unknown) {
60 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
61 errs()
62 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
63 TargetABI = ABI_Unknown;
64 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
65 TargetABI != ABI_Unknown) {
66 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
67 errs()
68 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
69 TargetABI = ABI_Unknown;
70 }
71
72 if (TargetABI != ABI_Unknown)
73 return TargetABI;
74
75 // If no explicit ABI is given, try to compute the default ABI.
76 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
77 if (!ISAInfo)
78 report_fatal_error(ISAInfo.takeError());
79 return getTargetABI((*ISAInfo)->computeDefaultABI());
80}
81
83 auto TargetABI = StringSwitch<ABI>(ABIName)
84 .Case("ilp32", ABI_ILP32)
85 .Case("ilp32f", ABI_ILP32F)
86 .Case("ilp32d", ABI_ILP32D)
87 .Case("ilp32e", ABI_ILP32E)
88 .Case("lp64", ABI_LP64)
89 .Case("lp64f", ABI_LP64F)
90 .Case("lp64d", ABI_LP64D)
91 .Case("lp64e", ABI_LP64E)
93 return TargetABI;
94}
95
96// To avoid the BP value clobbered by a function call, we need to choose a
97// callee saved register to save the value. RV32E only has X8 and X9 as callee
98// saved registers and X8 will be used as fp. So we choose X9 as bp.
99MCRegister getBPReg() { return RISCV::X9; }
100
101// Returns the register holding shadow call stack pointer.
102MCRegister getSCSPReg() { return RISCV::X3; }
103
104} // namespace RISCVABI
105
106namespace RISCVFeatures {
107
108void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
109 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
110 report_fatal_error("RV64 target requires an RV64 CPU");
111 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
112 report_fatal_error("RV32 target requires an RV32 CPU");
113 if (FeatureBits[RISCV::Feature32Bit] &&
114 FeatureBits[RISCV::Feature64Bit])
115 report_fatal_error("RV32 and RV64 can't be combined");
116}
117
119parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
120 unsigned XLen = IsRV64 ? 64 : 32;
121 std::vector<std::string> FeatureVector;
122 // Convert FeatureBitset to FeatureVector.
123 for (auto Feature : RISCVFeatureKV) {
124 if (FeatureBits[Feature.Value] &&
126 FeatureVector.push_back(std::string("+") + Feature.Key);
127 }
128 return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
129}
130
131} // namespace RISCVFeatures
132
133// Encode VTYPE into the binary format used by the the VSETVLI instruction which
134// is used by our MC layer representation.
135//
136// Bits | Name | Description
137// -----+------------+------------------------------------------------
138// 7 | vma | Vector mask agnostic
139// 6 | vta | Vector tail agnostic
140// 5:3 | vsew[2:0] | Standard element width (SEW) setting
141// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
143 bool TailAgnostic, bool MaskAgnostic) {
144 assert(isValidSEW(SEW) && "Invalid SEW");
145 unsigned VLMULBits = static_cast<unsigned>(VLMUL);
146 unsigned VSEWBits = encodeSEW(SEW);
147 unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
148 if (TailAgnostic)
149 VTypeI |= 0x40;
150 if (MaskAgnostic)
151 VTypeI |= 0x80;
152
153 return VTypeI;
154}
155
156std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
157 switch (VLMUL) {
158 default:
159 llvm_unreachable("Unexpected LMUL value!");
164 return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
168 return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
169 }
170}
171
172void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
173 unsigned Sew = getSEW(VType);
174 OS << "e" << Sew;
175
176 unsigned LMul;
177 bool Fractional;
178 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
179
180 if (Fractional)
181 OS << ", mf";
182 else
183 OS << ", m";
184 OS << LMul;
185
186 if (isTailAgnostic(VType))
187 OS << ", ta";
188 else
189 OS << ", tu";
190
191 if (isMaskAgnostic(VType))
192 OS << ", ma";
193 else
194 OS << ", mu";
195}
196
198 unsigned LMul;
199 bool Fractional;
200 std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
201
202 // Convert LMul to a fixed point value with 3 fractional bits.
203 LMul = Fractional ? (8 / LMul) : (LMul * 8);
204
205 assert(SEW >= 8 && "Unexpected SEW value");
206 return (SEW * 8) / LMul;
207}
208
209// Include the auto-generated portion of the compress emitter.
210#define GEN_UNCOMPRESS_INSTR
211#define GEN_COMPRESS_INSTR
212#include "RISCVGenCompressInstEmitter.inc"
213
214bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
215 const MCSubtargetInfo &STI) {
216 return compressInst(OutInst, MI, STI);
217}
218
219bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
220 const MCSubtargetInfo &STI) {
221 return uncompressInst(OutInst, MI, STI);
222}
223
224// Lookup table for fli.s for entries 2-31.
225static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
226 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
227 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
228 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
229 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
230 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
231 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
232 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
233 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
234 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
235 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
236};
237
239 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
240 &FPImm.getSemantics() == &APFloat::IEEEdouble() ||
241 &FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
242 "Unexpected semantics");
243
244 // Handle the minimum normalized value which is different for each type.
245 if (FPImm.isSmallestNormalized())
246 return 1;
247
248 // Convert to single precision to use its lookup table.
249 bool LosesInfo;
252 if (Status != APFloat::opOK || LosesInfo)
253 return -1;
254
255 APInt Imm = FPImm.bitcastToAPInt();
256
257 if (Imm.extractBitsAsZExtValue(21, 0) != 0)
258 return -1;
259
260 bool Sign = Imm.extractBitsAsZExtValue(1, 31);
261 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);
262 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);
263
264 auto EMI = llvm::lower_bound(LoadFP32ImmArr, std::make_pair(Exp, Mantissa));
265 if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp ||
266 EMI->second != Mantissa)
267 return -1;
268
269 // Table doesn't have entry 0 or 1.
270 int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2;
271
272 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
273 if (Sign) {
274 if (Entry == 16)
275 return 0;
276 return false;
277 }
278
279 return Entry;
280}
281
282float RISCVLoadFPImm::getFPImm(unsigned Imm) {
283 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
284
285 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
286 uint32_t Sign = 0;
287 if (Imm == 0) {
288 Sign = 0b1;
289 Imm = 16;
290 }
291
292 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
293 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
294
295 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
296 return bit_cast<float>(I);
297}
298
299void RISCVZC::printRlist(unsigned SlistEncode, raw_ostream &OS) {
300 OS << "{ra";
301 if (SlistEncode > 4) {
302 OS << ", s0";
303 if (SlistEncode == 15)
304 OS << "-s11";
305 else if (SlistEncode > 5 && SlistEncode <= 14)
306 OS << "-s" << (SlistEncode - 5);
307 }
308 OS << "}";
309}
310
311void RISCVZC::printSpimm(int64_t Spimm, raw_ostream &OS) { OS << Spimm; }
312
313} // namespace llvm
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
bool TailAgnostic
bool MaskAgnostic
RISCVII::VLMUL VLMul
unsigned SEW
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:5196
const fltSemantics & getSemantics() const
Definition: APFloat.h:1301
APInt bitcastToAPInt() const
Definition: APFloat.h:1208
bool isSmallestNormalized() const
Definition: APFloat.h:1313
Class for arbitrary precision integers.
Definition: APInt.h:76
Tagged union holding either a T or a Error.
Definition: Error.h:468
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
static bool isSupportedExtensionFeature(StringRef Ext)
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatures(unsigned XLen, const std::vector< std::string > &Features)
Parse RISC-V ISA info from feature vector.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
bool startswith(StringRef Prefix) const
Definition: StringRef.h:261
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
void printSpimm(int64_t Spimm, raw_ostream &OS)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static constexpr std::pair< uint8_t, uint8_t > LoadFP32ImmArr[]
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1946
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
static const fltSemantics & IEEEsingle() LLVM_READNONE
Definition: APFloat.cpp:249
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:230
static const fltSemantics & IEEEdouble() LLVM_READNONE
Definition: APFloat.cpp:250
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:247
opStatus
IEEE-754R 7: Default exception handling.
Definition: APFloat.h:246
Used to provide key value pairs for feature and CPU bit flags.