LLVM 17.0.0git
RISCVBaseInfo.cpp
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1//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVBaseInfo.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/MC/MCInst.h"
23
24namespace llvm {
25
26extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
27
28namespace RISCVSysReg {
29#define GET_SysRegsList_IMPL
30#include "RISCVGenSearchableTables.inc"
31} // namespace RISCVSysReg
32
33namespace RISCVInsnOpcode {
34#define GET_RISCVOpcodesList_IMPL
35#include "RISCVGenSearchableTables.inc"
36} // namespace RISCVInsnOpcode
37
38namespace RISCVABI {
40 StringRef ABIName) {
41 auto TargetABI = getTargetABI(ABIName);
42 bool IsRV64 = TT.isArch64Bit();
43 bool IsRVE = FeatureBits[RISCV::FeatureRVE];
44
45 if (!ABIName.empty() && TargetABI == ABI_Unknown) {
46 errs()
47 << "'" << ABIName
48 << "' is not a recognized ABI for this target (ignoring target-abi)\n";
49 } else if (ABIName.startswith("ilp32") && IsRV64) {
50 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
51 "target-abi)\n";
52 TargetABI = ABI_Unknown;
53 } else if (ABIName.startswith("lp64") && !IsRV64) {
54 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
55 "target-abi)\n";
56 TargetABI = ABI_Unknown;
57 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&
58 TargetABI != ABI_Unknown) {
59 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
60 errs()
61 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
62 TargetABI = ABI_Unknown;
63 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
64 TargetABI != ABI_Unknown) {
65 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
66 errs()
67 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
68 TargetABI = ABI_Unknown;
69 }
70
71 if (TargetABI != ABI_Unknown)
72 return TargetABI;
73
74 // If no explicit ABI is given, try to compute the default ABI.
75 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
76 if (!ISAInfo)
77 report_fatal_error(ISAInfo.takeError());
78 return getTargetABI((*ISAInfo)->computeDefaultABI());
79}
80
82 auto TargetABI = StringSwitch<ABI>(ABIName)
83 .Case("ilp32", ABI_ILP32)
84 .Case("ilp32f", ABI_ILP32F)
85 .Case("ilp32d", ABI_ILP32D)
86 .Case("ilp32e", ABI_ILP32E)
87 .Case("lp64", ABI_LP64)
88 .Case("lp64f", ABI_LP64F)
89 .Case("lp64d", ABI_LP64D)
90 .Case("lp64e", ABI_LP64E)
92 return TargetABI;
93}
94
95// To avoid the BP value clobbered by a function call, we need to choose a
96// callee saved register to save the value. RV32E only has X8 and X9 as callee
97// saved registers and X8 will be used as fp. So we choose X9 as bp.
98MCRegister getBPReg() { return RISCV::X9; }
99
100// Returns the register holding shadow call stack pointer.
101MCRegister getSCSPReg() { return RISCV::X18; }
102
103} // namespace RISCVABI
104
105namespace RISCVFeatures {
106
107void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
108 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
109 report_fatal_error("RV64 target requires an RV64 CPU");
110 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
111 report_fatal_error("RV32 target requires an RV32 CPU");
112 if (FeatureBits[RISCV::Feature32Bit] &&
113 FeatureBits[RISCV::Feature64Bit])
114 report_fatal_error("RV32 and RV64 can't be combined");
115}
116
118parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
119 unsigned XLen = IsRV64 ? 64 : 32;
120 std::vector<std::string> FeatureVector;
121 // Convert FeatureBitset to FeatureVector.
122 for (auto Feature : RISCVFeatureKV) {
123 if (FeatureBits[Feature.Value] &&
125 FeatureVector.push_back(std::string("+") + Feature.Key);
126 }
127 return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
128}
129
130} // namespace RISCVFeatures
131
132// Encode VTYPE into the binary format used by the the VSETVLI instruction which
133// is used by our MC layer representation.
134//
135// Bits | Name | Description
136// -----+------------+------------------------------------------------
137// 7 | vma | Vector mask agnostic
138// 6 | vta | Vector tail agnostic
139// 5:3 | vsew[2:0] | Standard element width (SEW) setting
140// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
142 bool TailAgnostic, bool MaskAgnostic) {
143 assert(isValidSEW(SEW) && "Invalid SEW");
144 unsigned VLMULBits = static_cast<unsigned>(VLMUL);
145 unsigned VSEWBits = encodeSEW(SEW);
146 unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
147 if (TailAgnostic)
148 VTypeI |= 0x40;
149 if (MaskAgnostic)
150 VTypeI |= 0x80;
151
152 return VTypeI;
153}
154
155std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
156 switch (VLMUL) {
157 default:
158 llvm_unreachable("Unexpected LMUL value!");
163 return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
167 return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
168 }
169}
170
171void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
172 unsigned Sew = getSEW(VType);
173 OS << "e" << Sew;
174
175 unsigned LMul;
176 bool Fractional;
177 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
178
179 if (Fractional)
180 OS << ", mf";
181 else
182 OS << ", m";
183 OS << LMul;
184
185 if (isTailAgnostic(VType))
186 OS << ", ta";
187 else
188 OS << ", tu";
189
190 if (isMaskAgnostic(VType))
191 OS << ", ma";
192 else
193 OS << ", mu";
194}
195
197 unsigned LMul;
198 bool Fractional;
199 std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
200
201 // Convert LMul to a fixed point value with 3 fractional bits.
202 LMul = Fractional ? (8 / LMul) : (LMul * 8);
203
204 assert(SEW >= 8 && "Unexpected SEW value");
205 return (SEW * 8) / LMul;
206}
207
208// Include the auto-generated portion of the compress emitter.
209#define GEN_UNCOMPRESS_INSTR
210#define GEN_COMPRESS_INSTR
211#include "RISCVGenCompressInstEmitter.inc"
212
213bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
214 const MCSubtargetInfo &STI) {
215 return compressInst(OutInst, MI, STI);
216}
217
218bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
219 const MCSubtargetInfo &STI) {
220 return uncompressInst(OutInst, MI, STI);
221}
222
223// Lookup table for fli.s for entries 2-31.
224static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
225 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
226 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
227 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
228 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
229 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
230 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
231 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
232 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
233 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
234 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
235};
236
238 assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
239 &FPImm.getSemantics() == &APFloat::IEEEdouble() ||
240 &FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
241 "Unexpected semantics");
242
243 // Handle the minimum normalized value which is different for each type.
244 if (FPImm.isSmallestNormalized())
245 return 1;
246
247 // Convert to single precision to use its lookup table.
248 bool LosesInfo;
251 if (Status != APFloat::opOK || LosesInfo)
252 return -1;
253
254 APInt Imm = FPImm.bitcastToAPInt();
255
256 if (Imm.extractBitsAsZExtValue(21, 0) != 0)
257 return -1;
258
259 bool Sign = Imm.extractBitsAsZExtValue(1, 31);
260 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);
261 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);
262
263 auto EMI = llvm::lower_bound(LoadFP32ImmArr, std::make_pair(Exp, Mantissa));
264 if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp ||
265 EMI->second != Mantissa)
266 return -1;
267
268 // Table doesn't have entry 0 or 1.
269 int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2;
270
271 // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
272 if (Sign) {
273 if (Entry == 16)
274 return 0;
275 return false;
276 }
277
278 return Entry;
279}
280
281float RISCVLoadFPImm::getFPImm(unsigned Imm) {
282 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
283
284 // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
285 uint32_t Sign = 0;
286 if (Imm == 0) {
287 Sign = 0b1;
288 Imm = 16;
289 }
290
291 uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
292 uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
293
294 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
295 return bit_cast<float>(I);
296}
297
298} // namespace llvm
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
RISCVII::VLMUL VLMul
unsigned SEW
bool MaskAgnostic
bool TailAgnostic
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:5450
const fltSemantics & getSemantics() const
Definition: APFloat.h:1277
APInt bitcastToAPInt() const
Definition: APFloat.h:1184
bool isSmallestNormalized() const
Definition: APFloat.h:1289
Class for arbitrary precision integers.
Definition: APInt.h:75
Tagged union holding either a T or a Error.
Definition: Error.h:470
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Generic base class for all target subtargets.
static bool isSupportedExtensionFeature(StringRef Ext)
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatures(unsigned XLen, const std::vector< std::string > &Features)
Parse RISC-V ISA info from feature vector.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
bool startswith(StringRef Prefix) const
Definition: StringRef.h:261
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ABI getTargetABI(StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static constexpr std::pair< uint8_t, uint8_t > LoadFP32ImmArr[]
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:2038
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
static const fltSemantics & IEEEsingle() LLVM_READNONE
Definition: APFloat.cpp:256
static constexpr roundingMode rmNearestTiesToEven
Definition: APFloat.h:225
static const fltSemantics & IEEEdouble() LLVM_READNONE
Definition: APFloat.cpp:259
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:250
opStatus
IEEE-754R 7: Default exception handling.
Definition: APFloat.h:241
Used to provide key value pairs for feature and CPU bit flags.