LLVM 17.0.0git
SparcInstrInfo.h
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1//===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Sparc implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
14#define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
15
16#include "SparcRegisterInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "SparcGenInstrInfo.inc"
21
22namespace llvm {
23
24class SparcSubtarget;
25
26/// SPII - This namespace holds all of the target specific flags that
27/// instruction info tracks.
28///
29namespace SPII {
30 enum {
31 Pseudo = (1<<0),
32 Load = (1<<1),
33 Store = (1<<2),
34 DelaySlot = (1<<3)
35 };
36}
37
39 const SparcRegisterInfo RI;
40 const SparcSubtarget& Subtarget;
41 virtual void anchor();
42public:
43 explicit SparcInstrInfo(SparcSubtarget &ST);
44
45 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
46 /// such, whenever a client has an instance of instruction info, it should
47 /// always be able to get register info as well (through this method).
48 ///
49 const SparcRegisterInfo &getRegisterInfo() const { return RI; }
50
51 /// isLoadFromStackSlot - If the specified machine instruction is a direct
52 /// load from a stack slot, return the virtual or physical register number of
53 /// the destination along with the FrameIndex of the loaded stack slot. If
54 /// not, return 0. This predicate must return 0 if the instruction has
55 /// any side effects other than loading from the stack slot.
56 unsigned isLoadFromStackSlot(const MachineInstr &MI,
57 int &FrameIndex) const override;
58
59 /// isStoreToStackSlot - If the specified machine instruction is a direct
60 /// store to a stack slot, return the virtual or physical register number of
61 /// the source reg along with the FrameIndex of the loaded stack slot. If
62 /// not, return 0. This predicate must return 0 if the instruction has
63 /// any side effects other than storing to the stack slot.
64 unsigned isStoreToStackSlot(const MachineInstr &MI,
65 int &FrameIndex) const override;
66
70 bool AllowModify = false) const override;
71
73 int *BytesRemoved = nullptr) const override;
74
77 const DebugLoc &DL,
78 int *BytesAdded = nullptr) const override;
79
80 bool
82
84 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
85 bool KillSrc) const override;
86
89 bool isKill, int FrameIndex,
90 const TargetRegisterClass *RC,
92 Register VReg) const override;
93
96 int FrameIndex, const TargetRegisterClass *RC,
98 Register VReg) const override;
99
101
102 // Lower pseudo instructions after register allocation.
103 bool expandPostRAPseudo(MachineInstr &MI) const override;
104};
105
106}
107
108#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
SmallVector< MachineOperand, 4 > Cond
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Representation of each machine instruction.
Definition: MachineInstr.h:68
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Register getGlobalBaseReg(MachineFunction *MF) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
const SparcRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18