LLVM  16.0.0git
SparcInstrInfo.cpp
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1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Sparc implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SparcInstrInfo.h"
14 #include "Sparc.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/MC/TargetRegistry.h"
25 
26 using namespace llvm;
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "SparcGenInstrInfo.inc"
30 
31 // Pin the vtable to this file.
32 void SparcInstrInfo::anchor() {}
33 
35  : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
36  Subtarget(ST) {}
37 
38 /// isLoadFromStackSlot - If the specified machine instruction is a direct
39 /// load from a stack slot, return the virtual or physical register number of
40 /// the destination along with the FrameIndex of the loaded stack slot. If
41 /// not, return 0. This predicate must return 0 if the instruction has
42 /// any side effects other than loading from the stack slot.
44  int &FrameIndex) const {
45  if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri ||
46  MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri ||
47  MI.getOpcode() == SP::LDQFri) {
48  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
49  MI.getOperand(2).getImm() == 0) {
50  FrameIndex = MI.getOperand(1).getIndex();
51  return MI.getOperand(0).getReg();
52  }
53  }
54  return 0;
55 }
56 
57 /// isStoreToStackSlot - If the specified machine instruction is a direct
58 /// store to a stack slot, return the virtual or physical register number of
59 /// the source reg along with the FrameIndex of the loaded stack slot. If
60 /// not, return 0. This predicate must return 0 if the instruction has
61 /// any side effects other than storing to the stack slot.
63  int &FrameIndex) const {
64  if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri ||
65  MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri ||
66  MI.getOpcode() == SP::STQFri) {
67  if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
68  MI.getOperand(1).getImm() == 0) {
69  FrameIndex = MI.getOperand(0).getIndex();
70  return MI.getOperand(2).getReg();
71  }
72  }
73  return 0;
74 }
75 
76 static bool IsIntegerCC(unsigned CC)
77 {
78  return (CC <= SPCC::ICC_VC);
79 }
80 
82 {
83  switch(CC) {
84  case SPCC::ICC_A: return SPCC::ICC_N;
85  case SPCC::ICC_N: return SPCC::ICC_A;
86  case SPCC::ICC_NE: return SPCC::ICC_E;
87  case SPCC::ICC_E: return SPCC::ICC_NE;
88  case SPCC::ICC_G: return SPCC::ICC_LE;
89  case SPCC::ICC_LE: return SPCC::ICC_G;
90  case SPCC::ICC_GE: return SPCC::ICC_L;
91  case SPCC::ICC_L: return SPCC::ICC_GE;
92  case SPCC::ICC_GU: return SPCC::ICC_LEU;
93  case SPCC::ICC_LEU: return SPCC::ICC_GU;
94  case SPCC::ICC_CC: return SPCC::ICC_CS;
95  case SPCC::ICC_CS: return SPCC::ICC_CC;
96  case SPCC::ICC_POS: return SPCC::ICC_NEG;
97  case SPCC::ICC_NEG: return SPCC::ICC_POS;
98  case SPCC::ICC_VC: return SPCC::ICC_VS;
99  case SPCC::ICC_VS: return SPCC::ICC_VC;
100 
101  case SPCC::FCC_A: return SPCC::FCC_N;
102  case SPCC::FCC_N: return SPCC::FCC_A;
103  case SPCC::FCC_U: return SPCC::FCC_O;
104  case SPCC::FCC_O: return SPCC::FCC_U;
105  case SPCC::FCC_G: return SPCC::FCC_ULE;
106  case SPCC::FCC_LE: return SPCC::FCC_UG;
107  case SPCC::FCC_UG: return SPCC::FCC_LE;
108  case SPCC::FCC_ULE: return SPCC::FCC_G;
109  case SPCC::FCC_L: return SPCC::FCC_UGE;
110  case SPCC::FCC_GE: return SPCC::FCC_UL;
111  case SPCC::FCC_UL: return SPCC::FCC_GE;
112  case SPCC::FCC_UGE: return SPCC::FCC_L;
113  case SPCC::FCC_LG: return SPCC::FCC_UE;
114  case SPCC::FCC_UE: return SPCC::FCC_LG;
115  case SPCC::FCC_NE: return SPCC::FCC_E;
116  case SPCC::FCC_E: return SPCC::FCC_NE;
117 
118  case SPCC::CPCC_A: return SPCC::CPCC_N;
119  case SPCC::CPCC_N: return SPCC::CPCC_A;
120  case SPCC::CPCC_3: [[fallthrough]];
121  case SPCC::CPCC_2: [[fallthrough]];
122  case SPCC::CPCC_23: [[fallthrough]];
123  case SPCC::CPCC_1: [[fallthrough]];
124  case SPCC::CPCC_13: [[fallthrough]];
125  case SPCC::CPCC_12: [[fallthrough]];
126  case SPCC::CPCC_123: [[fallthrough]];
127  case SPCC::CPCC_0: [[fallthrough]];
128  case SPCC::CPCC_03: [[fallthrough]];
129  case SPCC::CPCC_02: [[fallthrough]];
130  case SPCC::CPCC_023: [[fallthrough]];
131  case SPCC::CPCC_01: [[fallthrough]];
132  case SPCC::CPCC_013: [[fallthrough]];
133  case SPCC::CPCC_012:
134  // "Opposite" code is not meaningful, as we don't know
135  // what the CoProc condition means here. The cond-code will
136  // only be used in inline assembler, so this code should
137  // not be reached in a normal compilation pass.
138  llvm_unreachable("Meaningless inversion of co-processor cond code");
139  }
140  llvm_unreachable("Invalid cond code");
141 }
142 
143 static bool isUncondBranchOpcode(int Opc) {
144  return Opc == SP::BA || Opc == SP::BPA;
145 }
146 
147 static bool isI32CondBranchOpcode(int Opc) {
148  return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA ||
149  Opc == SP::BPICCNT || Opc == SP::BPICCANT;
150 }
151 
152 static bool isI64CondBranchOpcode(int Opc) {
153  return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT ||
154  Opc == SP::BPXCCANT;
155 }
156 
157 static bool isFCondBranchOpcode(int Opc) { return Opc == SP::FBCOND; }
158 
159 static bool isCondBranchOpcode(int Opc) {
160  return isI32CondBranchOpcode(Opc) || isI64CondBranchOpcode(Opc) ||
161  isFCondBranchOpcode(Opc);
162 }
163 
164 static bool isIndirectBranchOpcode(int Opc) {
165  return Opc == SP::BINDrr || Opc == SP::BINDri;
166 }
167 
170  unsigned Opc = LastInst->getOpcode();
171  int64_t CC = LastInst->getOperand(1).getImm();
172 
173  // Push the branch opcode into Cond too so later in insertBranch
174  // it can use the information to emit the correct SPARC branch opcode.
175  Cond.push_back(MachineOperand::CreateImm(Opc));
176  Cond.push_back(MachineOperand::CreateImm(CC));
177 
178  Target = LastInst->getOperand(0).getMBB();
179 }
180 
183  MachineBasicBlock *&FBB,
185  bool AllowModify) const {
187  if (I == MBB.end())
188  return false;
189 
190  if (!isUnpredicatedTerminator(*I))
191  return false;
192 
193  // Get the last instruction in the block.
194  MachineInstr *LastInst = &*I;
195  unsigned LastOpc = LastInst->getOpcode();
196 
197  // If there is only one terminator instruction, process it.
198  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
199  if (isUncondBranchOpcode(LastOpc)) {
200  TBB = LastInst->getOperand(0).getMBB();
201  return false;
202  }
203  if (isCondBranchOpcode(LastOpc)) {
204  // Block ends with fall-through condbranch.
205  parseCondBranch(LastInst, TBB, Cond);
206  return false;
207  }
208  return true; // Can't handle indirect branch.
209  }
210 
211  // Get the instruction before it if it is a terminator.
212  MachineInstr *SecondLastInst = &*I;
213  unsigned SecondLastOpc = SecondLastInst->getOpcode();
214 
215  // If AllowModify is true and the block ends with two or more unconditional
216  // branches, delete all but the first unconditional branch.
217  if (AllowModify && isUncondBranchOpcode(LastOpc)) {
218  while (isUncondBranchOpcode(SecondLastOpc)) {
219  LastInst->eraseFromParent();
220  LastInst = SecondLastInst;
221  LastOpc = LastInst->getOpcode();
222  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
223  // Return now the only terminator is an unconditional branch.
224  TBB = LastInst->getOperand(0).getMBB();
225  return false;
226  } else {
227  SecondLastInst = &*I;
228  SecondLastOpc = SecondLastInst->getOpcode();
229  }
230  }
231  }
232 
233  // If there are three terminators, we don't know what sort of block this is.
234  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
235  return true;
236 
237  // If the block ends with a B and a Bcc, handle it.
238  if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
239  parseCondBranch(SecondLastInst, TBB, Cond);
240  FBB = LastInst->getOperand(0).getMBB();
241  return false;
242  }
243 
244  // If the block ends with two unconditional branches, handle it. The second
245  // one is not executed.
246  if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
247  TBB = SecondLastInst->getOperand(0).getMBB();
248  return false;
249  }
250 
251  // ...likewise if it ends with an indirect branch followed by an unconditional
252  // branch.
253  if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
254  I = LastInst;
255  if (AllowModify)
256  I->eraseFromParent();
257  return true;
258  }
259 
260  // Otherwise, can't handle this.
261  return true;
262 }
263 
266  MachineBasicBlock *FBB,
268  const DebugLoc &DL,
269  int *BytesAdded) const {
270  assert(TBB && "insertBranch must not be told to insert a fallthrough");
271  assert((Cond.size() <= 2) &&
272  "Sparc branch conditions should have at most two components!");
273  assert(!BytesAdded && "code size not handled");
274 
275  if (Cond.empty()) {
276  assert(!FBB && "Unconditional branch with multiple successors!");
277  BuildMI(&MBB, DL, get(Subtarget.isV9() ? SP::BPA : SP::BA)).addMBB(TBB);
278  return 1;
279  }
280 
281  // Conditional branch
282  unsigned Opc = Cond[0].getImm();
283  unsigned CC = Cond[1].getImm();
284 
285  if (IsIntegerCC(CC)) {
286  BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC);
287  } else {
288  BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
289  }
290  if (!FBB)
291  return 1;
292 
293  BuildMI(&MBB, DL, get(Subtarget.isV9() ? SP::BPA : SP::BA)).addMBB(FBB);
294  return 2;
295 }
296 
298  int *BytesRemoved) const {
299  assert(!BytesRemoved && "code size not handled");
300 
302  unsigned Count = 0;
303  while (I != MBB.begin()) {
304  --I;
305 
306  if (I->isDebugInstr())
307  continue;
308 
309  if (!isCondBranchOpcode(I->getOpcode()) &&
310  !isUncondBranchOpcode(I->getOpcode()))
311  break; // Not a branch
312 
313  I->eraseFromParent();
314  I = MBB.end();
315  ++Count;
316  }
317  return Count;
318 }
319 
322  assert(Cond.size() <= 2);
323  SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm());
324  Cond[1].setImm(GetOppositeBranchCondition(CC));
325  return false;
326 }
327 
330  const DebugLoc &DL, MCRegister DestReg,
331  MCRegister SrcReg, bool KillSrc) const {
332  unsigned numSubRegs = 0;
333  unsigned movOpc = 0;
334  const unsigned *subRegIdx = nullptr;
335  bool ExtraG0 = false;
336 
337  const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
338  const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
339  const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
340  const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
341  SP::sub_odd64_then_sub_even,
342  SP::sub_odd64_then_sub_odd };
343 
344  if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
345  BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
346  .addReg(SrcReg, getKillRegState(KillSrc));
347  else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
348  subRegIdx = DW_SubRegsIdx;
349  numSubRegs = 2;
350  movOpc = SP::ORrr;
351  ExtraG0 = true;
352  } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
353  BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
354  .addReg(SrcReg, getKillRegState(KillSrc));
355  else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
356  if (Subtarget.isV9()) {
357  BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
358  .addReg(SrcReg, getKillRegState(KillSrc));
359  } else {
360  // Use two FMOVS instructions.
361  subRegIdx = DFP_FP_SubRegsIdx;
362  numSubRegs = 2;
363  movOpc = SP::FMOVS;
364  }
365  } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
366  if (Subtarget.isV9()) {
367  if (Subtarget.hasHardQuad()) {
368  BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
369  .addReg(SrcReg, getKillRegState(KillSrc));
370  } else {
371  // Use two FMOVD instructions.
372  subRegIdx = QFP_DFP_SubRegsIdx;
373  numSubRegs = 2;
374  movOpc = SP::FMOVD;
375  }
376  } else {
377  // Use four FMOVS instructions.
378  subRegIdx = QFP_FP_SubRegsIdx;
379  numSubRegs = 4;
380  movOpc = SP::FMOVS;
381  }
382  } else if (SP::ASRRegsRegClass.contains(DestReg) &&
383  SP::IntRegsRegClass.contains(SrcReg)) {
384  BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
385  .addReg(SP::G0)
386  .addReg(SrcReg, getKillRegState(KillSrc));
387  } else if (SP::IntRegsRegClass.contains(DestReg) &&
388  SP::ASRRegsRegClass.contains(SrcReg)) {
389  BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
390  .addReg(SrcReg, getKillRegState(KillSrc));
391  } else
392  llvm_unreachable("Impossible reg-to-reg copy");
393 
394  if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
395  return;
396 
398  MachineInstr *MovMI = nullptr;
399 
400  for (unsigned i = 0; i != numSubRegs; ++i) {
401  Register Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
402  Register Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
403  assert(Dst && Src && "Bad sub-register");
404 
405  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
406  if (ExtraG0)
407  MIB.addReg(SP::G0);
408  MIB.addReg(Src);
409  MovMI = MIB.getInstr();
410  }
411  // Add implicit super-register defs and kills to the last MovMI.
412  MovMI->addRegisterDefined(DestReg, TRI);
413  if (KillSrc)
414  MovMI->addRegisterKilled(SrcReg, TRI);
415 }
416 
417 void SparcInstrInfo::
419  Register SrcReg, bool isKill, int FI,
420  const TargetRegisterClass *RC,
421  const TargetRegisterInfo *TRI) const {
422  DebugLoc DL;
423  if (I != MBB.end()) DL = I->getDebugLoc();
424 
425  MachineFunction *MF = MBB.getParent();
426  const MachineFrameInfo &MFI = MF->getFrameInfo();
429  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
430 
431  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
432  if (RC == &SP::I64RegsRegClass)
433  BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
434  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
435  else if (RC == &SP::IntRegsRegClass)
436  BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
437  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
438  else if (RC == &SP::IntPairRegClass)
439  BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
440  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
441  else if (RC == &SP::FPRegsRegClass)
442  BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
443  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
444  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
445  BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
446  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
447  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
448  // Use STQFri irrespective of its legality. If STQ is not legal, it will be
449  // lowered into two STDs in eliminateFrameIndex.
450  BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
451  .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
452  else
453  llvm_unreachable("Can't store this register to stack slot");
454 }
455 
456 void SparcInstrInfo::
458  Register DestReg, int FI,
459  const TargetRegisterClass *RC,
460  const TargetRegisterInfo *TRI) const {
461  DebugLoc DL;
462  if (I != MBB.end()) DL = I->getDebugLoc();
463 
464  MachineFunction *MF = MBB.getParent();
465  const MachineFrameInfo &MFI = MF->getFrameInfo();
468  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
469 
470  if (RC == &SP::I64RegsRegClass)
471  BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
472  .addMemOperand(MMO);
473  else if (RC == &SP::IntRegsRegClass)
474  BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
475  .addMemOperand(MMO);
476  else if (RC == &SP::IntPairRegClass)
477  BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
478  .addMemOperand(MMO);
479  else if (RC == &SP::FPRegsRegClass)
480  BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
481  .addMemOperand(MMO);
482  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
483  BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
484  .addMemOperand(MMO);
485  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
486  // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
487  // lowered into two LDDs in eliminateFrameIndex.
488  BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
489  .addMemOperand(MMO);
490  else
491  llvm_unreachable("Can't load this register from stack slot");
492 }
493 
497  if (GlobalBaseReg)
498  return GlobalBaseReg;
499 
500  // Insert the set of GlobalBaseReg into the first MBB of the function
501  MachineBasicBlock &FirstMBB = MF->front();
503  MachineRegisterInfo &RegInfo = MF->getRegInfo();
504 
505  const TargetRegisterClass *PtrRC =
506  Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
507  GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
508 
509  DebugLoc dl;
510 
511  BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
513  return GlobalBaseReg;
514 }
515 
517  switch (MI.getOpcode()) {
518  case TargetOpcode::LOAD_STACK_GUARD: {
519  assert(Subtarget.isTargetLinux() &&
520  "Only Linux target is expected to contain LOAD_STACK_GUARD");
521  // offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc.
522  const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14;
523  MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
524  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
525  .addReg(SP::G7)
526  .addImm(Offset);
527  return true;
528  }
529  }
530  return false;
531 }
SparcInstrInfo.h
i
i
Definition: README.txt:29
llvm::SPCC::ICC_CS
@ ICC_CS
Definition: Sparc.h:52
llvm::SparcInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: SparcInstrInfo.cpp:297
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SparcInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: SparcInstrInfo.cpp:181
llvm::SPCC::FCC_N
@ FCC_N
Definition: Sparc.h:59
llvm::SparcInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Definition: SparcInstrInfo.cpp:43
llvm::SPCC::FCC_G
@ FCC_G
Definition: Sparc.h:61
llvm::SparcInstrInfo::getRegisterInfo
const SparcRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: SparcInstrInfo.h:49
llvm::SPCC::ICC_VS
@ ICC_VS
Definition: Sparc.h:56
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::SPCC::FCC_LE
@ FCC_LE
Definition: Sparc.h:71
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SPCC::ICC_LE
@ ICC_LE
Definition: Sparc.h:46
llvm::SPCC::CPCC_1
@ CPCC_1
Definition: Sparc.h:80
llvm::SparcSubtarget::isV9
bool isV9() const
Definition: SparcSubtarget.h:81
llvm::SPCC::FCC_UE
@ FCC_UE
Definition: Sparc.h:68
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::SPCC::CPCC_13
@ CPCC_13
Definition: Sparc.h:81
llvm::SPCC::ICC_L
@ ICC_L
Definition: Sparc.h:48
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
ErrorHandling.h
llvm::SPCC::CPCC_A
@ CPCC_A
Definition: Sparc.h:75
llvm::MachineInstr::addRegisterDefined
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
Definition: MachineInstr.cpp:2025
llvm::SparcInstrInfo::SparcInstrInfo
SparcInstrInfo(SparcSubtarget &ST)
Definition: SparcInstrInfo.cpp:34
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::SPCC::FCC_UG
@ FCC_UG
Definition: Sparc.h:62
llvm::SPCC::FCC_O
@ FCC_O
Definition: Sparc.h:73
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::isCondBranchOpcode
static bool isCondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:460
llvm::SPCC::ICC_LEU
@ ICC_LEU
Definition: Sparc.h:50
llvm::isUncondBranchOpcode
static bool isUncondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:458
llvm::SPCC::ICC_VC
@ ICC_VC
Definition: Sparc.h:55
STLExtras.h
llvm::SPCC::CondCodes
CondCodes
Definition: Sparc.h:40
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SPCC::CPCC_0
@ CPCC_0
Definition: Sparc.h:84
MachineRegisterInfo.h
llvm::SPCC::CPCC_12
@ CPCC_12
Definition: Sparc.h:82
llvm::SPCC::FCC_ULE
@ FCC_ULE
Definition: Sparc.h:72
llvm::SPCC::CPCC_01
@ CPCC_01
Definition: Sparc.h:88
llvm::SPCC::FCC_LG
@ FCC_LG
Definition: Sparc.h:65
llvm::SPCC::ICC_NEG
@ ICC_NEG
Definition: Sparc.h:54
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::SPCC::ICC_CC
@ ICC_CC
Definition: Sparc.h:51
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::PPCISD::GlobalBaseReg
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
Definition: PPCISelLowering.h:157
llvm::SPCC::CPCC_03
@ CPCC_03
Definition: Sparc.h:85
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::SPISD::BPICC
@ BPICC
Definition: SparcISelLowering.h:30
llvm::SparcMachineFunctionInfo::setGlobalBaseReg
void setGlobalBaseReg(Register Reg)
Definition: SparcMachineFunctionInfo.h:47
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::SPCC::FCC_L
@ FCC_L
Definition: Sparc.h:63
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1877
llvm::SPISD::BPXCC
@ BPXCC
Definition: SparcISelLowering.h:31
llvm::SparcSubtarget
Definition: SparcSubtarget.h:31
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
SparcSubtarget.h
llvm::SparcSubtarget::is64Bit
bool is64Bit() const
Definition: SparcSubtarget.h:107
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::SPCC::CPCC_3
@ CPCC_3
Definition: Sparc.h:77
llvm::isIndirectBranchOpcode
static bool isIndirectBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:477
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::SparcInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition: SparcInstrInfo.cpp:62
llvm::SPCC::FCC_NE
@ FCC_NE
Definition: Sparc.h:66
llvm::SPCC::CPCC_N
@ CPCC_N
Definition: Sparc.h:76
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
llvm::SparcSubtarget::hasHardQuad
bool hasHardQuad() const
Definition: SparcSubtarget.h:87
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SPCC::ICC_GE
@ ICC_GE
Definition: Sparc.h:47
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::SPCC::CPCC_123
@ CPCC_123
Definition: Sparc.h:83
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SparcInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SparcInstrInfo.cpp:418
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
parseCondBranch
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
Definition: SparcInstrInfo.cpp:168
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm::SPCC::ICC_A
@ ICC_A
Definition: Sparc.h:41
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::SparcInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: SparcInstrInfo.cpp:264
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
llvm::SPCC::ICC_G
@ ICC_G
Definition: Sparc.h:45
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SparcInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: SparcInstrInfo.cpp:328
SparcGenInstrInfo
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SPCC::CPCC_23
@ CPCC_23
Definition: Sparc.h:79
llvm::SPCC::FCC_GE
@ FCC_GE
Definition: Sparc.h:69
llvm::SPCC::ICC_N
@ ICC_N
Definition: Sparc.h:42
llvm::SparcSubtarget::isTargetLinux
bool isTargetLinux() const
Definition: SparcSubtarget.h:120
GetOppositeBranchCondition
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
Definition: SparcInstrInfo.cpp:81
llvm::SparcInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: SparcInstrInfo.cpp:516
llvm::SPCC::CPCC_013
@ CPCC_013
Definition: Sparc.h:89
isI64CondBranchOpcode
static bool isI64CondBranchOpcode(int Opc)
Definition: SparcInstrInfo.cpp:152
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
isFCondBranchOpcode
static bool isFCondBranchOpcode(int Opc)
Definition: SparcInstrInfo.cpp:157
llvm::SPCC::CPCC_02
@ CPCC_02
Definition: Sparc.h:86
SparcMachineFunctionInfo.h
MachineFrameInfo.h
Sparc.h
llvm::SPCC::FCC_U
@ FCC_U
Definition: Sparc.h:60
llvm::SPCC::CPCC_2
@ CPCC_2
Definition: Sparc.h:78
llvm::SparcInstrInfo::getGlobalBaseReg
Register getGlobalBaseReg(MachineFunction *MF) const
Definition: SparcInstrInfo.cpp:494
llvm::SPCC::FCC_E
@ FCC_E
Definition: Sparc.h:67
llvm::SparcMachineFunctionInfo::getGlobalBaseReg
Register getGlobalBaseReg() const
Definition: SparcMachineFunctionInfo.h:46
llvm::SPCC::ICC_NE
@ ICC_NE
Definition: Sparc.h:43
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::SPCC::FCC_UL
@ FCC_UL
Definition: Sparc.h:64
llvm::SPCC::ICC_E
@ ICC_E
Definition: Sparc.h:44
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::SPCC::ICC_GU
@ ICC_GU
Definition: Sparc.h:49
llvm::SPCC::FCC_A
@ FCC_A
Definition: Sparc.h:58
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1019
llvm::SparcInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: SparcInstrInfo.cpp:457
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
llvm::SPCC::FCC_UGE
@ FCC_UGE
Definition: Sparc.h:70
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1142
isI32CondBranchOpcode
static bool isI32CondBranchOpcode(int Opc)
Definition: SparcInstrInfo.cpp:147
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:692
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegistry.h
llvm::SparcInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: SparcInstrInfo.cpp:320
llvm::SPCC::CPCC_012
@ CPCC_012
Definition: Sparc.h:90
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
IsIntegerCC
static bool IsIntegerCC(unsigned CC)
Definition: SparcInstrInfo.cpp:76
llvm::SPCC::ICC_POS
@ ICC_POS
Definition: Sparc.h:53
llvm::SPCC::CPCC_023
@ CPCC_023
Definition: Sparc.h:87
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SparcMachineFunctionInfo
Definition: SparcMachineFunctionInfo.h:19