This is the parent TargetLowering class for hardware code gen targets. More...

#include "AMDGPUISelLowering.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUMachineFunction.h"
#include "AMDGPUMemoryUtils.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenCallingConv.inc"

Macros
#define	NODE_NAME_CASE(node)

Functions
static LLVM_READNONE bool	fnegFoldsIntoOpcode (unsigned Opc)
static bool	fnegFoldsIntoOp (const SDNode *N)
static LLVM_READONLY bool	opMustUseVOP3Encoding (const SDNode *N, MVT VT)
	`returns` true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.
static LLVM_READONLY bool	selectSupportsSourceMods (const SDNode *N)
	Return true if v_cndmask_b32 will support fabs/fneg source modifiers for the type for ISD::SELECT.
static LLVM_READONLY bool	hasSourceMods (const SDNode *N)
static SDValue	peekFNeg (SDValue Val)
static SDValue	peekFPSignOps (SDValue Val)
static SDValue	extractF64Exponent (SDValue Hi, const SDLoc &SL, SelectionDAG &DAG)
static bool	valueIsKnownNeverF32Denorm (SDValue Src)
	Return true if it's known that `Src` can never be an f32 denormal value.
static SDValue	getMad (SelectionDAG &DAG, const SDLoc &SL, EVT VT, SDValue X, SDValue Y, SDValue C, SDNodeFlags Flags=SDNodeFlags())
static bool	isCtlzOpc (unsigned Opc)
static bool	isCttzOpc (unsigned Opc)
static bool	isU24 (SDValue Op, SelectionDAG &DAG)
static bool	isI24 (SDValue Op, SelectionDAG &DAG)
static SDValue	simplifyMul24 (SDNode *Node24, TargetLowering::DAGCombinerInfo &DCI)
template<typename IntTy>
static SDValue	constantFoldBFE (SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, const SDLoc &DL)
static bool	hasVolatileUser (SDNode *Val)
static SDValue	getMul24 (SelectionDAG &DAG, const SDLoc &SL, SDValue N0, SDValue N1, unsigned Size, bool Signed)
static SDValue	getAddOneOp (const SDNode *V)
	If `V` is an add of a constant 1, returns the other operand.
static SDValue	distributeOpThroughSelect (TargetLowering::DAGCombinerInfo &DCI, unsigned Op, const SDLoc &SL, SDValue Cond, SDValue N1, SDValue N2)
static bool	isInv2Pi (const APFloat &APF)
static unsigned	inverseMinMax (unsigned Opc)
static int	getOrCreateFixedStackObject (MachineFrameInfo &MFI, unsigned Size, int64_t Offset)
static unsigned	workitemIntrinsicDim (unsigned ID)

Variables
static cl::opt< bool >	AMDGPUBypassSlowDiv ("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true))

Detailed Description

This is the parent TargetLowering class for hardware code gen targets.

Definition in file AMDGPUISelLowering.cpp.

Macro Definition Documentation

◆ NODE_NAME_CASE

#define NODE_NAME_CASE ( node )

Value:

case AMDGPUISD::node: return #node;

Definition at line 5681 of file AMDGPUISelLowering.cpp.

Referenced by llvm::AMDGPUTargetLowering::getTargetNodeName(), llvm::LoongArchTargetLowering::getTargetNodeName(), and llvm::X86TargetLowering::getTargetNodeName().

Function Documentation

◆ constantFoldBFE()

template<typename IntTy>

SDValue constantFoldBFE	(	SelectionDAG &	DAG,
		IntTy	Src0,
		uint32_t	Offset,
		uint32_t	Width,
		const SDLoc &	DL )

static

Definition at line 3831 of file AMDGPUISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getSignedConstant(), and llvm::Offset.

Referenced by llvm::AMDGPUTargetLowering::PerformDAGCombine().

◆ distributeOpThroughSelect()

SDValue distributeOpThroughSelect	(	TargetLowering::DAGCombinerInfo &	DCI,
		unsigned	Op,
		const SDLoc &	SL,
		SDValue	Cond,
		SDValue	N1,
		SDValue	N2 )

static

Definition at line 4760 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::ISD::SELECT.

Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect().

◆ extractF64Exponent()

SDValue extractF64Exponent	(	SDValue	Hi,
		const SDLoc &	SL,
		SelectionDAG &	DAG )

static

Definition at line 2463 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::BFE_U32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::Hi, and llvm::ISD::SUB.

Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), and llvm::AMDGPUTargetLowering::LowerFTRUNC().

◆ fnegFoldsIntoOp()

bool fnegFoldsIntoOp ( const SDNode * N )

static

Definition at line 700 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, fnegFoldsIntoOpcode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), N, Opc, and llvm::ISD::SELECT.

Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), llvm::AMDGPUTargetLowering::performFNegCombine(), and llvm::AMDGPUTargetLowering::shouldFoldFNegIntoSrc().

◆ fnegFoldsIntoOpcode()

LLVM_READNONE bool fnegFoldsIntoOpcode ( unsigned Opc )

static

Definition at line 661 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::AMDGPUISD::FMAX_LEGACY, llvm::AMDGPUISD::FMED3, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMUL, llvm::AMDGPUISD::FMUL_LEGACY, llvm::ISD::FSUB, llvm_unreachable, Opc, llvm::AMDGPUISD::RCP, llvm::AMDGPUISD::RCP_IFLAG, llvm::AMDGPUISD::RCP_LEGACY, llvm::ISD::SELECT, and llvm::AMDGPUISD::SIN_HW.

Referenced by fnegFoldsIntoOp().

◆ getAddOneOp()

SDValue getAddOneOp ( const SDNode * V )

static

If V is an add of a constant 1, returns the other operand.

Otherwise return SDValue().

Definition at line 4492 of file AMDGPUISelLowering.cpp.

References llvm::ISD::ADD, llvm::isOneConstant(), and SDValue().

Referenced by llvm::AMDGPUTargetLowering::performMulCombine().

◆ getMad()

SDValue getMad	(	SelectionDAG &	DAG,
		const SDLoc &	SL,
		EVT	VT,
		SDValue	X,
		SDValue	Y,
		SDValue	C,
		SDNodeFlags	Flags = SDNodeFlags() )

static

Definition at line 2755 of file AMDGPUISelLowering.cpp.

References llvm::CallingConv::C, llvm::ISD::FADD, llvm::ISD::FMUL, llvm::SelectionDAG::getNode(), Mul, X, and Y.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFlogCommon(), llvm::AMDGPUTargetLowering::lowerFEXP(), and llvm::AMDGPUTargetLowering::LowerFLOGCommon().

◆ getMul24()

SDValue getMul24	(	SelectionDAG &	DAG,
		const SDLoc &	SL,
		SDValue	N0,
		SDValue	N1,
		unsigned	Size,
		bool	Signed )

static

Definition at line 4474 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, Signed, and Size.

Referenced by llvm::AMDGPUTargetLowering::performMulCombine().

◆ getOrCreateFixedStackObject()

int getOrCreateFixedStackObject	(	MachineFrameInfo &	MFI,
		unsigned	Size,
		int64_t	Offset )

static

Definition at line 5588 of file AMDGPUISelLowering.cpp.

References assert(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), I, llvm::Offset, and Size.

Referenced by llvm::AMDGPUTargetLowering::loadStackInputValue().

◆ hasSourceMods()

LLVM_READONLY bool hasSourceMods ( const SDNode * N )

static

Definition at line 737 of file AMDGPUISelLowering.cpp.

References llvm::ISD::CopyToReg, llvm::AMDGPUISD::DIV_SCALE, llvm::ISD::FDIV, llvm::ISD::FREM, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), N, llvm::ISD::SELECT, and selectSupportsSourceMods().

◆ hasVolatileUser()

bool hasVolatileUser ( SDNode * Val )

static

Definition at line 3846 of file AMDGPUISelLowering.cpp.

References llvm::dyn_cast(), and llvm::SDNode::users().

Referenced by llvm::AMDGPUTargetLowering::performLoadCombine().

◆ inverseMinMax()

unsigned inverseMinMax ( unsigned Opc )

static

Definition at line 4941 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::FMAX_LEGACY, llvm::AMDGPUISD::FMIN_LEGACY, llvm_unreachable, and Opc.

◆ isCtlzOpc()

bool isCtlzOpc ( unsigned Opc )

static

Definition at line 3179 of file AMDGPUISelLowering.cpp.

References llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, and Opc.

Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::lowerCTLZResults(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().

◆ isCttzOpc()

bool isCttzOpc ( unsigned Opc )

static

Definition at line 3183 of file AMDGPUISelLowering.cpp.

References llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, and Opc.

Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().

◆ isI24()

bool isI24	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 3772 of file AMDGPUISelLowering.cpp.

References llvm::EVT::getSizeInBits(), and llvm::AMDGPUTargetLowering::numBitsSigned().

Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().

◆ isInv2Pi()

bool isInv2Pi ( const APFloat & APF )

static

Definition at line 4906 of file AMDGPUISelLowering.cpp.

References llvm::APFloat::bitwiseIsEqual(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), and llvm::APFloatBase::IEEEsingle().

◆ isU24()

bool isU24	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 3768 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUTargetLowering::numBitsUnsigned().

Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().

◆ opMustUseVOP3Encoding()

LLVM_READONLY bool opMustUseVOP3Encoding	(	const SDNode *	N,
		MVT	VT )

static

returns true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.

Definition at line 721 of file AMDGPUISelLowering.cpp.

References N, and llvm::ISD::SELECT.

◆ peekFNeg()

SDValue peekFNeg ( SDValue Val )

static

Definition at line 1647 of file AMDGPUISelLowering.cpp.

References llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().

Referenced by llvm::AMDGPUTargetLowering::combineFMinMaxLegacy().

◆ peekFPSignOps()

SDValue peekFPSignOps ( SDValue Val )

static

Definition at line 1654 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FCOPYSIGN, llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().

Referenced by llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine().

◆ selectSupportsSourceMods()

LLVM_READONLY bool selectSupportsSourceMods ( const SDNode * N )

static

Return true if v_cndmask_b32 will support fabs/fneg source modifiers for the type for ISD::SELECT.

Definition at line 729 of file AMDGPUISelLowering.cpp.

References N.

Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), and hasSourceMods().

◆ simplifyMul24()

SDValue simplifyMul24	(	SDNode *	Node24,
		TargetLowering::DAGCombinerInfo &	DCI )

static

◆ valueIsKnownNeverF32Denorm()

bool valueIsKnownNeverF32Denorm ( SDValue Src )

static

Return true if it's known that Src can never be an f32 denormal value.

Definition at line 2625 of file AMDGPUISelLowering.cpp.

References llvm::ISD::INTRINSIC_WO_CHAIN, and llvm_unreachable.

Referenced by llvm::AMDGPUTargetLowering::needsDenormHandlingF32(), and needsDenormHandlingF32().

◆ workitemIntrinsicDim()

unsigned workitemIntrinsicDim ( unsigned ID )

static

Definition at line 5883 of file AMDGPUISelLowering.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode().

Variable Documentation

◆ AMDGPUBypassSlowDiv

cl::opt< bool > AMDGPUBypassSlowDiv("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true))	(	"amdgpu-bypass-slow-div"	,
		cl::desc("Skip 64-bit divide for dynamic 32-bit values")	,
		cl::init(true)	)

static

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ NODE_NAME_CASE

Function Documentation

◆ constantFoldBFE()

◆ distributeOpThroughSelect()

◆ extractF64Exponent()

◆ fnegFoldsIntoOp()

◆ fnegFoldsIntoOpcode()

◆ getAddOneOp()

◆ getMad()

◆ getMul24()

◆ getOrCreateFixedStackObject()

◆ hasSourceMods()

◆ hasVolatileUser()

◆ inverseMinMax()

◆ isCtlzOpc()

◆ isCttzOpc()

◆ isI24()

◆ isInv2Pi()

◆ isU24()

◆ opMustUseVOP3Encoding()

◆ peekFNeg()

◆ peekFPSignOps()

◆ selectSupportsSourceMods()

◆ simplifyMul24()

◆ valueIsKnownNeverF32Denorm()

◆ workitemIntrinsicDim()

Variable Documentation

◆ AMDGPUBypassSlowDiv