LLVM 19.0.0git
Macros | Functions | Variables
AMDGPUISelLowering.cpp File Reference

This is the parent TargetLowering class for hardware code gen targets. More...

#include "AMDGPUISelLowering.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUMachineFunction.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenCallingConv.inc"

Go to the source code of this file.

Macros

#define NODE_NAME_CASE(node)   case AMDGPUISD::node: return #node;
 

Functions

static LLVM_READNONE bool fnegFoldsIntoOpcode (unsigned Opc)
 
static bool fnegFoldsIntoOp (const SDNode *N)
 
static LLVM_READONLY bool opMustUseVOP3Encoding (const SDNode *N, MVT VT)
 returns true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.
 
static LLVM_READONLY bool selectSupportsSourceMods (const SDNode *N)
 Return true if v_cndmask_b32 will support fabs/fneg source modifiers for the type for ISD::SELECT.
 
static LLVM_READONLY bool hasSourceMods (const SDNode *N)
 
static SDValue peekFNeg (SDValue Val)
 
static SDValue peekFPSignOps (SDValue Val)
 
static SDValue extractF64Exponent (SDValue Hi, const SDLoc &SL, SelectionDAG &DAG)
 
static bool valueIsKnownNeverF32Denorm (SDValue Src)
 Return true if it's known that Src can never be an f32 denormal value.
 
static SDValue getMad (SelectionDAG &DAG, const SDLoc &SL, EVT VT, SDValue X, SDValue Y, SDValue C, SDNodeFlags Flags=SDNodeFlags())
 
static bool isCtlzOpc (unsigned Opc)
 
static bool isCttzOpc (unsigned Opc)
 
static bool isU24 (SDValue Op, SelectionDAG &DAG)
 
static bool isI24 (SDValue Op, SelectionDAG &DAG)
 
static SDValue simplifyMul24 (SDNode *Node24, TargetLowering::DAGCombinerInfo &DCI)
 
template<typename IntTy >
static SDValue constantFoldBFE (SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, const SDLoc &DL)
 
static bool hasVolatileUser (SDNode *Val)
 
static SDValue getMul24 (SelectionDAG &DAG, const SDLoc &SL, SDValue N0, SDValue N1, unsigned Size, bool Signed)
 
static SDValue getAddOneOp (const SDNode *V)
 If V is an add of a constant 1, returns the other operand.
 
static SDValue distributeOpThroughSelect (TargetLowering::DAGCombinerInfo &DCI, unsigned Op, const SDLoc &SL, SDValue Cond, SDValue N1, SDValue N2)
 
static bool isInv2Pi (const APFloat &APF)
 
static unsigned inverseMinMax (unsigned Opc)
 
static int getOrCreateFixedStackObject (MachineFrameInfo &MFI, unsigned Size, int64_t Offset)
 
static unsigned workitemIntrinsicDim (unsigned ID)
 

Variables

static cl::opt< boolAMDGPUBypassSlowDiv ("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true))
 

Detailed Description

This is the parent TargetLowering class for hardware code gen targets.

Definition in file AMDGPUISelLowering.cpp.

Macro Definition Documentation

◆ NODE_NAME_CASE

#define NODE_NAME_CASE (   node)    case AMDGPUISD::node: return #node;

Definition at line 5356 of file AMDGPUISelLowering.cpp.

Function Documentation

◆ constantFoldBFE()

template<typename IntTy >
static SDValue constantFoldBFE ( SelectionDAG DAG,
IntTy  Src0,
uint32_t  Offset,
uint32_t  Width,
const SDLoc DL 
)
static

Definition at line 3708 of file AMDGPUISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), and llvm::Offset.

◆ distributeOpThroughSelect()

static SDValue distributeOpThroughSelect ( TargetLowering::DAGCombinerInfo DCI,
unsigned  Op,
const SDLoc SL,
SDValue  Cond,
SDValue  N1,
SDValue  N2 
)
static

◆ extractF64Exponent()

static SDValue extractF64Exponent ( SDValue  Hi,
const SDLoc SL,
SelectionDAG DAG 
)
static

◆ fnegFoldsIntoOp()

static bool fnegFoldsIntoOp ( const SDNode N)
static

◆ fnegFoldsIntoOpcode()

static LLVM_READNONE bool fnegFoldsIntoOpcode ( unsigned  Opc)
static

◆ getAddOneOp()

static SDValue getAddOneOp ( const SDNode V)
static

If V is an add of a constant 1, returns the other operand.

Otherwise return SDValue().

Definition at line 4206 of file AMDGPUISelLowering.cpp.

References llvm::ISD::ADD, and llvm::isOneConstant().

Referenced by llvm::AMDGPUTargetLowering::performMulCombine().

◆ getMad()

static SDValue getMad ( SelectionDAG DAG,
const SDLoc SL,
EVT  VT,
SDValue  X,
SDValue  Y,
SDValue  C,
SDNodeFlags  Flags = SDNodeFlags() 
)
static

◆ getMul24()

static SDValue getMul24 ( SelectionDAG DAG,
const SDLoc SL,
SDValue  N0,
SDValue  N1,
unsigned  Size,
bool  Signed 
)
static

◆ getOrCreateFixedStackObject()

static int getOrCreateFixedStackObject ( MachineFrameInfo MFI,
unsigned  Size,
int64_t  Offset 
)
static

◆ hasSourceMods()

static LLVM_READONLY bool hasSourceMods ( const SDNode N)
static

◆ hasVolatileUser()

static bool hasVolatileUser ( SDNode Val)
static

◆ inverseMinMax()

static unsigned inverseMinMax ( unsigned  Opc)
static

◆ isCtlzOpc()

static bool isCtlzOpc ( unsigned  Opc)
static

◆ isCttzOpc()

static bool isCttzOpc ( unsigned  Opc)
static

◆ isI24()

static bool isI24 ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ isInv2Pi()

static bool isInv2Pi ( const APFloat APF)
static

◆ isU24()

static bool isU24 ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ opMustUseVOP3Encoding()

static LLVM_READONLY bool opMustUseVOP3Encoding ( const SDNode N,
MVT  VT 
)
static

returns true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.

Definition at line 662 of file AMDGPUISelLowering.cpp.

References N, and llvm::ISD::SELECT.

◆ peekFNeg()

static SDValue peekFNeg ( SDValue  Val)
static

◆ peekFPSignOps()

static SDValue peekFPSignOps ( SDValue  Val)
static

◆ selectSupportsSourceMods()

static LLVM_READONLY bool selectSupportsSourceMods ( const SDNode N)
static

Return true if v_cndmask_b32 will support fabs/fneg source modifiers for the type for ISD::SELECT.

Definition at line 670 of file AMDGPUISelLowering.cpp.

References N.

Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), and hasSourceMods().

◆ simplifyMul24()

static SDValue simplifyMul24 ( SDNode Node24,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ valueIsKnownNeverF32Denorm()

static bool valueIsKnownNeverF32Denorm ( SDValue  Src)
static

Return true if it's known that Src can never be an f32 denormal value.

Definition at line 2515 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FFREXP, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm_unreachable.

Referenced by needsDenormHandlingF32(), and llvm::AMDGPUTargetLowering::needsDenormHandlingF32().

◆ workitemIntrinsicDim()

static unsigned workitemIntrinsicDim ( unsigned  ID)
static

Variable Documentation

◆ AMDGPUBypassSlowDiv

cl::opt< bool > AMDGPUBypassSlowDiv("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true)) ( "amdgpu-bypass-slow-div"  ,
cl::desc("Skip 64-bit divide for dynamic 32-bit values")  ,
cl::init(true  
)
static