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AMDGPUISelLowering.cpp
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1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This is the parent TargetLowering class for hardware code gen
11 /// targets.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define AMDGPU_LOG2E_F 1.44269504088896340735992468100189214f
16 #define AMDGPU_LN2_F 0.693147180559945309417232121458176568f
17 #define AMDGPU_LN10_F 2.30258509299404568401799145468436421f
18 
19 #include "AMDGPUISelLowering.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUCallLowering.h"
22 #include "AMDGPUFrameLowering.h"
23 #include "AMDGPURegisterInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "AMDGPUTargetMachine.h"
26 #include "Utils/AMDGPUBaseInfo.h"
28 #include "SIInstrInfo.h"
29 #include "SIMachineFunctionInfo.h"
31 #include "llvm/CodeGen/Analysis.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DiagnosticInfo.h"
39 #include "llvm/Support/KnownBits.h"
40 using namespace llvm;
41 
42 static bool allocateCCRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
43  CCValAssign::LocInfo LocInfo,
44  ISD::ArgFlagsTy ArgFlags, CCState &State,
45  const TargetRegisterClass *RC,
46  unsigned NumRegs) {
47  ArrayRef<MCPhysReg> RegList = makeArrayRef(RC->begin(), NumRegs);
48  unsigned RegResult = State.AllocateReg(RegList);
49  if (RegResult == AMDGPU::NoRegister)
50  return false;
51 
52  State.addLoc(CCValAssign::getReg(ValNo, ValVT, RegResult, LocVT, LocInfo));
53  return true;
54 }
55 
56 static bool allocateSGPRTuple(unsigned ValNo, MVT ValVT, MVT LocVT,
57  CCValAssign::LocInfo LocInfo,
58  ISD::ArgFlagsTy ArgFlags, CCState &State) {
59  switch (LocVT.SimpleTy) {
60  case MVT::i64:
61  case MVT::f64:
62  case MVT::v2i32:
63  case MVT::v2f32:
64  case MVT::v4i16:
65  case MVT::v4f16: {
66  // Up to SGPR0-SGPR105
67  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
68  &AMDGPU::SGPR_64RegClass, 53);
69  }
70  default:
71  return false;
72  }
73 }
74 
75 // Allocate up to VGPR31.
76 //
77 // TODO: Since there are no VGPR alignent requirements would it be better to
78 // split into individual scalar registers?
79 static bool allocateVGPRTuple(unsigned ValNo, MVT ValVT, MVT LocVT,
80  CCValAssign::LocInfo LocInfo,
81  ISD::ArgFlagsTy ArgFlags, CCState &State) {
82  switch (LocVT.SimpleTy) {
83  case MVT::i64:
84  case MVT::f64:
85  case MVT::v2i32:
86  case MVT::v2f32:
87  case MVT::v4i16:
88  case MVT::v4f16: {
89  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
90  &AMDGPU::VReg_64RegClass, 31);
91  }
92  case MVT::v4i32:
93  case MVT::v4f32:
94  case MVT::v2i64:
95  case MVT::v2f64: {
96  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
97  &AMDGPU::VReg_128RegClass, 29);
98  }
99  case MVT::v8i32:
100  case MVT::v8f32: {
101  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
102  &AMDGPU::VReg_256RegClass, 25);
103 
104  }
105  case MVT::v16i32:
106  case MVT::v16f32: {
107  return allocateCCRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State,
108  &AMDGPU::VReg_512RegClass, 17);
109 
110  }
111  default:
112  return false;
113  }
114 }
115 
116 #include "AMDGPUGenCallingConv.inc"
117 
118 // Find a larger type to do a load / store of a vector with.
120  unsigned StoreSize = VT.getStoreSizeInBits();
121  if (StoreSize <= 32)
122  return EVT::getIntegerVT(Ctx, StoreSize);
123 
124  assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
125  return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
126 }
127 
129  EVT VT = Op.getValueType();
130  KnownBits Known = DAG.computeKnownBits(Op);
131  return VT.getSizeInBits() - Known.countMinLeadingZeros();
132 }
133 
135  EVT VT = Op.getValueType();
136 
137  // In order for this to be a signed 24-bit value, bit 23, must
138  // be a sign bit.
139  return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
140 }
141 
143  const AMDGPUSubtarget &STI)
144  : TargetLowering(TM), Subtarget(&STI) {
145  // Lower floating point store/load to integer store/load to reduce the number
146  // of patterns in tablegen.
149 
152 
155 
158 
161 
164 
167 
170 
173 
176 
179 
182 
183  // There are no 64-bit extloads. These should be done as a 32-bit extload and
184  // an extension to 64-bit.
185  for (MVT VT : MVT::integer_valuetypes()) {
189  }
190 
191  for (MVT VT : MVT::integer_valuetypes()) {
192  if (VT == MVT::i64)
193  continue;
194 
199 
204 
209  }
210 
211  for (MVT VT : MVT::integer_vector_valuetypes()) {
224  }
225 
230 
235 
240 
243 
246 
249 
252 
255 
258 
261 
264 
267 
270 
273 
276 
281 
286 
291 
294 
297 
300 
303 
304 
309 
312 
313  // This is totally unsupported, just custom lower to produce an error.
315 
316  // Library functions. These default to Expand, but we have instructions
317  // for them.
328 
331 
335 
336 
339 
342 
343  // Expand to fneg + fadd.
345 
368 
372 
373  const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
374  for (MVT VT : ScalarIntVTs) {
375  // These should use [SU]DIVREM, so set them to expand
380 
381  // GPU does not have divrem function for signed or unsigned.
384 
385  // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
388 
392 
393  // AMDGPU uses ADDC/SUBC/ADDE/SUBE
398  }
399 
400  // The hardware supports 32-bit ROTR, but not ROTL.
402  setOperationAction(ISD::ROTL, MVT::i64, Expand);
403  setOperationAction(ISD::ROTR, MVT::i64, Expand);
404 
405  setOperationAction(ISD::MUL, MVT::i64, Expand);
413 
418 
419  setOperationAction(ISD::CTTZ, MVT::i64, Custom);
421  setOperationAction(ISD::CTLZ, MVT::i64, Custom);
423 
424  static const MVT::SimpleValueType VectorIntTypes[] = {
426  };
427 
428  for (MVT VT : VectorIntTypes) {
429  // Expand the following operations for the current type by default.
464  }
465 
466  static const MVT::SimpleValueType FloatVectorTypes[] = {
468  };
469 
470  for (MVT VT : FloatVectorTypes) {
501  }
502 
503  // This causes using an unrolled select operation rather than expansion with
504  // bit operations. This is in general better, but the alternative using BFI
505  // instructions may be better if the select sources are SGPRs.
508 
511 
514 
515  setOperationAction(ISD::SELECT, MVT::v5f32, Promote);
516  AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32);
517 
518  // There are no libcalls of any kind.
519  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I)
520  setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
521 
524 
526  setJumpIsExpensive(true);
527 
528  // FIXME: This is only partially true. If we have to do vector compares, any
529  // SGPR pair can be a condition register. If we have a uniform condition, we
530  // are better off doing SALU operations, where there is only one SCC. For now,
531  // we don't have a way of knowing during instruction selection if a condition
532  // will be uniform and we always use vector compares. Assume we are using
533  // vector compares until that is fixed.
535 
538 
540 
541  // We want to find all load dependencies for long chains of stores to enable
542  // merging into very wide vectors. The problem is with vectors with > 4
543  // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
544  // vectors are a legal type, even though we have to split the loads
545  // usually. When we can more precisely specify load legality per address
546  // space, we should be able to make FindBetterChain/MergeConsecutiveStores
547  // smarter so that they can figure out what to do in 2 iterations without all
548  // N > 4 stores on the same chain.
550 
551  // memcpy/memmove/memset are expanded in the IR, so we shouldn't need to worry
552  // about these during lowering.
553  MaxStoresPerMemcpy = 0xffffffff;
554  MaxStoresPerMemmove = 0xffffffff;
555  MaxStoresPerMemset = 0xffffffff;
556 
574 }
575 
576 //===----------------------------------------------------------------------===//
577 // Target Information
578 //===----------------------------------------------------------------------===//
579 
581 static bool fnegFoldsIntoOp(unsigned Opc) {
582  switch (Opc) {
583  case ISD::FADD:
584  case ISD::FSUB:
585  case ISD::FMUL:
586  case ISD::FMA:
587  case ISD::FMAD:
588  case ISD::FMINNUM:
589  case ISD::FMAXNUM:
590  case ISD::FMINNUM_IEEE:
591  case ISD::FMAXNUM_IEEE:
592  case ISD::FSIN:
593  case ISD::FTRUNC:
594  case ISD::FRINT:
595  case ISD::FNEARBYINT:
596  case ISD::FCANONICALIZE:
597  case AMDGPUISD::RCP:
600  case AMDGPUISD::SIN_HW:
604  case AMDGPUISD::FMED3:
605  return true;
606  default:
607  return false;
608  }
609 }
610 
611 /// \p returns true if the operation will definitely need to use a 64-bit
612 /// encoding, and thus will use a VOP3 encoding regardless of the source
613 /// modifiers.
615 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) {
616  return N->getNumOperands() > 2 || VT == MVT::f64;
617 }
618 
619 // Most FP instructions support source modifiers, but this could be refined
620 // slightly.
622 static bool hasSourceMods(const SDNode *N) {
623  if (isa<MemSDNode>(N))
624  return false;
625 
626  switch (N->getOpcode()) {
627  case ISD::CopyToReg:
628  case ISD::SELECT:
629  case ISD::FDIV:
630  case ISD::FREM:
631  case ISD::INLINEASM:
632  case ISD::INLINEASM_BR:
636 
637  // TODO: Should really be looking at the users of the bitcast. These are
638  // problematic because bitcasts are used to legalize all stores to integer
639  // types.
640  case ISD::BITCAST:
641  return false;
642  default:
643  return true;
644  }
645 }
646 
648  unsigned CostThreshold) {
649  // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
650  // it is truly free to use a source modifier in all cases. If there are
651  // multiple users but for each one will necessitate using VOP3, there will be
652  // a code size increase. Try to avoid increasing code size unless we know it
653  // will save on the instruction count.
654  unsigned NumMayIncreaseSize = 0;
655  MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
656 
657  // XXX - Should this limit number of uses to check?
658  for (const SDNode *U : N->uses()) {
659  if (!hasSourceMods(U))
660  return false;
661 
662  if (!opMustUseVOP3Encoding(U, VT)) {
663  if (++NumMayIncreaseSize > CostThreshold)
664  return false;
665  }
666  }
667 
668  return true;
669 }
670 
672  return MVT::i32;
673 }
674 
676  return true;
677 }
678 
679 // The backend supports 32 and 64 bit floating point immediates.
680 // FIXME: Why are we reporting vectors of FP immediates as legal?
682  bool ForCodeSize) const {
683  EVT ScalarVT = VT.getScalarType();
684  return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
685  (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
686 }
687 
688 // We don't want to shrink f64 / f32 constants.
690  EVT ScalarVT = VT.getScalarType();
691  return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
692 }
693 
695  ISD::LoadExtType ExtTy,
696  EVT NewVT) const {
697  // TODO: This may be worth removing. Check regression tests for diffs.
698  if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT))
699  return false;
700 
701  unsigned NewSize = NewVT.getStoreSizeInBits();
702 
703  // If we are reducing to a 32-bit load, this is always better.
704  if (NewSize == 32)
705  return true;
706 
707  EVT OldVT = N->getValueType(0);
708  unsigned OldSize = OldVT.getStoreSizeInBits();
709 
710  MemSDNode *MN = cast<MemSDNode>(N);
711  unsigned AS = MN->getAddressSpace();
712  // Do not shrink an aligned scalar load to sub-dword.
713  // Scalar engine cannot do sub-dword loads.
714  if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 &&
717  (isa<LoadSDNode>(N) &&
718  AS == AMDGPUAS::GLOBAL_ADDRESS && MN->isInvariant())) &&
720  return false;
721 
722  // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
723  // extloads, so doing one requires using a buffer_load. In cases where we
724  // still couldn't use a scalar load, using the wider load shouldn't really
725  // hurt anything.
726 
727  // If the old size already had to be an extload, there's no harm in continuing
728  // to reduce the width.
729  return (OldSize < 32);
730 }
731 
733  const SelectionDAG &DAG,
734  const MachineMemOperand &MMO) const {
735 
736  assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits());
737 
738  if (LoadTy.getScalarType() == MVT::i32)
739  return false;
740 
741  unsigned LScalarSize = LoadTy.getScalarSizeInBits();
742  unsigned CastScalarSize = CastTy.getScalarSizeInBits();
743 
744  if ((LScalarSize >= CastScalarSize) && (CastScalarSize < 32))
745  return false;
746 
747  bool Fast = false;
748  return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), CastTy,
749  MMO, &Fast) && Fast;
750 }
751 
752 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
753 // profitable with the expansion for 64-bit since it's generally good to
754 // speculate things.
755 // FIXME: These should really have the size as a parameter.
757  return true;
758 }
759 
761  return true;
762 }
763 
765  switch (N->getOpcode()) {
766  default:
767  return false;
768  case ISD::EntryToken:
769  case ISD::TokenFactor:
770  return true;
772  {
773  unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
774  switch (IntrID) {
775  default:
776  return false;
777  case Intrinsic::amdgcn_readfirstlane:
778  case Intrinsic::amdgcn_readlane:
779  return true;
780  }
781  }
782  break;
783  case ISD::LOAD:
784  {
785  const LoadSDNode * L = dyn_cast<LoadSDNode>(N);
786  if (L->getMemOperand()->getAddrSpace()
788  return true;
789  return false;
790  }
791  break;
792  }
793 }
794 
795 //===---------------------------------------------------------------------===//
796 // Target Properties
797 //===---------------------------------------------------------------------===//
798 
800  assert(VT.isFloatingPoint());
801 
802  // Packed operations do not have a fabs modifier.
803  return VT == MVT::f32 || VT == MVT::f64 ||
804  (Subtarget->has16BitInsts() && VT == MVT::f16);
805 }
806 
808  assert(VT.isFloatingPoint());
809  return VT == MVT::f32 || VT == MVT::f64 ||
810  (Subtarget->has16BitInsts() && VT == MVT::f16) ||
811  (Subtarget->hasVOP3PInsts() && VT == MVT::v2f16);
812 }
813 
815  unsigned NumElem,
816  unsigned AS) const {
817  return true;
818 }
819 
821  // There are few operations which truly have vector input operands. Any vector
822  // operation is going to involve operations on each component, and a
823  // build_vector will be a copy per element, so it always makes sense to use a
824  // build_vector input in place of the extracted element to avoid a copy into a
825  // super register.
826  //
827  // We should probably only do this if all users are extracts only, but this
828  // should be the common case.
829  return true;
830 }
831 
833  // Truncate is just accessing a subregister.
834 
835  unsigned SrcSize = Source.getSizeInBits();
836  unsigned DestSize = Dest.getSizeInBits();
837 
838  return DestSize < SrcSize && DestSize % 32 == 0 ;
839 }
840 
842  // Truncate is just accessing a subregister.
843 
844  unsigned SrcSize = Source->getScalarSizeInBits();
845  unsigned DestSize = Dest->getScalarSizeInBits();
846 
847  if (DestSize== 16 && Subtarget->has16BitInsts())
848  return SrcSize >= 32;
849 
850  return DestSize < SrcSize && DestSize % 32 == 0;
851 }
852 
853 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
854  unsigned SrcSize = Src->getScalarSizeInBits();
855  unsigned DestSize = Dest->getScalarSizeInBits();
856 
857  if (SrcSize == 16 && Subtarget->has16BitInsts())
858  return DestSize >= 32;
859 
860  return SrcSize == 32 && DestSize == 64;
861 }
862 
863 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
864  // Any register load of a 64-bit value really requires 2 32-bit moves. For all
865  // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
866  // this will enable reducing 64-bit operations the 32-bit, which is always
867  // good.
868 
869  if (Src == MVT::i16)
870  return Dest == MVT::i32 ||Dest == MVT::i64 ;
871 
872  return Src == MVT::i32 && Dest == MVT::i64;
873 }
874 
876  return isZExtFree(Val.getValueType(), VT2);
877 }
878 
880  // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
881  // limited number of native 64-bit operations. Shrinking an operation to fit
882  // in a single 32-bit register should always be helpful. As currently used,
883  // this is much less general than the name suggests, and is only used in
884  // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
885  // not profitable, and may actually be harmful.
886  return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
887 }
888 
889 //===---------------------------------------------------------------------===//
890 // TargetLowering Callbacks
891 //===---------------------------------------------------------------------===//
892 
894  bool IsVarArg) {
895  switch (CC) {
903  return CC_AMDGPU;
904  case CallingConv::C:
905  case CallingConv::Fast:
906  case CallingConv::Cold:
907  return CC_AMDGPU_Func;
910  default:
911  report_fatal_error("Unsupported calling convention for call");
912  }
913 }
914 
916  bool IsVarArg) {
917  switch (CC) {
920  llvm_unreachable("kernels should not be handled here");
928  return RetCC_SI_Shader;
929  case CallingConv::C:
930  case CallingConv::Fast:
931  case CallingConv::Cold:
932  return RetCC_AMDGPU_Func;
933  default:
934  report_fatal_error("Unsupported calling convention.");
935  }
936 }
937 
938 /// The SelectionDAGBuilder will automatically promote function arguments
939 /// with illegal types. However, this does not work for the AMDGPU targets
940 /// since the function arguments are stored in memory as these illegal types.
941 /// In order to handle this properly we need to get the original types sizes
942 /// from the LLVM IR Function and fixup the ISD:InputArg values before
943 /// passing them to AnalyzeFormalArguments()
944 
945 /// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
946 /// input values across multiple registers. Each item in the Ins array
947 /// represents a single value that will be stored in registers. Ins[x].VT is
948 /// the value type of the value that will be stored in the register, so
949 /// whatever SDNode we lower the argument to needs to be this type.
950 ///
951 /// In order to correctly lower the arguments we need to know the size of each
952 /// argument. Since Ins[x].VT gives us the size of the register that will
953 /// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
954 /// for the orignal function argument so that we can deduce the correct memory
955 /// type to use for Ins[x]. In most cases the correct memory type will be
956 /// Ins[x].ArgVT. However, this will not always be the case. If, for example,
957 /// we have a kernel argument of type v8i8, this argument will be split into
958 /// 8 parts and each part will be represented by its own item in the Ins array.
959 /// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
960 /// the argument before it was split. From this, we deduce that the memory type
961 /// for each individual part is i8. We pass the memory type as LocVT to the
962 /// calling convention analysis function and the register type (Ins[x].VT) as
963 /// the ValVT.
965  CCState &State,
966  const SmallVectorImpl<ISD::InputArg> &Ins) const {
967  const MachineFunction &MF = State.getMachineFunction();
968  const Function &Fn = MF.getFunction();
969  LLVMContext &Ctx = Fn.getParent()->getContext();
971  const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset(Fn);
973 
974  unsigned MaxAlign = 1;
975  uint64_t ExplicitArgOffset = 0;
976  const DataLayout &DL = Fn.getParent()->getDataLayout();
977 
978  unsigned InIndex = 0;
979 
980  for (const Argument &Arg : Fn.args()) {
981  Type *BaseArgTy = Arg.getType();
982  unsigned Align = DL.getABITypeAlignment(BaseArgTy);
983  MaxAlign = std::max(Align, MaxAlign);
984  unsigned AllocSize = DL.getTypeAllocSize(BaseArgTy);
985 
986  uint64_t ArgOffset = alignTo(ExplicitArgOffset, Align) + ExplicitOffset;
987  ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize;
988 
989  // We're basically throwing away everything passed into us and starting over
990  // to get accurate in-memory offsets. The "PartOffset" is completely useless
991  // to us as computed in Ins.
992  //
993  // We also need to figure out what type legalization is trying to do to get
994  // the correct memory offsets.
995 
996  SmallVector<EVT, 16> ValueVTs;
998  ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset);
999 
1000  for (unsigned Value = 0, NumValues = ValueVTs.size();
1001  Value != NumValues; ++Value) {
1002  uint64_t BasePartOffset = Offsets[Value];
1003 
1004  EVT ArgVT = ValueVTs[Value];
1005  EVT MemVT = ArgVT;
1006  MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT);
1007  unsigned NumRegs = getNumRegistersForCallingConv(Ctx, CC, ArgVT);
1008 
1009  if (NumRegs == 1) {
1010  // This argument is not split, so the IR type is the memory type.
1011  if (ArgVT.isExtended()) {
1012  // We have an extended type, like i24, so we should just use the
1013  // register type.
1014  MemVT = RegisterVT;
1015  } else {
1016  MemVT = ArgVT;
1017  }
1018  } else if (ArgVT.isVector() && RegisterVT.isVector() &&
1019  ArgVT.getScalarType() == RegisterVT.getScalarType()) {
1020  assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements());
1021  // We have a vector value which has been split into a vector with
1022  // the same scalar type, but fewer elements. This should handle
1023  // all the floating-point vector types.
1024  MemVT = RegisterVT;
1025  } else if (ArgVT.isVector() &&
1026  ArgVT.getVectorNumElements() == NumRegs) {
1027  // This arg has been split so that each element is stored in a separate
1028  // register.
1029  MemVT = ArgVT.getScalarType();
1030  } else if (ArgVT.isExtended()) {
1031  // We have an extended type, like i65.
1032  MemVT = RegisterVT;
1033  } else {
1034  unsigned MemoryBits = ArgVT.getStoreSizeInBits() / NumRegs;
1035  assert(ArgVT.getStoreSizeInBits() % NumRegs == 0);
1036  if (RegisterVT.isInteger()) {
1037  MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
1038  } else if (RegisterVT.isVector()) {
1039  assert(!RegisterVT.getScalarType().isFloatingPoint());
1040  unsigned NumElements = RegisterVT.getVectorNumElements();
1041  assert(MemoryBits % NumElements == 0);
1042  // This vector type has been split into another vector type with
1043  // a different elements size.
1044  EVT ScalarVT = EVT::getIntegerVT(State.getContext(),
1045  MemoryBits / NumElements);
1046  MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
1047  } else {
1048  llvm_unreachable("cannot deduce memory type.");
1049  }
1050  }
1051 
1052  // Convert one element vectors to scalar.
1053  if (MemVT.isVector() && MemVT.getVectorNumElements() == 1)
1054  MemVT = MemVT.getScalarType();
1055 
1056  // Round up vec3/vec5 argument.
1057  if (MemVT.isVector() && !MemVT.isPow2VectorType()) {
1058  assert(MemVT.getVectorNumElements() == 3 ||
1059  MemVT.getVectorNumElements() == 5);
1060  MemVT = MemVT.getPow2VectorType(State.getContext());
1061  }
1062 
1063  unsigned PartOffset = 0;
1064  for (unsigned i = 0; i != NumRegs; ++i) {
1065  State.addLoc(CCValAssign::getCustomMem(InIndex++, RegisterVT,
1066  BasePartOffset + PartOffset,
1067  MemVT.getSimpleVT(),
1069  PartOffset += MemVT.getStoreSize();
1070  }
1071  }
1072  }
1073 }
1074 
1076  SDValue Chain, CallingConv::ID CallConv,
1077  bool isVarArg,
1078  const SmallVectorImpl<ISD::OutputArg> &Outs,
1079  const SmallVectorImpl<SDValue> &OutVals,
1080  const SDLoc &DL, SelectionDAG &DAG) const {
1081  // FIXME: Fails for r600 tests
1082  //assert(!isVarArg && Outs.empty() && OutVals.empty() &&
1083  // "wave terminate should not have return values");
1084  return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
1085 }
1086 
1087 //===---------------------------------------------------------------------===//
1088 // Target specific lowering
1089 //===---------------------------------------------------------------------===//
1090 
1091 /// Selects the correct CCAssignFn for a given CallingConvention value.
1093  bool IsVarArg) {
1094  return AMDGPUCallLowering::CCAssignFnForCall(CC, IsVarArg);
1095 }
1096 
1098  bool IsVarArg) {
1099  return AMDGPUCallLowering::CCAssignFnForReturn(CC, IsVarArg);
1100 }
1101 
1103  SelectionDAG &DAG,
1104  MachineFrameInfo &MFI,
1105  int ClobberedFI) const {
1106  SmallVector<SDValue, 8> ArgChains;
1107  int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
1108  int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
1109 
1110  // Include the original chain at the beginning of the list. When this is
1111  // used by target LowerCall hooks, this helps legalize find the
1112  // CALLSEQ_BEGIN node.
1113  ArgChains.push_back(Chain);
1114 
1115  // Add a chain value for each stack argument corresponding
1116  for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1117  UE = DAG.getEntryNode().getNode()->use_end();
1118  U != UE; ++U) {
1119  if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) {
1120  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) {
1121  if (FI->getIndex() < 0) {
1122  int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
1123  int64_t InLastByte = InFirstByte;
1124  InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
1125 
1126  if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1127  (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1128  ArgChains.push_back(SDValue(L, 1));
1129  }
1130  }
1131  }
1132  }
1133 
1134  // Build a tokenfactor for all the chains.
1135  return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
1136 }
1137 
1139  SmallVectorImpl<SDValue> &InVals,
1140  StringRef Reason) const {
1141  SDValue Callee = CLI.Callee;
1142  SelectionDAG &DAG = CLI.DAG;
1143 
1144  const Function &Fn = DAG.getMachineFunction().getFunction();
1145 
1146  StringRef FuncName("<unknown>");
1147 
1148  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
1149  FuncName = G->getSymbol();
1150  else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1151  FuncName = G->getGlobal()->getName();
1152 
1153  DiagnosticInfoUnsupported NoCalls(
1154  Fn, Reason + FuncName, CLI.DL.getDebugLoc());
1155  DAG.getContext()->diagnose(NoCalls);
1156 
1157  if (!CLI.IsTailCall) {
1158  for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
1159  InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
1160  }
1161 
1162  return DAG.getEntryNode();
1163 }
1164 
1166  SmallVectorImpl<SDValue> &InVals) const {
1167  return lowerUnhandledCall(CLI, InVals, "unsupported call to function ");
1168 }
1169 
1171  SelectionDAG &DAG) const {
1172  const Function &Fn = DAG.getMachineFunction().getFunction();
1173 
1174  DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
1175  SDLoc(Op).getDebugLoc());
1176  DAG.getContext()->diagnose(NoDynamicAlloca);
1177  auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
1178  return DAG.getMergeValues(Ops, SDLoc());
1179 }
1180 
1182  SelectionDAG &DAG) const {
1183  switch (Op.getOpcode()) {
1184  default:
1185  Op->print(errs(), &DAG);
1186  llvm_unreachable("Custom lowering code for this"
1187  "instruction is not implemented yet!");
1188  break;
1189  case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
1190  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1191  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
1192  case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
1193  case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
1194  case ISD::FREM: return LowerFREM(Op, DAG);
1195  case ISD::FCEIL: return LowerFCEIL(Op, DAG);
1196  case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
1197  case ISD::FRINT: return LowerFRINT(Op, DAG);
1198  case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
1199  case ISD::FROUND: return LowerFROUND(Op, DAG);
1200  case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
1201  case ISD::FLOG:
1202  return LowerFLOG(Op, DAG, 1 / AMDGPU_LOG2E_F);
1203  case ISD::FLOG10:
1204  return LowerFLOG(Op, DAG, AMDGPU_LN2_F / AMDGPU_LN10_F);
1205  case ISD::FEXP:
1206  return lowerFEXP(Op, DAG);
1207  case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1208  case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
1209  case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
1210  case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1211  case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
1212  case ISD::CTTZ:
1213  case ISD::CTTZ_ZERO_UNDEF:
1214  case ISD::CTLZ:
1215  case ISD::CTLZ_ZERO_UNDEF:
1216  return LowerCTLZ_CTTZ(Op, DAG);
1217  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1218  }
1219  return Op;
1220 }
1221 
1224  SelectionDAG &DAG) const {
1225  switch (N->getOpcode()) {
1227  // Different parts of legalization seem to interpret which type of
1228  // sign_extend_inreg is the one to check for custom lowering. The extended
1229  // from type is what really matters, but some places check for custom
1230  // lowering of the result type. This results in trying to use
1231  // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
1232  // nothing here and let the illegal result integer be handled normally.
1233  return;
1234  default:
1235  return;
1236  }
1237 }
1238 
1239 static bool hasDefinedInitializer(const GlobalValue *GV) {
1240  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1241  if (!GVar || !GVar->hasInitializer())
1242  return false;
1243 
1244  return !isa<UndefValue>(GVar->getInitializer());
1245 }
1246 
1248  SDValue Op,
1249  SelectionDAG &DAG) const {
1250 
1251  const DataLayout &DL = DAG.getDataLayout();
1252  GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
1253  const GlobalValue *GV = G->getGlobal();
1254 
1257  if (!MFI->isEntryFunction()) {
1258  const Function &Fn = DAG.getMachineFunction().getFunction();
1259  DiagnosticInfoUnsupported BadLDSDecl(
1260  Fn, "local memory global used by non-kernel function", SDLoc(Op).getDebugLoc());
1261  DAG.getContext()->diagnose(BadLDSDecl);
1262  }
1263 
1264  // XXX: What does the value of G->getOffset() mean?
1265  assert(G->getOffset() == 0 &&
1266  "Do not know what to do with an non-zero offset");
1267 
1268  // TODO: We could emit code to handle the initialization somewhere.
1269  if (!hasDefinedInitializer(GV)) {
1270  unsigned Offset = MFI->allocateLDSGlobal(DL, *GV);
1271  return DAG.getConstant(Offset, SDLoc(Op), Op.getValueType());
1272  }
1273  }
1274 
1275  const Function &Fn = DAG.getMachineFunction().getFunction();
1276  DiagnosticInfoUnsupported BadInit(
1277  Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
1278  DAG.getContext()->diagnose(BadInit);
1279  return SDValue();
1280 }
1281 
1283  SelectionDAG &DAG) const {
1285 
1286  EVT VT = Op.getValueType();
1287  if (VT == MVT::v4i16 || VT == MVT::v4f16) {
1288  SDLoc SL(Op);
1289  SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1290  SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1291 
1292  SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi });
1293  return DAG.getNode(ISD::BITCAST, SL, VT, BV);
1294  }
1295 
1296  for (const SDUse &U : Op->ops())
1297  DAG.ExtractVectorElements(U.get(), Args);
1298 
1299  return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1300 }
1301 
1303  SelectionDAG &DAG) const {
1304 
1306  unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1307  EVT VT = Op.getValueType();
1308  DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
1309  VT.getVectorNumElements());
1310 
1311  return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1312 }
1313 
1314 /// Generate Min/Max node
1316  SDValue LHS, SDValue RHS,
1317  SDValue True, SDValue False,
1318  SDValue CC,
1319  DAGCombinerInfo &DCI) const {
1320  if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1321  return SDValue();
1322 
1323  SelectionDAG &DAG = DCI.DAG;
1324  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1325  switch (CCOpcode) {
1326  case ISD::SETOEQ:
1327  case ISD::SETONE:
1328  case ISD::SETUNE:
1329  case ISD::SETNE:
1330  case ISD::SETUEQ:
1331  case ISD::SETEQ:
1332  case ISD::SETFALSE:
1333  case ISD::SETFALSE2:
1334  case ISD::SETTRUE:
1335  case ISD::SETTRUE2:
1336  case ISD::SETUO:
1337  case ISD::SETO:
1338  break;
1339  case ISD::SETULE:
1340  case ISD::SETULT: {
1341  if (LHS == True)
1342  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1343  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1344  }
1345  case ISD::SETOLE:
1346  case ISD::SETOLT:
1347  case ISD::SETLE:
1348  case ISD::SETLT: {
1349  // Ordered. Assume ordered for undefined.
1350 
1351  // Only do this after legalization to avoid interfering with other combines
1352  // which might occur.
1353  if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1354  !DCI.isCalledByLegalizer())
1355  return SDValue();
1356 
1357  // We need to permute the operands to get the correct NaN behavior. The
1358  // selected operand is the second one based on the failing compare with NaN,
1359  // so permute it based on the compare type the hardware uses.
1360  if (LHS == True)
1361  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1362  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1363  }
1364  case ISD::SETUGE:
1365  case ISD::SETUGT: {
1366  if (LHS == True)
1367  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1368  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1369  }
1370  case ISD::SETGT:
1371  case ISD::SETGE:
1372  case ISD::SETOGE:
1373  case ISD::SETOGT: {
1374  if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1375  !DCI.isCalledByLegalizer())
1376  return SDValue();
1377 
1378  if (LHS == True)
1379  return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1380  return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1381  }
1382  case ISD::SETCC_INVALID:
1383  llvm_unreachable("Invalid setcc condcode!");
1384  }
1385  return SDValue();
1386 }
1387 
1388 std::pair<SDValue, SDValue>
1390  SDLoc SL(Op);
1391 
1392  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1393 
1394  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1395  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1396 
1397  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1398  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1399 
1400  return std::make_pair(Lo, Hi);
1401 }
1402 
1404  SDLoc SL(Op);
1405 
1406  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1407  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1408  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1409 }
1410 
1412  SDLoc SL(Op);
1413 
1414  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1415  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1416  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1417 }
1418 
1419 // Split a vector type into two parts. The first part is a power of two vector.
1420 // The second part is whatever is left over, and is a scalar if it would
1421 // otherwise be a 1-vector.
1422 std::pair<EVT, EVT>
1424  EVT LoVT, HiVT;
1425  EVT EltVT = VT.getVectorElementType();
1426  unsigned NumElts = VT.getVectorNumElements();
1427  unsigned LoNumElts = PowerOf2Ceil((NumElts + 1) / 2);
1428  LoVT = EVT::getVectorVT(*DAG.getContext(), EltVT, LoNumElts);
1429  HiVT = NumElts - LoNumElts == 1
1430  ? EltVT
1431  : EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts - LoNumElts);
1432  return std::make_pair(LoVT, HiVT);
1433 }
1434 
1435 // Split a vector value into two parts of types LoVT and HiVT. HiVT could be
1436 // scalar.
1437 std::pair<SDValue, SDValue>
1439  const EVT &LoVT, const EVT &HiVT,
1440  SelectionDAG &DAG) const {
1441  assert(LoVT.getVectorNumElements() +
1442  (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <=
1444  "More vector elements requested than available!");
1445  auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
1446  SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N,
1447  DAG.getConstant(0, DL, IdxTy));
1448  SDValue Hi = DAG.getNode(
1450  HiVT, N, DAG.getConstant(LoVT.getVectorNumElements(), DL, IdxTy));
1451  return std::make_pair(Lo, Hi);
1452 }
1453 
1455  SelectionDAG &DAG) const {
1456  LoadSDNode *Load = cast<LoadSDNode>(Op);
1457  EVT VT = Op.getValueType();
1458 
1459 
1460  // If this is a 2 element vector, we really want to scalarize and not create
1461  // weird 1 element vectors.
1462  if (VT.getVectorNumElements() == 2)
1463  return scalarizeVectorLoad(Load, DAG);
1464 
1465  SDValue BasePtr = Load->getBasePtr();
1466  EVT MemVT = Load->getMemoryVT();
1467  SDLoc SL(Op);
1468 
1469  const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1470 
1471  EVT LoVT, HiVT;
1472  EVT LoMemVT, HiMemVT;
1473  SDValue Lo, Hi;
1474 
1475  std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1476  std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1477  std::tie(Lo, Hi) = splitVector(Op, SL, LoVT, HiVT, DAG);
1478 
1479  unsigned Size = LoMemVT.getStoreSize();
1480  unsigned BaseAlign = Load->getAlignment();
1481  unsigned HiAlign = MinAlign(BaseAlign, Size);
1482 
1483  SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1484  Load->getChain(), BasePtr, SrcValue, LoMemVT,
1485  BaseAlign, Load->getMemOperand()->getFlags());
1486  SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, Size);
1487  SDValue HiLoad =
1488  DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1489  HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1490  HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1491 
1492  auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
1493  SDValue Join;
1494  if (LoVT == HiVT) {
1495  // This is the case that the vector is power of two so was evenly split.
1496  Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad);
1497  } else {
1498  Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad,
1499  DAG.getConstant(0, SL, IdxTy));
1500  Join = DAG.getNode(HiVT.isVector() ? ISD::INSERT_SUBVECTOR
1502  SL, VT, Join, HiLoad,
1503  DAG.getConstant(LoVT.getVectorNumElements(), SL, IdxTy));
1504  }
1505 
1506  SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1507  LoLoad.getValue(1), HiLoad.getValue(1))};
1508 
1509  return DAG.getMergeValues(Ops, SL);
1510 }
1511 
1512 // Widen a vector load from vec3 to vec4.
1514  SelectionDAG &DAG) const {
1515  LoadSDNode *Load = cast<LoadSDNode>(Op);
1516  EVT VT = Op.getValueType();
1517  assert(VT.getVectorNumElements() == 3);
1518  SDValue BasePtr = Load->getBasePtr();
1519  EVT MemVT = Load->getMemoryVT();
1520  SDLoc SL(Op);
1521  const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1522  unsigned BaseAlign = Load->getAlignment();
1523 
1524  EVT WideVT =
1525  EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
1526  EVT WideMemVT =
1527  EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), 4);
1528  SDValue WideLoad = DAG.getExtLoad(
1529  Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue,
1530  WideMemVT, BaseAlign, Load->getMemOperand()->getFlags());
1531  return DAG.getMergeValues(
1532  {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad,
1533  DAG.getConstant(0, SL, getVectorIdxTy(DAG.getDataLayout()))),
1534  WideLoad.getValue(1)},
1535  SL);
1536 }
1537 
1539  SelectionDAG &DAG) const {
1540  StoreSDNode *Store = cast<StoreSDNode>(Op);
1541  SDValue Val = Store->getValue();
1542  EVT VT = Val.getValueType();
1543 
1544  // If this is a 2 element vector, we really want to scalarize and not create
1545  // weird 1 element vectors.
1546  if (VT.getVectorNumElements() == 2)
1547  return scalarizeVectorStore(Store, DAG);
1548 
1549  EVT MemVT = Store->getMemoryVT();
1550  SDValue Chain = Store->getChain();
1551  SDValue BasePtr = Store->getBasePtr();
1552  SDLoc SL(Op);
1553 
1554  EVT LoVT, HiVT;
1555  EVT LoMemVT, HiMemVT;
1556  SDValue Lo, Hi;
1557 
1558  std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1559  std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1560  std::tie(Lo, Hi) = splitVector(Val, SL, LoVT, HiVT, DAG);
1561 
1562  SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize());
1563 
1564  const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1565  unsigned BaseAlign = Store->getAlignment();
1566  unsigned Size = LoMemVT.getStoreSize();
1567  unsigned HiAlign = MinAlign(BaseAlign, Size);
1568 
1569  SDValue LoStore =
1570  DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1571  Store->getMemOperand()->getFlags());
1572  SDValue HiStore =
1573  DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1574  HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1575 
1576  return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1577 }
1578 
1579 // This is a shortcut for integer division because we have fast i32<->f32
1580 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1581 // float is enough to accurately represent up to a 24-bit signed integer.
1583  bool Sign) const {
1584  SDLoc DL(Op);
1585  EVT VT = Op.getValueType();
1586  SDValue LHS = Op.getOperand(0);
1587  SDValue RHS = Op.getOperand(1);
1588  MVT IntVT = MVT::i32;
1589  MVT FltVT = MVT::f32;
1590 
1591  unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1592  if (LHSSignBits < 9)
1593  return SDValue();
1594 
1595  unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1596  if (RHSSignBits < 9)
1597  return SDValue();
1598 
1599  unsigned BitSize = VT.getSizeInBits();
1600  unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1601  unsigned DivBits = BitSize - SignBits;
1602  if (Sign)
1603  ++DivBits;
1604 
1607 
1608  SDValue jq = DAG.getConstant(1, DL, IntVT);
1609 
1610  if (Sign) {
1611  // char|short jq = ia ^ ib;
1612  jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1613 
1614  // jq = jq >> (bitsize - 2)
1615  jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1616  DAG.getConstant(BitSize - 2, DL, VT));
1617 
1618  // jq = jq | 0x1
1619  jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1620  }
1621 
1622  // int ia = (int)LHS;
1623  SDValue ia = LHS;
1624 
1625  // int ib, (int)RHS;
1626  SDValue ib = RHS;
1627 
1628  // float fa = (float)ia;
1629  SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1630 
1631  // float fb = (float)ib;
1632  SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1633 
1634  SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1635  fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1636 
1637  // fq = trunc(fq);
1638  fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1639 
1640  // float fqneg = -fq;
1641  SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1642 
1643  // float fr = mad(fqneg, fb, fa);
1644  unsigned OpCode = Subtarget->hasFP32Denormals() ?
1646  (unsigned)ISD::FMAD;
1647  SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
1648 
1649  // int iq = (int)fq;
1650  SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1651 
1652  // fr = fabs(fr);
1653  fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1654 
1655  // fb = fabs(fb);
1656  fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1657 
1658  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1659 
1660  // int cv = fr >= fb;
1661  SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1662 
1663  // jq = (cv ? jq : 0);
1664  jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1665 
1666  // dst = iq + jq;
1667  SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1668 
1669  // Rem needs compensation, it's easier to recompute it
1670  SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1671  Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1672 
1673  // Truncate to number of bits this divide really is.
1674  if (Sign) {
1675  SDValue InRegSize
1676  = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1677  Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1678  Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1679  } else {
1680  SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT);
1681  Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1682  Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1683  }
1684 
1685  return DAG.getMergeValues({ Div, Rem }, DL);
1686 }
1687 
1689  SelectionDAG &DAG,
1691  SDLoc DL(Op);
1692  EVT VT = Op.getValueType();
1693 
1694  assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64");
1695 
1696  EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1697 
1698  SDValue One = DAG.getConstant(1, DL, HalfVT);
1699  SDValue Zero = DAG.getConstant(0, DL, HalfVT);
1700 
1701  //HiLo split
1702  SDValue LHS = Op.getOperand(0);
1703  SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1704  SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);
1705 
1706  SDValue RHS = Op.getOperand(1);
1707  SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1708  SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);
1709 
1710  if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1711  DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1712 
1713  SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1714  LHS_Lo, RHS_Lo);
1715 
1716  SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero});
1717  SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero});
1718 
1719  Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1720  Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1721  return;
1722  }
1723 
1724  if (isTypeLegal(MVT::i64)) {
1725  // Compute denominator reciprocal.
1726  unsigned FMAD = Subtarget->hasFP32Denormals() ?
1728  (unsigned)ISD::FMAD;
1729 
1730  SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1731  SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
1732  SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
1733  DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
1734  Cvt_Lo);
1735  SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
1736  SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1737  DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32));
1738  SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
1739  DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32));
1740  SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
1741  SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,
1742  DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32),
1743  Mul1);
1744  SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);
1745  SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);
1746  SDValue Rcp64 = DAG.getBitcast(VT,
1747  DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi}));
1748 
1749  SDValue Zero64 = DAG.getConstant(0, DL, VT);
1750  SDValue One64 = DAG.getConstant(1, DL, VT);
1751  SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
1752  SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
1753 
1754  SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
1755  SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1756  SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1757  SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1758  Zero);
1759  SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1760  One);
1761 
1762  SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
1763  Mulhi1_Lo, Zero1);
1764  SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
1765  Mulhi1_Hi, Add1_Lo.getValue(1));
1766  SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);
1767  SDValue Add1 = DAG.getBitcast(VT,
1768  DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
1769 
1770  SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1771  SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1772  SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1773  Zero);
1774  SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1775  One);
1776 
1777  SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
1778  Mulhi2_Lo, Zero1);
1779  SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
1780  Mulhi2_Hi, Add1_Lo.getValue(1));
1781  SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
1782  Zero, Add2_Lo.getValue(1));
1783  SDValue Add2 = DAG.getBitcast(VT,
1784  DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
1785  SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1786 
1787  SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1788 
1789  SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);
1790  SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);
1791  SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1792  Mul3_Lo, Zero1);
1793  SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1794  Mul3_Hi, Sub1_Lo.getValue(1));
1795  SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
1796  SDValue Sub1 = DAG.getBitcast(VT,
1797  DAG.getBuildVector(MVT::v2i32, DL, {Sub1_Lo, Sub1_Hi}));
1798 
1799  SDValue MinusOne = DAG.getConstant(0xffffffffu, DL, HalfVT);
1800  SDValue C1 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, MinusOne, Zero,
1801  ISD::SETUGE);
1802  SDValue C2 = DAG.getSelectCC(DL, Sub1_Lo, RHS_Lo, MinusOne, Zero,
1803  ISD::SETUGE);
1804  SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1805 
1806  // TODO: Here and below portions of the code can be enclosed into if/endif.
1807  // Currently control flow is unconditional and we have 4 selects after
1808  // potential endif to substitute PHIs.
1809 
1810  // if C3 != 0 ...
1811  SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1812  RHS_Lo, Zero1);
1813  SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1814  RHS_Hi, Sub1_Lo.getValue(1));
1815  SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1816  Zero, Sub2_Lo.getValue(1));
1817  SDValue Sub2 = DAG.getBitcast(VT,
1818  DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi}));
1819 
1820  SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64);
1821 
1822  SDValue C4 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, MinusOne, Zero,
1823  ISD::SETUGE);
1824  SDValue C5 = DAG.getSelectCC(DL, Sub2_Lo, RHS_Lo, MinusOne, Zero,
1825  ISD::SETUGE);
1826  SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1827 
1828  // if (C6 != 0)
1829  SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);
1830 
1831  SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1832  RHS_Lo, Zero1);
1833  SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1834  RHS_Hi, Sub2_Lo.getValue(1));
1835  SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
1836  Zero, Sub3_Lo.getValue(1));
1837  SDValue Sub3 = DAG.getBitcast(VT,
1838  DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi}));
1839 
1840  // endif C6
1841  // endif C3
1842 
1843  SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE);
1844  SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE);
1845 
1846  SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE);
1847  SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE);
1848 
1849  Results.push_back(Div);
1850  Results.push_back(Rem);
1851 
1852  return;
1853  }
1854 
1855  // r600 expandion.
1856  // Get Speculative values
1857  SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1858  SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1859 
1860  SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1861  SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, Zero});
1862  REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1863 
1864  SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
1865  SDValue DIV_Lo = Zero;
1866 
1867  const unsigned halfBitWidth = HalfVT.getSizeInBits();
1868 
1869  for (unsigned i = 0; i < halfBitWidth; ++i) {
1870  const unsigned bitPos = halfBitWidth - i - 1;
1871  SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1872  // Get value of high bit
1873  SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1874  HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);
1875  HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1876 
1877  // Shift
1878  REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1879  // Add LHS high bit
1880  REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1881 
1882  SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1883  SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE);
1884 
1885  DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1886 
1887  // Update REM
1888  SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1889  REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1890  }
1891 
1892  SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1893  DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1894  Results.push_back(DIV);
1895  Results.push_back(REM);
1896 }
1897 
1899  SelectionDAG &DAG) const {
1900  SDLoc DL(Op);
1901  EVT VT = Op.getValueType();
1902 
1903  if (VT == MVT::i64) {
1905  LowerUDIVREM64(Op, DAG, Results);
1906  return DAG.getMergeValues(Results, DL);
1907  }
1908 
1909  if (VT == MVT::i32) {
1910  if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1911  return Res;
1912  }
1913 
1914  SDValue Num = Op.getOperand(0);
1915  SDValue Den = Op.getOperand(1);
1916 
1917  // RCP = URECIP(Den) = 2^32 / Den + e
1918  // e is rounding error.
1919  SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1920 
1921  // RCP_LO = mul(RCP, Den) */
1922  SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1923 
1924  // RCP_HI = mulhu (RCP, Den) */
1925  SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1926 
1927  // NEG_RCP_LO = -RCP_LO
1928  SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1929  RCP_LO);
1930 
1931  // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1932  SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1933  NEG_RCP_LO, RCP_LO,
1934  ISD::SETEQ);
1935  // Calculate the rounding error from the URECIP instruction
1936  // E = mulhu(ABS_RCP_LO, RCP)
1937  SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1938 
1939  // RCP_A_E = RCP + E
1940  SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1941 
1942  // RCP_S_E = RCP - E
1943  SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1944 
1945  // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1946  SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1947  RCP_A_E, RCP_S_E,
1948  ISD::SETEQ);
1949  // Quotient = mulhu(Tmp0, Num)
1950  SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1951 
1952  // Num_S_Remainder = Quotient * Den
1953  SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1954 
1955  // Remainder = Num - Num_S_Remainder
1956  SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1957 
1958  // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1959  SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1960  DAG.getConstant(-1, DL, VT),
1961  DAG.getConstant(0, DL, VT),
1962  ISD::SETUGE);
1963  // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1964  SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1965  Num_S_Remainder,
1966  DAG.getConstant(-1, DL, VT),
1967  DAG.getConstant(0, DL, VT),
1968  ISD::SETUGE);
1969  // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1970  SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1971  Remainder_GE_Zero);
1972 
1973  // Calculate Division result:
1974 
1975  // Quotient_A_One = Quotient + 1
1976  SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1977  DAG.getConstant(1, DL, VT));
1978 
1979  // Quotient_S_One = Quotient - 1
1980  SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1981  DAG.getConstant(1, DL, VT));
1982 
1983  // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1984  SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1985  Quotient, Quotient_A_One, ISD::SETEQ);
1986 
1987  // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1988  Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1989  Quotient_S_One, Div, ISD::SETEQ);
1990 
1991  // Calculate Rem result:
1992 
1993  // Remainder_S_Den = Remainder - Den
1994  SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1995 
1996  // Remainder_A_Den = Remainder + Den
1997  SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1998 
1999  // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
2000  SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
2001  Remainder, Remainder_S_Den, ISD::SETEQ);
2002 
2003  // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
2004  Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
2005  Remainder_A_Den, Rem, ISD::SETEQ);
2006  SDValue Ops[2] = {
2007  Div,
2008  Rem
2009  };
2010  return DAG.getMergeValues(Ops, DL);
2011 }
2012 
2014  SelectionDAG &DAG) const {
2015  SDLoc DL(Op);
2016  EVT VT = Op.getValueType();
2017 
2018  SDValue LHS = Op.getOperand(0);
2019  SDValue RHS = Op.getOperand(1);
2020 
2021  SDValue Zero = DAG.getConstant(0, DL, VT);
2022  SDValue NegOne = DAG.getConstant(-1, DL, VT);
2023 
2024  if (VT == MVT::i32) {
2025  if (SDValue Res = LowerDIVREM24(Op, DAG, true))
2026  return Res;
2027  }
2028 
2029  if (VT == MVT::i64 &&
2030  DAG.ComputeNumSignBits(LHS) > 32 &&
2031  DAG.ComputeNumSignBits(RHS) > 32) {
2032  EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
2033 
2034  //HiLo split
2035  SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
2036  SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
2037  SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
2038  LHS_Lo, RHS_Lo);
2039  SDValue Res[2] = {
2040  DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
2041  DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
2042  };
2043  return DAG.getMergeValues(Res, DL);
2044  }
2045 
2046  SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
2047  SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
2048  SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
2049  SDValue RSign = LHSign; // Remainder sign is the same as LHS
2050 
2051  LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
2052  RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
2053 
2054  LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
2055  RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
2056 
2057  SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
2058  SDValue Rem = Div.getValue(1);
2059 
2060  Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
2061  Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
2062 
2063  Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
2064  Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
2065 
2066  SDValue Res[2] = {
2067  Div,
2068  Rem
2069  };
2070  return DAG.getMergeValues(Res, DL);
2071 }
2072 
2073 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
2075  SDLoc SL(Op);
2076  EVT VT = Op.getValueType();
2077  SDValue X = Op.getOperand(0);
2078  SDValue Y = Op.getOperand(1);
2079 
2080  // TODO: Should this propagate fast-math-flags?
2081 
2082  SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
2083  SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
2084  SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
2085 
2086  return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
2087 }
2088 
2090  SDLoc SL(Op);
2091  SDValue Src = Op.getOperand(0);
2092 
2093  // result = trunc(src)
2094  // if (src > 0.0 && src != result)
2095  // result += 1.0
2096 
2097  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2098 
2099  const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2100  const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
2101 
2102  EVT SetCCVT =
2104 
2105  SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
2106  SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2107  SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2108 
2109  SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
2110  // TODO: Should this propagate fast-math-flags?
2111  return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2112 }
2113 
2115  SelectionDAG &DAG) {
2116  const unsigned FractBits = 52;
2117  const unsigned ExpBits = 11;
2118 
2119  SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
2120  Hi,
2121  DAG.getConstant(FractBits - 32, SL, MVT::i32),
2122  DAG.getConstant(ExpBits, SL, MVT::i32));
2123  SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
2124  DAG.getConstant(1023, SL, MVT::i32));
2125 
2126  return Exp;
2127 }
2128 
2130  SDLoc SL(Op);
2131  SDValue Src = Op.getOperand(0);
2132 
2133  assert(Op.getValueType() == MVT::f64);
2134 
2135  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2136  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2137 
2138  SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2139 
2140  // Extract the upper half, since this is where we will find the sign and
2141  // exponent.
2142  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
2143 
2144  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2145 
2146  const unsigned FractBits = 52;
2147 
2148  // Extract the sign bit.
2149  const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
2150  SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2151 
2152  // Extend back to 64-bits.
2153  SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
2154  SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2155 
2156  SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2157  const SDValue FractMask
2158  = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
2159 
2160  SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2161  SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2162  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2163 
2164  EVT SetCCVT =
2166 
2167  const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2168 
2169  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2170  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2171 
2172  SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2173  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2174 
2175  return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2176 }
2177 
2179  SDLoc SL(Op);
2180  SDValue Src = Op.getOperand(0);
2181 
2182  assert(Op.getValueType() == MVT::f64);
2183 
2184  APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
2185  SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2186  SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2187 
2188  // TODO: Should this propagate fast-math-flags?
2189 
2190  SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2191  SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2192 
2193  SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2194 
2195  APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
2196  SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2197 
2198  EVT SetCCVT =
2200  SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2201 
2202  return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2203 }
2204 
2206  // FNEARBYINT and FRINT are the same, except in their handling of FP
2207  // exceptions. Those aren't really meaningful for us, and OpenCL only has
2208  // rint, so just treat them as equivalent.
2209  return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2210 }
2211 
2212 // XXX - May require not supporting f32 denormals?
2213 
2214 // Don't handle v2f16. The extra instructions to scalarize and repack around the
2215 // compare and vselect end up producing worse code than scalarizing the whole
2216 // operation.
2218  SDLoc SL(Op);
2219  SDValue X = Op.getOperand(0);
2220  EVT VT = Op.getValueType();
2221 
2222  SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
2223 
2224  // TODO: Should this propagate fast-math-flags?
2225 
2226  SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
2227 
2228  SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
2229 
2230  const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
2231  const SDValue One = DAG.getConstantFP(1.0, SL, VT);
2232  const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
2233 
2234  SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
2235 
2236  EVT SetCCVT =
2237  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
2238 
2239  SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2240 
2241  SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
2242 
2243  return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2244 }
2245 
2247  SDLoc SL(Op);
2248  SDValue X = Op.getOperand(0);
2249 
2250  SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2251 
2252  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2253  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2254  const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2255  const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2256  EVT SetCCVT =
2258 
2259  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2260 
2261  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2262 
2263  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2264 
2265  const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2266  MVT::i64);
2267 
2268  SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2269  SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2270  DAG.getConstant(INT64_C(0x0008000000000000), SL,
2271  MVT::i64),
2272  Exp);
2273 
2274  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2275  SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2276  DAG.getConstant(0, SL, MVT::i64), Tmp0,
2277  ISD::SETNE);
2278 
2279  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2280  D, DAG.getConstant(0, SL, MVT::i64));
2281  SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2282 
2283  K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2284  K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2285 
2286  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2287  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2288  SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2289 
2290  SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2291  ExpEqNegOne,
2292  DAG.getConstantFP(1.0, SL, MVT::f64),
2293  DAG.getConstantFP(0.0, SL, MVT::f64));
2294 
2295  SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2296 
2297  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2298  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2299 
2300  return K;
2301 }
2302 
2304  EVT VT = Op.getValueType();
2305 
2306  if (VT == MVT::f32 || VT == MVT::f16)
2307  return LowerFROUND32_16(Op, DAG);
2308 
2309  if (VT == MVT::f64)
2310  return LowerFROUND64(Op, DAG);
2311 
2312  llvm_unreachable("unhandled type");
2313 }
2314 
2316  SDLoc SL(Op);
2317  SDValue Src = Op.getOperand(0);
2318 
2319  // result = trunc(src);
2320  // if (src < 0.0 && src != result)
2321  // result += -1.0.
2322 
2323  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2324 
2325  const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2326  const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2327 
2328  EVT SetCCVT =
2330 
2331  SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2332  SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2333  SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2334 
2335  SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2336  // TODO: Should this propagate fast-math-flags?
2337  return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2338 }
2339 
2341  double Log2BaseInverted) const {
2342  EVT VT = Op.getValueType();
2343 
2344  SDLoc SL(Op);
2345  SDValue Operand = Op.getOperand(0);
2346  SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
2347  SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
2348 
2349  return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2350 }
2351 
2352 // Return M_LOG2E of appropriate type
2353 static SDValue getLog2EVal(SelectionDAG &DAG, const SDLoc &SL, EVT VT) {
2354  switch (VT.getScalarType().getSimpleVT().SimpleTy) {
2355  case MVT::f32:
2356  return DAG.getConstantFP(1.44269504088896340735992468100189214f, SL, VT);
2357  case MVT::f16:
2358  return DAG.getConstantFP(
2359  APFloat(APFloat::IEEEhalf(), "1.44269504088896340735992468100189214"),
2360  SL, VT);
2361  case MVT::f64:
2362  return DAG.getConstantFP(
2363  APFloat(APFloat::IEEEdouble(), "0x1.71547652b82fep+0"), SL, VT);
2364  default:
2365  llvm_unreachable("unsupported fp type");
2366  }
2367 }
2368 
2369 // exp2(M_LOG2E_F * f);
2371  EVT VT = Op.getValueType();
2372  SDLoc SL(Op);
2373  SDValue Src = Op.getOperand(0);
2374 
2375  const SDValue K = getLog2EVal(DAG, SL, VT);
2376  SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2377  return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
2378 }
2379 
2380 static bool isCtlzOpc(unsigned Opc) {
2381  return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2382 }
2383 
2384 static bool isCttzOpc(unsigned Opc) {
2385  return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
2386 }
2387 
2389  SDLoc SL(Op);
2390  SDValue Src = Op.getOperand(0);
2391  bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
2393 
2394  unsigned ISDOpc, NewOpc;
2395  if (isCtlzOpc(Op.getOpcode())) {
2396  ISDOpc = ISD::CTLZ_ZERO_UNDEF;
2397  NewOpc = AMDGPUISD::FFBH_U32;
2398  } else if (isCttzOpc(Op.getOpcode())) {
2399  ISDOpc = ISD::CTTZ_ZERO_UNDEF;
2400  NewOpc = AMDGPUISD::FFBL_B32;
2401  } else
2402  llvm_unreachable("Unexpected OPCode!!!");
2403 
2404 
2405  if (ZeroUndef && Src.getValueType() == MVT::i32)
2406  return DAG.getNode(NewOpc, SL, MVT::i32, Src);
2407 
2408  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2409 
2410  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2411  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2412 
2413  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
2414  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
2415 
2416  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2417  *DAG.getContext(), MVT::i32);
2418 
2419  SDValue HiOrLo = isCtlzOpc(Op.getOpcode()) ? Hi : Lo;
2420  SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ);
2421 
2422  SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo);
2423  SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi);
2424 
2425  const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
2426  SDValue Add, NewOpr;
2427  if (isCtlzOpc(Op.getOpcode())) {
2428  Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32);
2429  // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
2430  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi);
2431  } else {
2432  Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32);
2433  // cttz(x) = lo_32(x) == 0 ? cttz(hi_32(x)) + 32 : cttz(lo_32(x))
2434  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo);
2435  }
2436 
2437  if (!ZeroUndef) {
2438  // Test if the full 64-bit input is zero.
2439 
2440  // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
2441  // which we probably don't want.
2442  SDValue LoOrHi = isCtlzOpc(Op.getOpcode()) ? Lo : Hi;
2443  SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ);
2444  SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0);
2445 
2446  // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
2447  // with the same cycles, otherwise it is slower.
2448  // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
2449  // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2450 
2451  const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
2452 
2453  // The instruction returns -1 for 0 input, but the defined intrinsic
2454  // behavior is to return the number of bits.
2455  NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32,
2456  SrcIsZero, Bits32, NewOpr);
2457  }
2458 
2459  return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
2460 }
2461 
2463  bool Signed) const {
2464  // Unsigned
2465  // cul2f(ulong u)
2466  //{
2467  // uint lz = clz(u);
2468  // uint e = (u != 0) ? 127U + 63U - lz : 0;
2469  // u = (u << lz) & 0x7fffffffffffffffUL;
2470  // ulong t = u & 0xffffffffffUL;
2471  // uint v = (e << 23) | (uint)(u >> 40);
2472  // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
2473  // return as_float(v + r);
2474  //}
2475  // Signed
2476  // cl2f(long l)
2477  //{
2478  // long s = l >> 63;
2479  // float r = cul2f((l + s) ^ s);
2480  // return s ? -r : r;
2481  //}
2482 
2483  SDLoc SL(Op);
2484  SDValue Src = Op.getOperand(0);
2485  SDValue L = Src;
2486 
2487  SDValue S;
2488  if (Signed) {
2489  const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2490  S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2491 
2492  SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2493  L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2494  }
2495 
2496  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2497  *DAG.getContext(), MVT::f32);
2498 
2499 
2500  SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
2501  SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2502  SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2503  LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2504 
2505  SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
2506  SDValue E = DAG.getSelect(SL, MVT::i32,
2507  DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
2508  DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2509  ZeroI32);
2510 
2511  SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2512  DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2513  DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2514 
2515  SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2516  DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2517 
2518  SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2519  U, DAG.getConstant(40, SL, MVT::i64));
2520 
2521  SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2522  DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2523  DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
2524 
2525  SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2526  SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
2527  SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2528 
2529  SDValue One = DAG.getConstant(1, SL, MVT::i32);
2530 
2531  SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2532 
2533  SDValue R = DAG.getSelect(SL, MVT::i32,
2534  RCmp,
2535  One,
2536  DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2537  R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2538  R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2539 
2540  if (!Signed)
2541  return R;
2542 
2543  SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2544  return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2545 }
2546 
2548  bool Signed) const {
2549  SDLoc SL(Op);
2550  SDValue Src = Op.getOperand(0);
2551 
2552  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2553 
2555  DAG.getConstant(0, SL, MVT::i32));
2557  DAG.getConstant(1, SL, MVT::i32));
2558 
2559  SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2560  SL, MVT::f64, Hi);
2561 
2562  SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2563 
2564  SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2565  DAG.getConstant(32, SL, MVT::i32));
2566  // TODO: Should this propagate fast-math-flags?
2567  return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2568 }
2569 
2571  SelectionDAG &DAG) const {
2572  assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2573  "operation should be legal");
2574 
2575  // TODO: Factor out code common with LowerSINT_TO_FP.
2576 
2577  EVT DestVT = Op.getValueType();
2578  if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2579  SDLoc DL(Op);
2580  SDValue Src = Op.getOperand(0);
2581 
2582  SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2583  SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2584  SDValue FPRound =
2585  DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2586 
2587  return FPRound;
2588  }
2589 
2590  if (DestVT == MVT::f32)
2591  return LowerINT_TO_FP32(Op, DAG, false);
2592 
2593  assert(DestVT == MVT::f64);
2594  return LowerINT_TO_FP64(Op, DAG, false);
2595 }
2596 
2598  SelectionDAG &DAG) const {
2599  assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2600  "operation should be legal");
2601 
2602  // TODO: Factor out code common with LowerUINT_TO_FP.
2603 
2604  EVT DestVT = Op.getValueType();
2605  if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2606  SDLoc DL(Op);
2607  SDValue Src = Op.getOperand(0);
2608 
2609  SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2610  SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2611  SDValue FPRound =
2612  DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2613 
2614  return FPRound;
2615  }
2616 
2617  if (DestVT == MVT::f32)
2618  return LowerINT_TO_FP32(Op, DAG, true);
2619 
2620  assert(DestVT == MVT::f64);
2621  return LowerINT_TO_FP64(Op, DAG, true);
2622 }
2623 
2625  bool Signed) const {
2626  SDLoc SL(Op);
2627 
2628  SDValue Src = Op.getOperand(0);
2629 
2630  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2631 
2632  SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2633  MVT::f64);
2634  SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2635  MVT::f64);
2636  // TODO: Should this propagate fast-math-flags?
2637  SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2638 
2639  SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2640 
2641 
2642  SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2643 
2644  SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2645  MVT::i32, FloorMul);
2646  SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2647 
2648  SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2649 
2650  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2651 }
2652 
2654  SDLoc DL(Op);
2655  SDValue N0 = Op.getOperand(0);
2656 
2657  // Convert to target node to get known bits
2658  if (N0.getValueType() == MVT::f32)
2659  return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2660 
2662  // There is a generic expand for FP_TO_FP16 with unsafe fast math.
2663  return SDValue();
2664  }
2665 
2667 
2668  // f64 -> f16 conversion using round-to-nearest-even rounding mode.
2669  const unsigned ExpMask = 0x7ff;
2670  const unsigned ExpBiasf64 = 1023;
2671  const unsigned ExpBiasf16 = 15;
2672  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2673  SDValue One = DAG.getConstant(1, DL, MVT::i32);
2674  SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2675  SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2676  DAG.getConstant(32, DL, MVT::i64));
2677  UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32);
2678  U = DAG.getZExtOrTrunc(U, DL, MVT::i32);
2679  SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2680  DAG.getConstant(20, DL, MVT::i64));
2681  E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2682  DAG.getConstant(ExpMask, DL, MVT::i32));
2683  // Subtract the fp64 exponent bias (1023) to get the real exponent and
2684  // add the f16 bias (15) to get the biased exponent for the f16 format.
2685  E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
2686  DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
2687 
2688  SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2689  DAG.getConstant(8, DL, MVT::i32));
2690  M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2691  DAG.getConstant(0xffe, DL, MVT::i32));
2692 
2693  SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2694  DAG.getConstant(0x1ff, DL, MVT::i32));
2695  MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2696 
2697  SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
2698  M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2699 
2700  // (M != 0 ? 0x0200 : 0) | 0x7c00;
2701  SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2702  DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32),
2703  Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32));
2704 
2705  // N = M | (E << 12);
2706  SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2707  DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2708  DAG.getConstant(12, DL, MVT::i32)));
2709 
2710  // B = clamp(1-E, 0, 13);
2711  SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
2712  One, E);
2713  SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
2714  B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
2715  DAG.getConstant(13, DL, MVT::i32));
2716 
2717  SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2718  DAG.getConstant(0x1000, DL, MVT::i32));
2719 
2720  SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2721  SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2722  SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE);
2723  D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2724 
2725  SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
2726  SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2727  DAG.getConstant(0x7, DL, MVT::i32));
2728  V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2729  DAG.getConstant(2, DL, MVT::i32));
2730  SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2731  One, Zero, ISD::SETEQ);
2732  SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32),
2733  One, Zero, ISD::SETGT);
2734  V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2735  V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);
2736 
2737  V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32),
2738  DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
2739  V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32),
2740  I, V, ISD::SETEQ);
2741 
2742  // Extract the sign bit.
2743  SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2744  DAG.getConstant(16, DL, MVT::i32));
2745  Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
2746  DAG.getConstant(0x8000, DL, MVT::i32));
2747 
2748  V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
2749  return DAG.getZExtOrTrunc(V, DL, Op.getValueType());
2750 }
2751 
2753  SelectionDAG &DAG) const {
2754  SDValue Src = Op.getOperand(0);
2755 
2756  // TODO: Factor out code common with LowerFP_TO_UINT.
2757 
2758  EVT SrcVT = Src.getValueType();
2759  if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2760  SDLoc DL(Op);
2761 
2762  SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2763  SDValue FpToInt32 =
2764  DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2765 
2766  return FpToInt32;
2767  }
2768 
2769  if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2770  return LowerFP64_TO_INT(Op, DAG, true);
2771 
2772  return SDValue();
2773 }
2774 
2776  SelectionDAG &DAG) const {
2777  SDValue Src = Op.getOperand(0);
2778 
2779  // TODO: Factor out code common with LowerFP_TO_SINT.
2780 
2781  EVT SrcVT = Src.getValueType();
2782  if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
2783  SDLoc DL(Op);
2784 
2785  SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2786  SDValue FpToInt32 =
2787  DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2788 
2789  return FpToInt32;
2790  }
2791 
2792  if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2793  return LowerFP64_TO_INT(Op, DAG, false);
2794 
2795  return SDValue();
2796 }
2797 
2799  SelectionDAG &DAG) const {
2800  EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2801  MVT VT = Op.getSimpleValueType();
2802  MVT ScalarVT = VT.getScalarType();
2803 
2804  assert(VT.isVector());
2805 
2806  SDValue Src = Op.getOperand(0);
2807  SDLoc DL(Op);
2808 
2809  // TODO: Don't scalarize on Evergreen?
2810  unsigned NElts = VT.getVectorNumElements();
2812  DAG.ExtractVectorElements(Src, Args, 0, NElts);
2813 
2814  SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2815  for (unsigned I = 0; I < NElts; ++I)
2816  Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2817 
2818  return DAG.getBuildVector(VT, DL, Args);
2819 }
2820 
2821 //===----------------------------------------------------------------------===//
2822 // Custom DAG optimizations
2823 //===----------------------------------------------------------------------===//
2824 
2825 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2826  return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2827 }
2828 
2829 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2830  EVT VT = Op.getValueType();
2831  return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2832  // as unsigned 24-bit values.
2834 }
2835 
2836 static SDValue simplifyI24(SDNode *Node24,
2838  SelectionDAG &DAG = DCI.DAG;
2839  SDValue LHS = Node24->getOperand(0);
2840  SDValue RHS = Node24->getOperand(1);
2841 
2842  APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24);
2843 
2844  // First try to simplify using GetDemandedBits which allows the operands to
2845  // have other uses, but will only perform simplifications that involve
2846  // bypassing some nodes for this user.
2847  SDValue DemandedLHS = DAG.GetDemandedBits(LHS, Demanded);
2848  SDValue DemandedRHS = DAG.GetDemandedBits(RHS, Demanded);
2849  if (DemandedLHS || DemandedRHS)
2850  return DAG.getNode(Node24->getOpcode(), SDLoc(Node24), Node24->getVTList(),
2851  DemandedLHS ? DemandedLHS : LHS,
2852  DemandedRHS ? DemandedRHS : RHS);
2853 
2854  // Now try SimplifyDemandedBits which can simplify the nodes used by our
2855  // operands if this node is the only user.
2856  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2857  if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI))
2858  return SDValue(Node24, 0);
2859  if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI))
2860  return SDValue(Node24, 0);
2861 
2862  return SDValue();
2863 }
2864 
2865 template <typename IntTy>
2867  uint32_t Width, const SDLoc &DL) {
2868  if (Width + Offset < 32) {
2869  uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2870  IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2871  return DAG.getConstant(Result, DL, MVT::i32);
2872  }
2873 
2874  return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2875 }
2876 
2877 static bool hasVolatileUser(SDNode *Val) {
2878  for (SDNode *U : Val->uses()) {
2879  if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2880  if (M->isVolatile())
2881  return true;
2882  }
2883  }
2884 
2885  return false;
2886 }
2887 
2889  // i32 vectors are the canonical memory type.
2890  if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT))
2891  return false;
2892 
2893  if (!VT.isByteSized())
2894  return false;
2895 
2896  unsigned Size = VT.getStoreSize();
2897 
2898  if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector())
2899  return false;
2900 
2901  if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2902  return false;
2903 
2904  return true;
2905 }
2906 
2907 // Find a load or store from corresponding pattern root.
2908 // Roots may be build_vector, bitconvert or their combinations.
2911  if (MemSDNode *MN = dyn_cast<MemSDNode>(N))
2912  return MN;
2913  assert(isa<BuildVectorSDNode>(N));
2914  for (SDValue V : N->op_values())
2915  if (MemSDNode *MN =
2916  dyn_cast<MemSDNode>(AMDGPUTargetLowering::stripBitcast(V)))
2917  return MN;
2918  llvm_unreachable("cannot find MemSDNode in the pattern!");
2919 }
2920 
2922  SelectionDAG &DAG,
2923  SDNode *N,
2924  SDValue Addr,
2925  SDValue &VAddr,
2926  SDValue &Offset,
2927  SDValue &SLC) const {
2928  const GCNSubtarget &ST =
2930  int64_t OffsetVal = 0;
2931 
2932  if (ST.hasFlatInstOffsets() &&
2933  (!ST.hasFlatSegmentOffsetBug() ||
2935  DAG.isBaseWithConstantOffset(Addr)) {
2936  SDValue N0 = Addr.getOperand(0);
2937  SDValue N1 = Addr.getOperand(1);
2938  int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
2939 
2940  const SIInstrInfo *TII = ST.getInstrInfo();
2941  if (TII->isLegalFLATOffset(COffsetVal, findMemSDNode(N)->getAddressSpace(),
2942  IsSigned)) {
2943  Addr = N0;
2944  OffsetVal = COffsetVal;
2945  }
2946  }
2947 
2948  VAddr = Addr;
2949  Offset = DAG.getTargetConstant(OffsetVal, SDLoc(), MVT::i16);
2950  SLC = DAG.getTargetConstant(0, SDLoc(), MVT::i1);
2951 
2952  return true;
2953 }
2954 
2955 // Replace load of an illegal type with a store of a bitcast to a friendlier
2956 // type.
2958  DAGCombinerInfo &DCI) const {
2959  if (!DCI.isBeforeLegalize())
2960  return SDValue();
2961 
2962  LoadSDNode *LN = cast<LoadSDNode>(N);
2963  if (LN->isVolatile() || !ISD::isNormalLoad(LN) || hasVolatileUser(LN))
2964  return SDValue();
2965 
2966  SDLoc SL(N);
2967  SelectionDAG &DAG = DCI.DAG;
2968  EVT VT = LN->getMemoryVT();
2969 
2970  unsigned Size = VT.getStoreSize();
2971  unsigned Align = LN->getAlignment();
2972  if (Align < Size && isTypeLegal(VT)) {
2973  bool IsFast;
2974  unsigned AS = LN->getAddressSpace();
2975 
2976  // Expand unaligned loads earlier than legalization. Due to visitation order
2977  // problems during legalization, the emitted instructions to pack and unpack
2978  // the bytes again are not eliminated in the case of an unaligned copy.
2980  VT, AS, Align, LN->getMemOperand()->getFlags(), &IsFast)) {
2981  if (VT.isVector())
2982  return scalarizeVectorLoad(LN, DAG);
2983 
2984  SDValue Ops[2];
2985  std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
2986  return DAG.getMergeValues(Ops, SDLoc(N));
2987  }
2988 
2989  if (!IsFast)
2990  return SDValue();
2991  }
2992 
2993  if (!shouldCombineMemoryType(VT))
2994  return SDValue();
2995 
2996  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2997 
2998  SDValue NewLoad
2999  = DAG.getLoad(NewVT, SL, LN->getChain(),
3000  LN->getBasePtr(), LN->getMemOperand());
3001 
3002  SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
3003  DCI.CombineTo(N, BC, NewLoad.getValue(1));
3004  return SDValue(N, 0);
3005 }
3006 
3007 // Replace store of an illegal type with a store of a bitcast to a friendlier
3008 // type.
3010  DAGCombinerInfo &DCI) const {
3011  if (!DCI.isBeforeLegalize())
3012  return SDValue();
3013 
3014  StoreSDNode *SN = cast<StoreSDNode>(N);
3015  if (SN->isVolatile() || !ISD::isNormalStore(SN))
3016  return SDValue();
3017 
3018  EVT VT = SN->getMemoryVT();
3019  unsigned Size = VT.getStoreSize();
3020 
3021  SDLoc SL(N);
3022  SelectionDAG &DAG = DCI.DAG;
3023  unsigned Align = SN->getAlignment();
3024  if (Align < Size && isTypeLegal(VT)) {
3025  bool IsFast;
3026  unsigned AS = SN->getAddressSpace();
3027 
3028  // Expand unaligned stores earlier than legalization. Due to visitation
3029  // order problems during legalization, the emitted instructions to pack and
3030  // unpack the bytes again are not eliminated in the case of an unaligned
3031  // copy.
3033  VT, AS, Align, SN->getMemOperand()->getFlags(), &IsFast)) {
3034  if (VT.isVector())
3035  return scalarizeVectorStore(SN, DAG);
3036 
3037  return expandUnalignedStore(SN, DAG);
3038  }
3039 
3040  if (!IsFast)
3041  return SDValue();
3042  }
3043 
3044  if (!shouldCombineMemoryType(VT))
3045  return SDValue();
3046 
3047  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
3048  SDValue Val = SN->getValue();
3049 
3050  //DCI.AddToWorklist(Val.getNode());
3051 
3052  bool OtherUses = !Val.hasOneUse();
3053  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
3054  if (OtherUses) {
3055  SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
3056  DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
3057  }
3058 
3059  return DAG.getStore(SN->getChain(), SL, CastVal,
3060  SN->getBasePtr(), SN->getMemOperand());
3061 }
3062 
3063 // FIXME: This should go in generic DAG combiner with an isTruncateFree check,
3064 // but isTruncateFree is inaccurate for i16 now because of SALU vs. VALU
3065 // issues.
3067  DAGCombinerInfo &DCI) const {
3068  SelectionDAG &DAG = DCI.DAG;
3069  SDValue N0 = N->getOperand(0);
3070 
3071  // (vt2 (assertzext (truncate vt0:x), vt1)) ->
3072  // (vt2 (truncate (assertzext vt0:x, vt1)))
3073  if (N0.getOpcode() == ISD::TRUNCATE) {
3074  SDValue N1 = N->getOperand(1);
3075  EVT ExtVT = cast<VTSDNode>(N1)->getVT();
3076  SDLoc SL(N);
3077 
3078  SDValue Src = N0.getOperand(0);
3079  EVT SrcVT = Src.getValueType();
3080  if (SrcVT.bitsGE(ExtVT)) {
3081  SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
3082  return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg);
3083  }
3084  }
3085 
3086  return SDValue();
3087 }
3088 /// Split the 64-bit value \p LHS into two 32-bit components, and perform the
3089 /// binary operation \p Opc to it with the corresponding constant operands.
3091  DAGCombinerInfo &DCI, const SDLoc &SL,
3092  unsigned Opc, SDValue LHS,
3093  uint32_t ValLo, uint32_t ValHi) const {
3094  SelectionDAG &DAG = DCI.DAG;
3095  SDValue Lo, Hi;
3096  std::tie(Lo, Hi) = split64BitValue(LHS, DAG);
3097 
3098  SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32);
3099  SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32);
3100 
3101  SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);
3102  SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);
3103 
3104  // Re-visit the ands. It's possible we eliminated one of them and it could
3105  // simplify the vector.
3106  DCI.AddToWorklist(Lo.getNode());
3107  DCI.AddToWorklist(Hi.getNode());
3108 
3109  SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
3110  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3111 }
3112 
3114  DAGCombinerInfo &DCI) const {
3115  EVT VT = N->getValueType(0);
3116 
3118  if (!RHS)
3119  return SDValue();
3120 
3121  SDValue LHS = N->getOperand(0);
3122  unsigned RHSVal = RHS->getZExtValue();
3123  if (!RHSVal)
3124  return LHS;
3125 
3126  SDLoc SL(N);
3127  SelectionDAG &DAG = DCI.DAG;
3128 
3129  switch (LHS->getOpcode()) {
3130  default:
3131  break;
3132  case ISD::ZERO_EXTEND:
3133  case ISD::SIGN_EXTEND:
3134  case ISD::ANY_EXTEND: {
3135  SDValue X = LHS->getOperand(0);
3136 
3137  if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 &&
3139  // Prefer build_vector as the canonical form if packed types are legal.
3140  // (shl ([asz]ext i16:x), 16 -> build_vector 0, x
3141  SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
3142  { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
3143  return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
3144  }
3145 
3146  // shl (ext x) => zext (shl x), if shift does not overflow int
3147  if (VT != MVT::i64)
3148  break;
3149  KnownBits Known = DAG.computeKnownBits(X);
3150  unsigned LZ = Known.countMinLeadingZeros();
3151  if (LZ < RHSVal)
3152  break;
3153  EVT XVT = X.getValueType();
3154  SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
3155  return DAG.getZExtOrTrunc(Shl, SL, VT);
3156  }
3157  }
3158 
3159  if (VT != MVT::i64)
3160  return SDValue();
3161 
3162  // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
3163 
3164  // On some subtargets, 64-bit shift is a quarter rate instruction. In the
3165  // common case, splitting this into a move and a 32-bit shift is faster and
3166  // the same code size.
3167  if (RHSVal < 32)
3168  return SDValue();
3169 
3170  SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
3171 
3172  SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
3173  SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
3174 
3175  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3176 
3177  SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
3178  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3179 }
3180 
3182  DAGCombinerInfo &DCI) const {
3183  if (N->getValueType(0) != MVT::i64)
3184  return SDValue();
3185 
3186  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3187  if (!RHS)
3188  return SDValue();
3189 
3190  SelectionDAG &DAG = DCI.DAG;
3191  SDLoc SL(N);
3192  unsigned RHSVal = RHS->getZExtValue();
3193 
3194  // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
3195  if (RHSVal == 32) {
3196  SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3197  SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3198  DAG.getConstant(31, SL, MVT::i32));
3199 
3200  SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
3201  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3202  }
3203 
3204  // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
3205  if (RHSVal == 63) {
3206  SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3207  SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3208  DAG.getConstant(31, SL, MVT::i32));
3209  SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
3210  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3211  }
3212 
3213  return SDValue();
3214 }
3215 
3217  DAGCombinerInfo &DCI) const {
3218  auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3219  if (!RHS)
3220  return SDValue();
3221 
3222  EVT VT = N->getValueType(0);
3223  SDValue LHS = N->getOperand(0);
3224  unsigned ShiftAmt = RHS->getZExtValue();
3225  SelectionDAG &DAG = DCI.DAG;
3226  SDLoc SL(N);
3227 
3228  // fold (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1)
3229  // this improves the ability to match BFE patterns in isel.
3230  if (LHS.getOpcode() == ISD::AND) {
3231  if (auto *Mask = dyn_cast<ConstantSDNode>(LHS.getOperand(1))) {
3232  if (Mask->getAPIntValue().isShiftedMask() &&
3233  Mask->getAPIntValue().countTrailingZeros() == ShiftAmt) {
3234  return DAG.getNode(
3235  ISD::AND, SL, VT,
3236  DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)),
3237  DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1)));
3238  }
3239  }
3240  }
3241 
3242  if (VT != MVT::i64)
3243  return SDValue();
3244 
3245  if (ShiftAmt < 32)
3246  return SDValue();
3247 
3248  // srl i64:x, C for C >= 32
3249  // =>
3250  // build_pair (srl hi_32(x), C - 32), 0
3251  SDValue One = DAG.getConstant(1, SL, MVT::i32);
3252  SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3253 
3254  SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS);
3255  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One);
3256 
3257  SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
3258  SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
3259 
3260  SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
3261 
3262  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
3263 }
3264 
3266  SDNode *N, DAGCombinerInfo &DCI) const {
3267  SDLoc SL(N);
3268  SelectionDAG &DAG = DCI.DAG;
3269  EVT VT = N->getValueType(0);
3270  SDValue Src = N->getOperand(0);
3271 
3272  // vt1 (truncate (bitcast (build_vector vt0:x, ...))) -> vt1 (bitcast vt0:x)
3273  if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) {
3274  SDValue Vec = Src.getOperand(0);
3275  if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3276  SDValue Elt0 = Vec.getOperand(0);
3277  EVT EltVT = Elt0.getValueType();
3278  if (VT.getSizeInBits() <= EltVT.getSizeInBits()) {
3279  if (EltVT.isFloatingPoint()) {
3280  Elt0 = DAG.getNode(ISD::BITCAST, SL,
3281  EltVT.changeTypeToInteger(), Elt0);
3282  }
3283 
3284  return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0);
3285  }
3286  }
3287  }
3288 
3289  // Equivalent of above for accessing the high element of a vector as an
3290  // integer operation.
3291  // trunc (srl (bitcast (build_vector x, y))), 16 -> trunc (bitcast y)
3292  if (Src.getOpcode() == ISD::SRL && !VT.isVector()) {
3293  if (auto K = isConstOrConstSplat(Src.getOperand(1))) {
3294  if (2 * K->getZExtValue() == Src.getValueType().getScalarSizeInBits()) {
3295  SDValue BV = stripBitcast(Src.getOperand(0));
3296  if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3297  BV.getValueType().getVectorNumElements() == 2) {
3298  SDValue SrcElt = BV.getOperand(1);
3299  EVT SrcEltVT = SrcElt.getValueType();
3300  if (SrcEltVT.isFloatingPoint()) {
3301  SrcElt = DAG.getNode(ISD::BITCAST, SL,
3302  SrcEltVT.changeTypeToInteger(), SrcElt);
3303  }
3304 
3305  return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt);
3306  }
3307  }
3308  }
3309  }
3310 
3311  // Partially shrink 64-bit shifts to 32-bit if reduced to 16-bit.
3312  //
3313  // i16 (trunc (srl i64:x, K)), K <= 16 ->
3314  // i16 (trunc (srl (i32 (trunc x), K)))
3315  if (VT.getScalarSizeInBits() < 32) {
3316  EVT SrcVT = Src.getValueType();
3317  if (SrcVT.getScalarSizeInBits() > 32 &&
3318  (Src.getOpcode() == ISD::SRL ||
3319  Src.getOpcode() == ISD::SRA ||
3320  Src.getOpcode() == ISD::SHL)) {
3321  SDValue Amt = Src.getOperand(1);
3322  KnownBits Known = DAG.computeKnownBits(Amt);
3323  unsigned Size = VT.getScalarSizeInBits();
3324  if ((Known.isConstant() && Known.getConstant().ule(Size)) ||
3325  (Known.getBitWidth() - Known.countMinLeadingZeros() <= Log2_32(Size))) {
3326  EVT MidVT = VT.isVector() ?
3329 
3330  EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout());
3331  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,
3332  Src.getOperand(0));
3333  DCI.AddToWorklist(Trunc.getNode());
3334 
3335  if (Amt.getValueType() != NewShiftVT) {
3336  Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT);
3337  DCI.AddToWorklist(Amt.getNode());
3338  }
3339 
3340  SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
3341  Trunc, Amt);
3342  return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift);
3343  }
3344  }
3345  }
3346 
3347  return SDValue();
3348 }
3349 
3350 // We need to specifically handle i64 mul here to avoid unnecessary conversion
3351 // instructions. If we only match on the legalized i64 mul expansion,
3352 // SimplifyDemandedBits will be unable to remove them because there will be
3353 // multiple uses due to the separate mul + mulh[su].
3354 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL,
3355  SDValue N0, SDValue N1, unsigned Size, bool Signed) {
3356  if (Size <= 32) {
3357  unsigned MulOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3358  return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
3359  }
3360 
3361  // Because we want to eliminate extension instructions before the
3362  // operation, we need to create a single user here (i.e. not the separate
3363  // mul_lo + mul_hi) so that SimplifyDemandedBits will deal with it.
3364 
3365  unsigned MulOpc = Signed ? AMDGPUISD::MUL_LOHI_I24 : AMDGPUISD::MUL_LOHI_U24;
3366 
3367  SDValue Mul = DAG.getNode(MulOpc, SL,
3368  DAG.getVTList(MVT::i32, MVT::i32), N0, N1);
3369 
3370  return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,
3371  Mul.getValue(0), Mul.getValue(1));
3372 }
3373 
3375  DAGCombinerInfo &DCI) const {
3376  EVT VT = N->getValueType(0);
3377 
3378  unsigned Size = VT.getSizeInBits();
3379  if (VT.isVector() || Size > 64)
3380  return SDValue();
3381 
3382  // There are i16 integer mul/mad.
3383  if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
3384  return SDValue();
3385 
3386  SelectionDAG &DAG = DCI.DAG;
3387  SDLoc DL(N);
3388 
3389  SDValue N0 = N->getOperand(0);
3390  SDValue N1 = N->getOperand(1);
3391 
3392  // SimplifyDemandedBits has the annoying habit of turning useful zero_extends
3393  // in the source into any_extends if the result of the mul is truncated. Since
3394  // we can assume the high bits are whatever we want, use the underlying value
3395  // to avoid the unknown high bits from interfering.
3396  if (N0.getOpcode() == ISD::ANY_EXTEND)
3397  N0 = N0.getOperand(0);
3398 
3399  if (N1.getOpcode() == ISD::ANY_EXTEND)
3400  N1 = N1.getOperand(0);
3401 
3402  SDValue Mul;
3403 
3404  if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
3405  N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3406  N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3407  Mul = getMul24(DAG, DL, N0, N1, Size, false);
3408  } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
3409  N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3410  N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3411  Mul = getMul24(DAG, DL, N0, N1, Size, true);
3412  } else {
3413  return SDValue();
3414  }
3415 
3416  // We need to use sext even for MUL_U24, because MUL_U24 is used
3417  // for signed multiply of 8 and 16-bit types.
3418  return DAG.getSExtOrTrunc(Mul, DL, VT);
3419 }
3420 
3422  DAGCombinerInfo &DCI) const {
3423  EVT VT = N->getValueType(0);
3424 
3425  if (!Subtarget->hasMulI24() || VT.isVector())
3426  return SDValue();
3427 
3428  SelectionDAG &DAG = DCI.DAG;
3429  SDLoc DL(N);
3430 
3431  SDValue N0 = N->getOperand(0);
3432  SDValue N1 = N->getOperand(1);
3433 
3434  if (!isI24(N0, DAG) || !isI24(N1, DAG))
3435  return SDValue();
3436 
3437  N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3438  N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3439 
3440  SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
3441  DCI.AddToWorklist(Mulhi.getNode());
3442  return DAG.getSExtOrTrunc(Mulhi, DL, VT);
3443 }
3444 
3446  DAGCombinerInfo &DCI) const {
3447  EVT VT = N->getValueType(0);
3448 
3449  if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32)
3450  return SDValue();
3451 
3452  SelectionDAG &DAG = DCI.DAG;
3453  SDLoc DL(N);
3454 
3455  SDValue N0 = N->getOperand(0);
3456  SDValue N1 = N->getOperand(1);
3457 
3458  if (!isU24(N0, DAG) || !isU24(N1, DAG))
3459  return SDValue();
3460 
3461  N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3462  N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3463 
3464  SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
3465  DCI.AddToWorklist(Mulhi.getNode());
3466  return DAG.getZExtOrTrunc(Mulhi, DL, VT);
3467 }
3468 
3470  SDNode *N, DAGCombinerInfo &DCI) const {
3471  SelectionDAG &DAG = DCI.DAG;
3472 
3473  // Simplify demanded bits before splitting into multiple users.
3474  if (SDValue V = simplifyI24(N, DCI))
3475  return V;
3476 
3477  SDValue N0 = N->getOperand(0);
3478  SDValue N1 = N->getOperand(1);
3479 
3480  bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
3481 
3482  unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
3483  unsigned MulHiOpc = Signed ? AMDGPUISD::MULHI_I24 : AMDGPUISD::MULHI_U24;
3484 
3485  SDLoc SL(N);
3486 
3487  SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
3488  SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
3489  return DAG.getMergeValues({ MulLo, MulHi }, SL);
3490 }
3491 
3492 static bool isNegativeOne(SDValue Val) {
3493  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
3494  return C->isAllOnesValue();
3495  return false;
3496 }
3497 
3498 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3499  SDValue Op,
3500  const SDLoc &DL,
3501  unsigned Opc) const {
3502  EVT VT = Op.getValueType();
3503  EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT);
3504  if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() &&
3505  LegalVT != MVT::i16))
3506  return SDValue();
3507 
3508  if (VT != MVT::i32)
3509  Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
3510 
3511  SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op);
3512  if (VT != MVT::i32)
3513  FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX);
3514 
3515  return FFBX;
3516 }
3517 
3518 // The native instructions return -1 on 0 input. Optimize out a select that
3519 // produces -1 on 0.
3520 //
3521 // TODO: If zero is not undef, we could also do this if the output is compared
3522 // against the bitwidth.
3523 //
3524 // TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
3526  SDValue LHS, SDValue RHS,
3527  DAGCombinerInfo &DCI) const {
3528  ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3529  if (!CmpRhs || !CmpRhs->isNullValue())
3530  return SDValue();
3531 
3532  SelectionDAG &DAG = DCI.DAG;
3533  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
3534  SDValue CmpLHS = Cond.getOperand(0);
3535 
3536  unsigned Opc = isCttzOpc(RHS.getOpcode()) ? AMDGPUISD::FFBL_B32 :
3538 
3539  // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
3540  // select (setcc x, 0, eq), -1, (cttz_zero_undef x) -> ffbl_u32 x
3541  if (CCOpcode == ISD::SETEQ &&
3542  (isCtlzOpc(RHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3543  RHS.getOperand(0) == CmpLHS &&
3544  isNegativeOne(LHS)) {
3545  return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3546  }
3547 
3548  // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
3549  // select (setcc x, 0, ne), (cttz_zero_undef x), -1 -> ffbl_u32 x
3550  if (CCOpcode == ISD::SETNE &&
3551  (isCtlzOpc(LHS.getOpcode()) || isCttzOpc(RHS.getOpcode())) &&
3552  LHS.getOperand(0) == CmpLHS &&
3553  isNegativeOne(RHS)) {
3554  return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3555  }
3556 
3557  return SDValue();
3558 }
3559 
3561  unsigned Op,
3562  const SDLoc &SL,
3563  SDValue Cond,
3564  SDValue N1,
3565  SDValue N2) {
3566  SelectionDAG &DAG = DCI.DAG;
3567  EVT VT = N1.getValueType();
3568 
3569  SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
3570  N1.getOperand(0), N2.getOperand(0));
3571  DCI.AddToWorklist(NewSelect.getNode());
3572  return DAG.getNode(Op, SL, VT, NewSelect);
3573 }
3574 
3575 // Pull a free FP operation out of a select so it may fold into uses.
3576 //
3577 // select c, (fneg x), (fneg y) -> fneg (select c, x, y)
3578 // select c, (fneg x), k -> fneg (select c, x, (fneg k))
3579 //
3580 // select c, (fabs x), (fabs y) -> fabs (select c, x, y)
3581 // select c, (fabs x), +k -> fabs (select c, x, k)
3583  SDValue N) {
3584  SelectionDAG &DAG = DCI.DAG;
3585  SDValue Cond = N.getOperand(0);
3586  SDValue LHS = N.getOperand(1);
3587  SDValue RHS = N.getOperand(2);
3588 
3589  EVT VT = N.getValueType();
3590  if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3591  (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) {
3592  return distributeOpThroughSelect(DCI, LHS.getOpcode(),
3593  SDLoc(N), Cond, LHS, RHS);
3594  }
3595 
3596  bool Inv = false;
3597  if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3598  std::swap(LHS, RHS);
3599  Inv = true;
3600  }
3601 
3602  // TODO: Support vector constants.
3604  if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3605  SDLoc SL(N);
3606  // If one side is an fneg/fabs and the other is a constant, we can push the
3607  // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
3608  SDValue NewLHS = LHS.getOperand(0);
3609  SDValue NewRHS = RHS;
3610 
3611  // Careful: if the neg can be folded up, don't try to pull it back down.
3612  bool ShouldFoldNeg = true;
3613 
3614  if (NewLHS.hasOneUse()) {
3615  unsigned Opc = NewLHS.getOpcode();
3616  if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc))
3617  ShouldFoldNeg = false;
3618  if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3619  ShouldFoldNeg = false;
3620  }
3621 
3622  if (ShouldFoldNeg) {
3623  if (LHS.getOpcode() == ISD::FNEG)
3624  NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3625  else if (CRHS->isNegative())
3626  return SDValue();
3627 
3628  if (Inv)
3629  std::swap(NewLHS, NewRHS);
3630 
3631  SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
3632  Cond, NewLHS, NewRHS);
3633  DCI.AddToWorklist(NewSelect.getNode());
3634  return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
3635  }
3636  }
3637 
3638  return SDValue();
3639 }
3640 
3641 
3643  DAGCombinerInfo &DCI) const {
3644  if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
3645  return Folded;
3646 
3647  SDValue Cond = N->getOperand(0);
3648  if (Cond.getOpcode() != ISD::SETCC)
3649  return SDValue();
3650 
3651  EVT VT = N->getValueType(0);
3652  SDValue LHS = Cond.getOperand(0);
3653  SDValue RHS = Cond.getOperand(1);
3654  SDValue CC = Cond.getOperand(2);
3655 
3656  SDValue True = N->getOperand(1);
3657  SDValue False = N->getOperand(2);
3658 
3659  if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
3660  SelectionDAG &DAG = DCI.DAG;
3661  if (DAG.isConstantValueOfAnyType(True) &&
3662  !DAG.isConstantValueOfAnyType(False)) {
3663  // Swap cmp + select pair to move constant to false input.
3664  // This will allow using VOPC cndmasks more often.
3665  // select (setcc x, y), k, x -> select (setccinv x, y), x, k
3666 
3667  SDLoc SL(N);
3668  ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3669  LHS.getValueType().isInteger());
3670 
3671  SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
3672  return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3673  }
3674 
3675  if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) {
3676  SDValue MinMax
3677  = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
3678  // Revisit this node so we can catch min3/max3/med3 patterns.
3679  //DCI.AddToWorklist(MinMax.getNode());
3680  return MinMax;
3681  }
3682  }
3683 
3684  // There's no reason to not do this if the condition has other uses.
3685  return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);
3686 }
3687 
3688 static bool isInv2Pi(const APFloat &APF) {
3689  static const APFloat KF16(APFloat::IEEEhalf(), APInt(16, 0x3118));
3690  static const APFloat KF32(APFloat::IEEEsingle(), APInt(32, 0x3e22f983));
3691  static const APFloat KF64(APFloat::IEEEdouble(), APInt(64, 0x3fc45f306dc9c882));
3692 
3693  return APF.bitwiseIsEqual(KF16) ||
3694  APF.bitwiseIsEqual(KF32) ||
3695  APF.bitwiseIsEqual(KF64);
3696 }
3697 
3698 // 0 and 1.0 / (0.5 * pi) do not have inline immmediates, so there is an
3699 // additional cost to negate them.
3701  if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N)) {
3702  if (C->isZero() && !C->isNegative())
3703  return true;
3704 
3705  if (Subtarget->hasInv2PiInlineImm() && isInv2Pi(C->getValueAPF()))
3706  return true;
3707  }
3708 
3709  return false;
3710 }
3711 
3712 static unsigned inverseMinMax(unsigned Opc) {
3713  switch (Opc) {
3714  case ISD::FMAXNUM:
3715  return ISD::FMINNUM;
3716  case ISD::FMINNUM:
3717  return ISD::FMAXNUM;
3718  case ISD::FMAXNUM_IEEE:
3719  return ISD::FMINNUM_IEEE;
3720  case ISD::FMINNUM_IEEE:
3721  return ISD::FMAXNUM_IEEE;
3723  return AMDGPUISD::FMIN_LEGACY;
3725  return AMDGPUISD::FMAX_LEGACY;
3726  default:
3727  llvm_unreachable("invalid min/max opcode");
3728  }
3729 }
3730 
3732  DAGCombinerInfo &DCI) const {
3733  SelectionDAG &DAG = DCI.DAG;
3734  SDValue N0 = N->getOperand(0);
3735  EVT VT = N->getValueType(0);
3736 
3737  unsigned Opc = N0.getOpcode();
3738 
3739  // If the input has multiple uses and we can either fold the negate down, or
3740  // the other uses cannot, give up. This both prevents unprofitable
3741  // transformations and infinite loops: we won't repeatedly try to fold around
3742  // a negate that has no 'good' form.
3743  if (N0.hasOneUse()) {
3744  // This may be able to fold into the source, but at a code size cost. Don't
3745  // fold if the fold into the user is free.
3746  if (allUsesHaveSourceMods(N, 0))
3747  return SDValue();
3748  } else {
3749  if (fnegFoldsIntoOp(Opc) &&
3751  return SDValue();
3752  }
3753 
3754  SDLoc SL(N);
3755  switch (Opc) {
3756  case ISD::FADD: {
3757  if (!mayIgnoreSignedZero(N0))
3758  return SDValue();
3759 
3760  // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
3761  SDValue LHS = N0.getOperand(0);
3762  SDValue RHS = N0.getOperand(1);
3763 
3764  if (LHS.getOpcode() != ISD::FNEG)
3765  LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3766  else
3767  LHS = LHS.getOperand(0);
3768 
3769  if (RHS.getOpcode() != ISD::FNEG)
3770  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3771  else
3772  RHS = RHS.getOperand(0);
3773 
3774  SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3775  if (Res.getOpcode() != ISD::FADD)
3776  return SDValue(); // Op got folded away.
3777  if (!N0.hasOneUse())
3778  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3779  return Res;
3780  }
3781  case ISD::FMUL:
3782  case AMDGPUISD::FMUL_LEGACY: {
3783  // (fneg (fmul x, y)) -> (fmul x, (fneg y))
3784  // (fneg (fmul_legacy x, y)) -> (fmul_legacy x, (fneg y))
3785  SDValue LHS = N0.getOperand(0);
3786  SDValue RHS = N0.getOperand(1);
3787 
3788  if (LHS.getOpcode() == ISD::FNEG)
3789  LHS = LHS.getOperand(0);
3790  else if (RHS.getOpcode() == ISD::FNEG)
3791  RHS = RHS.getOperand(0);
3792  else
3793  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3794 
3795  SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3796  if (Res.getOpcode() != Opc)
3797  return SDValue(); // Op got folded away.
3798  if (!N0.hasOneUse())
3799  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3800  return Res;
3801  }
3802  case ISD::FMA:
3803  case ISD::FMAD: {
3804  if (!mayIgnoreSignedZero(N0))
3805  return SDValue();
3806 
3807  // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
3808  SDValue LHS = N0.getOperand(0);
3809  SDValue MHS = N0.getOperand(1);
3810  SDValue RHS = N0.getOperand(2);
3811 
3812  if (LHS.getOpcode() == ISD::FNEG)
3813  LHS = LHS.getOperand(0);
3814  else if (MHS.getOpcode() == ISD::FNEG)
3815  MHS = MHS.getOperand(0);
3816  else
3817  MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3818 
3819  if (RHS.getOpcode() != ISD::FNEG)
3820  RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3821  else
3822  RHS = RHS.getOperand(0);
3823 
3824  SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
3825  if (Res.getOpcode() != Opc)
3826  return SDValue(); // Op got folded away.
3827  if (!N0.hasOneUse())
3828  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3829  return Res;
3830  }
3831  case ISD::FMAXNUM:
3832  case ISD::FMINNUM:
3833  case ISD::FMAXNUM_IEEE:
3834  case ISD::FMINNUM_IEEE:
3836  case AMDGPUISD::FMIN_LEGACY: {
3837  // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
3838  // fneg (fminnum x, y) -> fmaxnum (fneg x), (fneg y)
3839  // fneg (fmax_legacy x, y) -> fmin_legacy (fneg x), (fneg y)
3840  // fneg (fmin_legacy x, y) -> fmax_legacy (fneg x), (fneg y)
3841 
3842  SDValue LHS = N0.getOperand(0);
3843  SDValue RHS = N0.getOperand(1);
3844 
3845  // 0 doesn't have a negated inline immediate.
3846  // TODO: This constant check should be generalized to other operations.
3847  if (isConstantCostlierToNegate(RHS))
3848  return SDValue();
3849 
3850  SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3851  SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3852  unsigned Opposite = inverseMinMax(Opc);
3853 
3854  SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3855  if (Res.getOpcode() != Opposite)
3856  return SDValue(); // Op got folded away.
3857  if (!N0.hasOneUse())
3858  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3859  return Res;
3860  }
3861  case AMDGPUISD::FMED3: {
3862  SDValue Ops[3];
3863  for (unsigned I = 0; I < 3; ++I)
3864  Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3865 
3866  SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3867  if (Res.getOpcode() != AMDGPUISD::FMED3)
3868  return SDValue(); // Op got folded away.
3869  if (!N0.hasOneUse())
3870  DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3871  return Res;
3872  }
3873  case ISD::FP_EXTEND:
3874  case ISD::FTRUNC:
3875  case ISD::FRINT:
3876  case ISD::FNEARBYINT: // XXX - Should fround be handled?
3877  case ISD::FSIN:
3878  case ISD::FCANONICALIZE:
3879  case AMDGPUISD::RCP:
3880  case AMDGPUISD::RCP_LEGACY:
3881  case AMDGPUISD::RCP_IFLAG:
3882  case AMDGPUISD::SIN_HW: {
3883  SDValue CvtSrc = N0.getOperand(0);
3884  if (CvtSrc.getOpcode() == ISD::FNEG) {
3885  // (fneg (fp_extend (fneg x))) -> (fp_extend x)
3886  // (fneg (rcp (fneg x))) -> (rcp x)
3887  return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
3888  }
3889 
3890  if (!N0.hasOneUse())
3891  return SDValue();
3892 
3893  // (fneg (fp_extend x)) -> (fp_extend (fneg x))
3894  // (fneg (rcp x)) -> (rcp (fneg x))
3895  SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3896  return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3897  }
3898  case ISD::FP_ROUND: {
3899  SDValue CvtSrc = N0.getOperand(0);
3900 
3901  if (CvtSrc.getOpcode() == ISD::FNEG) {
3902  // (fneg (fp_round (fneg x))) -> (fp_round x)
3903  return DAG.getNode(ISD::FP_ROUND, SL, VT,
3904  CvtSrc.getOperand(0), N0.getOperand(1));
3905  }
3906 
3907  if (!N0.hasOneUse())
3908  return SDValue();
3909 
3910  // (fneg (fp_round x)) -> (fp_round (fneg x))
3911  SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3912  return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
3913  }
3914  case ISD::FP16_TO_FP: {
3915  // v_cvt_f32_f16 supports source modifiers on pre-VI targets without legal
3916  // f16, but legalization of f16 fneg ends up pulling it out of the source.
3917  // Put the fneg back as a legal source operation that can be matched later.
3918  SDLoc SL(N);
3919 
3920  SDValue Src = N0.getOperand(0);
3921  EVT SrcVT = Src.getValueType();
3922 
3923  // fneg (fp16_to_fp x) -> fp16_to_fp (xor x, 0x8000)
3924  SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3925  DAG.getConstant(0x8000, SL, SrcVT));
3926  return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
3927  }
3928  default:
3929  return SDValue();
3930  }
3931 }
3932 
3934  DAGCombinerInfo &DCI) const {
3935  SelectionDAG &DAG = DCI.DAG;
3936  SDValue N0 = N->getOperand(0);
3937 
3938  if (!N0.hasOneUse())
3939  return SDValue();
3940 
3941  switch (N0.getOpcode()) {
3942  case ISD::FP16_TO_FP: {
3943  assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal");
3944  SDLoc SL(N);
3945  SDValue Src = N0.getOperand(0);
3946  EVT SrcVT = Src.getValueType();
3947 
3948  // fabs (fp16_to_fp x) -> fp16_to_fp (and x, 0x7fff)
3949  SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3950  DAG.getConstant(0x7fff, SL, SrcVT));
3951  return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
3952  }
3953  default:
3954  return SDValue();
3955  }
3956 }
3957 
3959  DAGCombinerInfo &DCI) const {
3960  const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
3961  if (!CFP)
3962  return SDValue();
3963 
3964  // XXX - Should this flush denormals?
3965  const APFloat &Val = CFP->getValueAPF();
3966  APFloat One(Val.getSemantics(), "1.0");
3967  return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
3968 }
3969 
3971  DAGCombinerInfo &DCI) const {
3972  SelectionDAG &DAG = DCI.DAG;
3973  SDLoc DL(N);
3974 
3975  switch(N->getOpcode()) {
3976  default:
3977  break;
3978  case ISD::BITCAST: {
3979  EVT DestVT = N->getValueType(0);
3980 
3981  // Push casts through vector builds. This helps avoid emitting a large
3982  // number of copies when materializing floating point vector constants.
3983  //
3984  // vNt1 bitcast (vNt0 (build_vector t0:x, t0:y)) =>
3985  // vnt1 = build_vector (t1 (bitcast t0:x)), (t1 (bitcast t0:y))
3986  if (DestVT.isVector()) {
3987  SDValue Src = N->getOperand(0);
3988  if (Src.getOpcode() == ISD::BUILD_VECTOR) {
3989  EVT SrcVT = Src.getValueType();
3990  unsigned NElts = DestVT.getVectorNumElements();
3991 
3992  if (SrcVT.getVectorNumElements() == NElts) {
3993  EVT DestEltVT = DestVT.getVectorElementType();
3994 
3995  SmallVector<SDValue, 8> CastedElts;
3996  SDLoc SL(N);
3997  for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {
3998  SDValue Elt = Src.getOperand(I);
3999  CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
4000  }
4001 
4002  return DAG.getBuildVector(DestVT, SL, CastedElts);
4003  }
4004  }
4005  }
4006 
4007  if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
4008  break;
4009 
4010  // Fold bitcasts of constants.
4011  //
4012  // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
4013  // TODO: Generalize and move to DAGCombiner
4014  SDValue Src = N->getOperand(0);
4015  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
4016  if (Src.getValueType() == MVT::i64) {
4017  SDLoc SL(N);
4018  uint64_t CVal = C->getZExtValue();
4020  DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
4021  DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
4022  return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
4023  }
4024  }
4025 
4026  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
4027  const APInt &Val = C->getValueAPF().bitcastToAPInt();
4028  SDLoc SL(N);
4029  uint64_t CVal = Val.getZExtValue();
4031  DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
4032  DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
4033 
4034  return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
4035  }
4036 
4037  break;
4038  }
4039  case ISD::SHL: {
4041  break;
4042 
4043  return performShlCombine(N, DCI);
4044  }
4045  case ISD::SRL: {
4047  break;
4048 
4049  return performSrlCombine(N, DCI);
4050  }
4051  case ISD::SRA: {
4053  break;
4054 
4055  return performSraCombine(N, DCI);
4056  }
4057  case ISD::TRUNCATE:
4058  return performTruncateCombine(N, DCI);
4059  case ISD::MUL:
4060  return performMulCombine(N, DCI);
4061  case ISD::MULHS:
4062  return performMulhsCombine(N, DCI);
4063  case ISD::MULHU:
4064  return performMulhuCombine(N, DCI);
4065  case AMDGPUISD::MUL_I24:
4066  case AMDGPUISD::MUL_U24:
4067  case AMDGPUISD::MULHI_I24:
4068  case AMDGPUISD::MULHI_U24: {
4069  if (SDValue V = simplifyI24(N, DCI))
4070  return V;
4071  return SDValue();
4072  }
4075  return performMulLoHi24Combine(N, DCI);
4076  case ISD::SELECT:
4077  return performSelectCombine(N, DCI);
4078  case ISD::FNEG:
4079  return performFNegCombine(N, DCI);
4080  case ISD::FABS:
4081  return performFAbsCombine(N, DCI);
4082  case AMDGPUISD::BFE_I32:
4083  case AMDGPUISD::BFE_U32: {
4084  assert(!N->