LLVM 20.0.0git
AMDGPUISelLowering.h
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1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition of the TargetLowering class that is common
11/// to all AMD GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class AMDGPUSubtarget;
25struct ArgDescriptor;
26
28private:
29 const AMDGPUSubtarget *Subtarget;
30
31 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32 /// legalized from a smaller type VT. Need to match pre-legalized type because
33 /// the generic legalization inserts the add/sub between the select and
34 /// compare.
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36
37public:
38 /// \returns The minimum number of bits needed to store the value of \Op as an
39 /// unsigned integer. Truncating to this size and then zero-extending to the
40 /// original size will not change the value.
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
42
43 /// \returns The minimum number of bits needed to store the value of \Op as a
44 /// signed integer. Truncating to this size and then sign-extending to the
45 /// original size will not change the value.
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
47
48protected:
51 /// Split a vector store into multiple scalar stores.
52 /// \returns The resulting chain.
53
59
63
64 static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags);
65 static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src,
66 SDNodeFlags Flags);
68 SDNodeFlags Flags) const;
70 std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
71 const SDLoc SL, SDValue Op,
72 SDNodeFlags Flags) const;
73
78 bool IsLog10, SDNodeFlags Flags) const;
80
82 SDNodeFlags Flags) const;
84 SDNodeFlags Flags) const;
86
88
90
95
99
101
102protected:
103 bool shouldCombineMemoryType(EVT VT) const;
108
110 unsigned Opc, SDValue LHS,
111 uint32_t ValLo, uint32_t ValHi) const;
121 SDValue RHS, DAGCombinerInfo &DCI) const;
122
124 SDValue N) const;
126
129
135
136 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
137
139 SelectionDAG &DAG) const;
140
141 /// Return 64-bit value Op as two 32-bit integers.
142 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
143 SelectionDAG &DAG) const;
146
147 /// Split a vector type into two parts. The first part is a power of two
148 /// vector. The second part is whatever is left over, and is a scalar if it
149 /// would otherwise be a 1-vector.
150 std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
151
152 /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
153 /// scalar.
154 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
155 const EVT &LoVT, const EVT &HighVT,
156 SelectionDAG &DAG) const;
157
158 /// Split a vector load into 2 loads of half the vector.
160
161 /// Widen a suitably aligned v3 load. For all other cases, split the input
162 /// vector load.
164
165 /// Split a vector store into 2 stores of half the vector.
167
171 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
174
176 CCState &State,
177 const SmallVectorImpl<ISD::InputArg> &Ins) const;
178
179public:
181
182 bool mayIgnoreSignedZero(SDValue Op) const;
183
184 static inline SDValue stripBitcast(SDValue Val) {
185 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
186 }
187
188 static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc);
189 static bool allUsesHaveSourceMods(const SDNode *N,
190 unsigned CostThreshold = 4);
191 bool isFAbsFree(EVT VT) const override;
192 bool isFNegFree(EVT VT) const override;
193 bool isTruncateFree(EVT Src, EVT Dest) const override;
194 bool isTruncateFree(Type *Src, Type *Dest) const override;
195
196 bool isZExtFree(Type *Src, Type *Dest) const override;
197 bool isZExtFree(EVT Src, EVT Dest) const override;
198
200 bool LegalOperations, bool ForCodeSize,
202 unsigned Depth) const override;
203
204 bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override;
205
207 CombineLevel Level) const override;
208
210 ISD::NodeType ExtendKind) const override;
211
212 MVT getVectorIdxTy(const DataLayout &) const override;
213 bool isSelectSupported(SelectSupportKind) const override;
214
215 bool isFPImmLegal(const APFloat &Imm, EVT VT,
216 bool ForCodeSize) const override;
217 bool ShouldShrinkFPConstant(EVT VT) const override;
218 bool shouldReduceLoadWidth(SDNode *Load,
219 ISD::LoadExtType ExtType,
220 EVT ExtVT) const override;
221
223 const MachineMemOperand &MMO) const final;
224
225 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
226 unsigned NumElem,
227 unsigned AS) const override;
228 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
229 bool isCheapToSpeculateCttz(Type *Ty) const override;
230 bool isCheapToSpeculateCtlz(Type *Ty) const override;
231
232 bool isSDNodeAlwaysUniform(const SDNode *N) const override;
233
234 // FIXME: This hook should not exist
237 }
238
241 }
242
245 }
246
247 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
248 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
249
250 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
252 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
253 SelectionDAG &DAG) const override;
254
256 SelectionDAG &DAG,
257 MachineFrameInfo &MFI,
258 int ClobberedFI) const;
259
260 SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
262 StringRef Reason) const;
263 SDValue LowerCall(CallLoweringInfo &CLI,
264 SmallVectorImpl<SDValue> &InVals) const override;
265
267 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
268 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
271 SelectionDAG &DAG) const override;
272
274 SDValue RHS, SDValue True, SDValue False,
275 SDValue CC, DAGCombinerInfo &DCI) const;
276
278 SDValue RHS, SDValue True, SDValue False,
279 SDValue CC, DAGCombinerInfo &DCI) const;
280
281 const char* getTargetNodeName(unsigned Opcode) const override;
282
283 // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
284 // AMDGPU. Commit r319036,
285 // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
286 // turned on MergeConsecutiveStores() before Instruction Selection for all
287 // targets. Enough AMDGPU compiles go into an infinite loop (
288 // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
289 // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
290 // now.
291 bool mergeStoresAfterLegalization(EVT) const override { return false; }
292
293 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
294 return true;
295 }
297 int &RefinementSteps, bool &UseOneConstNR,
298 bool Reciprocal) const override;
300 int &RefinementSteps) const override;
301
303 SelectionDAG &DAG) const = 0;
304
305 /// Determine which of the bits specified in \p Mask are known to be
306 /// either zero or one and return them in the \p KnownZero and \p KnownOne
307 /// bitsets.
309 KnownBits &Known,
310 const APInt &DemandedElts,
311 const SelectionDAG &DAG,
312 unsigned Depth = 0) const override;
313
314 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
315 const SelectionDAG &DAG,
316 unsigned Depth = 0) const override;
317
319 Register R,
320 const APInt &DemandedElts,
322 unsigned Depth = 0) const override;
323
325 const SelectionDAG &DAG,
326 bool SNaN = false,
327 unsigned Depth = 0) const override;
328
330 Register N1) const override;
331
332 /// Helper function that adds Reg to the LiveIn list of the DAG's
333 /// MachineFunction.
334 ///
335 /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
336 /// a copy from the register.
338 const TargetRegisterClass *RC,
339 Register Reg, EVT VT,
340 const SDLoc &SL,
341 bool RawReg = false) const;
343 const TargetRegisterClass *RC,
344 Register Reg, EVT VT) const {
345 return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
346 }
347
348 // Returns the raw live in register rather than a copy from it.
350 const TargetRegisterClass *RC,
351 Register Reg, EVT VT) const {
352 return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
353 }
354
355 /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
356 /// slot rather than passed in a register.
358 EVT VT,
359 const SDLoc &SL,
360 int64_t Offset) const;
361
363 const SDLoc &SL,
364 SDValue Chain,
365 SDValue ArgVal,
366 int64_t Offset) const;
367
369 const TargetRegisterClass *RC,
370 EVT VT, const SDLoc &SL,
371 const ArgDescriptor &Arg) const;
372
378 };
379
380 /// Helper function that returns the byte offset of the given
381 /// type of implicit parameter.
383 const ImplicitParameter Param) const;
384 uint32_t getImplicitParameterOffset(const uint64_t ExplicitKernArgSize,
385 const ImplicitParameter Param) const;
386
387 MVT getFenceOperandTy(const DataLayout &DL) const override {
388 return MVT::i32;
389 }
390
392 SmallVectorImpl<Use *> &Ops) const override;
393};
394
395namespace AMDGPUISD {
396
397enum NodeType : unsigned {
398 // AMDIL ISD Opcodes
400 UMUL, // 32bit unsigned multiplication
402 // End AMDIL ISD Opcodes
403
404 // Function call.
410
411 // Masked control flow nodes.
415
416 // A uniform kernel return that terminates the wavefront.
418
419 // s_endpgm, but we may want to insert it in the middle of the block.
421
422 // "s_trap 2" equivalent on hardware that does not support it.
424
425 // Return to a shader part's epilog code.
427
428 // Return with values from a non-entry function.
430
431 // Convert a unswizzled wave uniform stack address to an address compatible
432 // with a vector offset for use in stack access.
434
437
438 /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
439 /// modifier behavior with dx10_enable.
441
442 // This is SETCC with the full mask result which is used for a compare with a
443 // result bit per item in the wavefront.
446
448
449 // FP ops with input and output chain.
452
453 // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
454 // Denormals handled on some parts.
459
476 // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
477 // treated as an illegal operation.
479
480 // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
481 // For f64, max error 2^29 ULP, handles denormals.
486
487 // log2, no denormal handling for f32.
489
490 // exp2, no denormal handling for f32.
492
499 BFE_U32, // Extract range of bits with zero extension to 32-bits.
500 BFE_I32, // Extract range of bits with sign extension to 32-bits.
501 BFI, // (src0 & src1) | (~src0 & src2)
502 BFM, // Insert a range of bits into a 32-bit word.
503 FFBH_U32, // ctlz with -1 if input is zero.
505 FFBL_B32, // cttz with -1 if input is zero.
524
525 // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
530
531 // Convert two float 32 numbers into a single register holding two packed f16
532 // with round to zero.
538
539 // Same as the standard node, except the high bits of the resulting integer
540 // are known 0.
542
543 /// This node is for VLIW targets and it is used to represent a vector
544 /// that is stored in consecutive registers with the same channel.
545 /// For example:
546 /// |X |Y|Z|W|
547 /// T0|v.x| | | |
548 /// T1|v.y| | | |
549 /// T2|v.z| | | |
550 /// T3|v.w| | | |
552 /// Pointer to the start of the shader's constant data.
557
566
616
619
620} // End namespace AMDGPUISD
621
622} // End namespace llvm
623
624#endif
unsigned const MachineRegisterInfo * MRI
#define AMDGPUSubtarget
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
block Block Frequency Analysis
static cl::opt< unsigned > CostThreshold("dfa-cost-threshold", cl::desc("Maximum cost accepted for the transformation"), cl::Hidden, cl::init(50))
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned Reg
const SmallVectorImpl< MachineOperand > & Cond
This file describes how to lower LLVM code to machine code.
Value * RHS
Value * LHS
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types.
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const
bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool shouldCombineMemoryType(EVT VT) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
bool isTruncateFree(EVT Src, EVT Dest) const override
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
TargetLowering::NegatibleCost getConstantNegateCost(const ConstantFPSDNode *C) const
SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, bool IsLog10, SDNodeFlags Flags) const
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isSDNodeAlwaysUniform(const SDNode *N) const override
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
bool isConstantCheaperToNegate(SDValue N) const
bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, Register N1) const override
static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src, SDNodeFlags Flags)
MVT getFenceOperandTy(const DataLayout &DL) const override
Return the type for operands of fence.
uint32_t getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
bool isConstantCostlierToNegate(SDValue N) const
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags) const
Emit approx-funcs appropriate lowering for exp10.
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isSelectSupported(SelectSupportKind) const override
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const
SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const
bool mayIgnoreSignedZero(SDValue Op) const
SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const
bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
Return true if it is profitable to reduce a load to a smaller type.
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
std::pair< SDValue, SDValue > splitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HighVT, SelectionDAG &DAG) const
Split a vector value into two parts of types LoVT and HiVT.
SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const
SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI, SDValue N) const
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Whether it is profitable to sink the operands of an Instruction I to the basic block of I.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...
bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override
Return true if it's profitable to narrow operations of type SrcVT to DestVT.
SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
static SDValue stripBitcast(SDValue Val)
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
std::pair< SDValue, SDValue > getScaledLogInput(SelectionDAG &DAG, const SDLoc SL, SDValue Op, SDNodeFlags Flags) const
If denormal handling is required return the scaled input to FLOG2, and the check for denormal range.
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags) const
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags)
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const
SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const
static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc)
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const
AtomicExpansionKind shouldCastAtomicRMWIInIR(AtomicRMWInst *) const override
Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Widen a suitably aligned v3 load.
bool mergeStoresAfterLegalization(EVT) const override
Allow store merging for the specified type after legalization in addition to before legalization.
std::pair< EVT, EVT > getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const
Split a vector type into two parts.
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Class for arbitrary precision integers.
Definition: APInt.h:78
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:696
CCState - This class holds information needed while lowering arguments and return values.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:174
Machine Value Type.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
A description of a memory reference used in the backend.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:226
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:570
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
An instruction for storing to memory.
Definition: Instructions.h:290
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
SelectSupportKind
Enum that describes what type of support for selects the target has.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
NegatibleCost
Enum that specifies when a float negation is beneficial.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
@ BUILD_VERTICAL_VECTOR
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
@ CONST_DATA_PTR
Pointer to the start of the shader's constant data.
@ CLAMP
CLAMP value between 0.0 and 1.0.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:953
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1480
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1492
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1583
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
CombineLevel
Definition: DAGCombine.h:15
#define N
Extended Value Type.
Definition: ValueTypes.h:35
These are IR-level optimization flags that may be propagated to SDNodes.