LLVM  14.0.0git
SIMachineFunctionInfo.h
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1 //==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 
17 #include "AMDGPUMachineFunction.h"
19 #include "SIInstrInfo.h"
20 #include "llvm/ADT/MapVector.h"
24 
25 namespace llvm {
26 
27 class MachineFrameInfo;
28 class MachineFunction;
29 class SIMachineFunctionInfo;
30 class SIRegisterInfo;
31 class TargetRegisterClass;
32 
34 public:
35  enum AMDGPUPSVKind : unsigned {
39  };
40 
41 protected:
43  : PseudoSourceValue(Kind, TII) {}
44 
45 public:
46  bool isConstant(const MachineFrameInfo *) const override {
47  // This should probably be true for most images, but we will start by being
48  // conservative.
49  return false;
50  }
51 
52  bool isAliased(const MachineFrameInfo *) const override {
53  return true;
54  }
55 
56  bool mayAlias(const MachineFrameInfo *) const override {
57  return true;
58  }
59 };
60 
62 public:
65 
66  static bool classof(const PseudoSourceValue *V) {
67  return V->kind() == PSVBuffer;
68  }
69 
70  void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
71 };
72 
74 public:
75  // TODO: Is the img rsrc useful?
78 
79  static bool classof(const PseudoSourceValue *V) {
80  return V->kind() == PSVImage;
81  }
82 
83  void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
84 };
85 
87 public:
90 
91  static bool classof(const PseudoSourceValue *V) {
92  return V->kind() == GWSResource;
93  }
94 
95  // These are inaccessible memory from IR.
96  bool isAliased(const MachineFrameInfo *) const override {
97  return false;
98  }
99 
100  // These are inaccessible memory from IR.
101  bool mayAlias(const MachineFrameInfo *) const override {
102  return false;
103  }
104 
105  void printCustom(raw_ostream &OS) const override {
106  OS << "GWSResource";
107  }
108 };
109 
110 namespace yaml {
111 
112 struct SIArgument {
114  union {
116  unsigned StackOffset;
117  };
119 
120  // Default constructor, which creates a stack argument.
122  SIArgument(const SIArgument &Other) {
123  IsRegister = Other.IsRegister;
124  if (IsRegister) {
125  ::new ((void *)std::addressof(RegisterName))
126  StringValue(Other.RegisterName);
127  } else
128  StackOffset = Other.StackOffset;
129  Mask = Other.Mask;
130  }
131  SIArgument &operator=(const SIArgument &Other) {
132  IsRegister = Other.IsRegister;
133  if (IsRegister) {
134  ::new ((void *)std::addressof(RegisterName))
135  StringValue(Other.RegisterName);
136  } else
137  StackOffset = Other.StackOffset;
138  Mask = Other.Mask;
139  return *this;
140  }
142  if (IsRegister)
143  RegisterName.~StringValue();
144  }
145 
146  // Helper to create a register or stack argument.
147  static inline SIArgument createArgument(bool IsReg) {
148  if (IsReg)
149  return SIArgument(IsReg);
150  return SIArgument();
151  }
152 
153 private:
154  // Construct a register argument.
155  SIArgument(bool) : IsRegister(true), RegisterName() {}
156 };
157 
158 template <> struct MappingTraits<SIArgument> {
159  static void mapping(IO &YamlIO, SIArgument &A) {
160  if (YamlIO.outputting()) {
161  if (A.IsRegister)
162  YamlIO.mapRequired("reg", A.RegisterName);
163  else
164  YamlIO.mapRequired("offset", A.StackOffset);
165  } else {
166  auto Keys = YamlIO.keys();
167  if (is_contained(Keys, "reg")) {
168  A = SIArgument::createArgument(true);
169  YamlIO.mapRequired("reg", A.RegisterName);
170  } else if (is_contained(Keys, "offset"))
171  YamlIO.mapRequired("offset", A.StackOffset);
172  else
173  YamlIO.setError("missing required key 'reg' or 'offset'");
174  }
175  YamlIO.mapOptional("mask", A.Mask);
176  }
177  static const bool flow = true;
178 };
179 
188 
194 
197 
201 };
202 
203 template <> struct MappingTraits<SIArgumentInfo> {
204  static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
205  YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
206  YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
207  YamlIO.mapOptional("queuePtr", AI.QueuePtr);
208  YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
209  YamlIO.mapOptional("dispatchID", AI.DispatchID);
210  YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
211  YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
212 
213  YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
214  YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
215  YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
216  YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
217  YamlIO.mapOptional("privateSegmentWaveByteOffset",
219 
220  YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
221  YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
222 
223  YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
224  YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
225  YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
226  }
227 };
228 
229 // Default to default mode for default calling convention.
230 struct SIMode {
231  bool IEEE = true;
232  bool DX10Clamp = true;
233  bool FP32InputDenormals = true;
234  bool FP32OutputDenormals = true;
237 
238  SIMode() = default;
239 
241  IEEE = Mode.IEEE;
242  DX10Clamp = Mode.DX10Clamp;
243  FP32InputDenormals = Mode.FP32InputDenormals;
244  FP32OutputDenormals = Mode.FP32OutputDenormals;
245  FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
246  FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
247  }
248 
249  bool operator ==(const SIMode Other) const {
250  return IEEE == Other.IEEE &&
251  DX10Clamp == Other.DX10Clamp &&
252  FP32InputDenormals == Other.FP32InputDenormals &&
253  FP32OutputDenormals == Other.FP32OutputDenormals &&
254  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
255  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
256  }
257 };
258 
259 template <> struct MappingTraits<SIMode> {
260  static void mapping(IO &YamlIO, SIMode &Mode) {
261  YamlIO.mapOptional("ieee", Mode.IEEE, true);
262  YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
263  YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
264  YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
265  YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
266  YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
267  }
268 };
269 
272  unsigned MaxKernArgAlign = 0;
273  unsigned LDSSize = 0;
275  bool IsEntryFunction = false;
276  bool NoSignedZerosFPMath = false;
277  bool MemoryBound = false;
278  bool WaveLimiter = false;
279  bool HasSpilledSGPRs = false;
280  bool HasSpilledVGPRs = false;
282 
283  // TODO: 10 may be a better default since it's the maximum.
284  unsigned Occupancy = 0;
285 
286  StringValue ScratchRSrcReg = "$private_rsrc_reg";
289 
293 
294  SIMachineFunctionInfo() = default;
296  const TargetRegisterInfo &TRI,
297  const llvm::MachineFunction &MF);
298 
299  void mappingImpl(yaml::IO &YamlIO) override;
300  ~SIMachineFunctionInfo() = default;
301 };
302 
304  static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
305  YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
306  UINT64_C(0));
307  YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
308  YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
309  YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
310  YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
311  YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
312  YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
313  YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
314  YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
315  YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
316  YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
317  StringValue("$private_rsrc_reg"));
318  YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
319  StringValue("$fp_reg"));
320  YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
321  StringValue("$sp_reg"));
322  YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
323  YamlIO.mapOptional("mode", MFI.Mode, SIMode());
324  YamlIO.mapOptional("highBitsOf32BitAddress",
325  MFI.HighBitsOf32BitAddress, 0u);
326  YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
327  YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
328  }
329 };
330 
331 } // end namespace yaml
332 
333 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
334 /// tells the hardware which interpolation parameters to load.
336  friend class GCNTargetMachine;
337 
338  Register TIDReg = AMDGPU::NoRegister;
339 
340  // Registers that may be reserved for spilling purposes. These may be the same
341  // as the input registers.
342  Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
343 
344  // This is the the unswizzled offset from the current dispatch's scratch wave
345  // base to the beginning of the current function's frame.
346  Register FrameOffsetReg = AMDGPU::FP_REG;
347 
348  // This is an ABI register used in the non-entry calling convention to
349  // communicate the unswizzled offset from the current dispatch's scratch wave
350  // base to the beginning of the new function's frame.
351  Register StackPtrOffsetReg = AMDGPU::SP_REG;
352 
353  AMDGPUFunctionArgInfo ArgInfo;
354 
355  // Graphics info.
356  unsigned PSInputAddr = 0;
357  unsigned PSInputEnable = 0;
358 
359  /// Number of bytes of arguments this function has on the stack. If the callee
360  /// is expected to restore the argument stack this should be a multiple of 16,
361  /// all usable during a tail call.
362  ///
363  /// The alternative would forbid tail call optimisation in some cases: if we
364  /// want to transfer control from a function with 8-bytes of stack-argument
365  /// space to a function with 16-bytes then misalignment of this value would
366  /// make a stack adjustment necessary, which could not be undone by the
367  /// callee.
368  unsigned BytesInStackArgArea = 0;
369 
370  bool ReturnsVoid = true;
371 
372  // A pair of default/requested minimum/maximum flat work group sizes.
373  // Minimum - first, maximum - second.
374  std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
375 
376  // A pair of default/requested minimum/maximum number of waves per execution
377  // unit. Minimum - first, maximum - second.
378  std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
379 
380  std::unique_ptr<const AMDGPUBufferPseudoSourceValue> BufferPSV;
381  std::unique_ptr<const AMDGPUImagePseudoSourceValue> ImagePSV;
382  std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
383 
384 private:
385  unsigned LDSWaveSpillSize = 0;
386  unsigned NumUserSGPRs = 0;
387  unsigned NumSystemSGPRs = 0;
388 
389  bool HasSpilledSGPRs = false;
390  bool HasSpilledVGPRs = false;
391  bool HasNonSpillStackObjects = false;
392  bool IsStackRealigned = false;
393 
394  unsigned NumSpilledSGPRs = 0;
395  unsigned NumSpilledVGPRs = 0;
396 
397  // Feature bits required for inputs passed in user SGPRs.
398  bool PrivateSegmentBuffer : 1;
399  bool DispatchPtr : 1;
400  bool QueuePtr : 1;
401  bool KernargSegmentPtr : 1;
402  bool DispatchID : 1;
403  bool FlatScratchInit : 1;
404 
405  // Feature bits required for inputs passed in system SGPRs.
406  bool WorkGroupIDX : 1; // Always initialized.
407  bool WorkGroupIDY : 1;
408  bool WorkGroupIDZ : 1;
409  bool WorkGroupInfo : 1;
410  bool PrivateSegmentWaveByteOffset : 1;
411 
412  bool WorkItemIDX : 1; // Always initialized.
413  bool WorkItemIDY : 1;
414  bool WorkItemIDZ : 1;
415 
416  // Private memory buffer
417  // Compute directly in sgpr[0:1]
418  // Other shaders indirect 64-bits at sgpr[0:1]
419  bool ImplicitBufferPtr : 1;
420 
421  // Pointer to where the ABI inserts special kernel arguments separate from the
422  // user arguments. This is an offset from the KernargSegmentPtr.
423  bool ImplicitArgPtr : 1;
424 
425  // The hard-wired high half of the address of the global information table
426  // for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
427  // current hardware only allows a 16 bit value.
428  unsigned GITPtrHigh;
429 
430  unsigned HighBitsOf32BitAddress;
431  unsigned GDSSize;
432 
433  // Current recorded maximum possible occupancy.
434  unsigned Occupancy;
435 
436  mutable Optional<bool> UsesAGPRs;
437 
438  MCPhysReg getNextUserSGPR() const;
439 
440  MCPhysReg getNextSystemSGPR() const;
441 
442 public:
443  struct SpilledReg {
445  int Lane = -1;
446 
447  SpilledReg() = default;
448  SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
449 
450  bool hasLane() { return Lane != -1;}
451  bool hasReg() { return VGPR != 0;}
452  };
453 
454  struct SGPRSpillVGPR {
455  // VGPR used for SGPR spills
457 
458  // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
459  // stack slot used to save/restore it in the prolog/epilog.
461 
463  };
464 
467  bool FullyAllocated = false;
468  };
469 
470  // Map WWM VGPR to a stack slot that is used to save/restore it in the
471  // prolog/epilog.
473 
474 private:
475  // Track VGPR + wave index for each subregister of the SGPR spilled to
476  // frameindex key.
477  DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
478  unsigned NumVGPRSpillLanes = 0;
480 
481  DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
482 
483  // AGPRs used for VGPR spills.
484  SmallVector<MCPhysReg, 32> SpillAGPR;
485 
486  // VGPRs used for AGPR spills.
487  SmallVector<MCPhysReg, 32> SpillVGPR;
488 
489  // Emergency stack slot. Sometimes, we create this before finalizing the stack
490  // frame, so save it here and add it to the RegScavenger later.
491  Optional<int> ScavengeFI;
492 
493 public: // FIXME
494  /// If this is set, an SGPR used for save/restore of the register used for the
495  /// frame pointer.
498 
499  /// If this is set, an SGPR used for save/restore of the register used for the
500  /// base pointer.
503 
505  bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
506 
507 public:
509 
511  const MachineFunction &MF,
513  SMDiagnostic &Error, SMRange &SourceRange);
514 
516  WWMReservedRegs.insert(std::make_pair(Reg, FI));
517  }
518 
520  auto I = SGPRToVGPRSpills.find(FrameIndex);
521  return (I == SGPRToVGPRSpills.end()) ?
522  ArrayRef<SpilledReg>() : makeArrayRef(I->second);
523  }
524 
525  ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
526 
527  void setSGPRSpillVGPRs(Register NewVGPR, Optional<int> newFI, int Index) {
528  SpillVGPRs[Index].VGPR = NewVGPR;
529  SpillVGPRs[Index].FI = newFI;
530  VGPRReservedForSGPRSpill = NewVGPR;
531  }
532 
533  bool removeVGPRForSGPRSpill(Register ReservedVGPR, MachineFunction &MF);
534 
536  return SpillAGPR;
537  }
538 
540  return SpillVGPR;
541  }
542 
543  MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
544  auto I = VGPRToAGPRSpills.find(FrameIndex);
545  return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
546  : I->second.Lanes[Lane];
547  }
548 
550  unsigned NumLane) const;
551  bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
553  bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
555 
557  Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
558 
559  bool hasCalculatedTID() const { return TIDReg != 0; };
560  Register getTIDReg() const { return TIDReg; };
561  void setTIDReg(Register Reg) { TIDReg = Reg; }
562 
563  unsigned getBytesInStackArgArea() const {
564  return BytesInStackArgArea;
565  }
566 
567  void setBytesInStackArgArea(unsigned Bytes) {
568  BytesInStackArgArea = Bytes;
569  }
570 
571  // Add user SGPRs.
579 
580  // Add system SGPRs.
582  ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
583  NumSystemSGPRs += 1;
584  return ArgInfo.WorkGroupIDX.getRegister();
585  }
586 
588  ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
589  NumSystemSGPRs += 1;
590  return ArgInfo.WorkGroupIDY.getRegister();
591  }
592 
594  ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
595  NumSystemSGPRs += 1;
596  return ArgInfo.WorkGroupIDZ.getRegister();
597  }
598 
600  ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
601  NumSystemSGPRs += 1;
602  return ArgInfo.WorkGroupInfo.getRegister();
603  }
604 
605  // Add special VGPR inputs
607  ArgInfo.WorkItemIDX = Arg;
608  }
609 
611  ArgInfo.WorkItemIDY = Arg;
612  }
613 
615  ArgInfo.WorkItemIDZ = Arg;
616  }
617 
620  = ArgDescriptor::createRegister(getNextSystemSGPR());
621  NumSystemSGPRs += 1;
622  return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
623  }
624 
627  }
628 
629  bool hasPrivateSegmentBuffer() const {
630  return PrivateSegmentBuffer;
631  }
632 
633  bool hasDispatchPtr() const {
634  return DispatchPtr;
635  }
636 
637  bool hasQueuePtr() const {
638  return QueuePtr;
639  }
640 
641  bool hasKernargSegmentPtr() const {
642  return KernargSegmentPtr;
643  }
644 
645  bool hasDispatchID() const {
646  return DispatchID;
647  }
648 
649  bool hasFlatScratchInit() const {
650  return FlatScratchInit;
651  }
652 
653  bool hasWorkGroupIDX() const {
654  return WorkGroupIDX;
655  }
656 
657  bool hasWorkGroupIDY() const {
658  return WorkGroupIDY;
659  }
660 
661  bool hasWorkGroupIDZ() const {
662  return WorkGroupIDZ;
663  }
664 
665  bool hasWorkGroupInfo() const {
666  return WorkGroupInfo;
667  }
668 
670  return PrivateSegmentWaveByteOffset;
671  }
672 
673  bool hasWorkItemIDX() const {
674  return WorkItemIDX;
675  }
676 
677  bool hasWorkItemIDY() const {
678  return WorkItemIDY;
679  }
680 
681  bool hasWorkItemIDZ() const {
682  return WorkItemIDZ;
683  }
684 
685  bool hasImplicitArgPtr() const {
686  return ImplicitArgPtr;
687  }
688 
689  bool hasImplicitBufferPtr() const {
690  return ImplicitBufferPtr;
691  }
692 
694  return ArgInfo;
695  }
696 
698  return ArgInfo;
699  }
700 
701  std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
703  return ArgInfo.getPreloadedValue(Value);
704  }
705 
707  auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
708  return Arg ? Arg->getRegister() : MCRegister();
709  }
710 
711  unsigned getGITPtrHigh() const {
712  return GITPtrHigh;
713  }
714 
715  Register getGITPtrLoReg(const MachineFunction &MF) const;
716 
718  return HighBitsOf32BitAddress;
719  }
720 
721  unsigned getGDSSize() const {
722  return GDSSize;
723  }
724 
725  unsigned getNumUserSGPRs() const {
726  return NumUserSGPRs;
727  }
728 
729  unsigned getNumPreloadedSGPRs() const {
730  return NumUserSGPRs + NumSystemSGPRs;
731  }
732 
734  return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
735  }
736 
737  /// Returns the physical register reserved for use as the resource
738  /// descriptor for scratch accesses.
740  return ScratchRSrcReg;
741  }
742 
744  assert(Reg != 0 && "Should never be unset");
745  ScratchRSrcReg = Reg;
746  }
747 
749  return FrameOffsetReg;
750  }
751 
753  assert(Reg != 0 && "Should never be unset");
754  FrameOffsetReg = Reg;
755  }
756 
758  assert(Reg != 0 && "Should never be unset");
759  StackPtrOffsetReg = Reg;
760  }
761 
762  // Note the unset value for this is AMDGPU::SP_REG rather than
763  // NoRegister. This is mostly a workaround for MIR tests where state that
764  // can't be directly computed from the function is not preserved in serialized
765  // MIR.
767  return StackPtrOffsetReg;
768  }
769 
771  return ArgInfo.QueuePtr.getRegister();
772  }
773 
775  return ArgInfo.ImplicitBufferPtr.getRegister();
776  }
777 
778  bool hasSpilledSGPRs() const {
779  return HasSpilledSGPRs;
780  }
781 
782  void setHasSpilledSGPRs(bool Spill = true) {
783  HasSpilledSGPRs = Spill;
784  }
785 
786  bool hasSpilledVGPRs() const {
787  return HasSpilledVGPRs;
788  }
789 
790  void setHasSpilledVGPRs(bool Spill = true) {
791  HasSpilledVGPRs = Spill;
792  }
793 
794  bool hasNonSpillStackObjects() const {
795  return HasNonSpillStackObjects;
796  }
797 
798  void setHasNonSpillStackObjects(bool StackObject = true) {
799  HasNonSpillStackObjects = StackObject;
800  }
801 
802  bool isStackRealigned() const {
803  return IsStackRealigned;
804  }
805 
806  void setIsStackRealigned(bool Realigned = true) {
807  IsStackRealigned = Realigned;
808  }
809 
810  unsigned getNumSpilledSGPRs() const {
811  return NumSpilledSGPRs;
812  }
813 
814  unsigned getNumSpilledVGPRs() const {
815  return NumSpilledVGPRs;
816  }
817 
818  void addToSpilledSGPRs(unsigned num) {
819  NumSpilledSGPRs += num;
820  }
821 
822  void addToSpilledVGPRs(unsigned num) {
823  NumSpilledVGPRs += num;
824  }
825 
826  unsigned getPSInputAddr() const {
827  return PSInputAddr;
828  }
829 
830  unsigned getPSInputEnable() const {
831  return PSInputEnable;
832  }
833 
834  bool isPSInputAllocated(unsigned Index) const {
835  return PSInputAddr & (1 << Index);
836  }
837 
838  void markPSInputAllocated(unsigned Index) {
839  PSInputAddr |= 1 << Index;
840  }
841 
842  void markPSInputEnabled(unsigned Index) {
843  PSInputEnable |= 1 << Index;
844  }
845 
846  bool returnsVoid() const {
847  return ReturnsVoid;
848  }
849 
850  void setIfReturnsVoid(bool Value) {
851  ReturnsVoid = Value;
852  }
853 
854  /// \returns A pair of default/requested minimum/maximum flat work group sizes
855  /// for this function.
856  std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
857  return FlatWorkGroupSizes;
858  }
859 
860  /// \returns Default/requested minimum flat work group size for this function.
861  unsigned getMinFlatWorkGroupSize() const {
862  return FlatWorkGroupSizes.first;
863  }
864 
865  /// \returns Default/requested maximum flat work group size for this function.
866  unsigned getMaxFlatWorkGroupSize() const {
867  return FlatWorkGroupSizes.second;
868  }
869 
870  /// \returns A pair of default/requested minimum/maximum number of waves per
871  /// execution unit.
872  std::pair<unsigned, unsigned> getWavesPerEU() const {
873  return WavesPerEU;
874  }
875 
876  /// \returns Default/requested minimum number of waves per execution unit.
877  unsigned getMinWavesPerEU() const {
878  return WavesPerEU.first;
879  }
880 
881  /// \returns Default/requested maximum number of waves per execution unit.
882  unsigned getMaxWavesPerEU() const {
883  return WavesPerEU.second;
884  }
885 
886  /// \returns SGPR used for \p Dim's work group ID.
887  Register getWorkGroupIDSGPR(unsigned Dim) const {
888  switch (Dim) {
889  case 0:
891  return ArgInfo.WorkGroupIDX.getRegister();
892  case 1:
894  return ArgInfo.WorkGroupIDY.getRegister();
895  case 2:
897  return ArgInfo.WorkGroupIDZ.getRegister();
898  }
899  llvm_unreachable("unexpected dimension");
900  }
901 
902  unsigned getLDSWaveSpillSize() const {
903  return LDSWaveSpillSize;
904  }
905 
907  if (!BufferPSV)
908  BufferPSV = std::make_unique<AMDGPUBufferPseudoSourceValue>(TII);
909 
910  return BufferPSV.get();
911  }
912 
914  if (!ImagePSV)
915  ImagePSV = std::make_unique<AMDGPUImagePseudoSourceValue>(TII);
916 
917  return ImagePSV.get();
918  }
919 
921  if (!GWSResourcePSV) {
922  GWSResourcePSV =
923  std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
924  }
925 
926  return GWSResourcePSV.get();
927  }
928 
929  unsigned getOccupancy() const {
930  return Occupancy;
931  }
932 
933  unsigned getMinAllowedOccupancy() const {
934  if (!isMemoryBound() && !needsWaveLimiter())
935  return Occupancy;
936  return (Occupancy < 4) ? Occupancy : 4;
937  }
938 
939  void limitOccupancy(const MachineFunction &MF);
940 
941  void limitOccupancy(unsigned Limit) {
942  if (Occupancy > Limit)
943  Occupancy = Limit;
944  }
945 
946  void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
947  if (Occupancy < Limit)
948  Occupancy = Limit;
949  limitOccupancy(MF);
950  }
951 
952  // \returns true if a function needs or may need AGPRs.
953  bool usesAGPRs(const MachineFunction &MF) const;
954 };
955 
956 } // end namespace llvm
957 
958 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
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Definition: PseudoSourceValue.h:35
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Definition: Alignment.h:39
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Definition: DenseMap.h:150
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Definition: SIMachineFunctionInfo.h:36
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Definition: ArrayRef.h:474
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Definition: SIMachineFunctionInfo.h:657
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Definition: SIMachineFunctionInfo.h:448
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Definition: SIMachineFunctionInfo.h:826
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Definition: SIMachineFunctionInfo.h:834
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Definition: SIMachineFunctionInfo.h:599
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Definition: SIMachineFunctionInfo.h:231
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Implement printing for PseudoSourceValue.
Definition: SIMachineFunctionInfo.h:70
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Definition: SIMachineFunctionInfo.h:782
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Definition: SIMachineFunctionInfo.h:822
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Definition: AMDGPUMetadata.h:263
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Definition: SIMachineFunctionInfo.h:116
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Definition: SIMachineFunctionInfo.h:454
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true
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Definition: AMDGPUMachineFunction.h:20
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Definition: SIMachineFunctionInfo.h:673
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Definition: Value.h:74
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Definition: SIMachineFunctionInfo.h:689
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Definition: SIMachineFunctionInfo.h:748
Other
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Definition: ELFYAML.cpp:1191
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Definition: MCRegister.h:24
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