LLVM 19.0.0git
SIModeRegisterDefaults.h
Go to the documentation of this file.
1//===-- SIModeRegisterDefaults.h --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
10#define LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
11
14
15namespace llvm {
16
17class GCNSubtarget;
18
19// Track defaults for fields in the MODE register.
21 /// Floating point opcodes that support exception flag gathering quiet and
22 /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
23 /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
24 /// quieting.
25 bool IEEE : 1;
26
27 /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
28 /// clamp NaN to zero; otherwise, pass NaN through.
29 bool DX10Clamp : 1;
30
31 /// If this is set, neither input or output denormals are flushed for most f32
32 /// instructions.
34
35 /// If this is set, neither input or output denormals are flushed for both f64
36 /// and f16/v2f16 instructions.
38
40 IEEE(true),
42 FP32Denormals(DenormalMode::getIEEE()),
43 FP64FP16Denormals(DenormalMode::getIEEE()) {}
44
46
49 Mode.IEEE = !AMDGPU::isShader(CC);
50 return Mode;
51 }
52
54 return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
55 FP32Denormals == Other.FP32Denormals &&
56 FP64FP16Denormals == Other.FP64FP16Denormals;
57 }
58
59 /// Get the encoding value for the FP_DENORM bits of the mode register for the
60 /// FP32 denormal mode.
67 return FP_DENORM_FLUSH_IN;
69 }
70
71 /// Get the encoding value for the FP_DENORM bits of the mode register for the
72 /// FP64/FP16 denormal mode.
79 return FP_DENORM_FLUSH_IN;
81 }
82
83 // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
84 // be able to override.
86 return DX10Clamp == CalleeMode.DX10Clamp && IEEE == CalleeMode.IEEE;
87 }
88};
89
90namespace AMDGPU {
91
92/// Return values used for llvm.get.rounding
93///
94/// When both the F32 and F64/F16 modes are the same, returns the standard
95/// values. If they differ, returns an extended mode starting at 8.
96enum AMDGPUFltRounds : int8_t {
97 // Inherit everything from RoundingMode
98 TowardZero = static_cast<int8_t>(RoundingMode::TowardZero),
104
105 Dynamic = static_cast<int8_t>(RoundingMode::Dynamic),
106
107 // Permute the mismatched rounding mode cases. If the modes are the same, use
108 // the standard values, otherwise, these values are sorted such that higher
109 // hardware encoded values have higher enum values.
114
119
124
129
130 Invalid = static_cast<int8_t>(RoundingMode::Invalid)
132
133/// Offset of nonstandard values for llvm.get.rounding results from the largest
134/// supported mode.
135static constexpr uint32_t ExtendedFltRoundOffset = 4;
136
137/// Offset in mode register of f32 rounding mode.
138static constexpr uint32_t F32FltRoundOffset = 0;
139
140/// Offset in mode register of f64/f16 rounding mode.
141static constexpr uint32_t F64FltRoundOffset = 2;
142
143// Bit indexed table to convert from hardware rounding mode values to FLT_ROUNDS
144// values.
146
147} // end namespace AMDGPU
148
149} // end namespace llvm
150
151#endif // LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
basic Basic Alias true
Utilities for dealing with flags related to floating point properties and mode controls.
#define F(x, y, z)
Definition: MD5.cpp:55
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
#define FP_DENORM_FLUSH_OUT
Definition: SIDefines.h:1172
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:1174
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:1171
#define FP_DENORM_FLUSH_IN
Definition: SIDefines.h:1173
static constexpr uint32_t F64FltRoundOffset
Offset in mode register of f64/f16 rounding mode.
static constexpr uint32_t ExtendedFltRoundOffset
Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
bool isShader(CallingConv::ID cc)
AMDGPUFltRounds
Return values used for llvm.get.rounding.
static constexpr uint32_t F32FltRoundOffset
Offset in mode register of f32 rounding mode.
const uint64_t FltRoundConversionTable
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Other
Any other memory.
@ TowardZero
roundTowardZero.
@ NearestTiesToEven
roundTiesToEven.
@ Invalid
Denotes invalid value.
@ Dynamic
Denotes mode unknown at compile time.
@ TowardPositive
roundTowardPositive.
@ NearestTiesToAway
roundTiesToAway.
@ TowardNegative
roundTowardNegative.
Represent subnormal handling kind for floating point instruction inputs and outputs.
DenormalModeKind Input
Denormal treatment kind for floating point instruction inputs in the default floating-point environme...
@ PreserveSign
The sign of a flushed-to-zero number is preserved in the sign of 0.
static constexpr DenormalMode getPreserveSign()
DenormalModeKind Output
Denormal flushing mode for floating point instruction results in the default floating point environme...
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
uint32_t fpDenormModeSPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.
DenormalMode FP64FP16Denormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const
bool operator==(const SIModeRegisterDefaults Other) const
DenormalMode FP32Denormals
If this is set, neither input or output denormals are flushed for most f32 instructions.