LLVM  15.0.0git
SIMachineFunctionInfo.cpp
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1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
34  BufferPSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
35  ImagePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
36  GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
37  PrivateSegmentBuffer(false),
38  DispatchPtr(false),
39  QueuePtr(false),
40  KernargSegmentPtr(false),
41  DispatchID(false),
42  FlatScratchInit(false),
43  WorkGroupIDX(false),
44  WorkGroupIDY(false),
45  WorkGroupIDZ(false),
46  WorkGroupInfo(false),
47  PrivateSegmentWaveByteOffset(false),
48  WorkItemIDX(false),
49  WorkItemIDY(false),
50  WorkItemIDZ(false),
51  ImplicitBufferPtr(false),
52  ImplicitArgPtr(false),
53  GITPtrHigh(0xffffffff),
54  HighBitsOf32BitAddress(0) {
56  const Function &F = MF.getFunction();
57  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
58  WavesPerEU = ST.getWavesPerEU(F);
59 
60  Occupancy = ST.computeOccupancy(F, getLDSSize());
61  CallingConv::ID CC = F.getCallingConv();
62 
63  // FIXME: Should have analysis or something rather than attribute to detect
64  // calls.
65  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
66 
67  const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
69 
70  if (IsKernel) {
71  if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
72  KernargSegmentPtr = true;
73  WorkGroupIDX = true;
74  WorkItemIDX = true;
75  } else if (CC == CallingConv::AMDGPU_PS) {
76  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
77  }
78 
79  MayNeedAGPRs = ST.hasMAIInsts();
80 
81  if (!isEntryFunction()) {
82  if (CC != CallingConv::AMDGPU_Gfx)
84 
85  // TODO: Pick a high register, and shift down, similar to a kernel.
86  FrameOffsetReg = AMDGPU::SGPR33;
87  StackPtrOffsetReg = AMDGPU::SGPR32;
88 
89  if (!ST.enableFlatScratch()) {
90  // Non-entry functions have no special inputs for now, other registers
91  // required for scratch access.
92  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
93 
94  ArgInfo.PrivateSegmentBuffer =
95  ArgDescriptor::createRegister(ScratchRSrcReg);
96  }
97 
98  if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
99  ImplicitArgPtr = true;
100  } else {
101  ImplicitArgPtr = false;
102  MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
104 
105  if (ST.hasGFX90AInsts() &&
106  ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
107  !mayUseAGPRs(MF))
108  MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
109  }
110 
111  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
112  if (isAmdHsaOrMesa && !ST.enableFlatScratch())
113  PrivateSegmentBuffer = true;
114  else if (ST.isMesaGfxShader(F))
115  ImplicitBufferPtr = true;
116 
117  if (!AMDGPU::isGraphics(CC)) {
118  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
119  WorkGroupIDX = true;
120 
121  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
122  WorkGroupIDY = true;
123 
124  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
125  WorkGroupIDZ = true;
126 
127  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
128  WorkItemIDX = true;
129 
130  if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
131  ST.getMaxWorkitemID(F, 1) != 0)
132  WorkItemIDY = true;
133 
134  if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
135  ST.getMaxWorkitemID(F, 2) != 0)
136  WorkItemIDZ = true;
137 
138  if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
139  DispatchPtr = true;
140 
141  if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
142  QueuePtr = true;
143 
144  if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
145  DispatchID = true;
146  }
147 
148  // FIXME: This attribute is a hack, we just need an analysis on the function
149  // to look for allocas.
150  bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
151 
152  // TODO: This could be refined a lot. The attribute is a poor way of
153  // detecting calls or stack objects that may require it before argument
154  // lowering.
155  if (ST.hasFlatAddressSpace() && isEntryFunction() &&
156  (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
157  (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
158  !ST.flatScratchIsArchitected()) {
159  FlatScratchInit = true;
160  }
161 
162  if (isEntryFunction()) {
163  // X, XY, and XYZ are the only supported combinations, so make sure Y is
164  // enabled if Z is.
165  if (WorkItemIDZ)
166  WorkItemIDY = true;
167 
168  if (!ST.flatScratchIsArchitected()) {
169  PrivateSegmentWaveByteOffset = true;
170 
171  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
172  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
174  ArgInfo.PrivateSegmentWaveByteOffset =
175  ArgDescriptor::createRegister(AMDGPU::SGPR5);
176  }
177  }
178 
179  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
180  StringRef S = A.getValueAsString();
181  if (!S.empty())
182  S.consumeInteger(0, GITPtrHigh);
183 
184  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
185  S = A.getValueAsString();
186  if (!S.empty())
187  S.consumeInteger(0, HighBitsOf32BitAddress);
188 
189  // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
190  // VGPR available at all times. For now, reserve highest available VGPR. After
191  // RA, shift it to the lowest available unused VGPR if the one exist.
192  if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
193  VGPRForAGPRCopy =
194  AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
195  }
196 }
197 
201  const {
202  return DestMF.cloneInfo<SIMachineFunctionInfo>(*this);
203 }
204 
207  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
208  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
209  MF.getFunction()));
210 }
211 
213  const SIRegisterInfo &TRI) {
214  ArgInfo.PrivateSegmentBuffer =
216  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
217  NumUserSGPRs += 4;
218  return ArgInfo.PrivateSegmentBuffer.getRegister();
219 }
220 
223  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
224  NumUserSGPRs += 2;
225  return ArgInfo.DispatchPtr.getRegister();
226 }
227 
230  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
231  NumUserSGPRs += 2;
232  return ArgInfo.QueuePtr.getRegister();
233 }
234 
236  ArgInfo.KernargSegmentPtr
238  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
239  NumUserSGPRs += 2;
240  return ArgInfo.KernargSegmentPtr.getRegister();
241 }
242 
245  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
246  NumUserSGPRs += 2;
247  return ArgInfo.DispatchID.getRegister();
248 }
249 
252  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
253  NumUserSGPRs += 2;
254  return ArgInfo.FlatScratchInit.getRegister();
255 }
256 
259  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
260  NumUserSGPRs += 2;
261  return ArgInfo.ImplicitBufferPtr.getRegister();
262 }
263 
265  MCPhysReg Reg) {
266  for (unsigned I = 0; CSRegs[I]; ++I) {
267  if (CSRegs[I] == Reg)
268  return true;
269  }
270 
271  return false;
272 }
273 
274 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
275 /// SGPR spilling.
276 //
277 // FIXME: This only works after processFunctionBeforeFrameFinalized
279  unsigned NumNeed) const {
280  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
281  unsigned WaveSize = ST.getWavefrontSize();
282  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
283 }
284 
285 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
287  int FI) {
288  std::vector<SIRegisterInfo::SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
289 
290  // This has already been allocated.
291  if (!SpillLanes.empty())
292  return true;
293 
294  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
295  const SIRegisterInfo *TRI = ST.getRegisterInfo();
296  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
298  unsigned WaveSize = ST.getWavefrontSize();
299 
300  unsigned Size = FrameInfo.getObjectSize(FI);
301  unsigned NumLanes = Size / 4;
302 
303  if (NumLanes > WaveSize)
304  return false;
305 
306  assert(Size >= 4 && "invalid sgpr spill size");
307  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
308 
309  // Make sure to handle the case where a wide SGPR spill may span between two
310  // VGPRs.
311  for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
312  Register LaneVGPR;
313  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
314 
315  if (VGPRIndex == 0) {
316  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
317  if (LaneVGPR == AMDGPU::NoRegister) {
318  // We have no VGPRs left for spilling SGPRs. Reset because we will not
319  // partially spill the SGPR to VGPRs.
320  SGPRToVGPRSpills.erase(FI);
321  NumVGPRSpillLanes -= I;
322 
323  // FIXME: We can run out of free registers with split allocation if
324  // IPRA is enabled and a called function already uses every VGPR.
325 #if 0
326  DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
327  "VGPRs for SGPR spilling",
328  0, DS_Error);
329  MF.getFunction().getContext().diagnose(DiagOutOfRegs);
330 #endif
331  return false;
332  }
333 
334  Optional<int> SpillFI;
335  // We need to preserve inactive lanes, so always save, even caller-save
336  // registers.
337  if (!isEntryFunction()) {
338  SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
339  }
340 
341  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
342 
343  // Add this register as live-in to all blocks to avoid machine verifier
344  // complaining about use of an undefined physical register.
345  for (MachineBasicBlock &BB : MF)
346  BB.addLiveIn(LaneVGPR);
347  } else {
348  LaneVGPR = SpillVGPRs.back().VGPR;
349  }
350 
351  SpillLanes.push_back(SIRegisterInfo::SpilledReg(LaneVGPR, VGPRIndex));
352  }
353 
354  return true;
355 }
356 
357 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
358 /// Either AGPR is spilled to VGPR to vice versa.
359 /// Returns true if a \p FI can be eliminated completely.
361  int FI,
362  bool isAGPRtoVGPR) {
364  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
365  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
366 
367  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
368 
369  auto &Spill = VGPRToAGPRSpills[FI];
370 
371  // This has already been allocated.
372  if (!Spill.Lanes.empty())
373  return Spill.FullyAllocated;
374 
375  unsigned Size = FrameInfo.getObjectSize(FI);
376  unsigned NumLanes = Size / 4;
377  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
378 
379  const TargetRegisterClass &RC =
380  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
381  auto Regs = RC.getRegisters();
382 
383  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
384  const SIRegisterInfo *TRI = ST.getRegisterInfo();
385  Spill.FullyAllocated = true;
386 
387  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
388  // once.
389  BitVector OtherUsedRegs;
390  OtherUsedRegs.resize(TRI->getNumRegs());
391 
392  const uint32_t *CSRMask =
394  if (CSRMask)
395  OtherUsedRegs.setBitsInMask(CSRMask);
396 
397  // TODO: Should include register tuples, but doesn't matter with current
398  // usage.
399  for (MCPhysReg Reg : SpillAGPR)
400  OtherUsedRegs.set(Reg);
401  for (MCPhysReg Reg : SpillVGPR)
402  OtherUsedRegs.set(Reg);
403 
404  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
405  for (int I = NumLanes - 1; I >= 0; --I) {
406  NextSpillReg = std::find_if(
407  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
408  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
409  !OtherUsedRegs[Reg];
410  });
411 
412  if (NextSpillReg == Regs.end()) { // Registers exhausted
413  Spill.FullyAllocated = false;
414  break;
415  }
416 
417  OtherUsedRegs.set(*NextSpillReg);
418  SpillRegs.push_back(*NextSpillReg);
419  Spill.Lanes[I] = *NextSpillReg++;
420  }
421 
422  return Spill.FullyAllocated;
423 }
424 
426  MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
427  // Remove dead frame indices from function frame, however keep FP & BP since
428  // spills for them haven't been inserted yet. And also make sure to remove the
429  // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
430  // result in an unexpected side effect and bug, in case of any re-mapping of
431  // freed frame indices by later pass(es) like "stack slot coloring".
432  for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
433  if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
434  MFI.RemoveStackObject(R.first);
435  SGPRToVGPRSpills.erase(R.first);
436  }
437  }
438 
439  bool HaveSGPRToMemory = false;
440 
441  if (ResetSGPRSpillStackIDs) {
442  // All other SPGRs must be allocated on the default stack, so reset the
443  // stack ID.
444  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
445  ++i) {
447  if (MFI.getStackID(i) == TargetStackID::SGPRSpill) {
449  HaveSGPRToMemory = true;
450  }
451  }
452  }
453  }
454 
455  for (auto &R : VGPRToAGPRSpills) {
456  if (R.second.IsDead)
457  MFI.RemoveStackObject(R.first);
458  }
459 
460  return HaveSGPRToMemory;
461 }
462 
464  MachineFrameInfo &MFI, const SIRegisterInfo &TRI) {
466 
468 
469  int I = 0;
470  for (Register VGPR : WWMReservedRegs) {
471  const TargetRegisterClass *RC = TRI.getPhysRegClass(VGPR);
473  TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC));
474  }
475 }
476 
478  const SIRegisterInfo &TRI) {
479  if (ScavengeFI)
480  return *ScavengeFI;
481  if (isEntryFunction()) {
482  ScavengeFI = MFI.CreateFixedObject(
483  TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
484  } else {
485  ScavengeFI = MFI.CreateStackObject(
486  TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
487  TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
488  }
489  return *ScavengeFI;
490 }
491 
492 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
493  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
494  return AMDGPU::SGPR0 + NumUserSGPRs;
495 }
496 
497 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
498  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
499 }
500 
501 Register
503  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
504  if (!ST.isAmdPalOS())
505  return Register();
506  Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
507  if (ST.hasMergedShaders()) {
508  switch (MF.getFunction().getCallingConv()) {
511  // Low GIT address is passed in s8 rather than s0 for an LS+HS or
512  // ES+GS merged shader on gfx9+.
513  GitPtrLo = AMDGPU::SGPR8;
514  return GitPtrLo;
515  default:
516  return GitPtrLo;
517  }
518  }
519  return GitPtrLo;
520 }
521 
523  const TargetRegisterInfo &TRI) {
524  yaml::StringValue Dest;
525  {
526  raw_string_ostream OS(Dest.Value);
527  OS << printReg(Reg, &TRI);
528  }
529  return Dest;
530 }
531 
534  const TargetRegisterInfo &TRI) {
536 
537  auto convertArg = [&](Optional<yaml::SIArgument> &A,
538  const ArgDescriptor &Arg) {
539  if (!Arg)
540  return false;
541 
542  // Create a register or stack argument.
544  if (Arg.isRegister()) {
546  OS << printReg(Arg.getRegister(), &TRI);
547  } else
548  SA.StackOffset = Arg.getStackOffset();
549  // Check and update the optional mask.
550  if (Arg.isMasked())
551  SA.Mask = Arg.getMask();
552 
553  A = SA;
554  return true;
555  };
556 
557  bool Any = false;
558  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
559  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
560  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
561  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
562  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
563  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
564  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
565  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
566  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
567  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
568  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
569  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
570  ArgInfo.PrivateSegmentWaveByteOffset);
571  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
572  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
573  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
574  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
575  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
576 
577  if (Any)
578  return AI;
579 
580  return None;
581 }
582 
585  const llvm::MachineFunction &MF)
586  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
587  MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
588  GDSSize(MFI.getGDSSize()),
589  DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
590  NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
591  MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
592  HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
593  HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
594  HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
595  Occupancy(MFI.getOccupancy()),
596  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
597  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
598  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
599  BytesInStackArgArea(MFI.getBytesInStackArgArea()),
600  ReturnsVoid(MFI.returnsVoid()),
601  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
602  for (Register Reg : MFI.WWMReservedRegs)
603  WWMReservedRegs.push_back(regToString(Reg, TRI));
604 
605  if (MFI.getVGPRForAGPRCopy())
607  auto SFI = MFI.getOptionalScavengeFI();
608  if (SFI)
610 }
611 
614 }
615 
617  const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
618  PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
621  LDSSize = YamlMFI.LDSSize;
622  GDSSize = YamlMFI.GDSSize;
623  DynLDSAlign = YamlMFI.DynLDSAlign;
625  Occupancy = YamlMFI.Occupancy;
628  MemoryBound = YamlMFI.MemoryBound;
629  WaveLimiter = YamlMFI.WaveLimiter;
633  ReturnsVoid = YamlMFI.ReturnsVoid;
634 
635  if (YamlMFI.ScavengeFI) {
636  auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
637  if (!FIOrErr) {
638  // Create a diagnostic for a the frame index.
639  const MemoryBuffer &Buffer =
640  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
641 
642  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
643  SourceMgr::DK_Error, toString(FIOrErr.takeError()),
644  "", None, None);
645  SourceRange = YamlMFI.ScavengeFI->SourceRange;
646  return true;
647  }
648  ScavengeFI = *FIOrErr;
649  } else {
650  ScavengeFI = None;
651  }
652  return false;
653 }
654 
656  for (const BasicBlock &BB : MF.getFunction()) {
657  for (const Instruction &I : BB) {
658  const auto *CB = dyn_cast<CallBase>(&I);
659  if (!CB)
660  continue;
661 
662  if (CB->isInlineAsm()) {
663  const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
664  for (const auto &CI : IA->ParseConstraints()) {
665  for (StringRef Code : CI.Codes) {
666  Code.consume_front("{");
667  if (Code.startswith("a"))
668  return true;
669  }
670  }
671  continue;
672  }
673 
674  const Function *Callee =
675  dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
676  if (!Callee)
677  return true;
678 
679  if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
680  return true;
681  }
682  }
683 
684  return false;
685 }
686 
688  if (UsesAGPRs)
689  return *UsesAGPRs;
690 
691  if (!mayNeedAGPRs()) {
692  UsesAGPRs = false;
693  return false;
694  }
695 
697  MF.getFrameInfo().hasCalls()) {
698  UsesAGPRs = true;
699  return true;
700  }
701 
702  const MachineRegisterInfo &MRI = MF.getRegInfo();
703 
704  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
707  if (RC && SIRegisterInfo::isAGPRClass(RC)) {
708  UsesAGPRs = true;
709  return true;
710  } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
711  // Defer caching UsesAGPRs, function might not yet been regbank selected.
712  return true;
713  }
714  }
715 
716  for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
717  if (MRI.isPhysRegUsed(Reg)) {
718  UsesAGPRs = true;
719  return true;
720  }
721  }
722 
723  UsesAGPRs = false;
724  return false;
725 }
i
i
Definition: README.txt:29
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Definition: GCNSubtarget.h:31
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Definition: Register.h:84
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@ not_intrinsic
Definition: Intrinsics.h:45
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Remove or mark dead a statically sized stack object.
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@ AMDGPU_Gfx
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Definition: CallingConv.h:250
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Definition: MemoryBuffer.h:50
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Definition: AMDGPUArgumentUsageInfo.h:97
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Definition: AMDGPUTargetMachine.h:28
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Diagnostic information for stack size etc.
Definition: DiagnosticInfo.h:186
false
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Definition: SIRegisterInfo.h:30
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Definition: BitVector.h:75
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Definition: None.h:24
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Definition: MachineRegisterInfo.h:514
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Definition: CallingConv.h:24
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Definition: MachineBasicBlock.h:94
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Definition: MachineFrameInfo.cpp:66
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Definition: SIMachineFunctionInfo.cpp:243
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Definition: InlineAsm.h:31
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Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:289
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Definition: SIMachineFunctionInfo.h:148
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Definition: SIMachineFunctionInfo.h:295
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Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:283
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Return the size of the specified object.
Definition: MachineFrameInfo.h:469
LiveIntervals.h
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Definition: SIMachineFunctionInfo.cpp:212
const
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Definition: AArch64PromoteConstant.cpp:232
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@ ST
Definition: ARMBaseInfo.h:73
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Definition: SIMachineFunctionInfo.h:917
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Definition: SIMachineFunctionInfo.h:593
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Definition: Allocator.h:63
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SIMachineFunctionInfo()=default
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constexpr double e
Definition: MathExtras.h:57
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Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:588
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Definition: DenseMap.h:716
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Optional< int > FramePointerSaveIndex
Definition: SIMachineFunctionInfo.h:525
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#define I(x, y, z)
Definition: MD5.cpp:58
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Definition: MCRegister.h:21
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Definition: SIMachineFunctionInfo.h:294
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Make a functionally equivalent copy of this MachineFunctionInfo in MF.
Definition: SIMachineFunctionInfo.cpp:198
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bool isEntryFunction() const
Definition: AMDGPUMachineFunction.h:86
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Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:618
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Definition: SIMachineFunctionInfo.h:473
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Definition: SIMachineFunctionInfo.h:299
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SmallVector< StringValue > WWMReservedRegs
Definition: SIMachineFunctionInfo.h:288
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:659
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
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Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
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int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:477
llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:360
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uint32_t LDSSize
Definition: SIMachineFunctionInfo.h:274
Mode
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Definition: SIWholeQuadMode.cpp:262
llvm::SIMachineFunctionInfo::getGITPtrLoReg
Register getGITPtrLoReg(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:502
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A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::yaml::SIMachineFunctionInfo::MemoryBound
bool MemoryBound
Definition: SIMachineFunctionInfo.h:279
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Definition: MachineFunction.h:257
llvm::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:32
llvm::MachineFrameInfo::setStackID
void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:728
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
uint32_t
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void limitOccupancy(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:205
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
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Optional< SIArgument > ImplicitBufferPtr
Definition: SIMachineFunctionInfo.h:197
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bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1679
llvm::SIMachineFunctionInfo::addImplicitBufferPtr
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:257
llvm::ArgInfo
Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:47
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1644
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bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:605
llvm::MachineFunction::cloneInfo
Ty * cloneInfo(const Ty &Old)
Definition: MachineFunction.h:765
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
Definition: SIMachineFunctionInfo.cpp:425
CallingConv.h
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::LLVMContext::diagnose
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:243
llvm::yaml::SIMachineFunctionInfo::Occupancy
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Definition: SIMachineFunctionInfo.h:286
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Definition: Any.h:28
llvm::MachineFunction::getFunction
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Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::yaml::SIArgumentInfo::WorkGroupInfo
Optional< SIArgument > WorkGroupInfo
Definition: SIMachineFunctionInfo.h:193
uint16_t
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Definition: SIMachineFunctionInfo.cpp:228
llvm::yaml::SIArgumentInfo::ImplicitArgPtr
Optional< SIArgument > ImplicitArgPtr
Definition: SIMachineFunctionInfo.h:196
llvm::yaml::SIArgumentInfo::KernargSegmentPtr
Optional< SIArgument > KernargSegmentPtr
Definition: SIMachineFunctionInfo.h:185
llvm::toString
const char * toString(DWARFSectionKind Kind)
Definition: DWARFUnitIndex.h:67
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Optional< SIArgument > WorkGroupIDY
Definition: SIMachineFunctionInfo.h:191
MachineFrameInfo.h
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Optional< int > BasePointerSaveIndex
Definition: SIMachineFunctionInfo.h:530
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std::string Value
Definition: MIRYamlMapping.h:35
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Optional< SIArgument > PrivateSegmentSize
Definition: SIMachineFunctionInfo.h:188
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:700
DiagnosticInfo.h
Function.h
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:710
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uint32_t GDSSize
Definition: SIMachineFunctionInfo.h:275
llvm::yaml::SIArgumentInfo::PrivateSegmentBuffer
Optional< SIArgument > PrivateSegmentBuffer
Definition: SIMachineFunctionInfo.h:182
llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs
bool HasSpilledSGPRs
Definition: SIMachineFunctionInfo.h:281
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:142
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:349
llvm::yaml::SIMachineFunctionInfo::DynLDSAlign
Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:276
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:152
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::yaml::SIArgument::StackOffset
unsigned StackOffset
Definition: SIMachineFunctionInfo.h:117
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::SIMachineFunctionInfo::SGPRSpillVGPR
Definition: SIMachineFunctionInfo.h:455
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:22
llvm::MachineFunctionInfo
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign
Align MaxKernArgAlign
Definition: SIMachineFunctionInfo.h:273
llvm::AMDGPUMachineFunction::MaxKernArgAlign
Align MaxKernArgAlign
Definition: AMDGPUMachineFunction.h:29
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:119
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:50
SIRegisterInfo.h
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:187
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
AMDGPUTargetMachine.h
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:83
llvm::SIMachineFunctionInfo::allocateWWMReservedSpillSlots
void allocateWWMReservedSpillSlots(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:463
MIParser.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:184
AMDGPUBaseInfo.h