LLVM  16.0.0git
SIMachineFunctionInfo.cpp
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1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
34  Mode(MF.getFunction()),
35  BufferPSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
36  ImagePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
37  GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
38  PrivateSegmentBuffer(false),
39  DispatchPtr(false),
40  QueuePtr(false),
41  KernargSegmentPtr(false),
42  DispatchID(false),
43  FlatScratchInit(false),
44  WorkGroupIDX(false),
45  WorkGroupIDY(false),
46  WorkGroupIDZ(false),
47  WorkGroupInfo(false),
48  LDSKernelId(false),
49  PrivateSegmentWaveByteOffset(false),
50  WorkItemIDX(false),
51  WorkItemIDY(false),
52  WorkItemIDZ(false),
53  ImplicitBufferPtr(false),
54  ImplicitArgPtr(false),
55  GITPtrHigh(0xffffffff),
56  HighBitsOf32BitAddress(0) {
58  const Function &F = MF.getFunction();
59  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
60  WavesPerEU = ST.getWavesPerEU(F);
61 
62  Occupancy = ST.computeOccupancy(F, getLDSSize());
63  CallingConv::ID CC = F.getCallingConv();
64 
65  // FIXME: Should have analysis or something rather than attribute to detect
66  // calls.
67  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
68 
69  const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
71 
72  if (IsKernel) {
73  if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
74  KernargSegmentPtr = true;
75  WorkGroupIDX = true;
76  WorkItemIDX = true;
77  } else if (CC == CallingConv::AMDGPU_PS) {
78  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
79  }
80 
81  MayNeedAGPRs = ST.hasMAIInsts();
82 
83  if (!isEntryFunction()) {
86 
87  // TODO: Pick a high register, and shift down, similar to a kernel.
88  FrameOffsetReg = AMDGPU::SGPR33;
89  StackPtrOffsetReg = AMDGPU::SGPR32;
90 
91  if (!ST.enableFlatScratch()) {
92  // Non-entry functions have no special inputs for now, other registers
93  // required for scratch access.
94  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
95 
96  ArgInfo.PrivateSegmentBuffer =
97  ArgDescriptor::createRegister(ScratchRSrcReg);
98  }
99 
100  if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
101  ImplicitArgPtr = true;
102  } else {
103  ImplicitArgPtr = false;
104  MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
106 
107  if (ST.hasGFX90AInsts() &&
108  ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
109  !mayUseAGPRs(F))
110  MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
111  }
112 
113  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
114  if (isAmdHsaOrMesa && !ST.enableFlatScratch())
115  PrivateSegmentBuffer = true;
116  else if (ST.isMesaGfxShader(F))
117  ImplicitBufferPtr = true;
118 
119  if (!AMDGPU::isGraphics(CC)) {
120  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
121  WorkGroupIDX = true;
122 
123  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
124  WorkGroupIDY = true;
125 
126  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
127  WorkGroupIDZ = true;
128 
129  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
130  WorkItemIDX = true;
131 
132  if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
133  ST.getMaxWorkitemID(F, 1) != 0)
134  WorkItemIDY = true;
135 
136  if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
137  ST.getMaxWorkitemID(F, 2) != 0)
138  WorkItemIDZ = true;
139 
140  if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
141  DispatchPtr = true;
142 
143  if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
144  QueuePtr = true;
145 
146  if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
147  DispatchID = true;
148 
149  if (!IsKernel && !F.hasFnAttribute("amdgpu-no-lds-kernel-id"))
150  LDSKernelId = true;
151  }
152 
153  // FIXME: This attribute is a hack, we just need an analysis on the function
154  // to look for allocas.
155  bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
156 
157  // TODO: This could be refined a lot. The attribute is a poor way of
158  // detecting calls or stack objects that may require it before argument
159  // lowering.
160  if (ST.hasFlatAddressSpace() && isEntryFunction() &&
161  (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
162  (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
163  !ST.flatScratchIsArchitected()) {
164  FlatScratchInit = true;
165  }
166 
167  if (isEntryFunction()) {
168  // X, XY, and XYZ are the only supported combinations, so make sure Y is
169  // enabled if Z is.
170  if (WorkItemIDZ)
171  WorkItemIDY = true;
172 
173  if (!ST.flatScratchIsArchitected()) {
174  PrivateSegmentWaveByteOffset = true;
175 
176  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
177  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
179  ArgInfo.PrivateSegmentWaveByteOffset =
180  ArgDescriptor::createRegister(AMDGPU::SGPR5);
181  }
182  }
183 
184  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
185  StringRef S = A.getValueAsString();
186  if (!S.empty())
187  S.consumeInteger(0, GITPtrHigh);
188 
189  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
190  S = A.getValueAsString();
191  if (!S.empty())
192  S.consumeInteger(0, HighBitsOf32BitAddress);
193 
194  // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
195  // VGPR available at all times. For now, reserve highest available VGPR. After
196  // RA, shift it to the lowest available unused VGPR if the one exist.
197  if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
198  VGPRForAGPRCopy =
199  AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
200  }
201 }
202 
206  const {
207  return DestMF.cloneInfo<SIMachineFunctionInfo>(*this);
208 }
209 
212  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
213  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
214  MF.getFunction()));
215 }
216 
218  const SIRegisterInfo &TRI) {
219  ArgInfo.PrivateSegmentBuffer =
221  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
222  NumUserSGPRs += 4;
223  return ArgInfo.PrivateSegmentBuffer.getRegister();
224 }
225 
228  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
229  NumUserSGPRs += 2;
230  return ArgInfo.DispatchPtr.getRegister();
231 }
232 
235  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
236  NumUserSGPRs += 2;
237  return ArgInfo.QueuePtr.getRegister();
238 }
239 
241  ArgInfo.KernargSegmentPtr
243  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
244  NumUserSGPRs += 2;
245  return ArgInfo.KernargSegmentPtr.getRegister();
246 }
247 
250  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
251  NumUserSGPRs += 2;
252  return ArgInfo.DispatchID.getRegister();
253 }
254 
257  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
258  NumUserSGPRs += 2;
259  return ArgInfo.FlatScratchInit.getRegister();
260 }
261 
264  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
265  NumUserSGPRs += 2;
266  return ArgInfo.ImplicitBufferPtr.getRegister();
267 }
268 
270  ArgInfo.LDSKernelId = ArgDescriptor::createRegister(getNextUserSGPR());
271  NumUserSGPRs += 1;
272  return ArgInfo.LDSKernelId.getRegister();
273 }
274 
276  MCPhysReg Reg) {
277  for (unsigned I = 0; CSRegs[I]; ++I) {
278  if (CSRegs[I] == Reg)
279  return true;
280  }
281 
282  return false;
283 }
284 
285 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
286 /// SGPR spilling.
287 //
288 // FIXME: This only works after processFunctionBeforeFrameFinalized
290  unsigned NumNeed) const {
291  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
292  unsigned WaveSize = ST.getWavefrontSize();
293  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
294 }
295 
296 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
298  int FI) {
299  std::vector<SIRegisterInfo::SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
300 
301  // This has already been allocated.
302  if (!SpillLanes.empty())
303  return true;
304 
305  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
306  const SIRegisterInfo *TRI = ST.getRegisterInfo();
307  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
309  unsigned WaveSize = ST.getWavefrontSize();
310 
311  unsigned Size = FrameInfo.getObjectSize(FI);
312  unsigned NumLanes = Size / 4;
313 
314  if (NumLanes > WaveSize)
315  return false;
316 
317  assert(Size >= 4 && "invalid sgpr spill size");
318  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
319 
320  // Make sure to handle the case where a wide SGPR spill may span between two
321  // VGPRs.
322  for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
323  Register LaneVGPR;
324  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
325 
326  if (VGPRIndex == 0) {
327  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
328  if (LaneVGPR == AMDGPU::NoRegister) {
329  // We have no VGPRs left for spilling SGPRs. Reset because we will not
330  // partially spill the SGPR to VGPRs.
331  SGPRToVGPRSpills.erase(FI);
332  NumVGPRSpillLanes -= I;
333 
334  // FIXME: We can run out of free registers with split allocation if
335  // IPRA is enabled and a called function already uses every VGPR.
336 #if 0
337  DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
338  "VGPRs for SGPR spilling",
339  0, DS_Error);
340  MF.getFunction().getContext().diagnose(DiagOutOfRegs);
341 #endif
342  return false;
343  }
344 
345  Optional<int> SpillFI;
346  // We need to preserve inactive lanes, so always save, even caller-save
347  // registers.
348  if (!isEntryFunction()) {
349  SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
350  }
351 
352  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
353 
354  // Add this register as live-in to all blocks to avoid machine verifier
355  // complaining about use of an undefined physical register.
356  for (MachineBasicBlock &BB : MF)
357  BB.addLiveIn(LaneVGPR);
358  } else {
359  LaneVGPR = SpillVGPRs.back().VGPR;
360  }
361 
362  SpillLanes.push_back(SIRegisterInfo::SpilledReg(LaneVGPR, VGPRIndex));
363  }
364 
365  return true;
366 }
367 
368 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
369 /// Either AGPR is spilled to VGPR to vice versa.
370 /// Returns true if a \p FI can be eliminated completely.
372  int FI,
373  bool isAGPRtoVGPR) {
375  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
376  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
377 
378  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
379 
380  auto &Spill = VGPRToAGPRSpills[FI];
381 
382  // This has already been allocated.
383  if (!Spill.Lanes.empty())
384  return Spill.FullyAllocated;
385 
386  unsigned Size = FrameInfo.getObjectSize(FI);
387  unsigned NumLanes = Size / 4;
388  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
389 
390  const TargetRegisterClass &RC =
391  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
392  auto Regs = RC.getRegisters();
393 
394  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
395  const SIRegisterInfo *TRI = ST.getRegisterInfo();
396  Spill.FullyAllocated = true;
397 
398  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
399  // once.
400  BitVector OtherUsedRegs;
401  OtherUsedRegs.resize(TRI->getNumRegs());
402 
403  const uint32_t *CSRMask =
405  if (CSRMask)
406  OtherUsedRegs.setBitsInMask(CSRMask);
407 
408  // TODO: Should include register tuples, but doesn't matter with current
409  // usage.
410  for (MCPhysReg Reg : SpillAGPR)
411  OtherUsedRegs.set(Reg);
412  for (MCPhysReg Reg : SpillVGPR)
413  OtherUsedRegs.set(Reg);
414 
415  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
416  for (int I = NumLanes - 1; I >= 0; --I) {
417  NextSpillReg = std::find_if(
418  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
419  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
420  !OtherUsedRegs[Reg];
421  });
422 
423  if (NextSpillReg == Regs.end()) { // Registers exhausted
424  Spill.FullyAllocated = false;
425  break;
426  }
427 
428  OtherUsedRegs.set(*NextSpillReg);
429  SpillRegs.push_back(*NextSpillReg);
430  Spill.Lanes[I] = *NextSpillReg++;
431  }
432 
433  return Spill.FullyAllocated;
434 }
435 
437  MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
438  // Remove dead frame indices from function frame, however keep FP & BP since
439  // spills for them haven't been inserted yet. And also make sure to remove the
440  // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
441  // result in an unexpected side effect and bug, in case of any re-mapping of
442  // freed frame indices by later pass(es) like "stack slot coloring".
443  for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
444  if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
445  MFI.RemoveStackObject(R.first);
446  SGPRToVGPRSpills.erase(R.first);
447  }
448  }
449 
450  bool HaveSGPRToMemory = false;
451 
452  if (ResetSGPRSpillStackIDs) {
453  // All other SPGRs must be allocated on the default stack, so reset the
454  // stack ID.
455  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
456  ++i) {
458  if (MFI.getStackID(i) == TargetStackID::SGPRSpill) {
460  HaveSGPRToMemory = true;
461  }
462  }
463  }
464  }
465 
466  for (auto &R : VGPRToAGPRSpills) {
467  if (R.second.IsDead)
468  MFI.RemoveStackObject(R.first);
469  }
470 
471  return HaveSGPRToMemory;
472 }
473 
475  MachineFrameInfo &MFI, const SIRegisterInfo &TRI) {
477 
479 
480  int I = 0;
481  for (Register VGPR : WWMReservedRegs) {
482  const TargetRegisterClass *RC = TRI.getPhysRegClass(VGPR);
484  TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC));
485  }
486 }
487 
489  const SIRegisterInfo &TRI) {
490  if (ScavengeFI)
491  return *ScavengeFI;
492  if (isEntryFunction()) {
493  ScavengeFI = MFI.CreateFixedObject(
494  TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
495  } else {
496  ScavengeFI = MFI.CreateStackObject(
497  TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
498  TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
499  }
500  return *ScavengeFI;
501 }
502 
503 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
504  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
505  return AMDGPU::SGPR0 + NumUserSGPRs;
506 }
507 
508 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
509  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
510 }
511 
512 Register
514  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
515  if (!ST.isAmdPalOS())
516  return Register();
517  Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
518  if (ST.hasMergedShaders()) {
519  switch (MF.getFunction().getCallingConv()) {
522  // Low GIT address is passed in s8 rather than s0 for an LS+HS or
523  // ES+GS merged shader on gfx9+.
524  GitPtrLo = AMDGPU::SGPR8;
525  return GitPtrLo;
526  default:
527  return GitPtrLo;
528  }
529  }
530  return GitPtrLo;
531 }
532 
534  const TargetRegisterInfo &TRI) {
535  yaml::StringValue Dest;
536  {
537  raw_string_ostream OS(Dest.Value);
538  OS << printReg(Reg, &TRI);
539  }
540  return Dest;
541 }
542 
545  const TargetRegisterInfo &TRI) {
547 
548  auto convertArg = [&](Optional<yaml::SIArgument> &A,
549  const ArgDescriptor &Arg) {
550  if (!Arg)
551  return false;
552 
553  // Create a register or stack argument.
555  if (Arg.isRegister()) {
557  OS << printReg(Arg.getRegister(), &TRI);
558  } else
559  SA.StackOffset = Arg.getStackOffset();
560  // Check and update the optional mask.
561  if (Arg.isMasked())
562  SA.Mask = Arg.getMask();
563 
564  A = SA;
565  return true;
566  };
567 
568  bool Any = false;
569  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
570  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
571  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
572  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
573  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
574  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
575  Any |= convertArg(AI.LDSKernelId, ArgInfo.LDSKernelId);
576  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
577  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
578  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
579  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
580  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
581  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
582  ArgInfo.PrivateSegmentWaveByteOffset);
583  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
584  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
585  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
586  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
587  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
588 
589  if (Any)
590  return AI;
591 
592  return None;
593 }
594 
597  const llvm::MachineFunction &MF)
598  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
599  MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
600  GDSSize(MFI.getGDSSize()),
601  DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
602  NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
603  MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
604  HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
605  HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
606  HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
607  Occupancy(MFI.getOccupancy()),
608  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
609  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
610  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
611  BytesInStackArgArea(MFI.getBytesInStackArgArea()),
612  ReturnsVoid(MFI.returnsVoid()),
613  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
614  for (Register Reg : MFI.WWMReservedRegs)
615  WWMReservedRegs.push_back(regToString(Reg, TRI));
616 
617  if (MFI.getVGPRForAGPRCopy())
619  auto SFI = MFI.getOptionalScavengeFI();
620  if (SFI)
622 }
623 
626 }
627 
629  const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
630  PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
633  LDSSize = YamlMFI.LDSSize;
634  GDSSize = YamlMFI.GDSSize;
635  DynLDSAlign = YamlMFI.DynLDSAlign;
637  Occupancy = YamlMFI.Occupancy;
640  MemoryBound = YamlMFI.MemoryBound;
641  WaveLimiter = YamlMFI.WaveLimiter;
645  ReturnsVoid = YamlMFI.ReturnsVoid;
646 
647  if (YamlMFI.ScavengeFI) {
648  auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
649  if (!FIOrErr) {
650  // Create a diagnostic for a the frame index.
651  const MemoryBuffer &Buffer =
652  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
653 
654  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
655  SourceMgr::DK_Error, toString(FIOrErr.takeError()),
656  "", None, None);
657  SourceRange = YamlMFI.ScavengeFI->SourceRange;
658  return true;
659  }
660  ScavengeFI = *FIOrErr;
661  } else {
662  ScavengeFI = None;
663  }
664  return false;
665 }
666 
668  for (const BasicBlock &BB : F) {
669  for (const Instruction &I : BB) {
670  const auto *CB = dyn_cast<CallBase>(&I);
671  if (!CB)
672  continue;
673 
674  if (CB->isInlineAsm()) {
675  const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
676  for (const auto &CI : IA->ParseConstraints()) {
677  for (StringRef Code : CI.Codes) {
678  Code.consume_front("{");
679  if (Code.startswith("a"))
680  return true;
681  }
682  }
683  continue;
684  }
685 
686  const Function *Callee =
687  dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
688  if (!Callee)
689  return true;
690 
691  if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
692  return true;
693  }
694  }
695 
696  return false;
697 }
698 
700  if (UsesAGPRs)
701  return *UsesAGPRs;
702 
703  if (!mayNeedAGPRs()) {
704  UsesAGPRs = false;
705  return false;
706  }
707 
709  MF.getFrameInfo().hasCalls()) {
710  UsesAGPRs = true;
711  return true;
712  }
713 
714  const MachineRegisterInfo &MRI = MF.getRegInfo();
715 
716  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
719  if (RC && SIRegisterInfo::isAGPRClass(RC)) {
720  UsesAGPRs = true;
721  return true;
722  } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
723  // Defer caching UsesAGPRs, function might not yet been regbank selected.
724  return true;
725  }
726  }
727 
728  for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
729  if (MRI.isPhysRegUsed(Reg)) {
730  UsesAGPRs = true;
731  return true;
732  }
733  }
734 
735  UsesAGPRs = false;
736  return false;
737 }
i
i
Definition: README.txt:29
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Definition: GCNSubtarget.h:31
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static Register index2VirtReg(unsigned Index)
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Definition: Register.h:84
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@ not_intrinsic
Definition: Intrinsics.h:45
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@ HasCalls
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Definition: MemoryBuffer.h:51
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Definition: MD5.cpp:55
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Definition: BasicBlock.h:55
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Definition: AMDGPUArgumentUsageInfo.h:97
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Definition: AMDGPUTargetMachine.h:28
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@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
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Definition: TargetRegisterInfo.h:46
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false
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Definition: Instruction.h:42
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@ IA
Definition: AArch64BaseInfo.h:819
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Definition: SIRegisterInfo.h:30
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Definition: BitVector.h:75
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Definition: CallingConv.h:24
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Definition: SIMachineFunctionInfo.h:282
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Definition: MachineBasicBlock.h:94
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Definition: AMDGPUBaseInfo.cpp:1802
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Definition: MachineFrameInfo.cpp:66
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Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:76
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Definition: SIMachineFunctionInfo.cpp:289
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Definition: InlineAsm.h:33
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Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
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Definition: SIMachineFunctionInfo.h:148
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Definition: SIMachineFunctionInfo.h:280
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Definition: SIMachineFunctionInfo.cpp:240
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Definition: SIMachineFunctionInfo.h:192
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bool ReturnsVoid
Definition: SIMachineFunctionInfo.h:297
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unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:286
AMDGPUMCTargetDesc.h
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int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
LiveIntervals.h
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CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
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Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:217
const
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Definition: AArch64PromoteConstant.cpp:232
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@ ST
Definition: ARMBaseInfo.h:73
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unsigned getMaxWavesPerEU() const
Definition: SIMachineFunctionInfo.h:930
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Definition: SIMachineFunctionInfo.h:603
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Definition: Allocator.h:63
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SIMachineFunctionInfo()=default
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Definition: MathExtras.h:53
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Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:601
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Definition: DenseMap.h:714
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Definition: SIMachineFunctionInfo.h:531
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#define I(x, y, z)
Definition: MD5.cpp:58
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Definition: SIMachineFunctionInfo.h:296
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Make a functionally equivalent copy of this MachineFunctionInfo in MF.
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Definition: AMDGPUMachineFunction.h:80
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Definition: STLExtras.h:716
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Definition: SIMachineFunctionInfo.h:479
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Definition: SIMachineFunctionInfo.h:301
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Definition: SIMachineFunctionInfo.h:290
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const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:664
assert
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Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
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getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
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int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:488
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@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:371
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uint32_t LDSSize
Definition: SIMachineFunctionInfo.h:276
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:264
llvm::SIMachineFunctionInfo::getGITPtrLoReg
Register getGITPtrLoReg(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:513
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::yaml::SIMachineFunctionInfo::MemoryBound
bool MemoryBound
Definition: SIMachineFunctionInfo.h:281
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Definition: MachineFunction.h:257
llvm::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:32
llvm::MachineFrameInfo::setStackID
void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:736
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
uint32_t
llvm::SIMachineFunctionInfo::limitOccupancy
void limitOccupancy(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:210
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
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Optional< SIArgument > ImplicitBufferPtr
Definition: SIMachineFunctionInfo.h:198
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
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bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1794
llvm::SIMachineFunctionInfo::addImplicitBufferPtr
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:262
llvm::ArgInfo
Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:49
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1736
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bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:613
llvm::MachineFunction::cloneInfo
Ty * cloneInfo(const Ty &Old)
Definition: MachineFunction.h:766
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:201
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
Definition: SIMachineFunctionInfo.cpp:436
CallingConv.h
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::LLVMContext::diagnose
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:248
llvm::yaml::SIMachineFunctionInfo::Occupancy
unsigned Occupancy
Definition: SIMachineFunctionInfo.h:288
llvm::Any
Definition: Any.h:28
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::yaml::SIArgumentInfo::WorkGroupInfo
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Definition: SIMachineFunctionInfo.h:193
uint16_t
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Definition: SIMachineFunctionInfo.cpp:233
llvm::yaml::SIArgumentInfo::ImplicitArgPtr
Optional< SIArgument > ImplicitArgPtr
Definition: SIMachineFunctionInfo.h:197
llvm::yaml::SIArgumentInfo::KernargSegmentPtr
Optional< SIArgument > KernargSegmentPtr
Definition: SIMachineFunctionInfo.h:185
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const char * toString(DWARFSectionKind Kind)
Definition: DWARFUnitIndex.h:67
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Optional< SIArgument > WorkGroupIDY
Definition: SIMachineFunctionInfo.h:191
MachineFrameInfo.h
llvm::SIMachineFunctionInfo::BasePointerSaveIndex
Optional< int > BasePointerSaveIndex
Definition: SIMachineFunctionInfo.h:536
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std::string Value
Definition: MIRYamlMapping.h:35
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Optional< SIArgument > PrivateSegmentSize
Definition: SIMachineFunctionInfo.h:188
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:700
DiagnosticInfo.h
Function.h
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:718
llvm::yaml::SIMachineFunctionInfo::GDSSize
uint32_t GDSSize
Definition: SIMachineFunctionInfo.h:277
llvm::yaml::SIArgumentInfo::PrivateSegmentBuffer
Optional< SIArgument > PrivateSegmentBuffer
Definition: SIMachineFunctionInfo.h:182
llvm::SIMachineFunctionInfo::mayUseAGPRs
bool mayUseAGPRs(const Function &F) const
Definition: SIMachineFunctionInfo.cpp:667
llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs
bool HasSpilledSGPRs
Definition: SIMachineFunctionInfo.h:283
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:143
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:351
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:233
llvm::yaml::SIMachineFunctionInfo::DynLDSAlign
Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:278
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::yaml::SIArgument::StackOffset
unsigned StackOffset
Definition: SIMachineFunctionInfo.h:117
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
llvm::SIMachineFunctionInfo::SGPRSpillVGPR
Definition: SIMachineFunctionInfo.h:461
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:23
llvm::MachineFunctionInfo
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign
Align MaxKernArgAlign
Definition: SIMachineFunctionInfo.h:275
llvm::AMDGPUMachineFunction::MaxKernArgAlign
Align MaxKernArgAlign
Definition: AMDGPUMachineFunction.h:30
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:119
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:50
SIRegisterInfo.h
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:187
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:483
AMDGPUTargetMachine.h
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:86
llvm::SIMachineFunctionInfo::allocateWWMReservedSpillSlots
void allocateWWMReservedSpillSlots(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:474
MIParser.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:184
AMDGPUBaseInfo.h