LLVM  14.0.0git
SIMachineFunctionInfo.cpp
Go to the documentation of this file.
1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
34  PrivateSegmentBuffer(false),
35  DispatchPtr(false),
36  QueuePtr(false),
37  KernargSegmentPtr(false),
38  DispatchID(false),
39  FlatScratchInit(false),
40  WorkGroupIDX(false),
41  WorkGroupIDY(false),
42  WorkGroupIDZ(false),
43  WorkGroupInfo(false),
44  PrivateSegmentWaveByteOffset(false),
45  WorkItemIDX(false),
46  WorkItemIDY(false),
47  WorkItemIDZ(false),
48  ImplicitBufferPtr(false),
49  ImplicitArgPtr(false),
50  GITPtrHigh(0xffffffff),
51  HighBitsOf32BitAddress(0),
52  GDSSize(0) {
54  const Function &F = MF.getFunction();
55  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
56  WavesPerEU = ST.getWavesPerEU(F);
57 
58  Occupancy = ST.computeOccupancy(F, getLDSSize());
59  CallingConv::ID CC = F.getCallingConv();
60 
61  // FIXME: Should have analysis or something rather than attribute to detect
62  // calls.
63  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
64 
65  const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
67 
68  if (IsKernel) {
69  if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
70  KernargSegmentPtr = true;
71  WorkGroupIDX = true;
72  WorkItemIDX = true;
73  } else if (CC == CallingConv::AMDGPU_PS) {
74  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
75  }
76 
77  if (!isEntryFunction()) {
78  if (CC != CallingConv::AMDGPU_Gfx)
80 
81  // TODO: Pick a high register, and shift down, similar to a kernel.
82  FrameOffsetReg = AMDGPU::SGPR33;
83  StackPtrOffsetReg = AMDGPU::SGPR32;
84 
85  if (!ST.enableFlatScratch()) {
86  // Non-entry functions have no special inputs for now, other registers
87  // required for scratch access.
88  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
89 
90  ArgInfo.PrivateSegmentBuffer =
91  ArgDescriptor::createRegister(ScratchRSrcReg);
92  }
93 
94  if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
95  ImplicitArgPtr = true;
96  } else {
97  ImplicitArgPtr = false;
98  MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
100  }
101 
102  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
103  if (isAmdHsaOrMesa && !ST.enableFlatScratch())
104  PrivateSegmentBuffer = true;
105  else if (ST.isMesaGfxShader(F))
106  ImplicitBufferPtr = true;
107 
108  if (!AMDGPU::isGraphics(CC)) {
109  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
110  WorkGroupIDX = true;
111 
112  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
113  WorkGroupIDY = true;
114 
115  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
116  WorkGroupIDZ = true;
117 
118  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
119  WorkItemIDX = true;
120 
121  if (!F.hasFnAttribute("amdgpu-no-workitem-id-y"))
122  WorkItemIDY = true;
123 
124  if (!F.hasFnAttribute("amdgpu-no-workitem-id-z"))
125  WorkItemIDZ = true;
126 
127  if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
128  DispatchPtr = true;
129 
130  if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
131  QueuePtr = true;
132 
133  if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
134  DispatchID = true;
135  }
136 
137  // FIXME: This attribute is a hack, we just need an analysis on the function
138  // to look for allocas.
139  bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
140 
141  // TODO: This could be refined a lot. The attribute is a poor way of
142  // detecting calls or stack objects that may require it before argument
143  // lowering.
144  if (ST.hasFlatAddressSpace() && isEntryFunction() &&
145  (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
146  (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
147  !ST.flatScratchIsArchitected()) {
148  FlatScratchInit = true;
149  }
150 
151  if (isEntryFunction()) {
152  // X, XY, and XYZ are the only supported combinations, so make sure Y is
153  // enabled if Z is.
154  if (WorkItemIDZ)
155  WorkItemIDY = true;
156 
157  if (!ST.flatScratchIsArchitected()) {
158  PrivateSegmentWaveByteOffset = true;
159 
160  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
161  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
164  ArgDescriptor::createRegister(AMDGPU::SGPR5);
165  }
166  }
167 
168  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
169  StringRef S = A.getValueAsString();
170  if (!S.empty())
171  S.consumeInteger(0, GITPtrHigh);
172 
173  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
174  S = A.getValueAsString();
175  if (!S.empty())
176  S.consumeInteger(0, HighBitsOf32BitAddress);
177 
178  S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
179  if (!S.empty())
180  S.consumeInteger(0, GDSSize);
181 }
182 
185  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
186  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
187  MF.getFunction()));
188 }
189 
191  const SIRegisterInfo &TRI) {
192  ArgInfo.PrivateSegmentBuffer =
194  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
195  NumUserSGPRs += 4;
196  return ArgInfo.PrivateSegmentBuffer.getRegister();
197 }
198 
201  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
202  NumUserSGPRs += 2;
203  return ArgInfo.DispatchPtr.getRegister();
204 }
205 
208  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
209  NumUserSGPRs += 2;
210  return ArgInfo.QueuePtr.getRegister();
211 }
212 
214  ArgInfo.KernargSegmentPtr
216  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
217  NumUserSGPRs += 2;
218  return ArgInfo.KernargSegmentPtr.getRegister();
219 }
220 
223  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
224  NumUserSGPRs += 2;
225  return ArgInfo.DispatchID.getRegister();
226 }
227 
230  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
231  NumUserSGPRs += 2;
232  return ArgInfo.FlatScratchInit.getRegister();
233 }
234 
237  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
238  NumUserSGPRs += 2;
239  return ArgInfo.ImplicitBufferPtr.getRegister();
240 }
241 
243  MCPhysReg Reg) {
244  for (unsigned I = 0; CSRegs[I]; ++I) {
245  if (CSRegs[I] == Reg)
246  return true;
247  }
248 
249  return false;
250 }
251 
252 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
253 /// SGPR spilling.
254 //
255 // FIXME: This only works after processFunctionBeforeFrameFinalized
257  unsigned NumNeed) const {
258  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
259  unsigned WaveSize = ST.getWavefrontSize();
260  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
261 }
262 
263 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
265  int FI) {
266  std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
267 
268  // This has already been allocated.
269  if (!SpillLanes.empty())
270  return true;
271 
272  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
273  const SIRegisterInfo *TRI = ST.getRegisterInfo();
274  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
276  unsigned WaveSize = ST.getWavefrontSize();
277 
278  unsigned Size = FrameInfo.getObjectSize(FI);
279  unsigned NumLanes = Size / 4;
280 
281  if (NumLanes > WaveSize)
282  return false;
283 
284  assert(Size >= 4 && "invalid sgpr spill size");
285  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
286 
287  // Make sure to handle the case where a wide SGPR spill may span between two
288  // VGPRs.
289  for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
290  Register LaneVGPR;
291  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
292 
293  if (VGPRIndex == 0) {
294  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
295  if (LaneVGPR == AMDGPU::NoRegister) {
296  // We have no VGPRs left for spilling SGPRs. Reset because we will not
297  // partially spill the SGPR to VGPRs.
298  SGPRToVGPRSpills.erase(FI);
299  NumVGPRSpillLanes -= I;
300 
301  // FIXME: We can run out of free registers with split allocation if
302  // IPRA is enabled and a called function already uses every VGPR.
303 #if 0
304  DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
305  "VGPRs for SGPR spilling",
306  0, DS_Error);
307  MF.getFunction().getContext().diagnose(DiagOutOfRegs);
308 #endif
309  return false;
310  }
311 
312  Optional<int> SpillFI;
313  // We need to preserve inactive lanes, so always save, even caller-save
314  // registers.
315  if (!isEntryFunction()) {
316  SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
317  }
318 
319  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
320 
321  // Add this register as live-in to all blocks to avoid machine verifer
322  // complaining about use of an undefined physical register.
323  for (MachineBasicBlock &BB : MF)
324  BB.addLiveIn(LaneVGPR);
325  } else {
326  LaneVGPR = SpillVGPRs.back().VGPR;
327  }
328 
329  SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
330  }
331 
332  return true;
333 }
334 
335 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
336 /// Either AGPR is spilled to VGPR to vice versa.
337 /// Returns true if a \p FI can be eliminated completely.
339  int FI,
340  bool isAGPRtoVGPR) {
342  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
343  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
344 
345  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
346 
347  auto &Spill = VGPRToAGPRSpills[FI];
348 
349  // This has already been allocated.
350  if (!Spill.Lanes.empty())
351  return Spill.FullyAllocated;
352 
353  unsigned Size = FrameInfo.getObjectSize(FI);
354  unsigned NumLanes = Size / 4;
355  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
356 
357  const TargetRegisterClass &RC =
358  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
359  auto Regs = RC.getRegisters();
360 
361  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
362  const SIRegisterInfo *TRI = ST.getRegisterInfo();
363  Spill.FullyAllocated = true;
364 
365  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
366  // once.
367  BitVector OtherUsedRegs;
368  OtherUsedRegs.resize(TRI->getNumRegs());
369 
370  const uint32_t *CSRMask =
372  if (CSRMask)
373  OtherUsedRegs.setBitsInMask(CSRMask);
374 
375  // TODO: Should include register tuples, but doesn't matter with current
376  // usage.
377  for (MCPhysReg Reg : SpillAGPR)
378  OtherUsedRegs.set(Reg);
379  for (MCPhysReg Reg : SpillVGPR)
380  OtherUsedRegs.set(Reg);
381 
382  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
383  for (int I = NumLanes - 1; I >= 0; --I) {
384  NextSpillReg = std::find_if(
385  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
386  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
387  !OtherUsedRegs[Reg];
388  });
389 
390  if (NextSpillReg == Regs.end()) { // Registers exhausted
391  Spill.FullyAllocated = false;
392  break;
393  }
394 
395  OtherUsedRegs.set(*NextSpillReg);
396  SpillRegs.push_back(*NextSpillReg);
397  Spill.Lanes[I] = *NextSpillReg++;
398  }
399 
400  return Spill.FullyAllocated;
401 }
402 
404  // Remove dead frame indices from function frame, however keep FP & BP since
405  // spills for them haven't been inserted yet. And also make sure to remove the
406  // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
407  // result in an unexpected side effect and bug, in case of any re-mapping of
408  // freed frame indices by later pass(es) like "stack slot coloring".
409  for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
410  if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
411  MFI.RemoveStackObject(R.first);
412  SGPRToVGPRSpills.erase(R.first);
413  }
414  }
415 
416  // All other SPGRs must be allocated on the default stack, so reset the stack
417  // ID.
418  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
419  ++i)
422 
423  for (auto &R : VGPRToAGPRSpills) {
424  if (R.second.IsDead)
425  MFI.RemoveStackObject(R.first);
426  }
427 }
428 
430  const SIRegisterInfo &TRI) {
431  if (ScavengeFI)
432  return *ScavengeFI;
433  if (isEntryFunction()) {
434  ScavengeFI = MFI.CreateFixedObject(
435  TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
436  } else {
437  ScavengeFI = MFI.CreateStackObject(
438  TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
439  TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
440  }
441  return *ScavengeFI;
442 }
443 
444 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
445  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
446  return AMDGPU::SGPR0 + NumUserSGPRs;
447 }
448 
449 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
450  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
451 }
452 
453 Register
455  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
456  if (!ST.isAmdPalOS())
457  return Register();
458  Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
459  if (ST.hasMergedShaders()) {
460  switch (MF.getFunction().getCallingConv()) {
463  // Low GIT address is passed in s8 rather than s0 for an LS+HS or
464  // ES+GS merged shader on gfx9+.
465  GitPtrLo = AMDGPU::SGPR8;
466  return GitPtrLo;
467  default:
468  return GitPtrLo;
469  }
470  }
471  return GitPtrLo;
472 }
473 
475  const TargetRegisterInfo &TRI) {
476  yaml::StringValue Dest;
477  {
478  raw_string_ostream OS(Dest.Value);
479  OS << printReg(Reg, &TRI);
480  }
481  return Dest;
482 }
483 
486  const TargetRegisterInfo &TRI) {
488 
489  auto convertArg = [&](Optional<yaml::SIArgument> &A,
490  const ArgDescriptor &Arg) {
491  if (!Arg)
492  return false;
493 
494  // Create a register or stack argument.
496  if (Arg.isRegister()) {
498  OS << printReg(Arg.getRegister(), &TRI);
499  } else
500  SA.StackOffset = Arg.getStackOffset();
501  // Check and update the optional mask.
502  if (Arg.isMasked())
503  SA.Mask = Arg.getMask();
504 
505  A = SA;
506  return true;
507  };
508 
509  bool Any = false;
510  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
511  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
512  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
513  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
514  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
515  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
516  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
517  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
518  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
519  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
520  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
521  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
523  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
524  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
525  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
526  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
527  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
528 
529  if (Any)
530  return AI;
531 
532  return None;
533 }
534 
537  const llvm::MachineFunction &MF)
538  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
539  MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
540  DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
541  NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
542  MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
543  HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
544  HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
545  HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
546  Occupancy(MFI.getOccupancy()),
547  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
548  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
549  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
550  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
551  auto SFI = MFI.getOptionalScavengeFI();
552  if (SFI)
554 }
555 
558 }
559 
561  const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
562  PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
565  LDSSize = YamlMFI.LDSSize;
566  DynLDSAlign = YamlMFI.DynLDSAlign;
568  Occupancy = YamlMFI.Occupancy;
571  MemoryBound = YamlMFI.MemoryBound;
572  WaveLimiter = YamlMFI.WaveLimiter;
575 
576  if (YamlMFI.ScavengeFI) {
577  auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
578  if (!FIOrErr) {
579  // Create a diagnostic for a the frame index.
580  const MemoryBuffer &Buffer =
581  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
582 
583  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
584  SourceMgr::DK_Error, toString(FIOrErr.takeError()),
585  "", None, None);
586  SourceRange = YamlMFI.ScavengeFI->SourceRange;
587  return true;
588  }
589  ScavengeFI = *FIOrErr;
590  } else {
591  ScavengeFI = None;
592  }
593  return false;
594 }
595 
597  if (UsesAGPRs)
598  return *UsesAGPRs;
599 
601  MF.getFrameInfo().hasCalls()) {
602  UsesAGPRs = true;
603  return true;
604  }
605 
606  const MachineRegisterInfo &MRI = MF.getRegInfo();
607 
608  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
611  if (RC && SIRegisterInfo::isAGPRClass(RC)) {
612  UsesAGPRs = true;
613  return true;
614  } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
615  // Defer caching UsesAGPRs, function might not yet been regbank selected.
616  return true;
617  }
618  }
619 
620  for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
621  if (MRI.isPhysRegUsed(Reg)) {
622  UsesAGPRs = true;
623  return true;
624  }
625  }
626 
627  UsesAGPRs = false;
628  return false;
629 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
regToString
static yaml::StringValue regToString(Register Reg, const TargetRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:474
llvm::yaml::SIMachineFunctionInfo::HighBitsOf32BitAddress
uint32_t HighBitsOf32BitAddress
Definition: SIMachineFunctionInfo.h:281
llvm::AMDGPUFunctionArgInfo::QueuePtr
ArgDescriptor QueuePtr
Definition: AMDGPUArgumentUsageInfo.h:126
llvm::SIRegisterInfo::isAGPRClass
static bool isAGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:191
llvm::BitVector::push_back
void push_back(bool Val)
Definition: BitVector.h:452
llvm::PerFunctionMIParsingState::SM
SourceMgr * SM
Definition: MIParser.h:165
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:583
convertArgumentInfo
static Optional< yaml::SIArgumentInfo > convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, const TargetRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:485
Optional.h
llvm::SIMachineFunctionInfo::isCalleeSavedReg
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg)
Definition: SIMachineFunctionInfo.cpp:242
SIMachineFunctionInfo.h
llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign
unsigned MaxKernArgAlign
Definition: SIMachineFunctionInfo.h:272
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::yaml::SIArgumentInfo::WorkGroupIDX
Optional< SIArgument > WorkGroupIDX
Definition: SIMachineFunctionInfo.h:189
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:62
llvm::Attribute
Definition: Attributes.h:53
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::yaml::SIArgumentInfo::DispatchPtr
Optional< SIArgument > DispatchPtr
Definition: SIMachineFunctionInfo.h:182
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:631
llvm::SIMachineFunctionInfo::addDispatchPtr
Register addDispatchPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:199
llvm::toString
std::string toString(Error E)
Write all error messages (if any) in E to a string.
Definition: Error.h:1030
llvm::yaml::SIArgumentInfo::PrivateSegmentWaveByteOffset
Optional< SIArgument > PrivateSegmentWaveByteOffset
Definition: SIMachineFunctionInfo.h:193
llvm::AMDGPUSubtarget::GFX9
@ GFX9
Definition: AMDGPUSubtarget.h:40
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::yaml::SIArgumentInfo
Definition: SIMachineFunctionInfo.h:180
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:166
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPR
bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI)
Reserve a slice of a VGPR to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:264
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::SIMachineFunctionInfo::addFlatScratchInit
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:228
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:270
llvm::AMDGPUMachineFunction::getLDSSize
unsigned getLDSSize() const
Definition: AMDGPUMachineFunction.h:68
llvm::yaml::SIArgumentInfo::WorkItemIDY
Optional< SIArgument > WorkItemIDY
Definition: SIMachineFunctionInfo.h:199
YamlIO
IO & YamlIO
Definition: ELFYAML.cpp:1197
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::Optional< int >
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::MachineFrameInfo::RemoveStackObject
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
Definition: MachineFrameInfo.h:744
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:393
llvm::yaml::MappingTraits
Definition: ModuleSummaryIndex.h:52
llvm::yaml::SIArgument
Definition: SIMachineFunctionInfo.h:112
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
HasCalls
@ HasCalls
Definition: AArch64InstrInfo.cpp:6536
llvm::SIMachineFunctionInfo::SpilledReg
Definition: SIMachineFunctionInfo.h:443
llvm::MemoryBuffer
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:50
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:128
MachineRegisterInfo.h
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:141
llvm::yaml::SIArgumentInfo::WorkItemIDZ
Optional< SIArgument > WorkItemIDZ
Definition: SIMachineFunctionInfo.h:200
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:185
llvm::yaml::SIMachineFunctionInfo::mappingImpl
void mappingImpl(yaml::IO &YamlIO) override
Definition: SIMachineFunctionInfo.cpp:556
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:133
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::AMDGPUFunctionArgInfo
Definition: AMDGPUArgumentUsageInfo.h:97
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::yaml::SIMachineFunctionInfo::HasSpilledVGPRs
bool HasSpilledVGPRs
Definition: SIMachineFunctionInfo.h:280
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:207
llvm::yaml::SIMachineFunctionInfo::IsEntryFunction
bool IsEntryFunction
Definition: SIMachineFunctionInfo.h:275
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:251
AMDGPUSubtarget.h
llvm::DiagnosticInfoResourceLimit
Diagnostic information for stack size etc.
Definition: DiagnosticInfo.h:181
false
Definition: StackSlotColoring.cpp:142
llvm::yaml::SIArgumentInfo::DispatchID
Optional< SIArgument > DispatchID
Definition: SIMachineFunctionInfo.h:185
llvm::yaml::SIArgumentInfo::WorkItemIDX
Optional< SIArgument > WorkItemIDX
Definition: SIMachineFunctionInfo.h:198
llvm::yaml::SIMachineFunctionInfo::ExplicitKernArgSize
uint64_t ExplicitKernArgSize
Definition: SIMachineFunctionInfo.h:271
llvm::yaml::SIArgument::RegisterName
StringValue RegisterName
Definition: SIMachineFunctionInfo.h:115
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1345
llvm::SIMachineFunctionInfo::usesAGPRs
bool usesAGPRs(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:596
llvm::SourceMgr::getMainFileID
unsigned getMainFileID() const
Definition: SourceMgr.h:129
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:74
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:390
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::yaml::SIMachineFunctionInfo::WaveLimiter
bool WaveLimiter
Definition: SIMachineFunctionInfo.h:278
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1383
llvm::SourceMgr::getMemoryBuffer
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:122
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::MemoryBuffer::getBufferIdentifier
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:75
llvm::SIMachineFunctionInfo::addDispatchID
Register addDispatchID(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:221
llvm::SIMachineFunctionInfo::haveFreeLanesForSGPRSpill
bool haveFreeLanesForSGPRSpill(const MachineFunction &MF, unsigned NumLane) const
returns true if NumLanes slots are available in VGPRs already used for SGPR spilling.
Definition: SIMachineFunctionInfo.cpp:256
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:288
llvm::yaml::SIArgument::createArgument
static SIArgument createArgument(bool IsReg)
Definition: SIMachineFunctionInfo.h:147
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::yaml::SIMachineFunctionInfo::NoSignedZerosFPMath
bool NoSignedZerosFPMath
Definition: SIMachineFunctionInfo.h:276
llvm::SIMachineFunctionInfo::addKernargSegmentPtr
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:213
llvm::yaml::SIArgumentInfo::WorkGroupIDZ
Optional< SIArgument > WorkGroupIDZ
Definition: SIMachineFunctionInfo.h:191
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
AMDGPUMCTargetDesc.h
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
LiveIntervals.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:240
llvm::SIMachineFunctionInfo::addPrivateSegmentBuffer
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:190
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:124
llvm::SIMachineFunctionInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU() const
Definition: SIMachineFunctionInfo.h:886
llvm::SIMachineFunctionInfo::getOptionalScavengeFI
Optional< int > getOptionalScavengeFI() const
Definition: SIMachineFunctionInfo.h:561
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
Definition: SIMachineFunctionInfo.cpp:560
llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo()=default
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:577
llvm::assumeAligned
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
Definition: Alignment.h:103
llvm::SIMachineFunctionInfo::FramePointerSaveIndex
Optional< int > FramePointerSaveIndex
Definition: SIMachineFunctionInfo.h:498
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::AMDGPUMachineFunction::isEntryFunction
bool isEntryFunction() const
Definition: AMDGPUMachineFunction.h:76
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:642
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::yaml::SIMachineFunctionInfo::ScavengeFI
Optional< FrameIndex > ScavengeFI
Definition: SIMachineFunctionInfo.h:292
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:134
llvm::yaml::SIMachineFunctionInfo::LDSSize
unsigned LDSSize
Definition: SIMachineFunctionInfo.h:273
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
llvm::SIMachineFunctionInfo::getScavengeFI
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:429
llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:338
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::SIMachineFunctionInfo::getGITPtrLoReg
Register getGITPtrLoReg(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:454
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::yaml::SIMachineFunctionInfo::MemoryBound
bool MemoryBound
Definition: SIMachineFunctionInfo.h:277
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:32
llvm::MachineFrameInfo::setStackID
void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:704
llvm::CallingConv::AMDGPU_HS
@ AMDGPU_HS
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:223
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
uint32_t
llvm::SIMachineFunctionInfo::limitOccupancy
void limitOccupancy(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:183
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::yaml::SIArgumentInfo::ImplicitBufferPtr
Optional< SIArgument > ImplicitBufferPtr
Definition: SIMachineFunctionInfo.h:196
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1375
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:144
llvm::SIMachineFunctionInfo::addImplicitBufferPtr
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:235
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1676
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:581
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
CallingConv.h
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::LLVMContext::diagnose
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:228
llvm::yaml::SIMachineFunctionInfo::Occupancy
unsigned Occupancy
Definition: SIMachineFunctionInfo.h:284
llvm::Any
Definition: Any.h:26
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::yaml::SIArgumentInfo::WorkGroupInfo
Optional< SIArgument > WorkGroupInfo
Definition: SIMachineFunctionInfo.h:192
uint16_t
llvm::SIMachineFunctionInfo::addQueuePtr
Register addQueuePtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:206
llvm::yaml::SIArgumentInfo::ImplicitArgPtr
Optional< SIArgument > ImplicitArgPtr
Definition: SIMachineFunctionInfo.h:195
llvm::yaml::SIArgumentInfo::KernargSegmentPtr
Optional< SIArgument > KernargSegmentPtr
Definition: SIMachineFunctionInfo.h:184
llvm::yaml::SIArgumentInfo::WorkGroupIDY
Optional< SIArgument > WorkGroupIDY
Definition: SIMachineFunctionInfo.h:190
MachineFrameInfo.h
llvm::SIMachineFunctionInfo::BasePointerSaveIndex
Optional< int > BasePointerSaveIndex
Definition: SIMachineFunctionInfo.h:503
llvm::yaml::StringValue::Value
std::string Value
Definition: MIRYamlMapping.h:35
llvm::yaml::SIArgumentInfo::PrivateSegmentSize
Optional< SIArgument > PrivateSegmentSize
Definition: SIMachineFunctionInfo.h:187
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:687
DiagnosticInfo.h
Function.h
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:686
llvm::yaml::SIArgumentInfo::PrivateSegmentBuffer
Optional< SIArgument > PrivateSegmentBuffer
Definition: SIMachineFunctionInfo.h:181
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:152
llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs
bool HasSpilledSGPRs
Definition: SIMachineFunctionInfo.h:279
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:250
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
void removeDeadFrameIndices(MachineFrameInfo &MFI)
Definition: SIMachineFunctionInfo.cpp:403
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::ArgDescriptor::getRegister
MCRegister getRegister() const
Definition: AMDGPUArgumentUsageInfo.h:71
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::yaml::SIMachineFunctionInfo::DynLDSAlign
Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:274
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::yaml::SIArgument::StackOffset
unsigned StackOffset
Definition: SIMachineFunctionInfo.h:116
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::SIMachineFunctionInfo::SGPRSpillVGPR
Definition: SIMachineFunctionInfo.h:454
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:18
llvm::AMDGPUMachineFunction::MaxKernArgAlign
Align MaxKernArgAlign
Definition: AMDGPUMachineFunction.h:25
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:118
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:46
SIRegisterInfo.h
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:186
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
AMDGPUTargetMachine.h
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:82
MIParser.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:183
AMDGPUBaseInfo.h