LLVM 18.0.0git
SIMachineFunctionInfo.cpp
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1//===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "AMDGPUSubtarget.h"
11#include "AMDGPUTargetMachine.h"
12#include "GCNSubtarget.h"
14#include "SIRegisterInfo.h"
22#include "llvm/IR/CallingConv.h"
24#include "llvm/IR/Function.h"
25#include <cassert>
26#include <optional>
27#include <vector>
28
29#define MAX_LANES 64
30
31using namespace llvm;
32
34 const SITargetLowering *TLI = STI->getTargetLowering();
35 return static_cast<const GCNTargetMachine &>(TLI->getTargetMachine());
36}
37
39 const GCNSubtarget *STI)
40 : AMDGPUMachineFunction(F, *STI), Mode(F), GWSResourcePSV(getTM(STI)),
41 UserSGPRInfo(F, *STI), WorkGroupIDX(false), WorkGroupIDY(false),
42 WorkGroupIDZ(false), WorkGroupInfo(false), LDSKernelId(false),
43 PrivateSegmentWaveByteOffset(false), WorkItemIDX(false),
44 WorkItemIDY(false), WorkItemIDZ(false), ImplicitArgPtr(false),
45 GITPtrHigh(0xffffffff), HighBitsOf32BitAddress(0) {
46 const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI);
47 FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
48 WavesPerEU = ST.getWavesPerEU(F);
49
50 Occupancy = ST.computeOccupancy(F, getLDSSize());
51 CallingConv::ID CC = F.getCallingConv();
52
53 VRegFlags.reserve(1024);
54
55 const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
57
58 if (IsKernel) {
59 WorkGroupIDX = true;
60 WorkItemIDX = true;
61 } else if (CC == CallingConv::AMDGPU_PS) {
62 PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
63 }
64
65 MayNeedAGPRs = ST.hasMAIInsts();
66
67 if (AMDGPU::isChainCC(CC)) {
68 // Chain functions don't receive an SP from their caller, but are free to
69 // set one up. For now, we can use s32 to match what amdgpu_gfx functions
70 // would use if called, but this can be revisited.
71 // FIXME: Only reserve this if we actually need it.
72 StackPtrOffsetReg = AMDGPU::SGPR32;
73
74 ScratchRSrcReg = AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51;
75
76 ArgInfo.PrivateSegmentBuffer =
77 ArgDescriptor::createRegister(ScratchRSrcReg);
78
79 ImplicitArgPtr = false;
80 } else if (!isEntryFunction()) {
83
84 // TODO: Pick a high register, and shift down, similar to a kernel.
85 FrameOffsetReg = AMDGPU::SGPR33;
86 StackPtrOffsetReg = AMDGPU::SGPR32;
87
88 if (!ST.enableFlatScratch()) {
89 // Non-entry functions have no special inputs for now, other registers
90 // required for scratch access.
91 ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
92
93 ArgInfo.PrivateSegmentBuffer =
94 ArgDescriptor::createRegister(ScratchRSrcReg);
95 }
96
97 if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
98 ImplicitArgPtr = true;
99 } else {
100 ImplicitArgPtr = false;
101 MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
103
104 if (ST.hasGFX90AInsts() &&
105 ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
106 !mayUseAGPRs(F))
107 MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
108 }
109
110 if (!AMDGPU::isGraphics(CC) ||
111 (CC == CallingConv::AMDGPU_CS && ST.hasArchitectedSGPRs())) {
112 if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
113 WorkGroupIDX = true;
114
115 if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
116 WorkGroupIDY = true;
117
118 if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
119 WorkGroupIDZ = true;
120 }
121
122 if (!AMDGPU::isGraphics(CC)) {
123 if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
124 WorkItemIDX = true;
125
126 if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
127 ST.getMaxWorkitemID(F, 1) != 0)
128 WorkItemIDY = true;
129
130 if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
131 ST.getMaxWorkitemID(F, 2) != 0)
132 WorkItemIDZ = true;
133
134 if (!IsKernel && !F.hasFnAttribute("amdgpu-no-lds-kernel-id"))
135 LDSKernelId = true;
136 }
137
138 if (isEntryFunction()) {
139 // X, XY, and XYZ are the only supported combinations, so make sure Y is
140 // enabled if Z is.
141 if (WorkItemIDZ)
142 WorkItemIDY = true;
143
144 if (!ST.flatScratchIsArchitected()) {
145 PrivateSegmentWaveByteOffset = true;
146
147 // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
148 if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
150 ArgInfo.PrivateSegmentWaveByteOffset =
151 ArgDescriptor::createRegister(AMDGPU::SGPR5);
152 }
153 }
154
155 Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
156 StringRef S = A.getValueAsString();
157 if (!S.empty())
158 S.consumeInteger(0, GITPtrHigh);
159
160 A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
161 S = A.getValueAsString();
162 if (!S.empty())
163 S.consumeInteger(0, HighBitsOf32BitAddress);
164
165 // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
166 // VGPR available at all times. For now, reserve highest available VGPR. After
167 // RA, shift it to the lowest available unused VGPR if the one exist.
168 if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
169 VGPRForAGPRCopy =
170 AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
171 }
172}
173
175 BumpPtrAllocator &Allocator, MachineFunction &DestMF,
177 const {
178 return DestMF.cloneInfo<SIMachineFunctionInfo>(*this);
179}
180
183 const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
184 limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
185 MF.getFunction()));
186}
187
189 const SIRegisterInfo &TRI) {
190 ArgInfo.PrivateSegmentBuffer =
191 ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
192 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
193 NumUserSGPRs += 4;
194 return ArgInfo.PrivateSegmentBuffer.getRegister();
195}
196
198 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
199 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
200 NumUserSGPRs += 2;
201 return ArgInfo.DispatchPtr.getRegister();
202}
203
205 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
206 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
207 NumUserSGPRs += 2;
208 return ArgInfo.QueuePtr.getRegister();
209}
210
212 ArgInfo.KernargSegmentPtr
213 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
214 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
215 NumUserSGPRs += 2;
216 return ArgInfo.KernargSegmentPtr.getRegister();
217}
218
220 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
221 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
222 NumUserSGPRs += 2;
223 return ArgInfo.DispatchID.getRegister();
224}
225
227 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
228 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
229 NumUserSGPRs += 2;
230 return ArgInfo.FlatScratchInit.getRegister();
231}
232
234 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
235 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
236 NumUserSGPRs += 2;
237 return ArgInfo.ImplicitBufferPtr.getRegister();
238}
239
241 ArgInfo.LDSKernelId = ArgDescriptor::createRegister(getNextUserSGPR());
242 NumUserSGPRs += 1;
243 return ArgInfo.LDSKernelId.getRegister();
244}
245
247 uint64_t Size, Align Alignment) {
248 // Skip if it is an entry function or the register is already added.
249 if (isEntryFunction() || WWMSpills.count(VGPR))
250 return;
251
252 WWMSpills.insert(std::make_pair(
253 VGPR, MF.getFrameInfo().CreateSpillStackObject(Size, Alignment)));
254}
255
256// Separate out the callee-saved and scratch registers.
258 MachineFunction &MF,
259 SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
260 SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const {
261 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
262 for (auto &Reg : WWMSpills) {
263 if (isCalleeSavedReg(CSRegs, Reg.first))
264 CalleeSavedRegs.push_back(Reg);
265 else
266 ScratchRegs.push_back(Reg);
267 }
268}
269
271 MCPhysReg Reg) const {
272 for (unsigned I = 0; CSRegs[I]; ++I) {
273 if (CSRegs[I] == Reg)
274 return true;
275 }
276
277 return false;
278}
279
280bool SIMachineFunctionInfo::allocateVirtualVGPRForSGPRSpills(
281 MachineFunction &MF, int FI, unsigned LaneIndex) {
283 Register LaneVGPR;
284 if (!LaneIndex) {
285 LaneVGPR = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
286 SpillVGPRs.push_back(LaneVGPR);
287 } else {
288 LaneVGPR = SpillVGPRs.back();
289 }
290
291 SGPRSpillsToVirtualVGPRLanes[FI].push_back(
292 SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
293 return true;
294}
295
296bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills(
297 MachineFunction &MF, int FI, unsigned LaneIndex) {
299 const SIRegisterInfo *TRI = ST.getRegisterInfo();
301 Register LaneVGPR;
302 if (!LaneIndex) {
303 LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
304 if (LaneVGPR == AMDGPU::NoRegister) {
305 // We have no VGPRs left for spilling SGPRs. Reset because we will not
306 // partially spill the SGPR to VGPRs.
307 SGPRSpillsToPhysicalVGPRLanes.erase(FI);
308 return false;
309 }
310
311 allocateWWMSpill(MF, LaneVGPR);
312 reserveWWMRegister(LaneVGPR);
313 for (MachineBasicBlock &MBB : MF) {
314 MBB.addLiveIn(LaneVGPR);
316 }
317 } else {
318 LaneVGPR = WWMReservedRegs.back();
319 }
320
321 SGPRSpillsToPhysicalVGPRLanes[FI].push_back(
322 SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
323 return true;
324}
325
327 int FI,
328 bool IsPrologEpilog) {
329 std::vector<SIRegisterInfo::SpilledReg> &SpillLanes =
330 IsPrologEpilog ? SGPRSpillsToPhysicalVGPRLanes[FI]
331 : SGPRSpillsToVirtualVGPRLanes[FI];
332
333 // This has already been allocated.
334 if (!SpillLanes.empty())
335 return true;
336
337 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
338 MachineFrameInfo &FrameInfo = MF.getFrameInfo();
339 unsigned WaveSize = ST.getWavefrontSize();
340
341 unsigned Size = FrameInfo.getObjectSize(FI);
342 unsigned NumLanes = Size / 4;
343
344 if (NumLanes > WaveSize)
345 return false;
346
347 assert(Size >= 4 && "invalid sgpr spill size");
348 assert(ST.getRegisterInfo()->spillSGPRToVGPR() &&
349 "not spilling SGPRs to VGPRs");
350
351 unsigned &NumSpillLanes =
352 IsPrologEpilog ? NumPhysicalVGPRSpillLanes : NumVirtualVGPRSpillLanes;
353
354 for (unsigned I = 0; I < NumLanes; ++I, ++NumSpillLanes) {
355 unsigned LaneIndex = (NumSpillLanes % WaveSize);
356
357 bool Allocated = IsPrologEpilog
358 ? allocatePhysicalVGPRForSGPRSpills(MF, FI, LaneIndex)
359 : allocateVirtualVGPRForSGPRSpills(MF, FI, LaneIndex);
360 if (!Allocated) {
361 NumSpillLanes -= I;
362 return false;
363 }
364 }
365
366 return true;
367}
368
369/// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
370/// Either AGPR is spilled to VGPR to vice versa.
371/// Returns true if a \p FI can be eliminated completely.
373 int FI,
374 bool isAGPRtoVGPR) {
376 MachineFrameInfo &FrameInfo = MF.getFrameInfo();
377 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
378
379 assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
380
381 auto &Spill = VGPRToAGPRSpills[FI];
382
383 // This has already been allocated.
384 if (!Spill.Lanes.empty())
385 return Spill.FullyAllocated;
386
387 unsigned Size = FrameInfo.getObjectSize(FI);
388 unsigned NumLanes = Size / 4;
389 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
390
391 const TargetRegisterClass &RC =
392 isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
393 auto Regs = RC.getRegisters();
394
395 auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
396 const SIRegisterInfo *TRI = ST.getRegisterInfo();
397 Spill.FullyAllocated = true;
398
399 // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
400 // once.
401 BitVector OtherUsedRegs;
402 OtherUsedRegs.resize(TRI->getNumRegs());
403
404 const uint32_t *CSRMask =
405 TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
406 if (CSRMask)
407 OtherUsedRegs.setBitsInMask(CSRMask);
408
409 // TODO: Should include register tuples, but doesn't matter with current
410 // usage.
411 for (MCPhysReg Reg : SpillAGPR)
412 OtherUsedRegs.set(Reg);
413 for (MCPhysReg Reg : SpillVGPR)
414 OtherUsedRegs.set(Reg);
415
416 SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
417 for (int I = NumLanes - 1; I >= 0; --I) {
418 NextSpillReg = std::find_if(
419 NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
420 return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
421 !OtherUsedRegs[Reg];
422 });
423
424 if (NextSpillReg == Regs.end()) { // Registers exhausted
425 Spill.FullyAllocated = false;
426 break;
427 }
428
429 OtherUsedRegs.set(*NextSpillReg);
430 SpillRegs.push_back(*NextSpillReg);
431 MRI.reserveReg(*NextSpillReg, TRI);
432 Spill.Lanes[I] = *NextSpillReg++;
433 }
434
435 return Spill.FullyAllocated;
436}
437
439 MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
440 // Remove dead frame indices from function frame, however keep FP & BP since
441 // spills for them haven't been inserted yet. And also make sure to remove the
442 // frame indices from `SGPRSpillsToVirtualVGPRLanes` data structure,
443 // otherwise, it could result in an unexpected side effect and bug, in case of
444 // any re-mapping of freed frame indices by later pass(es) like "stack slot
445 // coloring".
446 for (auto &R : make_early_inc_range(SGPRSpillsToVirtualVGPRLanes)) {
447 MFI.RemoveStackObject(R.first);
448 SGPRSpillsToVirtualVGPRLanes.erase(R.first);
449 }
450
451 // Remove the dead frame indices of CSR SGPRs which are spilled to physical
452 // VGPR lanes during SILowerSGPRSpills pass.
453 if (!ResetSGPRSpillStackIDs) {
454 for (auto &R : make_early_inc_range(SGPRSpillsToPhysicalVGPRLanes)) {
455 MFI.RemoveStackObject(R.first);
456 SGPRSpillsToPhysicalVGPRLanes.erase(R.first);
457 }
458 }
459 bool HaveSGPRToMemory = false;
460
461 if (ResetSGPRSpillStackIDs) {
462 // All other SGPRs must be allocated on the default stack, so reset the
463 // stack ID.
464 for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd(); I != E;
465 ++I) {
469 HaveSGPRToMemory = true;
470 }
471 }
472 }
473 }
474
475 for (auto &R : VGPRToAGPRSpills) {
476 if (R.second.IsDead)
477 MFI.RemoveStackObject(R.first);
478 }
479
480 return HaveSGPRToMemory;
481}
482
484 const SIRegisterInfo &TRI) {
485 if (ScavengeFI)
486 return *ScavengeFI;
487 if (isEntryFunction()) {
488 ScavengeFI = MFI.CreateFixedObject(
489 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
490 } else {
491 ScavengeFI = MFI.CreateStackObject(
492 TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
493 TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
494 }
495 return *ScavengeFI;
496}
497
498MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
499 assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
500 return AMDGPU::SGPR0 + NumUserSGPRs;
501}
502
503MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
504 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
505}
506
507void SIMachineFunctionInfo::MRI_NoteNewVirtualRegister(Register Reg) {
508 VRegFlags.grow(Reg);
509}
510
511void SIMachineFunctionInfo::MRI_NoteCloneVirtualRegister(Register NewReg,
512 Register SrcReg) {
513 VRegFlags.grow(NewReg);
514 VRegFlags[NewReg] = VRegFlags[SrcReg];
515}
516
519 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
520 if (!ST.isAmdPalOS())
521 return Register();
522 Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
523 if (ST.hasMergedShaders()) {
524 switch (MF.getFunction().getCallingConv()) {
527 // Low GIT address is passed in s8 rather than s0 for an LS+HS or
528 // ES+GS merged shader on gfx9+.
529 GitPtrLo = AMDGPU::SGPR8;
530 return GitPtrLo;
531 default:
532 return GitPtrLo;
533 }
534 }
535 return GitPtrLo;
536}
537
539 const TargetRegisterInfo &TRI) {
541 {
543 OS << printReg(Reg, &TRI);
544 }
545 return Dest;
546}
547
548static std::optional<yaml::SIArgumentInfo>
550 const TargetRegisterInfo &TRI) {
552
553 auto convertArg = [&](std::optional<yaml::SIArgument> &A,
554 const ArgDescriptor &Arg) {
555 if (!Arg)
556 return false;
557
558 // Create a register or stack argument.
560 if (Arg.isRegister()) {
562 OS << printReg(Arg.getRegister(), &TRI);
563 } else
564 SA.StackOffset = Arg.getStackOffset();
565 // Check and update the optional mask.
566 if (Arg.isMasked())
567 SA.Mask = Arg.getMask();
568
569 A = SA;
570 return true;
571 };
572
573 bool Any = false;
574 Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
575 Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
576 Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
577 Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
578 Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
579 Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
580 Any |= convertArg(AI.LDSKernelId, ArgInfo.LDSKernelId);
581 Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
582 Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
583 Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
584 Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
585 Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
586 Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
587 ArgInfo.PrivateSegmentWaveByteOffset);
588 Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
589 Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
590 Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
591 Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
592 Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
593
594 if (Any)
595 return AI;
596
597 return std::nullopt;
598}
599
602 const llvm::MachineFunction &MF)
603 : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
604 MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
605 GDSSize(MFI.getGDSSize()),
606 DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
607 NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
608 MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
609 HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
610 HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
611 HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
612 Occupancy(MFI.getOccupancy()),
613 ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
614 FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
615 StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
616 BytesInStackArgArea(MFI.getBytesInStackArgArea()),
617 ReturnsVoid(MFI.returnsVoid()),
618 ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
619 PSInputAddr(MFI.getPSInputAddr()),
620 PSInputEnable(MFI.getPSInputEnable()),
621 Mode(MFI.getMode()) {
622 for (Register Reg : MFI.getWWMReservedRegs())
623 WWMReservedRegs.push_back(regToString(Reg, TRI));
624
625 if (MFI.getLongBranchReservedReg())
627 if (MFI.getVGPRForAGPRCopy())
629
630 if (MFI.getSGPRForEXECCopy())
632
633 auto SFI = MFI.getOptionalScavengeFI();
634 if (SFI)
636}
637
640}
641
643 const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
647 LDSSize = YamlMFI.LDSSize;
648 GDSSize = YamlMFI.GDSSize;
649 DynLDSAlign = YamlMFI.DynLDSAlign;
650 PSInputAddr = YamlMFI.PSInputAddr;
653 Occupancy = YamlMFI.Occupancy;
656 MemoryBound = YamlMFI.MemoryBound;
657 WaveLimiter = YamlMFI.WaveLimiter;
661 ReturnsVoid = YamlMFI.ReturnsVoid;
662
663 if (YamlMFI.ScavengeFI) {
664 auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
665 if (!FIOrErr) {
666 // Create a diagnostic for a the frame index.
667 const MemoryBuffer &Buffer =
668 *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
669
670 Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
671 SourceMgr::DK_Error, toString(FIOrErr.takeError()),
672 "", std::nullopt, std::nullopt);
673 SourceRange = YamlMFI.ScavengeFI->SourceRange;
674 return true;
675 }
676 ScavengeFI = *FIOrErr;
677 } else {
678 ScavengeFI = std::nullopt;
679 }
680 return false;
681}
682
684 for (const BasicBlock &BB : F) {
685 for (const Instruction &I : BB) {
686 const auto *CB = dyn_cast<CallBase>(&I);
687 if (!CB)
688 continue;
689
690 if (CB->isInlineAsm()) {
691 const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
692 for (const auto &CI : IA->ParseConstraints()) {
693 for (StringRef Code : CI.Codes) {
694 Code.consume_front("{");
695 if (Code.startswith("a"))
696 return true;
697 }
698 }
699 continue;
700 }
701
702 const Function *Callee =
703 dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
704 if (!Callee)
705 return true;
706
707 if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
708 return true;
709 }
710 }
711
712 return false;
713}
714
716 if (UsesAGPRs)
717 return *UsesAGPRs;
718
719 if (!mayNeedAGPRs()) {
720 UsesAGPRs = false;
721 return false;
722 }
723
725 MF.getFrameInfo().hasCalls()) {
726 UsesAGPRs = true;
727 return true;
728 }
729
730 const MachineRegisterInfo &MRI = MF.getRegInfo();
731
732 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
734 const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
735 if (RC && SIRegisterInfo::isAGPRClass(RC)) {
736 UsesAGPRs = true;
737 return true;
738 } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
739 // Defer caching UsesAGPRs, function might not yet been regbank selected.
740 return true;
741 }
742 }
743
744 for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
745 if (MRI.isPhysRegUsed(Reg)) {
746 UsesAGPRs = true;
747 return true;
748 }
749 }
750
751 UsesAGPRs = false;
752 return false;
753}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
Provides AMDGPU specific target descriptions.
Base class for AMDGPU specific classes of TargetSubtarget.
The AMDGPU TargetMachine interface definition for hw codegen targets.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
uint64_t Size
IO & YamlIO
Definition: ELFYAML.cpp:1271
AMD GCN specific subclass of TargetSubtarget.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const GCNTargetMachine & getTM(const GCNSubtarget *STI)
static std::optional< yaml::SIArgumentInfo > convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, const TargetRegisterInfo &TRI)
static yaml::StringValue regToString(Register Reg, const TargetRegisterInfo &TRI)
Interface definition for SIRegisterInfo.
raw_pwrite_stream & OS
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: Any.h:28
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
BitVector & set()
Definition: BitVector.h:351
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:707
void push_back(bool Val)
Definition: BitVector.h:466
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
Lightweight error class with error context and mandatory checking.
Definition: Error.h:154
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
const SITargetLowering * getTargetLowering() const override
Definition: GCNSubtarget.h:239
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasCalls() const
Return true if the current function has any function calls.
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
void setStackID(int ObjectIdx, uint8_t ID)
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
uint8_t getStackID(int ObjectIdx) const
int getObjectIndexBegin() const
Return the minimum frame object index.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * cloneInfo(const Ty &Old)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
size_type count(const KeyT &Key) const
Definition: MapVector.h:144
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: MapVector.h:117
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:51
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:76
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool usesAGPRs(const MachineFunction &MF) const
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))
Register addDispatchPtr(const SIRegisterInfo &TRI)
Register addFlatScratchInit(const SIRegisterInfo &TRI)
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Register addQueuePtr(const SIRegisterInfo &TRI)
bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool IsPrologEpilog=false)
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default
Register getGITPtrLoReg(const MachineFunction &MF) const
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const
bool mayUseAGPRs(const Function &F) const
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Register addDispatchID(const SIRegisterInfo &TRI)
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool checkIndexInPrologEpilogSGPRSpills(int FI) const
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
const ReservedRegSet & getWWMReservedRegs() const
std::optional< int > getOptionalScavengeFI() const
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
void limitOccupancy(const MachineFunction &MF)
static bool isAGPRClass(const TargetRegisterClass *RC)
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a location in source code.
Definition: SMLoc.h:23
Represents a range in source code.
Definition: SMLoc.h:48
const value_type & back() const
Return the last element of the SetVector.
Definition: SetVector.h:149
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:582
unsigned getMainFileID() const
Definition: SourceMgr.h:132
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:125
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool consumeInteger(unsigned Radix, T &Result)
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:503
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
const TargetMachine & getTargetMachine() const
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
bool isEntryFunctionCC(CallingConv::ID CC)
bool isChainCC(CallingConv::ID CC)
unsigned getInitialPSInputAddr(const Function &F)
bool isGraphics(CallingConv::ID cc)
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:194
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:197
@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:229
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:203
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:188
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:191
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:666
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:41
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
A serializaable representation of a reference to a stack object or fixed stack object.
std::optional< SIArgument > PrivateSegmentWaveByteOffset
std::optional< SIArgument > WorkGroupIDY
std::optional< SIArgument > FlatScratchInit
std::optional< SIArgument > DispatchPtr
std::optional< SIArgument > DispatchID
std::optional< SIArgument > WorkItemIDY
std::optional< SIArgument > WorkGroupIDX
std::optional< SIArgument > ImplicitArgPtr
std::optional< SIArgument > QueuePtr
std::optional< SIArgument > WorkGroupInfo
std::optional< SIArgument > LDSKernelId
std::optional< SIArgument > ImplicitBufferPtr
std::optional< SIArgument > WorkItemIDX
std::optional< SIArgument > KernargSegmentPtr
std::optional< SIArgument > WorkItemIDZ
std::optional< SIArgument > PrivateSegmentSize
std::optional< SIArgument > PrivateSegmentBuffer
std::optional< SIArgument > WorkGroupIDZ
std::optional< unsigned > Mask
static SIArgument createArgument(bool IsReg)
SmallVector< StringValue > WWMReservedRegs
void mappingImpl(yaml::IO &YamlIO) override
std::optional< FrameIndex > ScavengeFI
A wrapper around std::string which contains a source range that's being set during parsing.