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SIISelLowering.h
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1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class SITargetLowering final : public AMDGPUTargetLowering {
24 private:
25  const GCNSubtarget *Subtarget;
26 
27 public:
29  CallingConv::ID CC,
30  EVT VT) const override;
32  CallingConv::ID CC,
33  EVT VT) const override;
34 
36  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
37  unsigned &NumIntermediates, MVT &RegisterVT) const override;
38 
39 private:
40  SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
41  SDValue Chain, uint64_t Offset) const;
42  SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
43  SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
44  const SDLoc &SL, SDValue Chain,
45  uint64_t Offset, unsigned Align, bool Signed,
46  const ISD::InputArg *Arg = nullptr) const;
47 
48  SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
49  const SDLoc &SL, SDValue Chain,
50  const ISD::InputArg &Arg) const;
51  SDValue getPreloadedValue(SelectionDAG &DAG,
52  const SIMachineFunctionInfo &MFI,
53  EVT VT,
55 
56  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
57  SelectionDAG &DAG) const override;
58  SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
59  MVT VT, unsigned Offset) const;
60  SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
61  SelectionDAG &DAG) const;
62  SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
63  SDValue GLC, SDValue DLC, SelectionDAG &DAG) const;
64 
65  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
66  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
67  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
68 
69  // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
70  // (the offset that is included in bounds checking and swizzling, to be split
71  // between the instruction's voffset and immoffset fields) and soffset (the
72  // offset that is excluded from bounds checking and swizzling, to go in the
73  // instruction's soffset field). This function takes the first kind of
74  // offset and figures out how to split it between voffset and immoffset.
75  std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
76  SelectionDAG &DAG) const;
77 
78  SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
79  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
80  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
81  SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
82  SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
83  SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
84  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
85  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
86  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
87  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
88  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
89  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
93  SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
95  bool IsIntrinsic = false) const;
96 
97  SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
98  ArrayRef<SDValue> Ops) const;
99 
100  // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
101  // dwordx4 if on SI.
102  SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
103  ArrayRef<SDValue> Ops, EVT MemVT,
104  MachineMemOperand *MMO, SelectionDAG &DAG) const;
105 
106  SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const;
107 
108  /// Converts \p Op, which must be of floating point type, to the
109  /// floating point type \p VT, by either extending or truncating it.
110  SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
111  SDValue Op,
112  const SDLoc &DL,
113  EVT VT) const;
114 
115  SDValue convertArgType(
116  SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
117  bool Signed, const ISD::InputArg *Arg = nullptr) const;
118 
119  /// Custom lowering for ISD::FP_ROUND for MVT::f16.
120  SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
121  SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
122 
123  SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
124  SelectionDAG &DAG) const;
125 
126  SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
127  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
128  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
129  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
130  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
131  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
132  SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
133  SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
134 
135  SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
136 
137  SDValue performUCharToFloatCombine(SDNode *N,
138  DAGCombinerInfo &DCI) const;
139  SDValue performSHLPtrCombine(SDNode *N,
140  unsigned AS,
141  EVT MemVT,
142  DAGCombinerInfo &DCI) const;
143 
144  SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
145 
146  SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
147  unsigned Opc, SDValue LHS,
148  const ConstantSDNode *CRHS) const;
149 
150  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
151  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
152  SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
153  SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
154  SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
155  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
156  SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
157  const APFloat &C) const;
158  SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
159 
160  SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
161  SDValue Op0, SDValue Op1) const;
162  SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
163  SDValue Op0, SDValue Op1, bool Signed) const;
164  SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
165  SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
166  SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
167  SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
168  SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
169 
170  SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
171  unsigned getFusedOpcode(const SelectionDAG &DAG,
172  const SDNode *N0, const SDNode *N1) const;
173  SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
174  SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
175  SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
176  SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
177  SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
178  SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
179  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
180  SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
181  SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
182  SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
183 
184  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
185  bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
186 
187  unsigned isCFIntrinsic(const SDNode *Intr) const;
188 
189 public:
190  /// \returns True if fixup needs to be emitted for given global value \p GV,
191  /// false otherwise.
192  bool shouldEmitFixup(const GlobalValue *GV) const;
193 
194  /// \returns True if GOT relocation needs to be emitted for given global value
195  /// \p GV, false otherwise.
196  bool shouldEmitGOTReloc(const GlobalValue *GV) const;
197 
198  /// \returns True if PC-relative relocation needs to be emitted for given
199  /// global value \p GV, false otherwise.
200  bool shouldEmitPCReloc(const GlobalValue *GV) const;
201 
202 private:
203  // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
204  // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
205  // pointed to by Offsets.
206  /// \returns 0 If there is a non-constant offset or if the offset is 0.
207  /// Otherwise returns the constant offset.
208  unsigned setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
209  SDValue *Offsets, unsigned Align = 4) const;
210 
211  // Handle 8 bit and 16 bit buffer loads
212  SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
213  ArrayRef<SDValue> Ops, MemSDNode *M) const;
214 
215  // Handle 8 bit and 16 bit buffer stores
216  SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
217  SDLoc DL, SDValue Ops[],
218  MemSDNode *M) const;
219 
220 public:
221  SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
222 
223  const GCNSubtarget *getSubtarget() const;
224 
225  bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
226 
227  bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
228 
229  bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
230  MachineFunction &MF,
231  unsigned IntrinsicID) const override;
232 
233  bool getAddrModeArguments(IntrinsicInst * /*I*/,
234  SmallVectorImpl<Value*> &/*Ops*/,
235  Type *&/*AccessTy*/) const override;
236 
237  bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
238  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
239  unsigned AS,
240  Instruction *I = nullptr) const override;
241 
242  bool canMergeStoresTo(unsigned AS, EVT MemVT,
243  const SelectionDAG &DAG) const override;
244 
246  unsigned Size, unsigned AS, unsigned Align,
248  bool *IsFast = nullptr) const;
249 
251  EVT VT, unsigned AS, unsigned Align,
253  bool *IsFast = nullptr) const override;
254 
255  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
256  unsigned SrcAlign, bool IsMemset,
257  bool ZeroMemset,
258  bool MemcpyStrSrc,
259  const AttributeList &FuncAttributes) const override;
260 
261  bool isMemOpUniform(const SDNode *N) const;
262  bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
263  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
264  bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
265 
267  getPreferredVectorAction(MVT VT) const override;
268 
270  Type *Ty) const override;
271 
272  bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
273 
274  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
275 
276  bool supportSplitCSR(MachineFunction *MF) const override;
277  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
279  MachineBasicBlock *Entry,
280  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
281 
283  bool isVarArg,
285  const SDLoc &DL, SelectionDAG &DAG,
286  SmallVectorImpl<SDValue> &InVals) const override;
287 
288  bool CanLowerReturn(CallingConv::ID CallConv,
289  MachineFunction &MF, bool isVarArg,
291  LLVMContext &Context) const override;
292 
293  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
295  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
296  SelectionDAG &DAG) const override;
297 
298  void passSpecialInputs(
299  CallLoweringInfo &CLI,
300  CCState &CCInfo,
302  SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
303  SmallVectorImpl<SDValue> &MemOpChains,
304  SDValue Chain) const;
305 
306  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
307  CallingConv::ID CallConv, bool isVarArg,
309  const SDLoc &DL, SelectionDAG &DAG,
310  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
311  SDValue ThisVal) const;
312 
313  bool mayBeEmittedAsTailCall(const CallInst *) const override;
314 
316  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
318  const SmallVectorImpl<SDValue> &OutVals,
319  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
320 
322  SmallVectorImpl<SDValue> &InVals) const override;
323 
324  Register getRegisterByName(const char* RegName, EVT VT,
325  const MachineFunction &MF) const override;
326 
328  MachineBasicBlock *BB) const;
329 
330  void bundleInstWithWaitcnt(MachineInstr &MI) const;
332  MachineBasicBlock *BB) const;
333 
336  MachineBasicBlock *BB) const override;
337 
338  bool hasBitPreservingFPLogic(EVT VT) const override;
339  bool enableAggressiveFMAFusion(EVT VT) const override;
340  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
341  EVT VT) const override;
342  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
343  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
347  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
348 
350  SelectionDAG &DAG) const override;
351 
352  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
353  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
355  SDNode *Node) const override;
356 
358 
360  SDValue Ptr) const;
361  MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
362  uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
363  std::pair<unsigned, const TargetRegisterClass *>
365  StringRef Constraint, MVT VT) const override;
366  ConstraintType getConstraintType(StringRef Constraint) const override;
367  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
368  SDValue V) const;
369 
370  void finalizeLowering(MachineFunction &MF) const override;
371 
373  KnownBits &Known,
374  const APInt &DemandedElts,
375  const SelectionDAG &DAG,
376  unsigned Depth = 0) const override;
377 
378  bool isSDNodeSourceOfDivergence(const SDNode *N,
379  FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
380 
381  bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
382  unsigned MaxDepth = 5) const;
383  bool denormalsEnabledForType(EVT VT) const;
384 
386  const SelectionDAG &DAG,
387  bool SNaN = false,
388  unsigned Depth = 0) const override;
390 
391  virtual const TargetRegisterClass *
392  getRegClassFor(MVT VT, bool isDivergent) const override;
393  virtual bool requiresUniformRegister(MachineFunction &MF,
394  const Value *V) const override;
395  Align getPrefLoopAlignment(MachineLoop *ML) const override;
396 
397  void allocateHSAUserSGPRs(CCState &CCInfo,
398  MachineFunction &MF,
399  const SIRegisterInfo &TRI,
400  SIMachineFunctionInfo &Info) const;
401 
402  void allocateSystemSGPRs(CCState &CCInfo,
403  MachineFunction &MF,
404  SIMachineFunctionInfo &Info,
405  CallingConv::ID CallConv,
406  bool IsShader) const;
407 
409  MachineFunction &MF,
410  const SIRegisterInfo &TRI,
411  SIMachineFunctionInfo &Info) const;
413  CCState &CCInfo,
414  MachineFunction &MF,
415  const SIRegisterInfo &TRI,
416  SIMachineFunctionInfo &Info) const;
417 
418  void allocateSpecialInputVGPRs(CCState &CCInfo,
419  MachineFunction &MF,
420  const SIRegisterInfo &TRI,
421  SIMachineFunctionInfo &Info) const;
422 };
423 
424 } // End namespace llvm
425 
426 #endif
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool shouldEmitFixup(const GlobalValue *GV) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
LLVMContext & Context
void allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Register getRegisterByName(const char *RegName, EVT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
This class represents a function call, abstracting a target machine&#39;s calling convention.
const GCNSubtarget * getSubtarget() const
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1136
Function Alias Analysis Results
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
unsigned const TargetRegisterInfo * TRI
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:699
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
A description of a memory reference used in the backend.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset...
bool isMemOpUniform(const SDNode *N) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
unsigned Intr
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool shouldEmitGOTReloc(const GlobalValue *GV) const
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const override
Insert explicit copies in entry and exit blocks.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
const unsigned MaxDepth
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the &#39;Add TID&#39; bit enabled The TID (Thread ID) is multiplied by the ...
CCState - This class holds information needed while lowering arguments and return values...
bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Interface definition of the TargetLowering class that is common to all AMD GPUs.
CCValAssign - Represent assignment of one arg/retval to a location.
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
Flags
Flags values. These may be or&#39;d together.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
void bundleInstWithWaitcnt(MachineInstr &MI) const
Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
Representation of each machine instruction.
Definition: MachineInstr.h:63
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override
Return the register class that should be used for the specified value type.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const override
Determine if the target supports unaligned memory accesses.
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
#define I(x, y, z)
Definition: MD5.cpp:58
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
#define N
bool allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
uint32_t Size
Definition: Profile.cpp:46
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *V) const override
Allows target to decide about the register class of the specific value that is live outside the defin...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
LLVM Value Representation.
Definition: Value.h:74
bool denormalsEnabledForType(EVT VT) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void computeKnownBitsForFrameIndex(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself...
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:43
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class is used to represent ISD::LOAD nodes.
bool shouldEmitPCReloc(const GlobalValue *GV) const