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SIISelLowering.h
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1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
20 
21 namespace llvm {
22 
23 class GCNSubtarget;
24 class SIMachineFunctionInfo;
25 class SIRegisterInfo;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 
31 class SITargetLowering final : public AMDGPUTargetLowering {
32 private:
33  const GCNSubtarget *Subtarget;
34 
35 public:
37  CallingConv::ID CC,
38  EVT VT) const override;
40  CallingConv::ID CC,
41  EVT VT) const override;
42 
44  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
45  unsigned &NumIntermediates, MVT &RegisterVT) const override;
46 
47 private:
48  SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
49  SDValue Chain, uint64_t Offset) const;
50  SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51  SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
52  const SDLoc &SL, SDValue Chain,
53  uint64_t Offset, Align Alignment,
54  bool Signed,
55  const ISD::InputArg *Arg = nullptr) const;
56  SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
57  Align Alignment,
58  ImplicitParameter Param) const;
59 
60  SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
61  const SDLoc &SL, SDValue Chain,
62  const ISD::InputArg &Arg) const;
63  SDValue getPreloadedValue(SelectionDAG &DAG,
64  const SIMachineFunctionInfo &MFI,
65  EVT VT,
67 
68  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
69  SelectionDAG &DAG) const override;
70  SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
71  MVT VT, unsigned Offset) const;
73  SelectionDAG &DAG, bool WithChain) const;
74  SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
75  SDValue CachePolicy, SelectionDAG &DAG) const;
76 
77  SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
78  unsigned NewOpcode) const;
79  SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
80  unsigned NewOpcode) const;
81 
82  SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
83  const ArgDescriptor &ArgDesc) const;
84 
85  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
86  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
87  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
88 
89  // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
90  // (the offset that is included in bounds checking and swizzling, to be split
91  // between the instruction's voffset and immoffset fields) and soffset (the
92  // offset that is excluded from bounds checking and swizzling, to go in the
93  // instruction's soffset field). This function takes the first kind of
94  // offset and figures out how to split it between voffset and immoffset.
95  std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
96  SelectionDAG &DAG) const;
97 
98  SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
99  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
100  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
101  SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
102  SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
103  SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
104  SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
105  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
106  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
107  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
108  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
109  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
110  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
111  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
112  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
113  SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
115  bool IsIntrinsic = false) const;
116 
117  SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
118  ArrayRef<SDValue> Ops) const;
119 
120  // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
121  // dwordx4 if on SI.
122  SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
123  ArrayRef<SDValue> Ops, EVT MemVT,
124  MachineMemOperand *MMO, SelectionDAG &DAG) const;
125 
126  SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
127  bool ImageStore = false) const;
128 
129  /// Converts \p Op, which must be of floating point type, to the
130  /// floating point type \p VT, by either extending or truncating it.
131  SDValue getFPExtOrFPRound(SelectionDAG &DAG,
132  SDValue Op,
133  const SDLoc &DL,
134  EVT VT) const;
135 
136  SDValue convertArgType(
137  SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
138  bool Signed, const ISD::InputArg *Arg = nullptr) const;
139 
140  /// Custom lowering for ISD::FP_ROUND for MVT::f16.
141  SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
142  SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
143  SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
144  SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
145 
146  SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
147  SelectionDAG &DAG) const;
148 
149  SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
150  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
151  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
152  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
153  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
154  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
155  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
156 
157  SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
158  SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
159  SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
160  SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
161  SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
162 
163  SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
164 
165  SDValue performUCharToFloatCombine(SDNode *N,
166  DAGCombinerInfo &DCI) const;
167  SDValue performSHLPtrCombine(SDNode *N,
168  unsigned AS,
169  EVT MemVT,
170  DAGCombinerInfo &DCI) const;
171 
172  SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
173 
174  SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
175  unsigned Opc, SDValue LHS,
176  const ConstantSDNode *CRHS) const;
177 
178  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
179  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
180  SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
181  SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
182  SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
183  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
184  SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
185  const APFloat &C) const;
186  SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
187 
188  SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
189  SDValue Op0, SDValue Op1) const;
190  SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
191  SDValue Op0, SDValue Op1, bool Signed) const;
192  SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
193  SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
194  SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
195  SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
196  SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
197 
198  SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
199  unsigned getFusedOpcode(const SelectionDAG &DAG,
200  const SDNode *N0, const SDNode *N1) const;
201  SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
202  SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
203  SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
204  SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
205  SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
206  SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
207  SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
208  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
209  SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
210  SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
211  SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
212 
213  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
214  bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
215 
216  unsigned isCFIntrinsic(const SDNode *Intr) const;
217 
218 public:
219  /// \returns True if fixup needs to be emitted for given global value \p GV,
220  /// false otherwise.
221  bool shouldEmitFixup(const GlobalValue *GV) const;
222 
223  /// \returns True if GOT relocation needs to be emitted for given global value
224  /// \p GV, false otherwise.
225  bool shouldEmitGOTReloc(const GlobalValue *GV) const;
226 
227  /// \returns True if PC-relative relocation needs to be emitted for given
228  /// global value \p GV, false otherwise.
229  bool shouldEmitPCReloc(const GlobalValue *GV) const;
230 
231  /// \returns true if this should use a literal constant for an LDS address,
232  /// and not emit a relocation for an LDS global.
233  bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
234 
235  /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
236  /// expanded into a set of cmp/select instructions.
237  static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
238  bool IsDivergentIdx);
239 
240 private:
241  // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
242  // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
243  // pointed to by Offsets.
244  void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
245  SDValue *Offsets, Align Alignment = Align(4)) const;
246 
247  // Handle 8 bit and 16 bit buffer loads
248  SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
249  ArrayRef<SDValue> Ops, MemSDNode *M) const;
250 
251  // Handle 8 bit and 16 bit buffer stores
252  SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
253  SDLoc DL, SDValue Ops[],
254  MemSDNode *M) const;
255 
256 public:
257  SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
258 
259  const GCNSubtarget *getSubtarget() const;
260 
261  bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
262  EVT SrcVT) const override;
263 
264  bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
265  LLT SrcTy) const override;
266 
267  bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
268 
269  bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
270  MachineFunction &MF,
271  unsigned IntrinsicID) const override;
272 
273  bool getAddrModeArguments(IntrinsicInst * /*I*/,
274  SmallVectorImpl<Value*> &/*Ops*/,
275  Type *&/*AccessTy*/) const override;
276 
277  bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
278  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
279  unsigned AS,
280  Instruction *I = nullptr) const override;
281 
282  bool canMergeStoresTo(unsigned AS, EVT MemVT,
283  const MachineFunction &MF) const override;
284 
286  unsigned Size, unsigned AddrSpace, Align Alignment,
288  bool *IsFast = nullptr) const;
289 
291  LLT Ty, unsigned AddrSpace, Align Alignment,
293  bool *IsFast = nullptr) const override {
294  if (IsFast)
295  *IsFast = false;
296  return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace,
297  Alignment, Flags, IsFast);
298  }
299 
301  EVT VT, unsigned AS, Align Alignment,
303  bool *IsFast = nullptr) const override;
304 
306  const AttributeList &FuncAttributes) const override;
307 
308  bool isMemOpUniform(const SDNode *N) const;
309  bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
310 
311  static bool isNonGlobalAddrSpace(unsigned AS);
312 
313  bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
314 
316  getPreferredVectorAction(MVT VT) const override;
317 
319  Type *Ty) const override;
320 
321  bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
322 
323  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
324 
325  bool supportSplitCSR(MachineFunction *MF) const override;
326  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
328  MachineBasicBlock *Entry,
329  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
330 
332  bool isVarArg,
334  const SDLoc &DL, SelectionDAG &DAG,
335  SmallVectorImpl<SDValue> &InVals) const override;
336 
337  bool CanLowerReturn(CallingConv::ID CallConv,
338  MachineFunction &MF, bool isVarArg,
340  LLVMContext &Context) const override;
341 
342  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
344  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
345  SelectionDAG &DAG) const override;
346 
347  void passSpecialInputs(
348  CallLoweringInfo &CLI,
349  CCState &CCInfo,
351  SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
352  SmallVectorImpl<SDValue> &MemOpChains,
353  SDValue Chain) const;
354 
355  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
356  CallingConv::ID CallConv, bool isVarArg,
358  const SDLoc &DL, SelectionDAG &DAG,
359  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
360  SDValue ThisVal) const;
361 
362  bool mayBeEmittedAsTailCall(const CallInst *) const override;
363 
365  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
367  const SmallVectorImpl<SDValue> &OutVals,
368  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
369 
370  SDValue LowerCall(CallLoweringInfo &CLI,
371  SmallVectorImpl<SDValue> &InVals) const override;
372 
375 
376  Register getRegisterByName(const char* RegName, LLT VT,
377  const MachineFunction &MF) const override;
378 
380  MachineBasicBlock *BB) const;
381 
384  MachineBasicBlock *BB) const;
385 
388  MachineBasicBlock *BB) const override;
389 
390  bool hasBitPreservingFPLogic(EVT VT) const override;
391  bool enableAggressiveFMAFusion(EVT VT) const override;
392  bool enableAggressiveFMAFusion(LLT Ty) const override;
394  EVT VT) const override;
395  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
396  LLT getPreferredShiftAmountTy(LLT Ty) const override;
397 
399  EVT VT) const override;
401  const LLT Ty) const override;
402  bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
403  bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
404 
408  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
409 
411  SelectionDAG &DAG) const override;
412 
413  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
414  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
415  void AddIMGInit(MachineInstr &MI) const;
417  SDNode *Node) const override;
418 
420 
422  SDValue Ptr) const;
423  MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
424  uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
425  std::pair<unsigned, const TargetRegisterClass *>
427  StringRef Constraint, MVT VT) const override;
428  ConstraintType getConstraintType(StringRef Constraint) const override;
430  std::string &Constraint,
431  std::vector<SDValue> &Ops,
432  SelectionDAG &DAG) const override;
433  bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
435  const std::string &Constraint,
436  uint64_t Val) const;
438  uint64_t Val,
439  unsigned MaxSize = 64) const;
440  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
441  SDValue V) const;
442 
443  void finalizeLowering(MachineFunction &MF) const override;
444 
445  void computeKnownBitsForFrameIndex(int FrameIdx,
446  KnownBits &Known,
447  const MachineFunction &MF) const override;
449  KnownBits &Known,
450  const APInt &DemandedElts,
451  const MachineRegisterInfo &MRI,
452  unsigned Depth = 0) const override;
453 
455  const MachineRegisterInfo &MRI,
456  unsigned Depth = 0) const override;
457  bool isSDNodeSourceOfDivergence(const SDNode *N,
458  FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
459 
460  bool hasMemSDNodeUser(SDNode *N) const;
461 
463  SDValue N1) const override;
464 
466  unsigned MaxDepth = 5) const;
468  unsigned MaxDepth = 5) const;
469  bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
470  bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const;
471 
473  const SelectionDAG &DAG,
474  bool SNaN = false,
475  unsigned Depth = 0) const override;
481 
482  virtual const TargetRegisterClass *
483  getRegClassFor(MVT VT, bool isDivergent) const override;
484  virtual bool requiresUniformRegister(MachineFunction &MF,
485  const Value *V) const override;
486  Align getPrefLoopAlignment(MachineLoop *ML) const override;
487 
488  void allocateHSAUserSGPRs(CCState &CCInfo,
489  MachineFunction &MF,
490  const SIRegisterInfo &TRI,
491  SIMachineFunctionInfo &Info) const;
492 
493  void allocateSystemSGPRs(CCState &CCInfo,
494  MachineFunction &MF,
496  CallingConv::ID CallConv,
497  bool IsShader) const;
498 
500  MachineFunction &MF,
501  const SIRegisterInfo &TRI,
502  SIMachineFunctionInfo &Info) const;
504  CCState &CCInfo,
505  MachineFunction &MF,
506  const SIRegisterInfo &TRI,
507  SIMachineFunctionInfo &Info) const;
508 
509  void allocateSpecialInputVGPRs(CCState &CCInfo,
510  MachineFunction &MF,
511  const SIRegisterInfo &TRI,
512  SIMachineFunctionInfo &Info) const;
514  MachineFunction &MF,
515  const SIRegisterInfo &TRI,
516  SIMachineFunctionInfo &Info) const;
517 
518  std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL,
519  Type *Ty) const;
520 
522  getTargetMMOFlags(const Instruction &I) const override;
523 };
524 
525 } // End namespace llvm
526 
527 #endif
llvm::SITargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SIISelLowering.cpp:4366
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::SITargetLowering::bundleInstWithWaitcnt
void bundleInstWithWaitcnt(MachineInstr &MI) const
Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
Definition: SIISelLowering.cpp:3439
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4637
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4394
llvm::SITargetLowering::isNonGlobalAddrSpace
static bool isNonGlobalAddrSpace(unsigned AS)
Definition: SIISelLowering.cpp:1539
llvm::SITargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: SIISelLowering.cpp:800
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SITargetLowering::allocateSystemSGPRs
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
Definition: SIISelLowering.cpp:2080
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::SITargetLowering::getAsmOperandConstVal
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const
Definition: SIISelLowering.cpp:12081
llvm::SITargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SIISelLowering.cpp:1563
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2867
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:47
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::SITargetLowering::LowerCallResult
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
Definition: SIISelLowering.cpp:2619
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2314
llvm::SITargetLowering::finalizeLowering
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Definition: SIISelLowering.cpp:12205
llvm::MemOp
Definition: TargetLowering.h:111
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::SITargetLowering::allocateHSAUserSGPRs
void allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:2025
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SITargetLowering::isFMADLegal
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override
Returns true if be combined with to form an ISD::FMAD.
Definition: SIISelLowering.cpp:4476
llvm::AttributeList
Definition: Attributes.h:408
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::SITargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: SIISelLowering.cpp:5878
llvm::SITargetLowering::shouldEmitFixup
bool shouldEmitFixup(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5059
llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SIISelLowering.cpp:4418
llvm::SITargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SIISelLowering.cpp:11915
llvm::SITargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SIISelLowering.cpp:2525
llvm::MemSDNode
This is an abstract virtual class for memory operations.
Definition: SelectionDAGNodes.h:1259
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SITargetLowering::insertCopiesSplitCSR
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
Definition: SIISelLowering.cpp:2230
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::SITargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: SIISelLowering.cpp:934
llvm::SPIRV::Dim
Dim
Definition: SPIRVBaseInfo.h:279
llvm::SITargetLowering::getTargetMMOFlags
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: SIISelLowering.cpp:12799
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::SITargetLowering::shouldExpandAtomicLoadInIR
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: SIISelLowering.cpp:12644
llvm::SITargetLowering::SITargetLowering
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)
Definition: SIISelLowering.cpp:76
llvm::SITargetLowering::legalizeTargetIndependentNode
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
Definition: SIISelLowering.cpp:11571
llvm::SITargetLowering::isReassocProfitable
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Definition: SIISelLowering.cpp:12785
llvm::SITargetLowering::PostISelFolding
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
Definition: SIISelLowering.cpp:11616
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::SITargetLowering::getSubtarget
const GCNSubtarget * getSubtarget() const
Definition: SIISelLowering.cpp:762
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::SITargetLowering::denormalsEnabledForType
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const
Definition: SIISelLowering.cpp:12495
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::SITargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SIISelLowering.cpp:12065
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2276
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SITargetLowering::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override
Return the register class that should be used for the specified value type.
Definition: SIISelLowering.cpp:12665
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::SITargetLowering::splitUnaryVectorOp
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4498
llvm::SITargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SIISelLowering.cpp:2508
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3781
Param
Value * Param
Definition: NVPTXLowerArgs.cpp:164
llvm::SITargetLowering::emitGWSMemViolTestLoop
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: SIISelLowering.cpp:3453
llvm::SITargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
Definition: SIISelLowering.cpp:11781
llvm::SITargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SIISelLowering.cpp:3338
llvm::SITargetLowering::requiresUniformRegister
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *V) const override
Allows target to decide about the register class of the specific value that is live outside the defin...
Definition: SIISelLowering.cpp:12731
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::SITargetLowering::computeKnownBitsForFrameIndex
void computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, const MachineFunction &MF) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
Definition: SIISelLowering.cpp:12260
llvm::SITargetLowering::checkAsmConstraintVal
bool checkAsmConstraintVal(SDValue Op, const std::string &Constraint, uint64_t Val) const
Definition: SIISelLowering.cpp:12115
llvm::Instruction
Definition: Instruction.h:42
AMDGPUISelLowering.h
llvm::SITargetLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:2877
llvm::SITargetLowering::isLegalGlobalAddressingMode
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
Definition: SIISelLowering.cpp:1191
llvm::LegacyDivergenceAnalysis
Definition: LegacyDivergenceAnalysis.h:31
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::SITargetLowering::computeKnownBitsForTargetInstr
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SIISelLowering.cpp:12277
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl
SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:3275
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SITargetLowering::allocateSpecialInputVGPRsFixed
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
Definition: SIISelLowering.cpp:1977
llvm::SITargetLowering::getAddrModeArguments
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
Definition: SIISelLowering.cpp:1148
llvm::SITargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SIISelLowering.cpp:2964
llvm::APFloat
Definition: APFloat.h:700
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:305
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::SITargetLowering::splitTernaryVectorOp
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4541
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::SITargetLowering::initializeSplitCSR
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Definition: SIISelLowering.cpp:2226
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::SITargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: SIISelLowering.cpp:826
llvm::SITargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: SIISelLowering.cpp:4391
llvm::SITargetLowering::isSDNodeSourceOfDivergence
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override
Definition: SIISelLowering.cpp:12428
llvm::SITargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: SIISelLowering.cpp:1331
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SITargetLowering::hasMemSDNodeUser
bool hasMemSDNodeUser(SDNode *N) const
Definition: SIISelLowering.cpp:12774
llvm::SITargetLowering::isMemOpHasNoClobberedMemOperand
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
Definition: SIISelLowering.cpp:1534
llvm::SITargetLowering::isTypeDesirableForOp
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: SIISelLowering.cpp:1576
llvm::SITargetLowering::splitKillBlock
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: SIISelLowering.cpp:3387
llvm::SITargetLowering::shouldEmitGOTReloc
bool shouldEmitGOTReloc(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5066
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:129
llvm::ISD::InputArg
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
Definition: TargetCallingConv.h:195
llvm::SITargetLowering::shouldUseLDSConstAddress
bool shouldUseLDSConstAddress(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5079
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::SITargetLowering::allocateSpecialInputVGPRs
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
Definition: SIISelLowering.cpp:1956
llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition: SIISelLowering.cpp:852
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::SITargetLowering::copyToM0
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
Definition: SIISelLowering.cpp:5993
llvm::SITargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SIISelLowering.cpp:4897
llvm::SITargetLowering::shouldExpandAtomicCmpXchgInIR
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: SIISelLowering.cpp:12658
llvm::SITargetLowering::computeKnownAlignForTargetInstr
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine the known alignment for the pointer value R.
Definition: SIISelLowering.cpp:12319
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SITargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: SIISelLowering.cpp:4383
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl
bool allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const
Definition: SIISelLowering.cpp:1344
llvm::SITargetLowering::shouldExpandAtomicRMWInIR
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: SIISelLowering.cpp:12549
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
uint32_t
llvm::SITargetLowering::shouldExpandVectorDynExt
static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, bool IsDivergentIdx)
Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be expanded into a set of cmp...
Definition: SIISelLowering.cpp:10425
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SITargetLowering::getPreferredShiftAmountTy
LLT getPreferredShiftAmountTy(LLT Ty) const override
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
Definition: SIISelLowering.cpp:4397
llvm::SITargetLowering::supportSplitCSR
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Definition: SIISelLowering.cpp:2221
Node
Definition: ItaniumDemangle.h:155
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:78
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:176
llvm::SITargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SIISelLowering.cpp:11270
llvm::SITargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const override
LLT handling variant.
Definition: SIISelLowering.h:290
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:727
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::SITargetLowering::isKnownNeverNaNForTargetNode
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
Definition: SIISelLowering.cpp:12521
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:897
llvm::SITargetLowering::allocateSpecialEntryInputVGPRs
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1834
llvm::SITargetLowering::buildRSRC
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
Definition: SIISelLowering.cpp:11880
llvm::SITargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SIISelLowering.cpp:4571
llvm::TargetLoweringBase::IntrinsicInfo
Definition: TargetLowering.h:1027
llvm::SITargetLowering::isMemOpUniform
bool isMemOpUniform(const SDNode *N) const
Definition: SIISelLowering.cpp:1556
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SITargetLowering::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Definition: SIISelLowering.cpp:12759
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::SITargetLowering::wrapAddr64Rsrc
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
Definition: SIISelLowering.cpp:11845
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::SITargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: SIISelLowering.cpp:12340
llvm::SITargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: SIISelLowering.cpp:1570
llvm::SITargetLowering
Definition: SIISelLowering.h:31
llvm::SITargetLowering::isFPExtFoldable
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance,...
Definition: SIISelLowering.cpp:774
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::M68kBeads::DA
@ DA
Definition: M68kBaseInfo.h:59
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:3324
llvm::SITargetLowering::passSpecialInputs
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
Definition: SIISelLowering.cpp:2677
llvm::SITargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SIISelLowering.cpp:2265
llvm::SITargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SIISelLowering.cpp:3887
N
#define N
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:348
llvm::SITargetLowering::isFreeAddrSpaceCast
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: SIISelLowering.cpp:1544
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2496
llvm::SITargetLowering::checkAsmConstraintValA
bool checkAsmConstraintValA(SDValue Op, uint64_t Val, unsigned MaxSize=64) const
Definition: SIISelLowering.cpp:12148
llvm::SITargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Definition: SIISelLowering.cpp:4370
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl< Value * >
llvm::SITargetLowering::shouldEmitPCReloc
bool shouldEmitPCReloc(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5075
llvm::SITargetLowering::splitBinaryVectorOp
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4518
RegName
#define RegName(no)
llvm::SITargetLowering::AddIMGInit
void AddIMGInit(MachineInstr &MI) const
Definition: SIISelLowering.cpp:11694
llvm::SITargetLowering::shouldExpandAtomicStoreInIR
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
Definition: SIISelLowering.cpp:12651
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SITargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: SIISelLowering.cpp:794
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1288
llvm::SITargetLowering::allocateSpecialInputSGPRs
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1990
llvm::SITargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: SIISelLowering.cpp:1516
MachineFunction.h
AMDGPUArgumentUsageInfo.h
llvm::AMDGPUTargetLowering::ImplicitParameter
ImplicitParameter
Definition: AMDGPUISelLowering.h:321
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:22
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:131
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
llvm::SITargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SIISelLowering.cpp:1249
llvm::SITargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SIISelLowering.cpp:2953
llvm::SITargetLowering::isCanonicalized
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
Definition: SIISelLowering.cpp:9840
llvm::SITargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SIISelLowering.cpp:12042
llvm::LLT
Definition: LowLevelTypeImpl.h:39