LLVM  14.0.0git
SIISelLowering.h
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1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUArgumentUsageInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 
21 namespace llvm {
22 
23 class GCNSubtarget;
24 class SIMachineFunctionInfo;
25 class SIRegisterInfo;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 
31 class SITargetLowering final : public AMDGPUTargetLowering {
32 private:
33  const GCNSubtarget *Subtarget;
34 
35 public:
36  MVT getRegisterTypeForCallingConv(LLVMContext &Context,
37  CallingConv::ID CC,
38  EVT VT) const override;
39  unsigned getNumRegistersForCallingConv(LLVMContext &Context,
40  CallingConv::ID CC,
41  EVT VT) const override;
42 
43  unsigned getVectorTypeBreakdownForCallingConv(
44  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
45  unsigned &NumIntermediates, MVT &RegisterVT) const override;
46 
47 private:
48  SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
49  SDValue Chain, uint64_t Offset) const;
50  SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51  SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
52  const SDLoc &SL, SDValue Chain,
53  uint64_t Offset, Align Alignment,
54  bool Signed,
55  const ISD::InputArg *Arg = nullptr) const;
56 
57  SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
58  const SDLoc &SL, SDValue Chain,
59  const ISD::InputArg &Arg) const;
60  SDValue getPreloadedValue(SelectionDAG &DAG,
61  const SIMachineFunctionInfo &MFI,
62  EVT VT,
63  AMDGPUFunctionArgInfo::PreloadedValue) const;
64 
65  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
66  SelectionDAG &DAG) const override;
67  SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
68  MVT VT, unsigned Offset) const;
69  SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
70  SelectionDAG &DAG, bool WithChain) const;
71  SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
72  SDValue CachePolicy, SelectionDAG &DAG) const;
73 
74  SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
75  unsigned NewOpcode) const;
76  SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
77  unsigned NewOpcode) const;
78 
79  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
80  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
81  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
82 
83  // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
84  // (the offset that is included in bounds checking and swizzling, to be split
85  // between the instruction's voffset and immoffset fields) and soffset (the
86  // offset that is excluded from bounds checking and swizzling, to go in the
87  // instruction's soffset field). This function takes the first kind of
88  // offset and figures out how to split it between voffset and immoffset.
89  std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
90  SelectionDAG &DAG) const;
91 
92  SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
93  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
94  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
95  SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
96  SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
97  SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
98  SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
99  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
100  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
101  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
102  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
103  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
104  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
105  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
106  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
107  SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
108  SelectionDAG &DAG, ArrayRef<SDValue> Ops,
109  bool IsIntrinsic = false) const;
110 
111  SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
112  ArrayRef<SDValue> Ops) const;
113 
114  // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
115  // dwordx4 if on SI.
116  SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
117  ArrayRef<SDValue> Ops, EVT MemVT,
118  MachineMemOperand *MMO, SelectionDAG &DAG) const;
119 
120  SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
121  bool ImageStore = false) const;
122 
123  /// Converts \p Op, which must be of floating point type, to the
124  /// floating point type \p VT, by either extending or truncating it.
125  SDValue getFPExtOrFPRound(SelectionDAG &DAG,
126  SDValue Op,
127  const SDLoc &DL,
128  EVT VT) const;
129 
130  SDValue convertArgType(
131  SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
132  bool Signed, const ISD::InputArg *Arg = nullptr) const;
133 
134  /// Custom lowering for ISD::FP_ROUND for MVT::f16.
135  SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
136  SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
137  SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
138 
139  SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
140  SelectionDAG &DAG) const;
141 
142  SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
143  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
144  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
145  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
146  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
147  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
148 
149  SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
150  SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
151  SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
152  SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
153  SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
154 
155  SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
156 
157  SDValue performUCharToFloatCombine(SDNode *N,
158  DAGCombinerInfo &DCI) const;
159  SDValue performSHLPtrCombine(SDNode *N,
160  unsigned AS,
161  EVT MemVT,
162  DAGCombinerInfo &DCI) const;
163 
164  SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
165 
166  SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
167  unsigned Opc, SDValue LHS,
168  const ConstantSDNode *CRHS) const;
169 
170  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
171  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
172  SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
173  SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
174  SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
175  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
176  SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
177  const APFloat &C) const;
178  SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
179 
180  SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
181  SDValue Op0, SDValue Op1) const;
182  SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
183  SDValue Op0, SDValue Op1, bool Signed) const;
184  SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
185  SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
186  SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
187  SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
188  SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
189 
190  SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
191  unsigned getFusedOpcode(const SelectionDAG &DAG,
192  const SDNode *N0, const SDNode *N1) const;
193  SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
194  SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
195  SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
196  SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
197  SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
198  SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
199  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
200  SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
201  SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
202  SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
203 
204  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
205  bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
206 
207  unsigned isCFIntrinsic(const SDNode *Intr) const;
208 
209 public:
210  /// \returns True if fixup needs to be emitted for given global value \p GV,
211  /// false otherwise.
212  bool shouldEmitFixup(const GlobalValue *GV) const;
213 
214  /// \returns True if GOT relocation needs to be emitted for given global value
215  /// \p GV, false otherwise.
216  bool shouldEmitGOTReloc(const GlobalValue *GV) const;
217 
218  /// \returns True if PC-relative relocation needs to be emitted for given
219  /// global value \p GV, false otherwise.
220  bool shouldEmitPCReloc(const GlobalValue *GV) const;
221 
222  /// \returns true if this should use a literal constant for an LDS address,
223  /// and not emit a relocation for an LDS global.
224  bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
225 
226  /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
227  /// expanded into a set of cmp/select instructions.
228  static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
229  bool IsDivergentIdx);
230 
231 private:
232  // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
233  // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
234  // pointed to by Offsets.
235  void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
236  SDValue *Offsets, Align Alignment = Align(4)) const;
237 
238  // Handle 8 bit and 16 bit buffer loads
239  SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
240  ArrayRef<SDValue> Ops, MemSDNode *M) const;
241 
242  // Handle 8 bit and 16 bit buffer stores
243  SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
244  SDLoc DL, SDValue Ops[],
245  MemSDNode *M) const;
246 
247 public:
248  SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
249 
250  const GCNSubtarget *getSubtarget() const;
251 
252  bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
253  EVT SrcVT) const override;
254 
255  bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
256 
257  bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
258  MachineFunction &MF,
259  unsigned IntrinsicID) const override;
260 
261  bool getAddrModeArguments(IntrinsicInst * /*I*/,
262  SmallVectorImpl<Value*> &/*Ops*/,
263  Type *&/*AccessTy*/) const override;
264 
265  bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
266  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
267  unsigned AS,
268  Instruction *I = nullptr) const override;
269 
270  bool canMergeStoresTo(unsigned AS, EVT MemVT,
271  const MachineFunction &MF) const override;
272 
273  bool allowsMisalignedMemoryAccessesImpl(
274  unsigned Size, unsigned AddrSpace, Align Alignment,
275  MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
276  bool *IsFast = nullptr) const;
277 
278  bool allowsMisalignedMemoryAccesses(
279  LLT Ty, unsigned AddrSpace, Align Alignment,
280  MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
281  bool *IsFast = nullptr) const override {
282  if (IsFast)
283  *IsFast = false;
284  return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace,
285  Alignment, Flags, IsFast);
286  }
287 
288  bool allowsMisalignedMemoryAccesses(
289  EVT VT, unsigned AS, Align Alignment,
290  MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
291  bool *IsFast = nullptr) const override;
292 
293  EVT getOptimalMemOpType(const MemOp &Op,
294  const AttributeList &FuncAttributes) const override;
295 
296  bool isMemOpUniform(const SDNode *N) const;
297  bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
298 
299  static bool isNonGlobalAddrSpace(unsigned AS);
300 
301  bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
302 
303  TargetLoweringBase::LegalizeTypeAction
304  getPreferredVectorAction(MVT VT) const override;
305 
306  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
307  Type *Ty) const override;
308 
309  bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
310 
311  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
312 
313  bool supportSplitCSR(MachineFunction *MF) const override;
314  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
315  void insertCopiesSplitCSR(
316  MachineBasicBlock *Entry,
317  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
318 
319  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
320  bool isVarArg,
321  const SmallVectorImpl<ISD::InputArg> &Ins,
322  const SDLoc &DL, SelectionDAG &DAG,
323  SmallVectorImpl<SDValue> &InVals) const override;
324 
325  bool CanLowerReturn(CallingConv::ID CallConv,
326  MachineFunction &MF, bool isVarArg,
327  const SmallVectorImpl<ISD::OutputArg> &Outs,
328  LLVMContext &Context) const override;
329 
330  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
331  const SmallVectorImpl<ISD::OutputArg> &Outs,
332  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
333  SelectionDAG &DAG) const override;
334 
335  void passSpecialInputs(
336  CallLoweringInfo &CLI,
337  CCState &CCInfo,
338  const SIMachineFunctionInfo &Info,
339  SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
340  SmallVectorImpl<SDValue> &MemOpChains,
341  SDValue Chain) const;
342 
343  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
344  CallingConv::ID CallConv, bool isVarArg,
345  const SmallVectorImpl<ISD::InputArg> &Ins,
346  const SDLoc &DL, SelectionDAG &DAG,
347  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
348  SDValue ThisVal) const;
349 
350  bool mayBeEmittedAsTailCall(const CallInst *) const override;
351 
352  bool isEligibleForTailCallOptimization(
353  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
354  const SmallVectorImpl<ISD::OutputArg> &Outs,
355  const SmallVectorImpl<SDValue> &OutVals,
356  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
357 
358  SDValue LowerCall(CallLoweringInfo &CLI,
359  SmallVectorImpl<SDValue> &InVals) const override;
360 
361  SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const;
362  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
363 
364  Register getRegisterByName(const char* RegName, LLT VT,
365  const MachineFunction &MF) const override;
366 
367  MachineBasicBlock *splitKillBlock(MachineInstr &MI,
368  MachineBasicBlock *BB) const;
369 
370  void bundleInstWithWaitcnt(MachineInstr &MI) const;
371  MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
372  MachineBasicBlock *BB) const;
373 
374  MachineBasicBlock *
375  EmitInstrWithCustomInserter(MachineInstr &MI,
376  MachineBasicBlock *BB) const override;
377 
378  bool hasBitPreservingFPLogic(EVT VT) const override;
379  bool enableAggressiveFMAFusion(EVT VT) const override;
380  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
381  EVT VT) const override;
382  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
383  LLT getPreferredShiftAmountTy(LLT Ty) const override;
384 
385  bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
386  EVT VT) const override;
387  bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
388 
389  SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
390  SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
391  SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
392  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
393 
394  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
395  SelectionDAG &DAG) const override;
396 
397  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
398  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
399  void AddIMGInit(MachineInstr &MI) const;
400  void AdjustInstrPostInstrSelection(MachineInstr &MI,
401  SDNode *Node) const override;
402 
403  SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
404 
405  MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
406  SDValue Ptr) const;
407  MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
408  uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
409  std::pair<unsigned, const TargetRegisterClass *>
410  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
411  StringRef Constraint, MVT VT) const override;
412  ConstraintType getConstraintType(StringRef Constraint) const override;
413  void LowerAsmOperandForConstraint(SDValue Op,
414  std::string &Constraint,
415  std::vector<SDValue> &Ops,
416  SelectionDAG &DAG) const override;
417  bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
418  bool checkAsmConstraintVal(SDValue Op,
419  const std::string &Constraint,
420  uint64_t Val) const;
421  bool checkAsmConstraintValA(SDValue Op,
422  uint64_t Val,
423  unsigned MaxSize = 64) const;
424  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
425  SDValue V) const;
426 
427  void finalizeLowering(MachineFunction &MF) const override;
428 
429  void computeKnownBitsForFrameIndex(int FrameIdx,
430  KnownBits &Known,
431  const MachineFunction &MF) const override;
432  void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R,
433  KnownBits &Known,
434  const APInt &DemandedElts,
435  const MachineRegisterInfo &MRI,
436  unsigned Depth = 0) const override;
437 
438  Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R,
439  const MachineRegisterInfo &MRI,
440  unsigned Depth = 0) const override;
441  bool isSDNodeSourceOfDivergence(const SDNode *N,
442  FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
443 
444  bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
445  unsigned MaxDepth = 5) const;
446  bool isCanonicalized(Register Reg, MachineFunction &MF,
447  unsigned MaxDepth = 5) const;
448  bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
449  bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const;
450 
451  bool isKnownNeverNaNForTargetNode(SDValue Op,
452  const SelectionDAG &DAG,
453  bool SNaN = false,
454  unsigned Depth = 0) const override;
455  AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
456 
457  virtual const TargetRegisterClass *
458  getRegClassFor(MVT VT, bool isDivergent) const override;
459  virtual bool requiresUniformRegister(MachineFunction &MF,
460  const Value *V) const override;
461  Align getPrefLoopAlignment(MachineLoop *ML) const override;
462 
463  void allocateHSAUserSGPRs(CCState &CCInfo,
464  MachineFunction &MF,
465  const SIRegisterInfo &TRI,
466  SIMachineFunctionInfo &Info) const;
467 
468  void allocateSystemSGPRs(CCState &CCInfo,
469  MachineFunction &MF,
470  SIMachineFunctionInfo &Info,
471  CallingConv::ID CallConv,
472  bool IsShader) const;
473 
474  void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
475  MachineFunction &MF,
476  const SIRegisterInfo &TRI,
477  SIMachineFunctionInfo &Info) const;
478  void allocateSpecialInputSGPRs(
479  CCState &CCInfo,
480  MachineFunction &MF,
481  const SIRegisterInfo &TRI,
482  SIMachineFunctionInfo &Info) const;
483 
484  void allocateSpecialInputVGPRs(CCState &CCInfo,
485  MachineFunction &MF,
486  const SIRegisterInfo &TRI,
487  SIMachineFunctionInfo &Info) const;
488  void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
489  MachineFunction &MF,
490  const SIRegisterInfo &TRI,
491  SIMachineFunctionInfo &Info) const;
492 
493  std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL,
494  Type *Ty) const;
495 };
496 
497 } // End namespace llvm
498 
499 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::SITargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SIISelLowering.cpp:4435
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1556
llvm::SITargetLowering::bundleInstWithWaitcnt
void bundleInstWithWaitcnt(MachineInstr &MI) const
Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
Definition: SIISelLowering.cpp:3519
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4636
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4163
llvm::SITargetLowering::isNonGlobalAddrSpace
static bool isNonGlobalAddrSpace(unsigned AS)
Definition: SIISelLowering.cpp:1592
llvm::SITargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: SIISelLowering.cpp:928
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SITargetLowering::allocateSystemSGPRs
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
Definition: SIISelLowering.cpp:2136
llvm::SITargetLowering::getAsmOperandConstVal
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const
Definition: SIISelLowering.cpp:11733
llvm::SITargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SIISelLowering.cpp:1616
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2746
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:50
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::SITargetLowering::LowerCallResult
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
Definition: SIISelLowering.cpp:2689
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2281
llvm::SITargetLowering::finalizeLowering
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Definition: SIISelLowering.cpp:11857
llvm::MemOp
Definition: TargetLowering.h:112
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::SITargetLowering::allocateHSAUserSGPRs
void allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:2081
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SITargetLowering::isFMADLegal
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override
Returns true if be combined with to form an ISD::FMAD.
Definition: SIISelLowering.cpp:4515
llvm::AttributeList
Definition: Attributes.h:399
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::SITargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: SIISelLowering.cpp:5759
llvm::SITargetLowering::shouldEmitFixup
bool shouldEmitFixup(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5069
llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SIISelLowering.cpp:4485
llvm::SITargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SIISelLowering.cpp:11593
llvm::SITargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SIISelLowering.cpp:2580
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MemSDNode
This is an abstract virtual class for memory operations.
Definition: SelectionDAGNodes.h:1254
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SITargetLowering::insertCopiesSplitCSR
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
Definition: SIISelLowering.cpp:2286
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::SITargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: SIISelLowering.cpp:1062
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SITargetLowering::SITargetLowering
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)
Definition: SIISelLowering.cpp:77
llvm::SITargetLowering::legalizeTargetIndependentNode
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
Definition: SIISelLowering.cpp:11221
llvm::SITargetLowering::PostISelFolding
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
Definition: SIISelLowering.cpp:11266
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::SITargetLowering::getSubtarget
const GCNSubtarget * getSubtarget() const
Definition: SIISelLowering.cpp:900
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::SITargetLowering::denormalsEnabledForType
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const
Definition: SIISelLowering.cpp:12150
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::SITargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SIISelLowering.cpp:11717
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:1991
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SITargetLowering::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override
Return the register class that should be used for the specified value type.
Definition: SIISelLowering.cpp:12295
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::SITargetLowering::splitUnaryVectorOp
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4537
llvm::SITargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SIISelLowering.cpp:2563
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3550
llvm::SITargetLowering::emitGWSMemViolTestLoop
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: SIISelLowering.cpp:3533
llvm::SITargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
Definition: SIISelLowering.cpp:11431
llvm::SITargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SIISelLowering.cpp:3418
llvm::SITargetLowering::requiresUniformRegister
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *V) const override
Allows target to decide about the register class of the specific value that is live outside the defin...
Definition: SIISelLowering.cpp:12361
llvm::SITargetLowering::computeKnownBitsForFrameIndex
void computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, const MachineFunction &MF) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
Definition: SIISelLowering.cpp:11919
llvm::SITargetLowering::checkAsmConstraintVal
bool checkAsmConstraintVal(SDValue Op, const std::string &Constraint, uint64_t Val) const
Definition: SIISelLowering.cpp:11767
llvm::Instruction
Definition: Instruction.h:45
AMDGPUISelLowering.h
llvm::M68kBeads::DA
@ DA
Definition: M68kBaseInfo.h:59
llvm::SITargetLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:2933
llvm::SITargetLowering::isLegalGlobalAddressingMode
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
Definition: SIISelLowering.cpp:1291
llvm::LegacyDivergenceAnalysis
Definition: LegacyDivergenceAnalysis.h:31
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::SITargetLowering::computeKnownBitsForTargetInstr
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SIISelLowering.cpp:11936
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl
SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:3355
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SITargetLowering::allocateSpecialInputVGPRsFixed
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
Definition: SIISelLowering.cpp:2030
llvm::SITargetLowering::getAddrModeArguments
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
Definition: SIISelLowering.cpp:1250
llvm::SITargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SIISelLowering.cpp:3020
llvm::APFloat
Definition: APFloat.h:701
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::SITargetLowering::splitTernaryVectorOp
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4579
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::SITargetLowering::initializeSplitCSR
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Definition: SIISelLowering.cpp:2282
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::SITargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: SIISelLowering.cpp:954
llvm::SITargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: SIISelLowering.cpp:4458
llvm::SITargetLowering::isSDNodeSourceOfDivergence
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override
Definition: SIISelLowering.cpp:12083
llvm::SITargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: SIISelLowering.cpp:1431
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SITargetLowering::isMemOpHasNoClobberedMemOperand
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
Definition: SIISelLowering.cpp:1585
llvm::SITargetLowering::isTypeDesirableForOp
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: SIISelLowering.cpp:1629
llvm::SITargetLowering::splitKillBlock
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: SIISelLowering.cpp:3467
llvm::SITargetLowering::shouldEmitGOTReloc
bool shouldEmitGOTReloc(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5076
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::ISD::InputArg
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
Definition: TargetCallingConv.h:195
llvm::SITargetLowering::shouldUseLDSConstAddress
bool shouldUseLDSConstAddress(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5089
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::SITargetLowering::allocateSpecialInputVGPRs
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
Definition: SIISelLowering.cpp:2009
llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition: SIISelLowering.cpp:980
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::SITargetLowering::copyToM0
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
Definition: SIISelLowering.cpp:5874
llvm::SITargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SIISelLowering.cpp:4907
llvm::SITargetLowering::computeKnownAlignForTargetInstr
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine the known alignment for the pointer value R.
Definition: SIISelLowering.cpp:11978
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::SITargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: SIISelLowering.cpp:4450
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl
bool allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const
Definition: SIISelLowering.cpp:1444
llvm::SITargetLowering::shouldExpandAtomicRMWInIR
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: SIISelLowering.cpp:12204
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
uint32_t
llvm::SITargetLowering::shouldExpandVectorDynExt
static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, bool IsDivergentIdx)
Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be expanded into a set of cmp...
Definition: SIISelLowering.cpp:10180
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SITargetLowering::getPreferredShiftAmountTy
LLT getPreferredShiftAmountTy(LLT Ty) const override
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
Definition: SIISelLowering.cpp:4464
llvm::SITargetLowering::supportSplitCSR
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Definition: SIISelLowering.cpp:2277
Node
Definition: ItaniumDemangle.h:235
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::SITargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SIISelLowering.cpp:10922
llvm::SITargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const override
LLT handling variant.
Definition: SIISelLowering.h:278
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:726
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::SITargetLowering::isKnownNeverNaNForTargetNode
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
Definition: SIISelLowering.cpp:12176
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:875
llvm::SITargetLowering::allocateSpecialEntryInputVGPRs
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1887
llvm::SITargetLowering::buildRSRC
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
Definition: SIISelLowering.cpp:11558
llvm::SITargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SIISelLowering.cpp:4604
llvm::TargetLoweringBase::IntrinsicInfo
Definition: TargetLowering.h:996
llvm::SITargetLowering::isMemOpUniform
bool isMemOpUniform(const SDNode *N) const
Definition: SIISelLowering.cpp:1609
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1718
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SITargetLowering::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Definition: SIISelLowering.cpp:12396
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
llvm::SITargetLowering::wrapAddr64Rsrc
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
Definition: SIISelLowering.cpp:11523
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::SITargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: SIISelLowering.cpp:11999
llvm::SITargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: SIISelLowering.cpp:1623
llvm::SITargetLowering
Definition: SIISelLowering.h:31
llvm::SITargetLowering::isFPExtFoldable
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance,...
Definition: SIISelLowering.cpp:912
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:206
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:3404
llvm::SITargetLowering::passSpecialInputs
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
Definition: SIISelLowering.cpp:2747
llvm::SITargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SIISelLowering.cpp:2321
llvm::SITargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SIISelLowering.cpp:3967
N
#define N
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::SITargetLowering::isFreeAddrSpaceCast
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: SIISelLowering.cpp:1597
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2368
llvm::SITargetLowering::checkAsmConstraintValA
bool checkAsmConstraintValA(SDValue Op, uint64_t Val, unsigned MaxSize=64) const
Definition: SIISelLowering.cpp:11800
llvm::SITargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Definition: SIISelLowering.cpp:4439
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl< Value * >
llvm::SITargetLowering::shouldEmitPCReloc
bool shouldEmitPCReloc(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5085
llvm::SITargetLowering::splitBinaryVectorOp
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4557
RegName
#define RegName(no)
llvm::SITargetLowering::AddIMGInit
void AddIMGInit(MachineInstr &MI) const
Definition: SIISelLowering.cpp:11344
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SITargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: SIISelLowering.cpp:922
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1263
llvm::SITargetLowering::allocateSpecialInputSGPRs
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:2043
llvm::SITargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: SIISelLowering.cpp:1567
MachineFunction.h
AMDGPUArgumentUsageInfo.h
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:20
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::SITargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SIISelLowering.cpp:1349
llvm::SITargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SIISelLowering.cpp:3009
llvm::SITargetLowering::isCanonicalized
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
Definition: SIISelLowering.cpp:9596
llvm::SITargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SIISelLowering.cpp:11694
llvm::LLT
Definition: LowLevelTypeImpl.h:40
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