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1//== llvm/CodeGen/GlobalISel/LoadStoreOpt.h - LoadStoreOpt -------*- C++ -*-==//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9/// This is an optimization pass for GlobalISel generic memory operations.
10/// Specifically, it focuses on merging stores and loads to consecutive
11/// addresses.
17#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/SmallSet.h"
26namespace llvm {
27// Forward declarations.
28class AnalysisUsage;
29class GStore;
30class LegalizerInfo;
31class MachineBasicBlock;
32class MachineInstr;
33class TargetLowering;
34struct LegalityQuery;
35class MachineRegisterInfo;
36namespace GISelAddressing {
37/// Helper struct to store a base, index and offset that forms an address
40 Register BaseReg;
41 Register IndexReg;
42 std::optional<int64_t> Offset;
45 BaseIndexOffset() = default;
46 Register getBase() { return BaseReg; }
47 Register getBase() const { return BaseReg; }
48 Register getIndex() { return IndexReg; }
49 Register getIndex() const { return IndexReg; }
50 void setBase(Register NewBase) { BaseReg = NewBase; }
51 void setIndex(Register NewIndex) { IndexReg = NewIndex; }
52 void setOffset(std::optional<int64_t> NewOff) { Offset = NewOff; }
53 bool hasValidOffset() const { return Offset.has_value(); }
54 int64_t getOffset() const { return *Offset; }
57/// Returns a BaseIndexOffset which describes the pointer in \p Ptr.
60/// Compute whether or not a memory access at \p MI1 aliases with an access at
61/// \p MI2 \returns true if either alias/no-alias is known. Sets \p IsAlias
62/// accordingly.
63bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2,
64 bool &IsAlias, MachineRegisterInfo &MRI);
66/// Returns true if the instruction \p MI may alias \p Other.
67/// This function uses multiple strategies to detect aliasing, whereas
68/// aliasIsKnownForLoadStore just looks at the addresses of load/stores and is
69/// tries to reason about base/index/offsets.
72} // namespace GISelAddressing
74using namespace GISelAddressing;
78 static char ID;
81 /// An input function to decide if the pass should run or not
82 /// on the given MachineFunction.
83 std::function<bool(const MachineFunction &)> DoNotRunPass;
85 MachineRegisterInfo *MRI = nullptr;
86 const TargetLowering *TLI = nullptr;
87 MachineFunction *MF = nullptr;
88 AliasAnalysis *AA = nullptr;
89 const LegalizerInfo *LI = nullptr;
91 MachineIRBuilder Builder;
93 /// Initialize the field members using \p MF.
94 void init(MachineFunction &MF);
96 class StoreMergeCandidate {
97 public:
98 // The base pointer used as the base for all stores in this candidate.
99 Register BasePtr;
100 // Our algorithm is very simple at the moment. We assume that in instruction
101 // order stores are writing to incremeneting consecutive addresses. So when
102 // we walk the block in reverse order, the next eligible store must write to
103 // an offset one store width lower than CurrentLowestOffset.
104 int64_t CurrentLowestOffset;
106 // A vector of MachineInstr/unsigned pairs to denote potential aliases that
107 // need to be checked before the candidate is considered safe to merge. The
108 // unsigned value is an index into the Stores vector. The indexed store is
109 // the highest-indexed store that has already been checked to not have an
110 // alias with the instruction. We record this so we don't have to repeat
111 // alias checks that have been already done, only those with stores added
112 // after the potential alias is recorded.
115 void addPotentialAlias(MachineInstr &MI);
117 /// Reset this candidate back to an empty one.
118 void reset() {
119 Stores.clear();
120 PotentialAliases.clear();
121 CurrentLowestOffset = 0;
122 BasePtr = Register();
123 }
124 };
126 bool isLegalOrBeforeLegalizer(const LegalityQuery &Query,
127 MachineFunction &MF) const;
128 /// If the given store is valid to be a member of the candidate, add it and
129 /// return true. Otherwise, returns false.
130 bool addStoreToCandidate(GStore &MI, StoreMergeCandidate &C);
131 /// Returns true if the instruction \p MI would potentially alias with any
132 /// stores in the candidate \p C.
133 bool operationAliasesWithCandidate(MachineInstr &MI, StoreMergeCandidate &C);
134 /// Merges the stores in the given vector into a wide store.
135 /// \p returns true if at least some of the stores were merged.
136 /// This may decide not to merge stores if heuristics predict it will not be
137 /// worth it.
138 bool mergeStores(SmallVectorImpl<GStore *> &StoresToMerge);
139 /// Perform a merge of all the stores in \p Stores into a single store.
140 /// Erases the old stores from the block when finished.
141 /// \returns true if merging was done. It may fail to perform a merge if
142 /// there are issues with materializing legal wide values.
143 bool doSingleStoreMerge(SmallVectorImpl<GStore *> &Stores);
144 bool processMergeCandidate(StoreMergeCandidate &C);
145 bool mergeBlockStores(MachineBasicBlock &MBB);
146 bool mergeFunctionStores(MachineFunction &MF);
148 bool mergeTruncStore(GStore &StoreMI,
149 SmallPtrSetImpl<GStore *> &DeletedStores);
150 bool mergeTruncStoresBlock(MachineBasicBlock &MBB);
152 /// Initialize some target-specific data structures for the store merging
153 /// optimization. \p AddrSpace indicates which address space to use when
154 /// probing the legalizer info for legal stores.
155 void initializeStoreMergeTargetInfo(unsigned AddrSpace = 0);
156 /// A map between address space numbers and a bitvector of supported stores
157 /// sizes. Each bit in the bitvector represents whether a store size of
158 /// that bit's value is legal. E.g. if bit 64 is set, then 64 bit scalar
159 /// stores are legal.
160 DenseMap<unsigned, BitVector> LegalStoreSizes;
161 bool IsPreLegalizer = false;
162 /// Contains instructions to be erased at the end of a block scan.
163 SmallSet<MachineInstr *, 16> InstsToErase;
166 LoadStoreOpt();
167 LoadStoreOpt(std::function<bool(const MachineFunction &)>);
169 StringRef getPassName() const override { return "LoadStoreOpt"; }
174 }
176 void getAnalysisUsage(AnalysisUsage &AU) const override;
178 bool runOnMachineFunction(MachineFunction &MF) override;
181} // End namespace llvm.
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
This file implements the BitVector class.
IRTranslator LLVM IR MI
This file declares the MachineIRBuilder class.
This file defines the SmallPtrSet class.
This file defines the SmallSet class.
This file defines the SmallVector class.
Represent the analysis usage information of a pass.
Helper struct to store a base, index and offset that forms an address.
Definition: LoadStoreOpt.h:38
void setOffset(std::optional< int64_t > NewOff)
Definition: LoadStoreOpt.h:52
void setIndex(Register NewIndex)
Definition: LoadStoreOpt.h:51
static char ID
Definition: LoadStoreOpt.h:78
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
MachineFunctionProperties getRequiredProperties() const override
Definition: LoadStoreOpt.h:171
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
Definition: LoadStoreOpt.h:169
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2, bool &IsAlias, MachineRegisterInfo &MRI)
Compute whether or not a memory access at MI1 aliases with an access at MI2.
BaseIndexOffset getPointerInfo(Register Ptr, MachineRegisterInfo &MRI)
Returns a BaseIndexOffset which describes the pointer in Ptr.
bool instMayAlias(const MachineInstr &MI, const MachineInstr &Other, MachineRegisterInfo &MRI, AliasAnalysis *AA)
Returns true if the instruction MI may alias Other.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Other
Any other memory.