14#ifndef LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H
15#define LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H
25class ARCTargetMachine;
117 bool mayBeEmittedAsTailCall(
const CallInst *CI)
const override;
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
This class represents a function call, abstracting a target machine's calling convention.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
This is an important class for using LLVM in a threaded context.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
The instances of the Type class are immutable: once they are created, they are never changed.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
This is an optimization pass for GlobalISel generic memory operations.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
This structure contains all information that is necessary for lowering calls.