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31 #define DEBUG_TYPE "arc-lower"
71 void ARCTargetLowering::ReplaceNodeResults(
SDNode *
N,
78 switch (
N->getOpcode()) {
184 return "ARCISD::CMOV";
186 return "ARCISD::CMP";
188 return "ARCISD::BRcc";
190 return "ARCISD::RET";
192 return "ARCISD::GAWRAPPER";
220 "Unhandled target sign_extend_inreg.");
222 unsigned Width = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
249 auto *
N = cast<JumpTableSDNode>(
Op);
254 #include "ARCGenCallingConv.inc"
280 CCInfo.AnalyzeCallOperands(Outs, CC_ARC);
286 RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(),
Align(4));
287 RetCCInfo.AnalyzeCallResult(
Ins, RetCC_ARC);
290 unsigned NumBytes = RetCCInfo.getNextStackOffset();
300 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
324 RegsToPass.push_back(std::make_pair(VA.
getLocReg(),
Arg));
337 MemOpChains.push_back(
Store);
344 if (!MemOpChains.empty())
352 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i) {
354 RegsToPass[
i].second, Glue);
361 bool IsDirect =
true;
362 if (
auto *
G = dyn_cast<GlobalAddressSDNode>(Callee))
364 else if (
auto *
E = dyn_cast<ExternalSymbolSDNode>(Callee))
374 Ops.push_back(Chain);
375 Ops.push_back(Callee);
377 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i)
379 RegsToPass[
i].second.getValueType()));
385 assert(
Mask &&
"Missing call preserved mask for calling convention");
414 for (
unsigned i = 0,
e = RVLocs.size();
i !=
e; ++
i) {
422 InVals.push_back(RetValue);
425 ResultMemLocs.push_back(
435 for (
unsigned i = 0,
e = ResultMemLocs.size();
i !=
e; ++
i) {
436 int Offset = ResultMemLocs[
i].first;
437 unsigned Index = ResultMemLocs[
i].second;
443 InVals[Index] =
Load;
444 MemOpChains.push_back(
Load.getValue(1));
449 if (!MemOpChains.empty())
469 SDValue ARCTargetLowering::LowerFormalArguments(
478 return LowerCallArguments(Chain, CallConv, IsVarArg,
Ins, dl, DAG, InVals);
484 SDValue ARCTargetLowering::LowerCallArguments(
498 CCInfo.AnalyzeFormalArguments(
Ins, CC_ARC);
500 unsigned StackSlotSize = 4;
503 AFI->setReturnStackOffset(CCInfo.getNextStackOffset());
517 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
526 LLVM_DEBUG(
errs() <<
"LowerFormalArguments Unhandled argument type: "
541 assert((ObjSize <= StackSlotSize) &&
"Unhandled argument");
552 const ArgDataPair ADP = {ArgIn,
Ins[
i].Flags};
553 ArgData.push_back(ADP);
562 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
571 CCInfo.getNextStackOffset(),
true);
572 AFI->setVarArgsFrameIndex(VarFI);
585 MemOps.push_back(
Store);
594 if (!CFRegNode.empty())
601 for (
const auto &ArgDI : ArgData) {
602 if (ArgDI.Flags.isByVal() && ArgDI.Flags.getByValSize()) {
603 unsigned Size = ArgDI.Flags.getByValSize();
605 std::max(
Align(StackSlotSize), ArgDI.Flags.getNonZeroByValAlign());
609 InVals.push_back(FIN);
615 InVals.push_back(ArgDI.SDV);
620 if (!MemOps.empty()) {
621 MemOps.push_back(Chain);
632 bool ARCTargetLowering::CanLowerReturn(
637 if (!CCInfo.CheckReturn(Outs, RetCC_ARC))
639 if (CCInfo.getNextStackOffset() != 0 && IsVarArg)
663 CCInfo.AllocateStack(AFI->getReturnStackOffset(),
Align(4));
665 CCInfo.AnalyzeReturn(Outs, RetCC_ARC);
671 for (
unsigned i = 0,
e = RVLocs.size();
i !=
e; ++
i) {
683 int FI = MFI.CreateFixedObject(ObjSize, Offset,
false);
689 Chain, dl, OutVals[
i], FIN,
695 if (!MemOpChains.empty())
699 for (
unsigned i = 0,
e = RVLocs.size();
i !=
e; ++
i) {
716 RetOps.push_back(
Flag);
727 DAGCombinerInfo &DCI)
const {
741 return AM.
Scale == 0;
745 bool ARCTargetLowering::mayBeEmittedAsTailCall(
const CallInst *CI)
const {
755 EVT VT =
Op.getValueType();
757 assert(cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue() == 0 &&
758 "Only support lowering frame addr of current frame.");
782 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
783 return DAG.
getStore(
Op.getOperand(0), dl, FR,
Op.getOperand(1),
788 switch (
Op.getOpcode()) {
790 return LowerGlobalAddress(
Op, DAG);
792 return LowerFRAMEADDR(
Op, DAG);
794 return LowerSELECT_CC(
Op, DAG);
796 return LowerBR_CC(
Op, DAG);
798 return LowerSIGN_EXTEND_INREG(
Op, DAG);
800 return LowerJumpTable(
Op, DAG);
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
This is an optimization pass for GlobalISel generic memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
@ BR_JT
BR_JT - Jumptable branch.
CCState - This class holds information needed while lowering arguments and return values.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
SDNode * getNode() const
get the SDNode which holds the desired result
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Function Alias Analysis Results
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Register getFrameRegister(const MachineFunction &MF) const override
unsigned const TargetRegisterInfo * TRI
LLVMContext * getContext() const
@ BRCOND
BRCOND - Conditional branch.
SDValue getRegister(unsigned Reg, EVT VT)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ BR_CC
BR_CC - Conditional branch.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
EVT getValueType() const
Return the ValueType of the referenced return value.
CCValAssign - Represent assignment of one arg/retval to a location.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Register getLocReg() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
const TargetLowering & getTargetLoweringInfo() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
@ AND
Bitwise operators - logical and, logical or, logical xor.
LocInfo getLocInfo() const
const GlobalValue * getGlobal() const
unsigned getLocMemOffset() const
This struct is a compact representation of a valid (non-zero power of two) alignment.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SmallVector< ISD::OutputArg, 32 > Outs
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
int64_t getOffset() const
SDValue getValue(unsigned R) const
This structure contains all information that is necessary for lowering calls.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SmallVector< ISD::InputArg, 32 > Ins
const ARCRegisterInfo * getRegisterInfo() const override
static ARCCC::CondCode ISDCCtoARCCC(ISD::CondCode isdCC)
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
C - The default llvm calling convention, compatible with C.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ UNDEF
UNDEF - An undefined node.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Wrapper class representing virtual and physical registers.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
amdgpu Simplify well known AMD library false FunctionCallee Callee
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
const DataLayout & getDataLayout() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
@ ZeroOrOneBooleanContent
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ ADD
Simple integer binary arithmetic operators.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
@ SHL
Shift and rotation operations.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
ARCTargetLowering(const TargetMachine &TM, const ARCSubtarget &Subtarget)
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
SDValue getRegisterMask(const uint32_t *RegMask)
Align max(MaybeAlign Lhs, Align Rhs)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
SmallVector< SDValue, 32 > OutVals
static SDValue lowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
Lower the result values of a call into the appropriate copies out of physical registers / memory loca...
const char LLVMTargetMachineRef TM
This class represents a function call, abstracting a target machine's calling convention.
MachineFunction & getMachineFunction() const
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
void setFrameAddressIsTaken(bool T)
@ SIGN_EXTEND
Conversion operators.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
ARCFunctionInfo - This class is derived from MachineFunction private ARC target-specific information ...
LLVM Value Representation.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.