LLVM  14.0.0git
ARCRegisterInfo.cpp
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1 //===- ARCRegisterInfo.cpp - ARC Register Information -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARC implementation of the MRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARCRegisterInfo.h"
14 #include "ARC.h"
15 #include "ARCInstrInfo.h"
16 #include "ARCMachineFunctionInfo.h"
17 #include "ARCSubtarget.h"
18 #include "llvm/ADT/BitVector.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/Debug.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "arc-reg-info"
34 
35 #define GET_REGINFO_TARGET_DESC
36 #include "ARCGenRegisterInfo.inc"
37 
39  const ARCInstrInfo &TII, unsigned Reg,
40  unsigned FrameReg, int Offset, int StackSize,
41  int ObjSize, RegScavenger *RS, int SPAdj) {
42  assert(RS && "Need register scavenger.");
43  MachineInstr &MI = *II;
44  MachineBasicBlock &MBB = *MI.getParent();
45  DebugLoc DL = MI.getDebugLoc();
46  unsigned BaseReg = FrameReg;
47  unsigned KillState = 0;
48  if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) {
49  // Loads can always be reached with LD_rlimm.
50  BuildMI(MBB, II, DL, TII.get(ARC::LD_rlimm), Reg)
51  .addReg(BaseReg)
52  .addImm(Offset)
53  .addMemOperand(*MI.memoperands_begin());
54  MBB.erase(II);
55  return;
56  }
57 
58  if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {
59  // We need to use a scratch register to reach the far-away frame indexes.
60  BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);
61  if (!BaseReg) {
62  // We can be sure that the scavenged-register slot is within the range
63  // of the load offset.
64  const TargetRegisterInfo *TRI =
66  BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
67  assert(BaseReg && "Register scavenging failed.");
68  LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
69  << " for FrameReg=" << printReg(FrameReg, TRI)
70  << "+Offset=" << Offset << "\n");
71  (void)TRI;
72  RS->setRegUsed(BaseReg);
73  }
74  unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
75  BuildMI(MBB, II, DL, TII.get(AddOpc))
76  .addReg(BaseReg, RegState::Define)
77  .addReg(FrameReg)
78  .addImm(Offset);
79  Offset = 0;
80  KillState = RegState::Kill;
81  }
82  switch (MI.getOpcode()) {
83  case ARC::LD_rs9:
84  assert((Offset % 4 == 0) && "LD needs 4 byte alignment.");
86  case ARC::LDH_rs9:
87  case ARC::LDH_X_rs9:
88  assert((Offset % 2 == 0) && "LDH needs 2 byte alignment.");
90  case ARC::LDB_rs9:
91  case ARC::LDB_X_rs9:
92  LLVM_DEBUG(dbgs() << "Building LDFI\n");
93  BuildMI(MBB, II, DL, TII.get(MI.getOpcode()), Reg)
94  .addReg(BaseReg, KillState)
95  .addImm(Offset)
96  .addMemOperand(*MI.memoperands_begin());
97  break;
98  case ARC::ST_rs9:
99  assert((Offset % 4 == 0) && "ST needs 4 byte alignment.");
101  case ARC::STH_rs9:
102  assert((Offset % 2 == 0) && "STH needs 2 byte alignment.");
104  case ARC::STB_rs9:
105  LLVM_DEBUG(dbgs() << "Building STFI\n");
106  BuildMI(MBB, II, DL, TII.get(MI.getOpcode()))
107  .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
108  .addReg(BaseReg, KillState)
109  .addImm(Offset)
110  .addMemOperand(*MI.memoperands_begin());
111  break;
112  case ARC::GETFI:
113  LLVM_DEBUG(dbgs() << "Building GETFI\n");
114  BuildMI(MBB, II, DL,
115  TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
117  .addReg(FrameReg)
118  .addImm(Offset);
119  break;
120  default:
121  llvm_unreachable("Unhandled opcode.");
122  }
123 
124  // Erase old instruction.
125  MBB.erase(II);
126 }
127 
129  : ARCGenRegisterInfo(ARC::BLINK), ST(ST) {}
130 
132  return MF.needsFrameMoves();
133 }
134 
135 const MCPhysReg *
137  return CSR_ARC_SaveList;
138 }
139 
141  BitVector Reserved(getNumRegs());
142 
143  Reserved.set(ARC::ILINK);
144  Reserved.set(ARC::SP);
145  Reserved.set(ARC::GP);
146  Reserved.set(ARC::R25);
147  Reserved.set(ARC::BLINK);
148  Reserved.set(ARC::FP);
149 
150  return Reserved;
151 }
152 
154  const MachineFunction &MF) const {
155  return true;
156 }
157 
159  return true;
160 }
161 
163  int SPAdj, unsigned FIOperandNum,
164  RegScavenger *RS) const {
165  assert(SPAdj == 0 && "Unexpected");
166  MachineInstr &MI = *II;
167  MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
168  int FrameIndex = FrameOp.getIndex();
169 
170  MachineFunction &MF = *MI.getParent()->getParent();
171  const ARCInstrInfo &TII = *MF.getSubtarget<ARCSubtarget>().getInstrInfo();
172  const ARCFrameLowering *TFI = getFrameLowering(MF);
174  int ObjSize = MF.getFrameInfo().getObjectSize(FrameIndex);
175  int StackSize = MF.getFrameInfo().getStackSize();
176  int LocalFrameSize = MF.getFrameInfo().getLocalFrameSize();
177 
178  LLVM_DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n");
179  LLVM_DEBUG(dbgs() << "<--------->\n");
180  LLVM_DEBUG(dbgs() << MI << "\n");
181  LLVM_DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n");
182  LLVM_DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n");
183  LLVM_DEBUG(dbgs() << "FrameOffset : " << Offset << "\n");
184  LLVM_DEBUG(dbgs() << "StackSize : " << StackSize << "\n");
185  LLVM_DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n");
186  (void)LocalFrameSize;
187 
188  // Special handling of DBG_VALUE instructions.
189  if (MI.isDebugValue()) {
190  Register FrameReg = getFrameRegister(MF);
191  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
192  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
193  return;
194  }
195 
196  // fold constant into offset.
197  Offset += MI.getOperand(FIOperandNum + 1).getImm();
198 
199  // TODO: assert based on the load type:
200  // ldb needs no alignment,
201  // ldh needs 2 byte alignment
202  // ld needs 4 byte alignment
203  LLVM_DEBUG(dbgs() << "Offset : " << Offset << "\n"
204  << "<--------->\n");
205 
206  Register Reg = MI.getOperand(0).getReg();
207  assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand");
208 
209  if (!TFI->hasFP(MF)) {
210  Offset = StackSize + Offset;
211  if (FrameIndex >= 0)
212  assert((Offset >= 0 && Offset < StackSize) && "SP Offset not in bounds.");
213  } else {
214  if (FrameIndex >= 0) {
215  assert((Offset < 0 && -Offset <= StackSize) &&
216  "FP Offset not in bounds.");
217  }
218  }
219  replaceFrameIndex(II, TII, Reg, getFrameRegister(MF), Offset, StackSize,
220  ObjSize, RS, SPAdj);
221 }
222 
224  const ARCFrameLowering *TFI = getFrameLowering(MF);
225  return TFI->hasFP(MF) ? ARC::FP : ARC::SP;
226 }
227 
228 const uint32_t *
230  CallingConv::ID CC) const {
231  return CSR_ARC_RegMask;
232 }
ARCGenRegisterInfo
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
TargetFrameLowering.h
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::ARCRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: ARCRegisterInfo.cpp:162
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
ARCSubtarget.h
llvm::ARCRegisterInfo::useFPForScavengingIndex
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Definition: ARCRegisterInfo.cpp:158
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::ARCRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: ARCRegisterInfo.cpp:223
llvm::ARCFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: ARCFrameLowering.cpp:491
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::RegScavenger::FindUnusedReg
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
Definition: RegisterScavenging.cpp:268
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1304
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::ARCFrameLowering
Definition: ARCFrameLowering.h:27
ARCRegisterInfo.h
TargetMachine.h
llvm::RegScavenger::scavengeRegister
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
Definition: RegisterScavenging.cpp:520
llvm::ARCSubtarget
Definition: ARCSubtarget.h:31
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::ARCRegisterInfo::needsFrameMoves
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
Definition: ARCRegisterInfo.cpp:131
llvm::ARCRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Definition: ARCRegisterInfo.cpp:153
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:553
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
llvm::BitVector
Definition: BitVector.h:74
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ARCRegisterInfo::ARCRegisterInfo
ARCRegisterInfo(const ARCSubtarget &)
Definition: ARCRegisterInfo.cpp:128
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
ARCMachineFunctionInfo.h
llvm::MachineFrameInfo::getLocalFrameSize
int64_t getLocalFrameSize() const
Get the size of the local object blob.
Definition: MachineFrameInfo.h:421
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::ARCRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: ARCRegisterInfo.cpp:136
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::ARCRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: ARCRegisterInfo.cpp:140
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:541
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ARCRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: ARCRegisterInfo.cpp:229
TargetOptions.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
ARCInstrInfo.h
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
replaceFrameIndex
static void replaceFrameIndex(MachineBasicBlock::iterator II, const ARCInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, int StackSize, int ObjSize, RegScavenger *RS, int SPAdj)
Definition: ARCRegisterInfo.cpp:38
llvm::MachineFunction::needsFrameMoves
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
Definition: MachineFunction.cpp:587
uint16_t
llvm::ARCInstrInfo
Definition: ARCInstrInfo.h:26
MachineFrameInfo.h
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
llvm::RegScavenger::setRegUsed
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Definition: RegisterScavenging.cpp:53
Function.h
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
ARC.h
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
RegisterScavenging.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< MachineInstr >
Debug.h